A storage chip performance testing method based on sparse matrix decomposition

Abstract

The present invention discloses a storage chip performance testing method based on sparse matrix decomposition, comprising the following steps: S1, constructing a performance test data set; S2, preprocessing the performance test data set; S3, constructing the preprocessed performance test data set into a high-dimensional sparse matrix; S4, performing sparse matrix decomposition on the high-dimensional sparse matrix to obtain a low-rank feature matrix and a sparse error matrix; S5, constructing a generative adversarial network based on the low-rank feature matrix; S6, optimizing the generator network to generate virtual performance test data that is closer to the distribution of real performance test data; S7, forming an enhanced performance test data set; S8, performing sparse matrix decomposition on the enhanced performance test data set again; and S9, evaluating the performance of the storage chip based on the new low-rank feature matrix and sparse error matrix. The present invention enables a test system to process a large amount of test data in a relatively short period of time, thereby improving overall test efficiency.

Description

Technical Field

[0001] The present invention relates to the field of storage chip technology, and in particular to a storage chip performance testing method based on sparse matrix decomposition. Background Art

[0002] In the field of storage chip performance testing, with the rapid development of semiconductor technology and the continuous improvement of integration, traditional testing methods are facing unprecedented challenges. Traditional storage chip performance testing relies on large-scale data acquisition and complex computational analysis. However, in the face of the ever-increasing data scale, it often consumes a lot of computing resources and time, and easily leads to a significant decrease in test efficiency. At the same time, during the data processing process, traditional methods have the problem of being unable to fully extract key information from the data due to the complexity and diversity of the test data, which affects the accuracy and reliability of the test results.

[0003] Existing storage chip performance testing technologies mainly focus on testing and analyzing different performance indicators one by one. Linear testing methods are easily limited by computing resources and time costs when processing large-scale data sets. In addition, existing technologies usually rely on the processing and analysis of the entire data set, making it impossible for the system to effectively identify and extract the main performance characteristics and potential abnormal behaviors of storage chips when faced with massive amounts of data. As the internal structure of chips becomes more complex and diversified, traditional testing methods often require tedious manual intervention when dealing with complex test data, which not only increases the complexity of the testing process, but also easily introduces human errors, resulting in inconsistent and unreliable test results.

[0004] In addition, most performance evaluation methods in existing technologies are based on the analysis of a single performance indicator and lack in-depth research on the relationship between multiple performance indicators. This limits the ability to evaluate the overall performance of storage chips to a certain extent. In particular, when processing performance data under complex and extreme working conditions, existing technologies find it difficult to comprehensively and accurately identify performance bottlenecks and potential problems. When faced with rare abnormal data that may exist in storage chips, traditional methods are often unable to effectively detect and analyze these key data, thereby affecting the testing process's ability to identify potential defects in the chip.

[0005] In summary, existing storage chip performance testing methods have many defects in data processing efficiency, accuracy and reliability of test results, and detection of abnormal data. With the increasing complexity of chip design and the increasing market demand for efficient testing methods, the existing technology urgently needs a storage chip performance testing method based on sparse matrix decomposition to solve the defects of the existing technology. Summary of the Invention

[0006] One object of the present invention is to propose a storage chip performance testing method based on sparse matrix decomposition, which enables the testing system to process a large amount of test data in a shorter time, thereby improving the overall testing efficiency.

[0007] A storage chip performance testing method based on sparse matrix decomposition according to an embodiment of the present invention includes the following steps:

[0008] S1. Initialize the storage chip, set the storage chip to test mode, receive and process the read and write speed, data integrity, power consumption and operation delay of the storage chip under different working conditions, and build a performance test data set;

[0009] S2. Preprocessing the performance test data set, including data denoising, data normalization, data format standardization, and missing value processing;

[0010] S3. Construct the preprocessed performance test data set into a high-dimensional sparse matrix, where each row of the high-dimensional sparse matrix represents multi-dimensional performance data of different storage chip test samples, and each column represents different performance indicators of the storage chip;

[0011] S4. Performing sparse matrix decomposition on the high-dimensional sparse matrix to obtain a low-rank feature matrix and a sparse error matrix, wherein the low-rank feature matrix is used to represent performance characteristics of the storage chip, and the sparse error matrix is used to represent abnormal data or rare data in the performance test of the storage chip;

[0012] S5. Based on the low-rank feature matrix, a generative adversarial network is constructed, including a generator network and a discriminator network. The generator network receives the low-rank feature matrix as input and generates virtual performance test data through a neural network. The virtual performance test data is similar to the actual performance test data set in statistical distribution. The discriminator network is used to receive the virtual performance test data and the actual performance test data set and output a probability of judging whether the input is real data.

[0013] S6. Perform adversarial training on the generative adversarial network to optimize the generator network to generate virtual performance test data that is closer to the distribution of real performance test data, and optimize the discriminator network to improve the ability to distinguish between real performance test data sets and virtual performance test data;

[0014] S7. Fusing the virtual performance test data generated by the generative adversarial network with the real performance test dataset to form an enhanced performance test dataset, including potential performance patterns and data under extreme test conditions;

[0015] S8. Perform sparse matrix decomposition again on the enhanced performance test dataset to extract a new low-rank feature matrix and a sparse error matrix. The new low-rank feature matrix is used to represent the optimized storage chip performance characteristics, and the sparse error matrix is used to represent abnormal performance data and potential performance issues.

[0016] S9. Based on the new low-rank feature matrix and sparse error matrix, the performance of the storage chip is evaluated to identify and locate the performance bottlenecks, abnormal behaviors and potential problems of the storage chip.

[0017] Optionally, the S1 includes the following steps:

[0018] S11, initializing the storage chip under different working conditions and setting it to a test mode, the working conditions including different voltage levels, temperature ranges and operating frequencies;

[0019] S12. Under each working condition, perform read and write operations and record the read and write speed R of each operation. i , where i is the test sample number;

[0020] S13. Monitor data integrity while performing read and write operations. i ,Data integrity is expressed by comparing the bit error rate of the original data with the read data;

[0021] S14. Record the power consumption P under each working condition i , power consumption is measured by measuring the current I consumed by the storage chip during read and write operations i and voltage V i Calculated;

[0022] S15. Measure and record the operation delay L of the storage chip under different working conditions i ,The operation delay is the time required from sending the read or write instruction to the completion of the operation;

[0023] S16, the reading and writing speed R of each test sample under different working conditions i , data integrity D i , power consumption P i and operation delay L i Combine and construct the performance test dataset T:

[0024]

[0025] Where n is the number of test samples, each row represents the multi-dimensional performance data of a test sample, and each column represents a performance indicator of the storage chip under different working conditions.

[0026] Optionally, S3 includes the following steps:

[0027] S31, standardizing each data in the pre-processed performance test data set T to obtain a standardized performance test data set T';

[0028] S32. Construct the standardized performance test data set T' into a high-dimensional sparse matrix M. Each row of the matrix M represents the multi-dimensional performance data of different storage chip test samples, and each column represents different performance indicators of the storage chip:

[0029]

[0030] Among them, R′ i , D′ i , P′ i and L′ i They represent the normalized read and write speed, normalized data integrity, normalized power consumption, and normalized operation delay of the i-th test sample, respectively, and n is the number of test samples;

[0031] S33. Perform sparsity analysis on the constructed high-dimensional sparse matrix M, identify and retain the sparse features in the matrix that have an impact on the performance of the storage chip, filter out redundant features and features that are irrelevant to the performance of the storage chip, and obtain the optimized high-dimensional sparse matrix M. opt .

[0032] Optionally, the S4 includes the following steps:

[0033] S41, the optimized high-dimensional sparse matrix M opt Perform matrix decomposition to decompose the high-dimensional sparse matrix into a low-rank feature matrix L1 and a sparse error matrix S1, so that M opt =L1+S1, where the low-rank feature matrix L1 represents the performance characteristics of the storage chip under various working conditions, and the sparse error matrix S1 represents abnormal data or rare data that appears during the test;

[0034] S42. Define the objective function based on the storage chip performance test. Considering the characteristics of the test data, the objective function is in the form of:

[0035]

[0036] where ‖L1‖ * represents the nuclear norm of the low-rank feature matrix L1, which is used to ensure the extraction of the main performance characteristics of the storage chip. ‖S1‖1 represents the l1 norm of the sparse error matrix S1, which is used to ensure the sparsity of the detected abnormal data. is the weighted l2 norm of the sparse error matrix S1, the weight matrix W is used to adjust the detection sensitivity of abnormal data, λ1 and λ2 are regularization parameters, which adjust the balance between the low-rank feature matrix and the sparse error matrix;

[0037] S43, use the alternating direction multiplier method for iterative optimization, in the k+1th iteration, update the low-rank feature matrix

[0038]

[0039] in, is the Lagrange multiplier, μ1 is the penalty parameter, ‖·‖ F Represents the Frobenius norm, which is used to measure the difference between matrices;

[0040] In the k+1th iteration, the sparse error matrix is updated

[0041]

[0042] Update the Lagrange multiplier Y1:

[0043]

[0044] Check the iterative convergence conditions when When it is less than the set threshold, the iteration is stopped and the final low-rank feature matrix L1 and sparse error matrix S1 are obtained.

[0045] Optionally, the S5 includes the following steps:

[0046] S51. Construct a generative adversarial network based on the low-rank feature matrix L1, including a generator network G and a discriminator network D.

[0047] S52, the generator network G receives the low-rank feature matrix L1 as input, and the input vector z of the generator network i Defined as:

[0048] z i =f(L1,W G ,b G )+∈ i ;

[0049] Among them, f(L1,W G ,b G ) represents the mapping function from the low-rank feature matrix L1 to the input space of the generator network, W G and b G are the weight matrix and bias vector of the generator network, ∈ i is a random noise vector, which is used to simulate the random disturbance effect of the storage chip under different working conditions;

[0050] S53, the generator network generates virtual performance test data through the neural network structure Simulate the various performances of memory chips under different operating conditions:

[0051]

[0052] Where h(L1) represents the intermediate feature representation after processing by the nonlinear activation function, and σ(·) is the output activation function of the generator network, which is used to generate virtual performance test data with a statistical distribution similar to the real performance test data.

[0053] S54, the discriminator network D receives virtual performance test data and actual performance test data T real As input, the discrimination result of the discriminator network is defined as:

[0054]

[0055] Where x represents the input data (i.e. or T real , W D and b D are the weight matrix and bias vector of the discriminator network, α D is the adjustment coefficient of the discriminator, which controls the output sensitivity of the discriminator network;

[0056] S55. Define the objective function of the generative adversarial network to optimize the performance of the generator and discriminator networks:

[0057]

[0058] Among them, p data (T) represents the distribution of real performance test data, p z (z) represents the noise distribution of the generator input, It is the difference measure between the generated data and the low-rank feature matrix. By introducing the difference measure, the generated data is kept consistent with the performance characteristics of the actual storage chip. λ is a regularization parameter used to adjust the balance between the authenticity of the generated data and the consistency of the features.

[0059] S56, through iterative training of the generative adversarial network, the virtual performance test data generated by the generator network G Compared with the actual performance test data T real The distribution is gradually approaching.

[0060] Optionally, the S7 includes the following steps:

[0061] S71, the virtual performance test data generated by the generative adversarial network G Compared with the real performance test dataset T realPerform preprocessing to standardize and normalize the data structures of both;

[0062] S72. Define the objective function of the fusion operation:

[0063]

[0064] Among them, T enhanced is the enhanced performance test data set, α is the weight parameter, which controls the ratio of real performance test data and virtual performance test data in the fusion process. is the virtual performance test data, T real For real performance test data;

[0065] S73. Based on the performance of the storage chip under extreme test conditions, adjust the weight parameter α to increase the proportion of data under extreme conditions in the enhanced data set.

[0066] Optionally, the S8 includes the following steps:

[0067] S81, the enhanced performance test data set T enhanced Perform standardization to obtain the standardized enhanced performance test data set T′ enhanced ;

[0068] S82. Test the standardized enhanced performance data set T′ enhanced Construct an enhanced high-dimensional sparse matrix M enhanced ,Each row of the enhanced high-dimensional sparse matrix represents the enhanced performance data of different storage chips under different test conditions, and each column represents a different performance indicator;

[0069] S83, enhance the high-dimensional sparse matrix M enhanced Perform sparse matrix decomposition and decompose it into enhanced low-rank feature matrix L2 and enhanced sparse error matrix S2, so that M enhanced =L2+S2;

[0070] S84, the enhanced low-rank feature matrix L2 represents the main performance characteristics of the optimized storage chip, and the enhanced sparse error matrix S2 represents abnormal performance data and potential performance problems;

[0071] S85. Use the optimization method of S4 to iteratively optimize, and finally obtain the enhanced low-rank feature matrix L2 and the enhanced sparse error matrix S2.

[0072] Optionally, the S9 includes the following steps:

[0073] S91. Based on the enhanced low-rank feature matrix L2 and the enhanced sparse error matrix S2, a storage chip performance evaluation model P is established. eval :

[0074]

[0075] Among them, K represents the total number of different working conditions of the storage chip, n k represents the number of test samples under each working condition, m is the performance index number of the storage chip, w kij is the weight of the jth performance indicator of the i-th test sample of the storage chip under working condition k, α k is an adjustment parameter used to control the mutual influence between the low-rank feature matrix and the sparse error matrix under different working conditions. γ and η are regularization parameters that control the contribution ratio of different items in the evaluation results.

[0076] S92, in the storage chip performance evaluation model P eval , identify the performance bottleneck of storage chips:

[0077]

[0078] Among them, B bottleneck Indicates the dimension where the performance bottleneck is located, λ k It is a regulation factor related to the working condition k, which is used to adjust the relative contributions of the low-rank feature matrix and the sparse error matrix;

[0079] S93. Based on the enhanced sparse error matrix S2, locate abnormal behaviors and potential problems of the storage chip:

[0080]

[0081] Among them, A anomaly is a collection of abnormal behaviors, and are the mean and standard deviation of the elements in the i-th row and j-th column of the sparse error matrix S2, ∈ is a small constant to prevent the denominator from being zero, and θ is a threshold parameter used to determine when to mark a data point as an anomaly;

[0082] S94. Generate a storage chip performance evaluation report, which includes the results of locating performance bottlenecks, identifying abnormal behaviors, and optimization suggestions for potential problems.

[0083] A storage chip performance testing device based on sparse matrix decomposition includes the following modules:

[0084] Data acquisition module, which acquires and pre-processes the performance test data of the storage chip under different working conditions, and collects and stores the test data in real time;

[0085] The matrix construction module is used to construct a high-dimensional sparse matrix based on the preprocessed performance test data set and automatically generate the corresponding sparse matrix based on the data formatting results;

[0086] Sparse matrix decomposition module, which generates low-rank feature matrix and sparse error matrix. The decomposition module includes sparsity analysis unit, decomposition algorithm unit and optimization unit;

[0087] Generate adversarial network module, which generates virtual performance test data and integrates it with real data. It includes generator network unit, discriminator network unit and adversarial training unit, and automatically adjusts network parameters to generate virtual data.

[0088] Performance evaluation module, which identifies and locates performance bottlenecks and abnormal behaviors, and generates performance reports based on the evaluation results;

[0089] The system control module is used to coordinate the work of each module, manage the test process and store the test results.

[0090] The beneficial effects of the present invention are:

[0091] (1) The present invention introduces sparse matrix decomposition technology to greatly improve the efficiency of large-scale test data processing. Compared with traditional linear data processing methods, sparse matrix decomposition can effectively decompose high-dimensional test data into low-rank feature matrices and sparse error matrices, which not only retains the key performance information in the data, but also significantly reduces the computational complexity, enabling the test system to process a large amount of test data in a shorter time, thereby improving the overall test efficiency.

[0092] (2) The present invention combines generative adversarial networks to enhance the diversity and reliability of test data. Through adversarial training of the generator network and the discriminator network, it can generate virtual performance test data that is highly similar to the distribution of actual test data. The enhanced data set formed by fusing the virtual data with the actual data not only effectively covers the potential performance of the storage chip under extreme working conditions, but also improves the detection capability of rare abnormal data, thereby enhancing the comprehensiveness and accuracy of the test results.

[0093] (3) The present invention accurately identifies and locates the performance bottlenecks and abnormal behaviors of storage chips through in-depth analysis of low-rank feature matrices and sparse error matrices. It not only reveals the main performance characteristics of storage chips under various working conditions, but also effectively detects abnormal data and potential performance problems, thereby providing reliable data support for the design optimization and defect repair of storage chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0094] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0095] Figure 1 This is a flow chart of a storage chip performance testing method based on sparse matrix decomposition proposed by the present invention;

[0096] Figure 2 This is a structural schematic diagram of the sparse matrix decomposition module in the storage chip performance testing method based on sparse matrix decomposition proposed by the present invention. DETAILED DESCRIPTION

[0097] The present invention will now be described in further detail with reference to the accompanying drawings, which are simplified schematic diagrams that illustrate the basic structure of the present invention in a schematic manner.

[0098] refer to Figure 1-2 , a storage chip performance testing method based on sparse matrix decomposition, comprising the following steps:

[0099] S1. Initialize the storage chip, set the storage chip to test mode, receive and process the read and write speed, data integrity, power consumption and operation delay of the storage chip under different working conditions, and build a performance test data set;

[0100] S2. Preprocess the performance test data set, including data denoising, data normalization, data format standardization, and missing value processing;

[0101] S3. Construct the preprocessed performance test data set into a high-dimensional sparse matrix, where each row of the high-dimensional sparse matrix represents multi-dimensional performance data of different storage chip test samples, and each column represents different performance indicators of the storage chip;

[0102] S4. Performing sparse matrix decomposition on the high-dimensional sparse matrix to obtain a low-rank feature matrix and a sparse error matrix. The low-rank feature matrix is used to represent the performance characteristics of the storage chip, and the sparse error matrix is used to represent abnormal data or rare data in the performance test of the storage chip.

[0103] S5. Based on the low-rank feature matrix, a generative adversarial network is constructed, including a generator network and a discriminator network. The generator network receives the low-rank feature matrix as input and generates virtual performance test data through a neural network. The virtual performance test data is similar to the actual performance test data set in statistical distribution. The discriminator network is used to receive the virtual performance test data and the actual performance test data set and output a probability of judging whether the input is real data.

[0104] S6. Perform adversarial training on the generative adversarial network to optimize the generator network to generate virtual performance test data that is closer to the distribution of real performance test data, and optimize the discriminator network to improve the ability to distinguish between real performance test data sets and virtual performance test data;

[0105] S7. Fusing the virtual performance test data generated by the generative adversarial network with the real performance test dataset to form an enhanced performance test dataset, including potential performance patterns and data under extreme test conditions;

[0106] S8. Perform sparse matrix decomposition again on the enhanced performance test dataset to extract a new low-rank feature matrix and a sparse error matrix. The new low-rank feature matrix is used to represent the optimized storage chip performance characteristics, and the sparse error matrix is used to represent abnormal performance data and potential performance issues.

[0107] S9. Based on the new low-rank feature matrix and sparse error matrix, the performance of the storage chip is evaluated to identify and locate the performance bottlenecks, abnormal behaviors and potential problems of the storage chip.

[0108] In this embodiment, S1 includes the following steps:

[0109] S11, initializing the storage chip under different working conditions and setting it to a test mode, the working conditions including different voltage levels, temperature ranges and operating frequencies;

[0110] S12. Under each working condition, perform read and write operations and record the read and write speed R of each operation. i , where i is the test sample number;

[0111] S13. Monitor data integrity while performing read and write operations. i ,Data integrity is expressed by comparing the bit error rate of the original data with the read data;

[0112] S14. Record the power consumption P under each working condition i , power consumption is measured by measuring the current I consumed by the storage chip during read and write operations i and voltage V i Calculated;

[0113] S15. Measure and record the operation delay L of the storage chip under different working conditions i ,The operation delay is the time required from sending the read or write instruction to the completion of the operation;

[0114] S16, the reading and writing speed R of each test sample under different working conditions i , data integrity D i , power consumption P i and operation delay L i Combine and construct the performance test dataset T:

[0115]

[0116] Where n is the number of test samples, each row represents the multi-dimensional performance data of a test sample, and each column represents a performance indicator of the storage chip under different working conditions.

[0117] In this embodiment, S3 includes the following steps:

[0118] S31, standardizing each data in the pre-processed performance test data set T to obtain a standardized performance test data set T';

[0119] S32. Construct the standardized performance test data set T' into a high-dimensional sparse matrix M. Each row of the matrix M represents the multi-dimensional performance data of different storage chip test samples, and each column represents different performance indicators of the storage chip:

[0120]

[0121] Among them, R′ i , D′ i , P′ i and L′ i They represent the normalized read and write speed, normalized data integrity, normalized power consumption, and normalized operation delay of the i-th test sample, respectively, and n is the number of test samples;

[0122] S33. Perform sparsity analysis on the constructed high-dimensional sparse matrix M, identify and retain the sparse features in the matrix that have an impact on the performance of the storage chip, filter out redundant features and features that are irrelevant to the performance of the storage chip, and obtain the optimized high-dimensional sparse matrix M. opt .

[0123] In this embodiment, S4 includes the following steps:

[0124] S41, the optimized high-dimensional sparse matrix M opt Perform matrix decomposition to decompose the high-dimensional sparse matrix into a low-rank feature matrix L1 and a sparse error matrix S1, so that M opt =L1+S1, where the low-rank feature matrix L1 represents the performance characteristics of the storage chip under various working conditions, and the sparse error matrix S1 represents abnormal data or rare data that appears during the test;

[0125] S42. Define the objective function based on the storage chip performance test. Considering the characteristics of the test data, the objective function is in the form of:

[0126]

[0127] where ‖L1‖ *represents the nuclear norm of the low-rank feature matrix L1, which is used to ensure the extraction of the main performance characteristics of the storage chip. ‖S1‖1 represents the l1 norm of the sparse error matrix S1, which is used to ensure the sparsity of the detected abnormal data. is the weighted l2 norm of the sparse error matrix S1, the weight matrix W is used to adjust the detection sensitivity of abnormal data, λ1 and λ2 are regularization parameters, which adjust the balance between the low-rank feature matrix and the sparse error matrix;

[0128] S43, use the alternating direction multiplier method for iterative optimization, in the k+1th iteration, update the low-rank feature matrix

[0129]

[0130] in, is the Lagrange multiplier, μ1 is the penalty parameter, ‖·‖ F Represents the Frobenius norm, which is used to measure the difference between matrices;

[0131] In the k+1th iteration, the sparse error matrix is updated

[0132]

[0133] Update the Lagrange multiplier Y1:

[0134]

[0135] Check the iterative convergence conditions when When it is less than the set threshold, the iteration is stopped and the final low-rank feature matrix L1 and sparse error matrix S1 are obtained.

[0136] In this embodiment, S5 includes the following steps:

[0137] S51. Construct a generative adversarial network based on the low-rank feature matrix L1, including a generator network G and a discriminator network D.

[0138] S52, the generator network G receives the low-rank feature matrix L1 as input, and the input vector z of the generator network i Defined as:

[0139] z i =f(L1,W G ,b G )+∈ i ;

[0140] Among them, f(L1,W G ,b G ) represents the mapping function from the low-rank feature matrix L1 to the input space of the generator network, WG and b G are the weight matrix and bias vector of the generator network, ∈ i is a random noise vector, which is used to simulate the random disturbance effect of the storage chip under different working conditions;

[0141] S53, the generator network generates virtual performance test data through the neural network structure Simulate the various performances of memory chips under different operating conditions:

[0142]

[0143] Where h(L1) represents the intermediate feature representation after processing by the nonlinear activation function, and σ(·) is the output activation function of the generator network, which is used to generate virtual performance test data with a statistical distribution similar to the real performance test data.

[0144] S54, the discriminator network D receives virtual performance test data and actual performance test data T real As input, the discrimination result of the discriminator network is defined as:

[0145]

[0146] Where x represents the input data (i.e. or T real , W D and b D are the weight matrix and bias vector of the discriminator network, α D is the adjustment coefficient of the discriminator, which controls the output sensitivity of the discriminator network;

[0147] S55. Define the objective function of the generative adversarial network to optimize the performance of the generator and discriminator networks:

[0148]

[0149] Among them, p data (T) represents the distribution of real performance test data, p z (z) represents the noise distribution of the generator input, It is the difference measure between the generated data and the low-rank feature matrix. By introducing the difference measure, the generated data is kept consistent with the performance characteristics of the actual storage chip. λ is a regularization parameter used to adjust the balance between the authenticity of the generated data and the consistency of the features.

[0150] S56, through iterative training of the generative adversarial network, the virtual performance test data generated by the generator network G Compared with the actual performance test data Treal The distribution is gradually approaching.

[0151] In this embodiment, S7 includes the following steps:

[0152] S71, the virtual performance test data generated by the generative adversarial network G Compared with the real performance test dataset T real Perform preprocessing to standardize and normalize the data structures of both;

[0153] S72. Define the objective function of the fusion operation:

[0154]

[0155] Among them, T enhanced is the enhanced performance test data set, α is the weight parameter, which controls the ratio of real performance test data and virtual performance test data in the fusion process. is the virtual performance test data, T real For real performance test data;

[0156] S73. Based on the performance of the storage chip under extreme test conditions, adjust the weight parameter α to increase the proportion of data under extreme conditions in the enhanced data set.

[0157] In this embodiment, S8 includes the following steps:

[0158] S81, the enhanced performance test data set T enhanced Perform standardization to obtain the standardized enhanced performance test data set T′ enhanced ;

[0159] S82. Test the standardized enhanced performance data set T′ enhanced Construct an enhanced high-dimensional sparse matrix M enhanced ,Each row of the enhanced high-dimensional sparse matrix represents the enhanced performance data of different storage chips under different test conditions, and each column represents a different performance indicator;

[0160] S83, enhance the high-dimensional sparse matrix M enhanced Perform sparse matrix decomposition and decompose it into enhanced low-rank feature matrix L2 and enhanced sparse error matrix S2, so that M enhanced =L2+S2;

[0161] S84, the enhanced low-rank feature matrix L2 represents the main performance characteristics of the optimized storage chip, and the enhanced sparse error matrix S2 represents abnormal performance data and potential performance problems;

[0162] S85. Use the optimization method of S4 to iteratively optimize, and finally obtain the enhanced low-rank feature matrix L2 and the enhanced sparse error matrix S2.

[0163] In this embodiment, S9 includes the following steps:

[0164] S91. Based on the enhanced low-rank feature matrix L2 and the enhanced sparse error matrix S2, a storage chip performance evaluation model P is established. eval :

[0165]

[0166] Among them, K represents the total number of different working conditions of the storage chip, n k represents the number of test samples under each working condition, m is the performance index number of the storage chip, w kij is the weight of the jth performance indicator of the i-th test sample of the storage chip under working condition k, α k is an adjustment parameter used to control the mutual influence between the low-rank feature matrix and the sparse error matrix under different working conditions. γ and η are regularization parameters that control the contribution ratio of different items in the evaluation results.

[0167] S92, in the storage chip performance evaluation model P eval , identify the performance bottleneck of storage chips:

[0168]

[0169] Among them, B bottleneck Indicates the dimension where the performance bottleneck is located, λ k It is a regulation factor related to the working condition k, which is used to adjust the relative contributions of the low-rank feature matrix and the sparse error matrix;

[0170] S93. Based on the enhanced sparse error matrix S2, locate abnormal behaviors and potential problems of the storage chip:

[0171]

[0172] Among them, A anomaly is a collection of abnormal behaviors, and are the mean and standard deviation of the elements in the i-th row and j-th column of the sparse error matrix S2, ∈ is a small constant to prevent the denominator from being zero, and θ is a threshold parameter used to determine when to mark a data point as an anomaly;

[0173] S94. Generate a storage chip performance evaluation report, which includes the results of locating performance bottlenecks, identifying abnormal behaviors, and optimization suggestions for potential problems.

[0174] A storage chip performance testing device based on sparse matrix decomposition includes the following modules:

[0175] Data acquisition module, which acquires and pre-processes the performance test data of the storage chip under different working conditions, and collects and stores the test data in real time;

[0176] The matrix construction module is used to construct a high-dimensional sparse matrix based on the preprocessed performance test data set and automatically generate the corresponding sparse matrix based on the data formatting results;

[0177] Sparse matrix decomposition module, which generates low-rank feature matrix and sparse error matrix. The decomposition module includes sparsity analysis unit, decomposition algorithm unit and optimization unit;

[0178] Generate adversarial network module, which generates virtual performance test data and integrates it with real data. It includes generator network unit, discriminator network unit and adversarial training unit, and automatically adjusts network parameters to generate virtual data.

[0179] Performance evaluation module, which identifies and locates performance bottlenecks and abnormal behaviors, and generates performance reports based on the evaluation results;

[0180] The system control module is used to coordinate the work of each module, manage the test process and store the test results.

[0181] Example 1:

[0182] In this embodiment, an actual storage chip performance test scenario is described. The scenario takes place in a high-performance server memory module test in July 2023. The goal of this test is to evaluate the performance of a batch of new DDR5 DRAM chips under extreme working conditions.

[0183] The test was conducted at a semiconductor research and development center in City A. The testing team selected 3,000 DDR5 chips and set different test conditions, including four temperatures (25°C, 60°C, 85°C, 100°C), three operating voltages (1.1V, 1.3V, 1.5V) and three operating frequencies (3200MHz, 3600MHz, 4000MHz). A total of 36 test combinations were formed, and the number of test samples in each test combination was no less than 500.

[0184] First, at 8:00 am on July 3, 2023, the test team started the data acquisition module, placed all 3000 DDR5 chips on the test platform, performed initialization operations in sequence, and started data acquisition. The test platform recorded the performance indicators of each chip such as read and write speed, data integrity, power consumption and latency under different temperature, voltage and frequency combinations. In the embodiment, in the sample with the test number "Test-1254", the test platform recorded its read and write speed of 5600MB / s at a high temperature of 85°C, a voltage of 1.3V and a frequency of 4000MHz, a power consumption of 1.8W, and a data integrity BER of 1.2×10 -6 , the delay is 85ns.

[0185] Over the next few hours, the system continued to collect data. By 5:00 PM on July 3rd, preliminary data collection for all test samples was complete, generating a preliminary performance test dataset containing 100,000 records. The dataset was then subjected to a preprocessing module for denoising, normalization, data format standardization, and missing value handling. In the example, during preprocessing, the data for test number "Test-1347" exhibited some abnormal fluctuations. The system filtered the data, removed high-frequency noise, and supplemented some missing data, stabilizing the sample's read and write speed from the original 5560MB / s to 5590MB / s.

[0186] After data preprocessing is completed, the system automatically constructs the processed data set into a high-dimensional sparse matrix. In the embodiment, the sample with the test number "Test-1876" is represented in the matrix as follows: each sample is represented as a row of a multi-dimensional sparse matrix. Then, the sparse matrix decomposition module performs a robust principal component analysis decomposition on the matrix to generate a low-rank feature matrix and a sparse error matrix. In the "Test-1876" sample, the main features extracted from the low-rank feature matrix show that there are certain abnormalities in the power consumption and delay characteristics of the sample under high temperature and high frequency conditions, and the outliers in the sparse error matrix indicate that the data integrity of the sample under high temperature conditions has decreased.

[0187] To more comprehensively evaluate the chip's performance, the system uses a generative adversarial network module to generate virtual performance test data through a generator network. In the test number "Test-2048," the generative adversarial network generated virtual performance data at 100°C, 1.5V, and 4000MHz, showing a possible read and write speed of 5500MB / s and a power consumption of 2.2W. The virtual data is very close to the actual test data. Subsequently, the system fuses the virtual data with the actual data to form an enhanced performance test data set. After this process, the system performs sparse matrix decomposition on the enhanced data set again to extract a new low-rank feature matrix and sparse error matrix.

[0188] After this series of operations, the system evaluated the performance of the chip. In the embodiment, in the chip with test number "Test-2233", the system found through the performance evaluation module that the chip power consumption under the conditions of 85°C, 1.5V, and 4000MHz was significantly higher than that under other conditions, reaching 2.5W, and the delay increased to 95ns, indicating that the chip had a performance bottleneck under these conditions. The analysis of the sparse error matrix also revealed obvious abnormal data under certain test conditions. In the test number "Test-2567", the system detected that the data integrity BER of the chip under the conditions of 100°C and 1.3V soared to 3.5×10 -6 , suggesting potential stability issues under extreme conditions.

[0189] To demonstrate the effectiveness of our method, the testing team compared the performance of traditional methods and our method when processing the same data set. The following are the specific comparison data:

[0190] Data processing efficiency: The traditional method takes 18 hours to process 100,000 test records from 3,000 chips, of which 6 hours are for data preprocessing and 12 hours for data analysis. The method of the present invention takes only 7 hours to process the same amount of data, of which 3 hours is for data preprocessing and 4 hours is for sparse matrix decomposition and generative adversarial network training.

[0191] Accuracy of test results: Traditional methods: Under extreme conditions, only 2% of samples were identified as having performance bottlenecks, and some abnormal data could not be effectively detected. The method of the present invention: Under the same conditions, 7% of samples were identified as having obvious performance bottlenecks, and 4% of samples were detected as having potential abnormalities under high temperature and high frequency conditions.

[0192] Abnormal data detection capability: Traditional methods detected less than 0.8% of abnormal data, and the explanation of abnormal behavior was relatively vague. The method of the present invention detected 3.2% of abnormal data and clarified the specific manifestations and occurrence conditions of abnormal behavior through analysis of the sparse error matrix.

[0193] Data enhancement effect: Traditional methods: The generated virtual data is unstable under extreme conditions, and the distribution coverage is only 70%. The method of the present invention: The data enhanced by generating adversarial networks covers more extreme working conditions, and the distribution similarity between the generated data and the actual test data reaches 98%.

[0194] Through the application of the method of the present invention, the testing team significantly shortened the testing cycle, improved the efficiency of data processing and the accuracy of the results. In the final test report on July 10, 2023, the system generated detailed performance evaluation results, which helped the R&D team quickly locate and solve the performance bottleneck problems of multiple chips under high temperature and high frequency conditions, providing reliable data support for subsequent product optimization and large-scale production.

[0195] The present invention introduces sparse matrix decomposition technology to greatly improve the efficiency of large-scale test data processing. Compared with traditional linear data processing methods, sparse matrix decomposition can effectively decompose high-dimensional test data into low-rank feature matrices and sparse error matrices, which not only retains the key performance information in the data, but also significantly reduces the computational complexity, enabling the test system to process a large amount of test data in a shorter time, thereby improving overall test efficiency.

[0196] The present invention combines generative adversarial networks to enhance the diversity and reliability of test data. Through adversarial training of the generator network and the discriminator network, it can generate virtual performance test data that is highly similar to the distribution of actual test data. The enhanced data set formed by fusing the virtual data with the actual data not only effectively covers the potential performance of the storage chip under extreme working conditions, but also improves the detection capability of rare abnormal data, thereby enhancing the comprehensiveness and accuracy of the test results.

[0197] Through in-depth analysis of low-rank feature matrices and sparse error matrices, the present invention accurately identifies and locates the performance bottlenecks and abnormal behaviors of storage chips. It not only reveals the main performance characteristics of storage chips under various working conditions, but also effectively detects abnormal data and potential performance problems, thereby providing reliable data support for design optimization and defect repair of storage chips.

[0198] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the technical field, within the technical scope disclosed by the present invention, who makes equivalent replacements or changes based on the technical solution and inventive concept of the present invention, should be covered by the scope of protection of the present invention.

Claims

1. A storage chip performance testing method based on sparse matrix decomposition, characterized in that: The steps include: S1. Initialize the storage chip, set the storage chip to test mode, receive and process the read and write speed, data integrity, power consumption and operation delay of the storage chip under different working conditions, and build a performance test data set; S2. Preprocessing the performance test data set, including data denoising, data normalization, data format standardization, and missing value processing; S3. Construct the preprocessed performance test data set into a high-dimensional sparse matrix, where each row of the high-dimensional sparse matrix represents multi-dimensional performance data of different storage chip test samples, and each column represents different performance indicators of the storage chip; S4. Performing sparse matrix decomposition on the high-dimensional sparse matrix to obtain a low-rank feature matrix and a sparse error matrix, wherein the low-rank feature matrix is used to represent performance characteristics of the storage chip, and the sparse error matrix is used to represent abnormal data or rare data in the performance test of the storage chip; S5. Based on the low-rank feature matrix, a generative adversarial network is constructed, including a generator network and a discriminator network. The generator network receives the low-rank feature matrix as input and generates virtual performance test data through a neural network. The virtual performance test data is similar to the actual performance test data set in statistical distribution. The discriminator network is used to receive the virtual performance test data and the actual performance test data set and output a probability of judging whether the input is real data. S6. Perform adversarial training on the generative adversarial network to optimize the generator network and the discriminator network; S7. Fusing the virtual performance test data generated by the generative adversarial network with the real performance test dataset to form an enhanced performance test dataset, including potential performance patterns and data under extreme test conditions; S8. Perform sparse matrix decomposition again on the enhanced performance test dataset to extract a new low-rank feature matrix and a sparse error matrix. The new low-rank feature matrix is used to represent the optimized storage chip performance characteristics, and the sparse error matrix is used to represent abnormal performance data and potential performance issues. S9. Evaluate the performance of storage chips based on the new low-rank feature matrix and sparse error matrix to identify and locate performance bottlenecks, abnormal behaviors, and potential problems of storage chips. The S9 comprises the following steps: S91. Based on the enhanced low-rank feature matrix L2 and the enhanced sparse error matrix S2, a storage chip performance evaluation model P is established. eval : Among them, K represents the total number of different working conditions of the storage chip, n k represents the number of test samples under each working condition, m is the performance index number of the storage chip, w kij is the weight of the jth performance indicator of the i-th test sample of the storage chip under working condition k, α k is an adjustment parameter used to control the mutual influence between the low-rank feature matrix and the sparse error matrix under different working conditions. γ and η are regularization parameters that control the contribution ratio of different items in the evaluation results. S92, in the storage chip performance evaluation model P eval , identify the performance bottleneck of storage chips: Among them, B bottleneck Indicates the dimension where the performance bottleneck is located, λ k It is a regulation factor related to the working condition k, which is used to adjust the relative contributions of the low-rank feature matrix and the sparse error matrix; S93. Based on the enhanced sparse error matrix S2, locate abnormal behaviors and potential problems of the storage chip: Among them, A anomaly is a collection of abnormal behaviors, and are the mean and standard deviation of the elements in the i-th row and j-th column of the sparse error matrix S2, ∈ is a small constant to prevent the denominator from being zero, and θ is a threshold parameter used to determine when to mark a data point as an anomaly; S94. Generate a storage chip performance evaluation report, which includes the results of locating performance bottlenecks, identifying abnormal behaviors, and optimization suggestions for potential problems.

2. The storage chip performance testing method based on sparse matrix decomposition according to claim 1, characterized in that: Said S1 comprises the following steps: S11, initializing the storage chip under different working conditions and setting it to a test mode, the working conditions including different voltage levels, temperature ranges and operating frequencies; S12. Under each working condition, perform read and write operations and record the read and write speed R of each operation. i , where i is the test sample number; S13. Monitor data integrity while performing read and write operations. i ,Data integrity is expressed by comparing the bit error rate of the original data with the read data; S14. Record the power consumption P under each working condition i , power consumption is measured by measuring the current I consumed by the storage chip during read and write operations i and voltage V i Calculated; S15. Measure and record the operation delay L of the storage chip under different working conditions i ,The operation delay is the time required from sending the read or write instruction to the completion of the operation; S16, the reading and writing speed R of each test sample under different working conditions i , data integrity D i , power consumption P i and operation delay L i Combine and construct the performance test dataset T: Where n is the number of test samples, each row represents the multi-dimensional performance data of a test sample, and each column represents a performance indicator of the storage chip under different working conditions.

3. The storage chip performance testing method based on sparse matrix decomposition according to claim 1, characterized in that: The S3 includes the following steps: S31, standardizing each data in the pre-processed performance test data set T to obtain a standardized performance test data set T'; S32. Construct the standardized performance test data set T' into a high-dimensional sparse matrix M. Each row of the matrix M represents the multi-dimensional performance data of different storage chip test samples, and each column represents different performance indicators of the storage chip: Among them, R′ i , D′ i , P′ i and L′ i They represent the normalized read and write speed, normalized data integrity, normalized power consumption, and normalized operation delay of the i-th test sample, respectively, and n is the number of test samples; S33. Perform sparsity analysis on the constructed high-dimensional sparse matrix M, identify and retain the sparse features in the matrix that have an impact on the performance of the storage chip, filter out redundant features and features that are irrelevant to the performance of the storage chip, and obtain the optimized high-dimensional sparse matrix M. opt .

4. The storage chip performance testing method based on sparse matrix decomposition according to claim 1, characterized in that: The S4 comprises the following steps: S41, the optimized high-dimensional sparse matrix M opt Perform matrix decomposition to decompose the high-dimensional sparse matrix into a low-rank feature matrix L1 and a sparse error matrix S1, so that M opt =L1+S1, where the low-rank feature matrix L1 represents the performance characteristics of the storage chip under various working conditions, and the sparse error matrix S1 represents abnormal data or rare data that appears during the test; S42. Define the objective function based on the storage chip performance test. Considering the characteristics of the test data, the objective function is in the form of: where ||L1|| * represents the nuclear norm of the low-rank feature matrix L1, which is used to ensure the extraction of the main performance characteristics of the storage chip. ||S1||1 represents the l1 norm of the sparse error matrix S1, which is used to ensure the sparsity of the detected abnormal data. is the weighted l2 norm of the sparse error matrix S1, the weight matrix W is used to adjust the detection sensitivity of abnormal data, λ1 and λ2 are regularization parameters, which adjust the balance between the low-rank feature matrix and the sparse error matrix; S43, use the alternating direction multiplier method for iterative optimization, in the k+1th iteration, update the low-rank feature matrix in, is the Lagrange multiplier, μ1 is the penalty parameter, ||·|| F Represents the Frobenius norm, which is used to measure the difference between matrices; In the k+1th iteration, the sparse error matrix is updated Update the Lagrange multiplier Y1: Check the iterative convergence conditions when When it is less than the set threshold, the iteration is stopped and the final low-rank feature matrix L1 and sparse error matrix S1 are obtained.

5. The storage chip performance testing method based on sparse matrix decomposition according to claim 1, characterized in that: The S5 comprises the following steps: S51. Construct a generative adversarial network based on the low-rank feature matrix L1, including a generator network G and a discriminator network D. S52, the generator network G receives the low-rank feature matrix L1 as input, and the input vector z of the generator network i Defined as: z i =f(L1,W G ,b G )+∈ i ; Among them, f(L1,W G ,b G ) represents the mapping function from the low-rank feature matrix L1 to the input space of the generator network, W G and b G are the weight matrix and bias vector of the generator network, ∈ i is a random noise vector, which is used to simulate the random disturbance effect of the storage chip under different working conditions; S53, the generator network generates virtual performance test data through the neural network structure Simulate the various performances of memory chips under different operating conditions: Where h(L1) represents the intermediate feature representation after processing by the nonlinear activation function, and σ(·) is the output activation function of the generator network, which is used to generate virtual performance test data with a statistical distribution similar to the real performance test data. S54, the discriminator network D receives virtual performance test data and actual performance test data T real As input, the discrimination result of the discriminator network is defined as: Where x represents the input data (i.e. or T real , W D and b D are the weight matrix and bias vector of the discriminator network, α D is the adjustment coefficient of the discriminator, which controls the output sensitivity of the discriminator network; S55. Define the objective function of the generative adversarial network to optimize the performance of the generator and discriminator networks: Among them, p data (T) represents the distribution of real performance test data, p z (z) represents the noise distribution of the generator input, It is the difference measure between the generated data and the low-rank feature matrix. By introducing the difference measure, the generated data is kept consistent with the performance characteristics of the actual storage chip. λ is a regularization parameter used to adjust the balance between the authenticity of the generated data and the consistency of the features. S56, through iterative training of the generative adversarial network, the virtual performance test data generated by the generator network G Compared with the actual performance test data T real The distribution is gradually approaching.

6. The method for testing storage chip performance based on sparse matrix decomposition according to claim 1, characterized in that: The S7 comprises the following steps: S71, the virtual performance test data generated by the generative adversarial network G Compared with the real performance test dataset T real Perform preprocessing to standardize and normalize the data structures of both; S72. Define the objective function of the fusion operation: Among them, T enhanced is the enhanced performance test data set, α is the weight parameter, which controls the ratio of real performance test data and virtual performance test data in the fusion process. is the virtual performance test data, T real For real performance test data; S73. Based on the performance of the storage chip under extreme test conditions, adjust the weight parameter α to increase the proportion of data under extreme conditions in the enhanced data set.

7. The method for testing storage chip performance based on sparse matrix decomposition according to claim 1, characterized in that: The S8 comprises the following steps: S81, the enhanced performance test data set T enhanced Perform standardization to obtain the standardized enhanced performance test data set T′ enhanced ; S82. Test the standardized enhanced performance data set T′ enhanced Construct an enhanced high-dimensional sparse matrix M enhanced ,Each row of the enhanced high-dimensional sparse matrix represents the enhanced performance data of different storage chips under different test conditions, and each column represents a different performance indicator; S83, enhance the high-dimensional sparse matrix M enhanced Perform sparse matrix decomposition and decompose it into enhanced low-rank feature matrix L2 and enhanced sparse error matrix S2, so that M enhanced =L2+S2; S84, the enhanced low-rank feature matrix L2 represents the main performance characteristics of the optimized storage chip, and the enhanced sparse error matrix S2 represents abnormal performance data and potential performance problems; S85. Use the optimization method of S4 to iteratively optimize, and finally obtain the enhanced low-rank feature matrix L2 and the enhanced sparse error matrix S2.

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