Error correction method, memory system and memory controller

Abstract

Embodiments of the present application provide a memory system error correction method, a memory system and a memory controller. The error correction method comprises: obtaining corresponding first soft data according to first hard read data and buffered second hard read data after hard decision decoding of the first hard read data fails; the first hard read data is read by the memory system according to a first hard read voltage; the second hard read data is read by the memory system according to a second hard read voltage before the first hard read data is read; performing first soft decision decoding according to the first soft data and the first hard read data, or performing first soft decision decoding according to the first soft data and the second hard read data; the first hard read voltage is one of a plurality of re-read voltages corresponding to a read command; and the second hard read voltage is an initial read voltage or a re-read voltage other than the first hard read voltage in the plurality of re-read voltages.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to an error correction method for a memory system, a memory system, and a memory controller. Background Technology

[0002] With the development of storage technology, 3D NAND flash memory has evolved from single-level cells (SLC) capable of storing 1 bit of information, to double-level cells (DLC) capable of storing 2 bits of information, to triple-level cells (TLC) capable of storing 3 bits of information, and even quadruple-level cells (QLC) capable of storing 4 bits of information; the number of stacked layers is also increasing. Faced with memory devices with increasingly more layers and storage bits, low-density parity code (LDPC) is typically used for error correction during data retrieval to enhance the reliability of the stored data. However, as the structure of 3D NAND flash becomes more complex and it stores more data, the types of errors it contains become increasingly complex. Using current error correction methods results in slow error correction speeds, reduced efficiency, and a significant impact on read speeds. Summary of the Invention

[0003] In view of this, embodiments of this application provide an error correction method, a memory system, and a memory controller for a memory system, which can improve the error correction rate.

[0004] In a first aspect, embodiments of this application provide an error correction method for a memory system, the method comprising:

[0005] After a hard-decision decoding of the first hard read data fails, the corresponding first soft data is obtained based on the first hard read data and the cached second hard read data; wherein, the first hard read data is read by the memory system according to the first hard read voltage; and the second hard read data is read by the memory system according to the second hard read voltage before reading the first hard read data;

[0006] Perform a first soft decision decoding based on the first soft data and the first hard read data, or perform a first soft decision decoding based on the first soft data and the second hard read data;

[0007] Wherein, the first hard read voltage is one of a plurality of reread voltages having a certain offset from the initial read voltage; the second hard read voltage is the initial read voltage or a reread voltage other than the first hard read voltage among the plurality of reread voltages.

[0008] In the above scheme, the method further includes:

[0009] Cache the first hard read data;

[0010] After the first soft decision decoding fails, the third hard read data is read according to the third hard read voltage; and the hard decision decoding is performed on the third hard read data.

[0011] After the hard decision decoding of the third hard read data fails, the corresponding second soft data is obtained based on the cached first hard read data and the third hard read data.

[0012] The first soft decision decoding is performed based on the second soft data and the first hard read data, or the first soft decision decoding is performed based on the second soft data and the third hard read data;

[0013] The third hard read voltage is one of the plurality of reread voltages other than the first hard read voltage and the second hard read voltage.

[0014] In the above scheme, the method further includes: ending the first stage of error correction code (ECC) error correction when one of the following occurs: the hard decision decoding is successful, the first soft decision decoding is successful, or the number of hard read retries reaches a first set threshold.

[0015] In the above scheme, obtaining the corresponding first soft data based on the first hard read data and the cached second hard read data includes: performing an XOR operation on the first hard read data and the second hard read data to obtain the first soft data.

[0016] In the above scheme, the method further includes:

[0017] The selection is based on a first number of error bits in the first hard read data and a second number of error bits in the second hard read data, choosing between performing a first soft decision decoding based on the first soft data and the first hard read data, or performing a first soft decision decoding based on the first soft data and the second hard read data.

[0018] In the above scheme, the number of error bits contained in the hard read data is measured by a comprehensive weight value, and the larger the comprehensive weight value, the more error bits the hard read data contains; the step of selecting whether to perform the first soft decision decoding based on the first soft data and the first hard read data, or based on the first soft data and the second hard read data, according to the first number of error bits contained in the first hard read data and the second number of error bits contained in the second hard read data, includes:

[0019] Obtain the first comprehensive weight value corresponding to the first hard read data;

[0020] Obtain the second comprehensive weight value corresponding to the second hard read data;

[0021] Compare the first comprehensive weight value corresponding to the first hard read data with the second comprehensive weight value corresponding to the second hard read data;

[0022] When the comparison result includes the first comprehensive weight being less than the second comprehensive weight, a first soft decision decoding is performed based on the first soft data and the first hard read data;

[0023] When the comparison result includes the first comprehensive weight being greater than the second comprehensive weight, a first soft decision decoding is performed based on the first soft data and the second hard read data;

[0024] When the comparison result includes the first comprehensive weight being equal to the second comprehensive weight, a first soft decision decoding is performed based on the first soft data and the first hard read data, or a first soft decision decoding is performed based on the first soft data and the second hard read data.

[0025] In the above scheme, the method further includes:

[0026] After performing a first soft decision decoding based on the first soft data and the first hard read data, or after performing a first soft decision decoding based on the first soft data and the second hard read data, the cached second hard read data is deleted.

[0027] After performing the first soft decision decoding based on the second soft data and the first hard read data, or after performing the first soft decision decoding based on the second soft data and the third hard read data, the cached first hard read data is deleted.

[0028] In the above scheme, the method further includes:

[0029] If the first stage of ECC error correction fails, the second stage of ECC error correction is performed, wherein...

[0030] The second phase of ECC error correction includes performing at least one second soft-decision decoding.

[0031] In the above scheme, the method further includes:

[0032] A set of soft read voltages is determined; the set of soft read voltages includes an optimal read voltage and multiple soft reread voltages that have a certain offset relative to the optimal read voltage;

[0033] The fourth hard read data and the third soft data are read according to the soft read voltage in the set of soft read voltages; and the second soft decision decoding is performed according to the fourth hard read data and the third soft data;

[0034] In the event of one of the following: the second soft decision decoding is successful, or the number of soft read retries reaches the second set threshold, the second stage of ECC error correction ends.

[0035] In the above scheme, the method further includes:

[0036] After the ECC error correction in the second stage fails, the third stage of independent NAND redundant array RAIN error correction is performed.

[0037] In the above scheme, the method further includes:

[0038] After the RAIN error correction fails in the third stage, an indication message is output to characterize the error correction failure.

[0039] In the above scheme, the method further includes:

[0040] When one of the following occurs: the first stage of ECC error correction is successful, the second stage of ECC error correction is successful, or the third stage of RAIN error correction is successful, the read data that has been successfully corrected is output.

[0041] In the above scheme, the voltage interval between each read voltage in the set of soft read voltages is the same as the voltage interval between the hard read voltages in the set of hard read voltages used to perform the hard decision decoding, wherein the set of hard read voltages includes the initial read voltage and the plurality of reread voltages.

[0042] Secondly, embodiments of this application also provide a memory system, including: a memory device for storing data;

[0043] A memory controller, coupled to the memory device, is configured to: after a hard-decision decoding of first hard-read data fails, obtain corresponding first soft data based on the first hard-read data and cached second hard-read data; wherein the first hard-read data is read by the memory system according to a first hard-read voltage; and the second hard-read data is read by the memory system according to a second hard-read voltage before reading the first hard-read data;

[0044] Perform a first soft decision decoding based on the first soft data and the first hard read data, or perform a first soft decision decoding based on the first soft data and the second hard read data;

[0045] Wherein, the first hard read voltage is one of a plurality of reread voltages having a certain offset from the initial read voltage; the second hard read voltage is the initial read voltage or a reread voltage other than the first hard read voltage among the plurality of reread voltages.

[0046] In the above scheme, the memory controller includes: a processor, memory, a hardware decoder, and a software decoder, wherein;

[0047] The processor is configured to: read the first hard read data from the memory device according to the first hard read voltage; read the second hard read data according to the second hard read voltage before reading the first hard read data; and cache the second hard read data in the memory;

[0048] The hard decoder is used to: perform the hard decision decoding on the first hard read data;

[0049] The processor is further configured to: after the hard decision decoding of the first hard read data fails, obtain corresponding first soft data based on the first hard read data and the cached second hard read data; send the first hard read data or the second hard read data to the soft decoder; and send the first soft data to the soft decoder.

[0050] The soft decoder is configured to: perform a first soft decision decoding based on the first soft data and the first hard read data, or perform a first soft decision decoding based on the first soft data and the second hard read data.

[0051] In the above scheme, the memory is also used to cache the first hard-read data;

[0052] The processor is further configured to: read third hard read data according to the third hard read voltage after the first soft decision decoding fails;

[0053] The hard decoder is also used to: perform the hard decision decoding on the third hard read data;

[0054] The processor is further configured to: after the hard decision decoding of the third hard read data fails, obtain the corresponding second soft data based on the cached first hard read data and the third hard read data;

[0055] The soft decoder is further configured to: perform the first soft decision decoding based on the second soft data and the first hard read data, or perform the first soft decision decoding based on the second soft data and the third hard read data.

[0056] In the above scheme, the processor is further configured to: determine whether one of the following situations occurs: the hard decision decoding is successful, the first soft decision decoding is successful, or the number of hard read retries reaches a first set threshold; if so, terminate the first stage of error correction code (ECC) error correction.

[0057] In the above scheme, the soft decoder is further configured to: perform a second stage of ECC error correction after the first stage of ECC error correction fails, wherein the second stage of ECC error correction includes: performing at least one second soft decision decoding; wherein the second stage of ECC error correction ends when one of the following occurs: the second soft decision decoding is successful or the number of soft read retries reaches a second set threshold.

[0058] In the above scheme, the memory controller further includes: a RAIN error corrector, used to: perform a third stage of independent NAND redundant array RAIN error correction after the ECC error correction in the second stage fails;

[0059] The processor is further configured to: output indication information indicating decoding failure after the RAIN error correction in the third stage fails; and output successfully decoded read data if one of the following occurs: the ECC error correction in the first stage succeeds, the ECC error correction in the second stage succeeds, or the RAIN error correction in the third stage succeeds.

[0060] Thirdly, embodiments of this application also provide a memory controller, including: a processor, memory, a hardware decoder, and a software decoder, wherein;

[0061] The processor is configured to: read first hard read data from a memory device coupled to the memory controller according to a first hard read voltage; read second hard read data from the memory device according to a second hard read voltage before reading the first hard read data; and cache the second hard read data in the memory.

[0062] The hard decoder is used to: perform hard decision decoding on the first hard read data;

[0063] The processor is further configured to: after the hard decision decoding of the first hard read data fails, obtain corresponding first soft data based on the first hard read data and the cached second hard read data; send the first hard read data or the second hard read data to the soft decoder; and send the first soft data to the soft decoder.

[0064] The soft decoder is configured to: perform a first soft decision decoding based on the first soft data and the first hard read data, or perform a first soft decision decoding based on the first soft data and the second hard read data;

[0065] The processor is further configured to: determine whether one of the following conditions occurs: the hard decision decoding is successful, the first soft decision decoding is successful, or the number of hard read retries reaches a first preset threshold; if any of these conditions occur, terminate the first stage of error correction code (ECC) error correction.

[0066] Wherein, the first hard read voltage is one of a plurality of reread voltages having a certain offset from the initial read voltage; the second hard read voltage is the initial read voltage or a reread voltage other than the first hard read voltage among the plurality of reread voltages.

[0067] This application provides an error correction method, a memory system, and a memory controller for a memory system. The error correction method includes: after a hard-decision decoding of first hard-read data fails, obtaining corresponding first soft data based on the first hard-read data and cached second hard-read data; wherein the first hard-read data is read by the memory system according to a first hard-read voltage; the second hard-read data is read by the memory system according to a second hard-read voltage before reading the first hard-read data; performing first soft-decision decoding based on the first soft data and the first hard-read data, or performing first soft-decision decoding based on the first soft data and the second hard-read data; wherein the first hard-read voltage is one of a plurality of reread voltages having a certain offset from the initial read voltage; the second hard-read voltage is the initial read voltage or a reread voltage other than the first hard-read voltage among the plurality of reread voltages. The error correction method provided in this application, when performing a read operation on the memory system, adds a first soft-decision decoding after a hard-decision decoding failure during rereading, thereby utilizing the high error correction capability of soft-decision decoding to improve the error correction speed and thus improve the read speed. Attached Figure Description

[0068] In accompanying drawings that are not necessarily drawn to scale, the same reference numerals can describe similar components in different views. The same numbers with different letter suffixes can represent different instances of similar components. The accompanying drawings generally illustrate the various embodiments discussed in this document by way of example, not limitation.

[0069] Figure 1 A schematic diagram of an exemplary system with a memory system provided in an embodiment of this application;

[0070] Figure 2a A schematic diagram of an exemplary memory card with a memory system provided in an embodiment of this application;

[0071] Figure 2b A schematic diagram of an exemplary solid-state drive with a memory system provided in an embodiment of this application;

[0072] Figure 3 A schematic diagram of an exemplary memory including peripheral circuitry provided in an embodiment of this application;

[0073] Figure 4 This is a schematic diagram of the structure of memory strings, word lines, and bit lines in a memory according to an embodiment of this application;

[0074] Figure 5 A cross-sectional schematic diagram of a memory array containing NAND flash memory strings provided in an embodiment of this application;

[0075] Figure 6 A schematic diagram of an exemplary memory including a memory array and peripheral circuitry, provided for an embodiment of this application;

[0076] Figure 7 A flowchart illustrating an error correction method for a memory system provided in an embodiment of this application. Figure 1 ;

[0077] Figure 8 A schematic flowchart of an error correction method for a memory system provided in an embodiment of this application is shown in Figure 2.

[0078] Figure 9 A flowchart illustrating an error correction method for a memory system provided in an embodiment of this application. Figure 3 ;

[0079] Figure 10 An exemplary schematic diagram of soft decision decoding provided in an embodiment of this application;

[0080] Figure 11 A flowchart illustrating an error correction method for a memory system provided in an embodiment of this application. Figure 4 ;

[0081] Figure 12 A flowchart illustrating an error correction method for a memory system provided in an embodiment of this application. Figure 5

[0082] Figure 13 A schematic diagram of the ECC error correction process in the first stage of an embodiment of this application;

[0083] Figure 14 This is a schematic diagram of the structure of a memory system provided in an embodiment of this application. Detailed Implementation

[0084] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0085] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described: that is, not all features of the actual embodiments described herein, nor well-known functions and structures are described in detail.

[0086] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0087] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," "coupled to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intermediate elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intermediate elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. When discussing a second element, component, region, layer, or portion, it does not imply that the application necessarily contains a first element, component, region, layer, or portion.

[0088] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0089] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0090] In order to gain a more detailed understanding of the features and technical content of the embodiments of this application, the implementation of the embodiments of this application will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this application.

[0091] The memory devices in the embodiments of this application include, but are not limited to, three-dimensional NAND type memory. For ease of understanding, three-dimensional NAND type memory will be used as an example for explanation.

[0092] The embodiments of this application will be further described in detail below with reference to the accompanying drawings and specific examples.

[0093] Figure 1 A block diagram of an exemplary system with a memory system is shown. Figure 1 In this context, system 100 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a memory system therein. For example... Figure 1As shown, the electronic device 100 may include a host 108 and a memory system 102. The host 108 may include a processor, such as a central processing unit (CPU) or a system-on-a-chip (SoC), where the SoC may be, for example, an application processor (AP). The host 108 also includes at least one operating system (OS) that can typically manage and control the functions and operations performed within the host 108. The OS enables interoperability between the host 108 coupled to the memory system 102 and users who need and use the memory system 102. The OS may support functions and operations corresponding to user requests. For example, and not limited to, depending on whether the host 102 is a removable host, the OS may be classified as a general-purpose operating system and a mobile operating system. The general-purpose operating system may include personal operating systems and enterprise operating systems. The personal operating system may be an operating system, including Windows and Chrome, used for general purposes to support services; the enterprise operating system may be an operating system, including Windows Server, Linux, Unix, etc., specifically designed to ensure and support higher performance. The mobile operating system can refer to an operating system for services or functions related to mobility (such as power saving). Generally, a mobile operating system can be an operating system such as Android, iOS, or Windows Mobile. In some embodiments, the host 108 may include multiple OSes; correspondingly, the host 108 may run multiple operating systems associated with the memory system 102. In other embodiments, the host 108 translates a user's request into one or more commands and transmits the one or more commands to the memory system 102 so that the memory system 102 performs operations related to the one or more commands.

[0094] The memory system 102 is capable of responding to requests from the host 108, performing specific functions, or performing various internal operations. In some embodiments, the memory system 102 is capable of storing data accessed by the host 108. The memory system 102 can be used as the main memory system or auxiliary memory system of the host 108. The memory system 102 and the host 108 can be electrically connected and communicate with each other according to appropriate protocols. The memory system 102 can be implemented and packaged into different types of terminal electronic products, such as, and not limited to, solid-state drives (SSDs), multimedia cards (MMCs), embedded MMCs (eMMCs), miniature MMCs (RSMMCs), micro MMCs, secure digital cards (SDs), mini SDs, micro SDs, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, compact flash memory (CF) cards, smart media (SM) cards, and memory sticks, etc.

[0095] In some embodiments, the memory system 102 may also be configured as part of, for example, a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a network tablet, a tablet computer, a wireless telephone, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a portable game console, a navigation system, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a three-dimensional (3D) television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device configured for a data center, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices configured for a home network, one of various electronic devices configured for a computer network, one of various electronic devices configured for a telematics network, a radio frequency identification (RFID) device, or one of various components configured for a computing system.

[0096] Return as Figure 1 As shown, the memory system 102 may have one or more memory devices 104 and a memory controller 106. The memory controller 106 can respond to requests from the host 108 and control the memory devices 104. For example, the memory controller 106 can read data from the memory devices 104 and transfer the read data to the host 108; it can also receive data to be stored from the host 108 and store the data to be stored in the memory devices 104. In other words, the memory controller 106 can control the write (or programming) operations, read operations, erase operations, and background operations of the memory devices 104, etc. Furthermore, the memory system 102 can be implemented and packaged into different types of terminal electronic products. Figure 2aIn one example shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2b In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0097] The memory device 104 may include non-volatile memory, which retains stored data even when no power is supplied. The memory device 104 may also include volatile memory. The device 104 can store data provided from the host 108 via write operations; the memory device 104 can also provide the stored data to the host 108 via read operations. In embodiments of this application, the memory device 104 may include any publicly disclosed memory, such as volatile memory devices like Dynamic Random Access Memory (DRAM) and Static RAM (SRAM), or non-volatile memory devices such as Read-Only Memory (ROM), Mask ROM (MROM), Programmable ROM (PROM), Erasable Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), Ferroelectric RAM (FRAM), Phase Change RAM (PRAM), Magnetoresistive RAM (MRAM), Resistive RAM (RRAM or ReRAM), and flash memory (e.g., 3D NAND flash memory).

[0098] Figure 3 A schematic circuit diagram of an exemplary memory device 300, including peripheral circuitry, is shown according to some aspects of this disclosure. The memory device 300 may be... Figure 1An example of memory device 104 is provided. Memory device 300 may include memory array 301 and peripheral circuitry 302 coupled to memory array 301. Taking memory array 301 as an example of a three-dimensional NAND-type memory array, memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0099] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing more than one bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-bit cell (TLC), a four-bit cell (QLC), or five bits per cell (also known as a five-bit cell (PLC)). Each MLC may be programmed to take a range of possible nominal stored values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of three possible nominal storage values ​​to the cell, with a fourth nominal storage value that can be used for the erase state.

[0100] like Figure 3As shown, each NAND memory string 308 may include a lower select gate (BSG) 310 at its source end and an upper select gate (TSG) 312 at its drain end. BSG 310 and TSG 312 may be configured to activate a selected NAND memory string 308 during read and program operations. In some embodiments, the sources of NAND memory strings 308 within the same memory block 304 are coupled via a common source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 within the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 312) or a deselection voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 310) or a deselection voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0101] like Figure 3As shown, NAND memory strings 308 can be organized into multiple memory blocks 304, each of which may have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block 304, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) biased and coupled to the source line 314 of the selected memory block 304 and the unselected memory blocks 304 on the same plane as the selected memory block 304 can be used. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some implementations, each word line 318 is coupled to a page 320 of memory cell 306, which is a basic unit of data used for programming operations. The size of a page 320, in bits, can be related to the number of NAND memory strings 308 coupled by word lines 318 in a memory block 304. Each word line 318 may include multiple control gates (gate electrodes) at each memory cell 306 in the corresponding page 320, as well as gate lines coupling the control gates.

[0102] refer to Figure 3 as well as Figure 4 Each memory cell 306 in the multiple memory cells is coupled to a corresponding word line 318, and each memory string 308 is coupled to a corresponding bit line 316 through a corresponding selection transistor (such as the above selection transistor (TSG) 312).

[0103] Specifically, refer to Figure 4 The memory device may include one or more memory strings 308 (reference 308). Figure 4 As shown by the middle arrow, each memory string may include an upper selection transistor SST corresponding to the upper selection transistor gate line SSL, a ground selection transistor GST corresponding to the lower selection transistor gate line GSL, and multiple memory cells located between the upper selection transistor and the ground selection transistor. Each memory string is connected to the corresponding bit line BL and a unified common source line.

[0104] Here, for reference Figure 4The word line coupled to the selected page is called the selected word line (Sel.WL). This selected word line can be any word line among multiple word lines in the memory. The other word lines are called unselected word lines (Usel.WL) or dummy word lines (Dummy WL). The bit lines BL in the memory are divided into two parts. One part of the bit lines is connected to the memory cell in the lowest state (i.e., erase state) of the memory cell coupled to the selected word line, and is called the first bit line (BL_min). The other part of the bit lines is connected to the memory cells other than those in the lowest state (i.e., erase state) and those that have reached the target state of the memory cell coupled to the selected word line, and is called the second bit line (BL_other). In actual operation, a target memory cell among multiple memory cells can be selected by selecting the corresponding word line and bit line to perform the corresponding read and program operations.

[0105] Figure 5 A schematic cross-sectional view of an exemplary memory array 301 including NAND memory strings 308 is shown, according to some aspects of this disclosure. Figure 5 As shown, the NAND memory string 308 may include a stacked structure 510, which includes multiple gate layers 511 and multiple insulating layers 512 stacked alternately in sequence, and a memory string 308 perpendicularly penetrating the gate layers 511 and insulating layers 512. The gate layers 511 and insulating layers 512 may be stacked alternately, with adjacent gate layers 511 separated by an insulating layer 512. The number of pairs of gate layers 511 and insulating layers 512 in the stacked structure 510 can determine the number of memory cells included in the memory array 301.

[0106] The constituent materials of the gate layer 511 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 511 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 511 includes a doped polysilicon layer. Each gate layer 511 may include a control gate surrounding a memory cell. The gate layer 511 at the top of the stacked structure 510 may extend laterally as an upper select gate line 513, the gate layer 511 at the bottom of the stacked structure 510 may extend laterally as a lower select gate line 514, and the gate layer 511 extending laterally between the upper and lower select gate lines may serve as a word line layer 503.

[0107] In some embodiments, the stacked structure 510 may be disposed on the substrate 501. The substrate 501 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0108] In some embodiments, the NAND memory string 308 includes a channel structure extending vertically through the stacked structure 510. In some embodiments, the channel structure includes channel vias filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0109] Return to reference Figure 3 The peripheral circuitry 302 can be coupled to the memory array 301 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 6 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensing amplifier 604, a column decoder / bit line driver 606, a row decoder / word line driver 608, a voltage generator 610, control logic 612, a register 614, an interface 616, and a data bus 618. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 6 Additional peripheral circuitry not shown.

[0110] Page buffer / sensor amplifier 604 can be configured to read data from memory array 301 and program (write) data to memory array 301 according to control signals from control logic 612. In one example, page buffer / sensor amplifier 604 can store a page of programming data (write data) to be programmed into a page 320 of memory array 301. In another example, page buffer / sensor amplifier 604 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 604 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 606 can be configured to be controlled by control logic 612 and select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 610.

[0111] The row decoder / word line driver 608 can be configured to be controlled by control logic 612 and to select / deselect memory blocks 304 of memory array 301 and select / deselect word lines 318 of memory blocks 304. The row decoder / word line driver 608 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 610. In some embodiments, the row decoder / word line driver 608 can also select / deselect and drive BSG lines 315 and TSG lines 313. The row decoder / word line driver 608 can be configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 610 can be configured to be controlled by control logic 612 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, channel boost voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 301.

[0112] Control logic 612 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 614 can be coupled to control logic 612 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 616 can be coupled to control logic 612 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 612, as well as to buffer status information received from control logic 612 and relay it to the host. Interface 616 can also be coupled to column decoder / bitline driver 606 via data bus 618 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 301.

[0113] In 3NAND memory devices, single-cell memory (SLC) holds a certain share of the memory market due to its advantages such as fast read / write speed, high reliability, and long lifespan; while double-cell memory (MLC), triple-cell memory (TLC), and quad-cell memory (QLC) are becoming the development trend of the memory market due to their higher storage density and larger storage capacity.

[0114] However, as the number of bits in the storage cell and the number of stacking layers increase, the types of errors it contains become more and more complex. The commonly used error correction process (including: first perform hard decision error correction; if error correction fails, then perform soft decision error correction; if error correction fails, finally perform independent NAND redundant array error correction) takes a long time, which seriously affects the read speed.

[0115] Based on one or more of the above-mentioned problems, embodiments of this application provide an error correction method for a memory system. In the hard-decision error correction stage, after the hard-decision decoding fails during rereading, a first soft-decision decoding is added. In this way, the high error correction capability of soft-decision decoding is utilized to improve the error correction speed, thereby improving the read speed.

[0116] See Figure 7 , Figure 7 This is a flowchart illustrating an error correction method for a memory system provided in an embodiment of this application.

[0117] Specifically, the error correction method may include:

[0118] S701: After failing to hard-decode the first hard read data, obtain the corresponding first soft data based on the first hard read data and the cached second hard read data;

[0119] S702: Perform a first soft decision decoding based on the first soft data and the first hard read data, or perform a first soft decision decoding based on the first soft data and the second hard read data;

[0120] Wherein, the first hard read data is read by the memory system according to the first hard read voltage; the second hard read data is read by the memory system according to the second hard read voltage before reading the first hard read data;

[0121] Wherein, the first hard read voltage is one of a plurality of reread voltages having a certain offset from the initial read voltage; the second hard read voltage is the initial read voltage or a reread voltage other than the first hard read voltage among the plurality of reread voltages.

[0122] It should be noted that the memory system can be any of the memory systems described above, possessing one or more of the functions described above. The technical solution described here is that after a hard-decision decoding of the first hard-read data fails, a first soft-decision decoding is added, utilizing the high error correction capability of soft-decision decoding to accelerate the error correction speed.

[0123] Here, the first hard read data can be obtained by the memory system based on a first hard read voltage; and this first hard read voltage can be one of multiple reread voltages that have a certain offset from the initial read voltage. The initial read voltage can refer to the first voltage value used for the read operation during hard decision error correction, and this initial read voltage can be preset in the memory system based on experience. This initial read voltage can be the same as or different from the reference voltage in the Retry Read Table (RRT).

[0124] It should be noted that the RRT is a table containing multiple voltage offsets, each of which is relative to a reference voltage. These voltage offsets are implemented by the hardware circuitry within the memory, for example, by setting these voltage offsets through registers included in the memory. In other words, all read voltages are obtained by deriving the required voltage offset from this RRT table, then superimposing it on the reference voltage (including the sign of the superposition; that is, if the voltage offset is negative, the final read voltage will be less than the reference voltage) to obtain the desired voltage value, which is then applied to the corresponding word line.

[0125] In other words, during the hard decision error correction phase, the initial read voltage in a set of hard read voltages (including the initial read voltage and multiple reread voltages) can be obtained from the Reference Time Limit (RRT). When its voltage offset is 0, the initial read voltage is numerically the same as the reference voltage; when its voltage offset is not 0, the initial read voltage is numerically different from the reference voltage. Furthermore, the multiple reread voltages are a set of voltage values ​​with a certain offset from the initial read voltage. The interval between this offset and the voltage offset in the aforementioned RRT can be different or the same.

[0126] Table 1 RRT

[0127]

[0128] For example, as shown in Table 1, it represents the RRT corresponding to a TLC type memory cell provided in this application embodiment. Rd1 to Rd7 in Table 1 represent the voltage offset between different data states; each column represents a set of voltage offsets of adjacent programming states relative to the corresponding reference voltage, wherein the set of voltage offsets includes positive offsets that increase in the direction greater than the reference voltage and negative offsets that decrease in the direction less than the reference voltage. For example, for Rd7, +V1, +V2, +V3, and +V4 are positive offsets, wherein the values ​​of V1, V2, V3, and V4 increase sequentially; -V5 to -V11 are negative offsets, wherein the values ​​of V5 to V11 decrease sequentially.

[0129] Based on Table 1 above, an example is given of a set of hard read voltages used in this application embodiment. The initial read voltage included can be without offset relative to the reference voltage in the RRT table, i.e., taking Rd7 as an example. The initial read voltage has an offset of 0 relative to the reference voltage, i.e., the value corresponding to the first row in Table 1. This initial read voltage can also be offset by +V1 from the reference voltage in the RRT table; in this case, the initial read voltage is the sum of the reference voltage and V1. The other hard read voltages in this set, excluding the initial read voltage, are distributed on both sides of the initial read voltage, and the offset of each hard read voltage relative to the initial read voltage can be different from or the same as the offset in the RRT.

[0130] The first soft data required for the first soft decision decoding can be obtained based on the first hard read data and the cached second hard read data. Specifically, in some embodiments, obtaining the corresponding first soft data based on the first hard read data and the cached second hard read data may include: performing an XOR operation between the first hard read data and the second hard read data to obtain the first soft data.

[0131] Here, the second hard read data can be read by the memory system according to a second hard read voltage. The second hard read voltage can be the initial read voltage or one of the plurality of reread voltages other than the first hard read voltage, and this second hard read data is read before the first hard read data. Specifically, if the first hard read voltage is the first reread after the initial read voltage, then the second hard read voltage is the initial read voltage; if the first hard read voltage is not the first reread after the initial read voltage, then the second hard read voltage is one of the plurality of reread voltages other than the first hard read voltage.

[0132] Figure 7 The described technical solution involves adding a first soft-decision decoding step after a hard-decision decoding failure. In this first soft-decision decoding, the required first soft-read data is not read from the memory system, but rather obtained by XORing the two previously cached hard-read data, thus saving time. Furthermore, the first soft-decision decoding has higher decoding capability and a higher probability of successful decoding than hard-decision decoding, thereby reducing the number of rereads and further saving time and improving the read speed.

[0133] In some embodiments, such as Figure 8 As shown, the method may further include:

[0134] S703: Cache the first hard read data;

[0135] S704: After the first soft decision decoding fails, read the third hard read data according to the third hard read voltage; and perform the hard decision decoding on the third hard read data;

[0136] S705: After the hard decision decoding of the third hard read data fails, the corresponding second soft data is obtained based on the cached first hard read data and the third hard read data.

[0137] S706: Perform the first soft decision decoding based on the second soft data and the first hard read data, or perform the first soft decision decoding based on the second soft data and the third hard read data;

[0138] The third hard read voltage is one of the plurality of reread voltages other than the first hard read voltage and the second hard read voltage.

[0139] It should be noted that soft-decision decoding has a higher capability than hard-decision decoding. In practical applications, if there are many erroneous bits in the read data, a single soft-decision decoding attempt will not be successful. Therefore, the first hard read data is cached for later use. After the first soft-decision failure, a third hard read voltage is used to reread the data. Then, hard-decision decoding is performed on this third hard read data. If this hard-decision decoding fails, another soft-decision decoding attempt is performed. This second soft-decision decoding uses soft data calculated by XORing the third hard read data and the cached first hard read data.

[0140] In practical applications, the method may further include:

[0141] The first stage of error correction code (ECC) correction ends when one of the following occurs: the hard decision decoding is successful, the first soft decision decoding is successful, or the number of hard read retries reaches a first set threshold.

[0142] It should be noted that the first-stage error correction code (ECC) error correction mentioned here can be understood as the aforementioned hard-decision error correction stage, which includes the first soft-decision decoding. In other words, the error correction method provided in this application adds a soft-decision decoding step after a hard-decision decoding failure during a reread in the hard-decision error correction stage. The soft data required for this soft-decision decoding is obtained using cached hard-read data. This leverages the high decoding capability of soft-decision decoding to shorten decoding time, thereby reducing reading time and improving reading efficiency. It should be understood that when hard-decision decoding or the first soft-decision decoding is successful, not only does the first-stage ECC error correction end, but the entire error correction process also ends, because the read data has been corrected and is now correct. Furthermore, the first-stage ECC error correction will not execute indefinitely. When the number of hard-read retries reaches a first set threshold, the first-stage ECC error correction will also end, proceeding to the next stage of error correction or outputting an error correction failure indication message, etc. In other words, the first stage of ECC error correction can end when one of the following conditions is met: the hard decision decoding is successful, the first soft decision decoding is successful, or the number of hard read retries reaches a first preset threshold. Here, the first preset threshold can be determined by the designer based on the actual situation.

[0143] Regarding the aforementioned step 702, specifically selecting either the first hard read data or the second hard read data, and performing first soft decision decoding together with the first soft data, in some embodiments, such as... Figure 9 As shown, the method may further include:

[0144] S7021: Select, based on the first number of error bits in the first hard read data and the second number of error bits in the second hard read data, whether to perform first soft decision decoding based on the first soft data and the first hard read data, or to perform first soft decision decoding based on the first soft data and the second hard read data.

[0145] In other words, the choice between performing first soft-decision decoding based on the number of error bits contained in the first and second hard read data depends on the specific number of error bits in each data set. Specifically, if the first number is greater than the second number, the first soft-decision decoding is performed using the first soft data and the second hard read data; if the first number is less than the second number, the first soft data and the first hard read data are used; and if the first number is equal to the second number, either the first soft data and the first hard read data, or the first soft data and the second hard read data, are used. This is because the more error bits a hard read data contains, the lower its probability of being correctly corrected. Therefore, when performing first soft-decision decoding, hard read data with fewer error bits should be selected as the reference read data for the first soft-decision decoding. It should be understood that the information input to the next stage decoder for soft-decision decoding can be the log-likelihood ratio (LLR), i.e., the so-called soft data. This soft data is probabilistic information about the reliability of different decisions, used to measure the reliability of a decision. Therefore, it is necessary to have a reference data as a benchmark, and then use the soft data to measure its reliability.

[0146] For an understanding of soft-decision decoding, please refer to [link to documentation / reference]. Figure 10 .exist Figure 10 In this example, suppose the first hard read data read using the first hard read voltage is 100; the second hard read data read using the second hard read voltage is 110; correspondingly, the first soft data is 010. If data is read based on the first hard read data, then a bit that is "0" in the first soft data indicates that the reliability of that bit in the first hard read data is relatively high; in other words, that bit is judged to be relatively close to the truth. For example, in... Figure 10In the process of reading data based on the first hard read data, the leftmost bit is "1", while the corresponding bit in the first soft data is "0". Therefore, this bit has high reliability, i.e., a strong "1". Similarly, if the middle bit in the first hard read data corresponds to a "1" in the first soft data, then the middle bit has weak reliability, i.e., a weak "1" or "0". The rightmost bit in the first hard read data is a strong "0". Reading data based on the second hard read data follows a similar analysis and will not be elaborated further. The choice between the first and second hard read data has already been described above, and the implementation method is given later.

[0147] In practical applications, the number of error bits contained in the hard read data is measured by a syndrome weight value, and the larger the syndrome weight value, the more error bits the hard read data contains. The selection of whether to perform first soft-decision decoding based on the first soft data and the first hard read data, or based on the first soft data and the second hard read data, is made based on a first number of error bits in the first hard read data and a second number of error bits in the second hard read data. Figure 11 As shown, it may include:

[0148] S1101: Obtain the first comprehensive weight value corresponding to the first hard read data;

[0149] S1102: Obtain the second comprehensive weight value corresponding to the second hard read data;

[0150] S1103: Compare the first comprehensive weight value corresponding to the first hard read data with the second comprehensive weight value corresponding to the second hard read data;

[0151] S1104: When the comparison result includes the first comprehensive weight being less than the second comprehensive weight, perform first soft decision decoding based on the first soft data and the first hard read data;

[0152] S1105: When the comparison result includes the first comprehensive weight being greater than the second comprehensive weight, perform a first soft decision decoding based on the first soft data and the second hard read data;

[0153] S1106: When the comparison result includes the first comprehensive weight being equal to the second comprehensive weight, perform a first soft decision decoding based on the first soft data and the first hard read data, or perform a first soft decision decoding based on the first soft data and the second hard read data.

[0154] It should be noted that the number of error bits contained in the hard read data can be measured by the syndrome weight value, where a larger syndrome weight value indicates a greater number of error bits in the hard read data. In some embodiments, the syndrome weight value corresponding to the hard read data can be assigned by the memory controller when the hard read data is obtained; the more error bits the hard read data contains, the larger this assigned value. In some embodiments, the memory controller can pre-store a mapping table between error bits and synthesis weights. When the hard read data is obtained, the number of error bits it contains is counted, and then a value is assigned according to the mapping table. That is, the methods described above for obtaining the first synthesis weight corresponding to the first hard read data and the second synthesis weight corresponding to the second hard read data can refer to the previously described method of assigning values ​​using the mapping table. The assignment can also be dynamic. For example, the overall weight corresponding to the first hard read data is randomly assigned. Then, the number of error bits in the second hard read data is compared with the number of error bits in the first hard read data. If the number of error bits in the second hard read data is greater than the number of error bits in the first hard read data, the overall weight corresponding to the second hard read data is assigned a value greater than the randomly assigned value; otherwise, if it is less than, the overall weight corresponding to the second hard read data is assigned a value less than the randomly assigned value; if it is equal, the overall weight corresponding to the second hard read data is assigned a value equal to the randomly assigned value. After that, when assigning the overall weight of the subsequent hard read data, it needs to be compared with the number of error bits in each of the previous hard read data, and then the value is assigned according to the comparison result.

[0155] Here, it is necessary to obtain the first comprehensive weight value corresponding to the first hard read data and the second comprehensive weight value corresponding to the second hard read data. Then, the first comprehensive weight value corresponding to the first hard read data and the second comprehensive weight value corresponding to the second hard read data are compared. Based on the comparison result, it is selected whether to perform first soft-decision decoding based on the first soft data and the first hard read data, or based on the first soft data and the second hard read data. Specifically, when the comparison result includes the first comprehensive weight value being less than the second comprehensive weight value, first soft-decision decoding is performed based on the first soft data and the first hard read data; when the comparison result includes the first comprehensive weight value being greater than the second comprehensive weight value, first soft-decision decoding is performed based on the first soft data and the second hard read data; when the comparison result includes the first comprehensive weight value being equal to the second comprehensive weight value, first soft-decision decoding can be performed based on either the first soft data and the first hard read data, or based on the first soft data and the second hard read data.

[0156] To save storage space in the memory controller's memory, in some embodiments, the method may further include:

[0157] After performing a first soft decision decoding based on the first soft data and the first hard read data, or after performing a first soft decision decoding based on the first soft data and the second hard read data, the cached second hard read data is deleted.

[0158] After performing the first soft decision decoding based on the second soft data and the first hard read data, or after performing the first soft decision decoding based on the second soft data and the third hard read data, the cached first hard read data is deleted.

[0159] In other words, delete hard read data that is not needed later to save memory space.

[0160] In some embodiments, the method may further include:

[0161] If the first stage of ECC error correction fails, the second stage of ECC error correction is performed, wherein...

[0162] The second phase of ECC error correction includes performing at least one second soft-decision decoding.

[0163] In some embodiments, performing the second soft-decision decoding includes:

[0164] A set of soft read voltages is determined; the set of soft read voltages includes an optimal read voltage and multiple soft reread voltages that have a certain offset relative to the optimal read voltage;

[0165] The fourth hard read data and the third soft data are read according to the soft read voltage in the set of soft read voltages; and the second soft decision decoding is performed according to the fourth hard read data and the third soft data;

[0166] The second stage of ECC error correction will end if one of the following occurs: the second soft decision decoding is successful or the number of soft read retries reaches the second set threshold.

[0167] It should be noted that after the failure of the first-stage ECC error correction, there will be other error correction measures, such as at least one second soft-decision decoding. Here, the algorithm of the second soft-decision decoding can be the same as or different from that of the first soft-decision decoding. For example, the second soft-decision decoding can be the confidence propagation algorithm; or the first soft-decision decoding can be the confidence propagation algorithm, and the second soft-decision decoding can be the min-sum algorithm. Regardless of whether the algorithms for the first and second soft-decision decoding are the same, their biggest difference lies in the soft data and reference read data they use. Specifically, the first soft data used in the first soft-decision decoding is obtained by logical operations based on the cached hard read data; while the third soft data used in the second soft-decision decoding is data read from memory based on the set soft read voltage. In other words, the third soft data is data fed back to the memory controller by the memory in response to the soft read voltage applied by the memory controller, rather than being calculated in the memory controller using the cached hard read data. Furthermore, the reference read data used in the first soft-decision decoding is one of the cached hard read data; while the reference read data used in the second soft-decision decoding is data read from memory based on the aforementioned optimal read voltage.

[0168] The above description of performing at least one second soft-decision decoding is also intended to increase the probability of correctly reading data. Each execution of the second soft-decision decoding process may include the following steps: determining a set of soft read voltages; this set of soft read voltages may include: an optimal read voltage and multiple soft reread voltages with a certain offset relative to the optimal read voltage; wherein, the optimal read voltage can be obtained according to the aforementioned RRT table, specifically, the RRT table can be traversed to obtain the optimal voltage offset; then, the optimal voltage offset is superimposed with a reference voltage to form the optimal read voltage; under this optimal read voltage, the number of error bits in the obtained reference read data is minimized. In some embodiments, the voltage interval between each soft read voltage in this set of soft read voltages may be the same as the voltage interval between the hard read voltages in the set of hard read voltages used to perform the hard-decision decoding, wherein the set of hard read voltages includes the initial read voltage and the multiple reread voltages. In other embodiments, the voltage interval between each soft read voltage in this set of soft read voltages may also be different from the voltage interval between the hard read voltages in this set of hard read voltages. The specific method of performing soft-decision decoding has been described above and will not be repeated here.

[0169] The second stage of ECC error correction ends when the second soft-decision decoding is successful and the number of soft-read retries reaches one of the second preset thresholds. The second preset threshold is manually set based on actual conditions and may be the same as or different from the first preset threshold. Here, the number of soft-read retries refers to the number of times the second soft-decision decoding is performed.

[0170] In some embodiments, the method may further include:

[0171] After the ECC error correction in the second stage fails, the third stage of independent NAND redundant array RAIN error correction is performed.

[0172] In some embodiments, the method may further include:

[0173] After the RAIN error correction fails in the third stage, an indication message is output to characterize the error correction failure.

[0174] In some embodiments, the method further includes:

[0175] When one of the following occurs: the first stage of ECC error correction is successful, the second stage of ECC error correction is successful, or the third stage of RAIN error correction is successful, the read data that has been successfully corrected is output.

[0176] It should be noted that in extreme cases, if both the first and second stages of ECC error correction fail, a third stage of independent NAND redundant array RAIN error correction can be activated. If this also fails, an indication of error correction failure will be output; this indication can be one of the following: sound, image, text, symbol, or any combination thereof. If one of the following conditions occurs: the first stage of ECC error correction succeeds, the second stage of ECC error correction succeeds, and the third stage of RAIN error correction succeeds, the successfully corrected read data will be output. That is, regardless of the stage, if error correction is successful, the successfully corrected read data will be output.

[0177] To understand this application, as Figure 12 As shown, it illustrates a schematic diagram of an error correction process for a memory system provided in an embodiment of the present invention.

[0178] The specific process includes:

[0179] S1201: First stage of ECC error correction.

[0180] Among them, such as Figure 13 As shown, the first stage of ECC error correction includes: initial read; hard-decision decoding of the initial read data; if the initial read fails, a first reread and hard-decision decoding are performed; if the first reread fails, a first soft-decision decoding is performed; and so on, proceeding to the next decoding step if decoding fails. The first stage of ECC error correction ends when one of the following occurs: the number of rereads reaches a first set threshold, hard-decision decoding succeeds, or the first soft-decision decoding succeeds.

[0181] S1202: Second-stage ECC error correction.

[0182] The second phase of ECC error correction includes at least one second soft-decision decoding. The similarities and differences with the first soft-decision decoding, already described in detail above, will not be repeated here.

[0183] S1203: Third-stage RAIN error correction.

[0184] Specifically, after the RAIN error correction fails in the third stage, an indication message indicating the error correction failure is output; when the RAIN error correction succeeds in the third stage, the read data that has been successfully corrected is output.

[0185] The error correction method provided in this application accelerates the error correction process and improves reading efficiency by adding a soft-decision decoding after each failed hard-decision decoding in the first-stage ECC error correction process (hard-decision error correction).

[0186] Based on the foregoing inventive concept, embodiments of this application also provide a memory system, see [link to relevant documentation]. Figure 14 , Figure 14 A block diagram of a memory system is shown. The memory system 140 includes a memory device 1401 for storing data;

[0187] A memory controller 1402, coupled to the memory device, is configured to: after a hard-decision decoding of the first hard read data fails, obtain corresponding first soft data based on the first hard read data and cached second hard read data; wherein the first hard read data is read by the memory system according to a first hard read voltage; and the second hard read data is read by the memory system according to a second hard read voltage before reading the first hard read data;

[0188] Perform a first soft decision decoding based on the first soft data and the first hard read data, or perform a first soft decision decoding based on the first soft data and the second hard read data;

[0189] Wherein, the first hard read voltage is one of a plurality of reread voltages having a certain offset from the initial read voltage; the second hard read voltage is the initial read voltage or a reread voltage other than the first hard read voltage among the plurality of reread voltages.

[0190] In some embodiments, the memory controller 1402 may include: a processor 1423, a memory 1427, a hardware decoder 1425, and a software decoder 1426, wherein;

[0191] The processor is configured to: read the first hard read data from the memory device according to the first hard read voltage; read the second hard read data according to the second hard read voltage before reading the first hard read data; and cache the second hard read data in the memory;

[0192] The hard decoder is used to: perform the hard decision decoding on the first hard read data;

[0193] The processor is further configured to: after the hard decision decoding of the first hard read data fails, obtain corresponding first soft data based on the first hard read data and the cached second hard read data; send the first hard read data or the second hard read data to the soft decoder; and send the first soft data to the soft decoder.

[0194] The soft decoder is configured to: perform a first soft decision decoding based on the first soft data and the first hard read data, or perform a first soft decision decoding based on the first soft data and the second hard read data.

[0195] In some embodiments, the memory is further used to cache the first hard-read data;

[0196] The processor is further configured to: read third hard read data according to the third hard read voltage after the first soft decision decoding fails;

[0197] The hard decoder is also used to: perform the hard decision decoding on the third hard read data;

[0198] The processor is further configured to: after the hard decision decoding of the third hard read data fails, obtain the corresponding second soft data based on the cached first hard read data and the third hard read data;

[0199] The soft decoder is further configured to: perform the first soft decision decoding based on the second soft data and the first hard read data, or perform the first soft decision decoding based on the second soft data and the third hard read data.

[0200] In some embodiments, the processor is further configured to: determine whether one of the following conditions occurs: the hard decision decoding is successful, the first soft decision decoding is successful, or the number of hard read retries reaches a first preset threshold; if such condition occurs, terminate the first stage of error correction code (ECC) correction.

[0201] In some embodiments, the soft decoder is further configured to: perform a second stage of ECC error correction after the first stage of ECC error correction fails, wherein the second stage of ECC error correction includes: performing at least one second soft decision decoding;

[0202] The second stage of ECC error correction will end if one of the following occurs: the second soft decision decoding is successful or the number of soft read retries reaches the second set threshold.

[0203] In some embodiments, the memory controller further includes: a RAIN error corrector 1428, configured to: perform a third stage of independent NAND redundant array RAIN error correction after the ECC error correction in the second stage fails;

[0204] The processor is further configured to: output indication information indicating decoding failure after the RAIN error correction in the third stage fails; and output successfully decoded read data if one of the following occurs: the ECC error correction in the first stage succeeds, the ECC error correction in the second stage succeeds, or the RAIN error correction in the third stage succeeds.

[0205] It should be noted that, Figure 14 In the illustrated memory system 140, the memory controller 1402 controls the memory device 1401 to perform various operations, such as read and write operations. Here, the memory controller 1402 and the memory device 1401 can be coupled in any suitable manner. In this embodiment, the memory device 1401 can be a non-volatile semiconductor memory for storing data, such as a NAND flash memory. Figure 14 As shown, the memory system 140 is connected to the host 141, which can be an electronic device such as a personal computer or a mobile terminal. The host I / F 1421 outputs commands and valid data (write data) received from the host 141 to the internal bus 1420, and sends valid data (read data) read from the memory device 1401 and responses from the control unit 1423 back to the host 141. The host I / F 1421 includes, but is not limited to, at least one of the following: Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed ​​Peripheral Component Interconnect (PCI-e or PCIe), Small Computer System Interface (SCSI), Serial SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Electronic Integrated Drive (IDE). In some embodiments, the host I / F 1421 is a component of the memory system used to exchange data with the host 108, and can be implemented through firmware referred to as the Host Interface Layer (HIL).

[0206] The memory I / F 1422 controls the processes of writing valid data to and reading data from the memory device 1401 based on instructions from the control unit 1423. The control unit 1423, such as a central processing unit (CPU) or microprocessor (MPU), controls the memory system 140 as a whole. The control unit 1423 performs control according to commands received from the host 141 via the host I / F 1421. For example, the control unit 1423 instructs the memory I / F 1422 to write valid data and parity data to the memory device 1401 based on commands from the host 141. Furthermore, the control unit 1423 instructs the memory I / F 1422 to read valid data and parity data from the memory device 1401 based on commands from the host 141. The memory I / F 1422 can be implemented as a component for exchanging data with the memory device 104 via firmware called a Flash Interface Layer (FIL).

[0207] The error correction (ECC) module 1424 includes a hard decision decoder 1425, a soft decision decoder 1426, and a RAIN decoder 1428, the functions of which have been described above and will not be repeated here.

[0208] The data buffer 1427 temporarily saves valid data received from the host 141 before storing it in the memory device 1401, and temporarily saves data read from the memory device 1401 before sending it to the host 141.

[0209] Memory 1427 can also be the working memory of memory controller 1402, configured to store data for driving memory controller 1402. More specifically, when memory controller 1402 controls memory device 1401 in response to a request from host 141, memory 1427 can store firmware driven by the processor of control unit 1423 and data (e.g., metadata) required to drive the firmware. Memory 1427 can also be a buffer memory of memory controller 1401, configured to temporarily store write data transferred from host 141 to memory device 1401 and read data transferred from memory device 1401 to host 141. Memory 1427 may include program memory, data memory, write buffer / cache, read buffer / cache, data buffer / cache, and mapped buffer / cache for storing write data and read data. Memory 1427 can be implemented using volatile memory. Memory 1427 can be implemented using static random access memory (SRAM), dynamic random access memory (DRAM), or both.

[0210] Although Figure 14The illustration shows that memory 1427 is included in memory controller 1402, but this application is not limited thereto. In embodiments, memory 1427 may be included externally to memory controller 1402, and memory controller 1402 may input and output data to memory 1427 via a separate memory interface (not shown).

[0211] Based on the foregoing inventive concept, embodiments of this application also provide a memory controller, which may include: a processor, memory, a hardware decoder, and a software decoder, wherein;

[0212] The processor is configured to: read first hard read data from a memory device coupled to the memory controller according to a first hard read voltage; read second hard read data from the memory device according to a second hard read voltage before reading the first hard read data; and cache the second hard read data in the memory.

[0213] The hard decoder is used to: perform hard decision decoding on the first hard read data;

[0214] The processor is further configured to: after the hard decision decoding of the first hard read data fails, obtain corresponding first soft data based on the first hard read data and the cached second hard read data; send the first hard read data or the second hard read data to the soft decoder; and send the first soft data to the soft decoder.

[0215] The soft decoder is configured to: perform a first soft decision decoding based on the first soft data and the first hard read data, or perform a first soft decision decoding based on the first soft data and the second hard read data;

[0216] The processor is further configured to: determine whether one of the following conditions occurs: the hard decision decoding is successful, the first soft decision decoding is successful, or the number of hard read retries reaches a first preset threshold; if any of these conditions occur, terminate the first stage of error correction code (ECC) error correction.

[0217] Wherein, the first hard read voltage is one of a plurality of reread voltages having a certain offset from the initial read voltage; the second hard read voltage is the initial read voltage or a reread voltage other than the first hard read voltage among the plurality of reread voltages.

[0218] It should be noted that the memory controller described herein is included in the aforementioned memory system. Therefore, the structure of the memory controller and its operation related to the error correction method provided in the embodiments of this application have been described in detail above, and will not be repeated here.

[0219] The above description is intended to be illustrative and not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used, such as those applicable to a person skilled in the art upon reading the above description. It should be understood that it is not intended to interpret or limit the scope or meaning of the claims. Furthermore, in the above detailed description, various features may be combined to simplify the application. This should not be construed as meaning that any unclaimed disclosed feature is essential to any claim. Rather, the subject matter of the disclosure may lie in fewer than all features of a particular disclosed embodiment. Therefore, the appended claims are thus incorporated into the detailed description, wherein each claim is an independent, separate embodiment, and these embodiments are contemplated to be combined with each other in various combinations or substitutions. The scope of this application should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. An error correction method for a memory system, characterized in that, The method includes: After a hard-decision decoding of the first hard read data fails, the corresponding first soft data is obtained based on the first hard read data and the cached second hard read data; wherein, the first hard read data is read by the memory system according to the first hard read voltage; and the second hard read data is read by the memory system according to the second hard read voltage before reading the first hard read data; Perform a first soft decision decoding based on the first soft data and the first hard read data, or perform a first soft decision decoding based on the first soft data and the second hard read data; Wherein, the first hard read voltage is one of a plurality of reread voltages having a certain offset from the initial read voltage; the second hard read voltage is the initial read voltage or a reread voltage other than the first hard read voltage among the plurality of reread voltages.

2. The error correction method according to claim 1, characterized in that, The method further includes: Cache the first hard read data; After the first soft decision decoding fails, the third hard read data is read according to the third hard read voltage; and the hard decision decoding is performed on the third hard read data. After the hard decision decoding of the third hard read data fails, the corresponding second soft data is obtained based on the cached first hard read data and the third hard read data. The first soft decision decoding is performed based on the second soft data and the first hard read data, or the first soft decision decoding is performed based on the second soft data and the third hard read data; The third hard read voltage is one of the plurality of reread voltages other than the first hard read voltage and the second hard read voltage.

3. The error correction method according to claim 2, characterized in that, The method further includes: The first stage of error correction code (ECC) correction ends when one of the following occurs: the hard decision decoding is successful, the first soft decision decoding is successful, or the number of hard read retries reaches a first set threshold.

4. The error correction method according to claim 1, characterized in that, The step of obtaining the corresponding first soft data based on the first hard read data and the cached second hard read data includes: The first hard read data and the second hard read data are XORed to obtain the first soft data.

5. The error correction method according to claim 1, characterized in that, The method further includes: The selection is based on a first number of error bits in the first hard read data and a second number of error bits in the second hard read data, choosing between performing a first soft decision decoding based on the first soft data and the first hard read data, or performing a first soft decision decoding based on the first soft data and the second hard read data.

6. The error correction method according to claim 5, characterized in that, The number of erroneous bits contained in the hard read data is measured by a comprehensive weight, and the larger the comprehensive weight, the more erroneous bits the hard read data contains; the selection based on the first number of erroneous bits in the first hard read data and the second number of erroneous bits in the second hard read data—whether to perform first soft decision decoding based on the first soft data and the first hard read data, or based on the first soft data and the second hard read data—includes: Obtain the first comprehensive weight value corresponding to the first hard read data; Obtain the second comprehensive weight value corresponding to the second hard read data; Compare the first comprehensive weight value corresponding to the first hard read data with the second comprehensive weight value corresponding to the second hard read data; When the comparison result includes the first comprehensive weight being less than the second comprehensive weight, a first soft decision decoding is performed based on the first soft data and the first hard read data; When the comparison result includes the first comprehensive weight being greater than the second comprehensive weight, a first soft decision decoding is performed based on the first soft data and the second hard read data; When the comparison result includes the first comprehensive weight being equal to the second comprehensive weight, a first soft decision decoding is performed based on the first soft data and the first hard read data, or a first soft decision decoding is performed based on the first soft data and the second hard read data.

7. The error correction method according to claim 2, characterized in that, The method further includes: After performing a first soft decision decoding based on the first soft data and the first hard read data, or after performing a first soft decision decoding based on the first soft data and the second hard read data, the cached second hard read data is deleted. After performing the first soft decision decoding based on the second soft data and the first hard read data, or after performing the first soft decision decoding based on the second soft data and the third hard read data, the cached first hard read data is deleted.

8. The error correction method according to claim 3, characterized in that, The method further includes: If the first stage of ECC error correction fails, the second stage of ECC error correction is performed, wherein... The second phase of ECC error correction includes performing at least one second soft-decision decoding.

9. The error correction method according to claim 8, characterized in that, Performing the second soft-decision decoding includes: A set of soft read voltages is determined; the set of soft read voltages includes an optimal read voltage and multiple soft reread voltages that have a certain offset relative to the optimal read voltage; The fourth hard read data and the third soft data are read according to the soft read voltage in the set of soft read voltages; and the second soft decision decoding is performed according to the fourth hard read data and the third soft data; In the event of one of the following: the second soft decision decoding is successful, or the number of soft read retries reaches the second set threshold, the second stage of ECC error correction ends.

10. The error correction method according to claim 9, characterized in that, The method further includes: After the ECC error correction in the second stage fails, the third stage of independent NAND redundant array RAIN error correction is performed.

11. The error correction method according to claim 10, characterized in that, The method further includes: After the RAIN error correction fails in the third stage, an indication message is output to characterize the error correction failure.

12. The error correction method according to claim 10, characterized in that, The method further includes: When one of the following occurs: the first stage of ECC error correction is successful, the second stage of ECC error correction is successful, or the third stage of RAIN error correction is successful, the read data that has been successfully corrected is output.

13. The error correction method according to claim 9, characterized in that, The voltage interval between each read voltage in the set of soft read voltages is the same as the voltage interval between the hard read voltages in the set of hard read voltages used to perform the hard decision decoding, wherein the set of hard read voltages includes the initial read voltage and the plurality of reread voltages.

14. A memory system, characterized in that, include: Memory devices used to store data; A memory controller, coupled to the memory device, is configured to: after a hard-decision decoding of first hard-read data fails, obtain corresponding first soft data based on the first hard-read data and cached second hard-read data; wherein the first hard-read data is read by the memory system according to a first hard-read voltage; and the second hard-read data is read by the memory system according to a second hard-read voltage before reading the first hard-read data; Perform a first soft decision decoding based on the first soft data and the first hard read data, or perform a first soft decision decoding based on the first soft data and the second hard read data; Wherein, the first hard read voltage is one of a plurality of reread voltages having a certain offset from the initial read voltage; the second hard read voltage is the initial read voltage or a reread voltage other than the first hard read voltage among the plurality of reread voltages.

15. The memory system according to claim 14, characterized in that, The memory controller includes: a processor, memory, a hardware decoder, and a software decoder, wherein; The processor is configured to: read the first hard read data from the memory device according to the first hard read voltage; read the second hard read data according to the second hard read voltage before reading the first hard read data; and cache the second hard read data in the memory; The hard decoder is used to: perform the hard decision decoding on the first hard read data; The processor is further configured to: after the hard decision decoding of the first hard read data fails, obtain corresponding first soft data based on the first hard read data and the cached second hard read data; send the first hard read data or the second hard read data to the soft decoder; and send the first soft data to the soft decoder. The soft decoder is configured to: perform a first soft decision decoding based on the first soft data and the first hard read data, or perform a first soft decision decoding based on the first soft data and the second hard read data.

16. The memory system according to claim 15, characterized in that, The memory is also used to cache the first hard read data; The processor is further configured to: read third hard read data according to the third hard read voltage after the first soft decision decoding fails; The hard decoder is also used to: perform the hard decision decoding on the third hard read data; The processor is further configured to: after the hard decision decoding of the third hard read data fails, obtain the corresponding second soft data based on the cached first hard read data and the third hard read data; The soft decoder is further configured to: perform the first soft decision decoding based on the second soft data and the first hard read data, or perform the first soft decision decoding based on the second soft data and the third hard read data.

17. The memory system according to claim 16, characterized in that, The processor is further configured to: determine whether one of the following conditions occurs: the hard decision decoding is successful, the first soft decision decoding is successful, or the number of hard read retries reaches a first set threshold; if any of these conditions occur, terminate the first stage of error correction code (ECC) correction.

18. The memory system according to claim 17, characterized in that, The soft decoder is further configured to: perform a second stage of ECC error correction after the first stage of ECC error correction fails, wherein the second stage of ECC error correction includes: performing at least one second soft decision decoding; In the event of one of the following: the second soft decision decoding is successful, or the number of soft read retries reaches the second set threshold, the second stage of ECC error correction ends.

19. The memory system according to claim 18, characterized in that, The memory controller further includes a RAIN error corrector, configured to perform a third stage of independent NAND redundant array RAIN error correction after the ECC error correction in the second stage fails. The processor is further configured to: output indication information indicating decoding failure after the RAIN error correction in the third stage fails; and output successfully decoded read data if one of the following occurs: the ECC error correction in the first stage succeeds, the ECC error correction in the second stage succeeds, or the RAIN error correction in the third stage succeeds.

20. A memory controller, characterized in that, include: The processor, memory, hardware decoder, and software decoder, among which; The processor is configured to: read first hard read data from a memory device coupled to the memory controller according to a first hard read voltage; and read second hard read data from the memory device according to a second hard read voltage before reading the first hard read data; And cache the second hard read data into the memory; The hard decoder is used to: perform hard decision decoding on the first hard read data; The processor is further configured to: after the hard decision decoding of the first hard read data fails, obtain the corresponding first soft data based on the first hard read data and the cached second hard read data; Send the first hard read data or the second hard read data to the software decoder; Send the first soft data to the soft decoder; The soft decoder is configured to: perform a first soft decision decoding based on the first soft data and the first hard read data, or perform a first soft decision decoding based on the first soft data and the second hard read data; The processor is further configured to: determine whether one of the following conditions occurs: the hard decision decoding is successful, the first soft decision decoding is successful, or the number of hard read retries reaches a first preset threshold; if any of these conditions occur, terminate the first stage of error correction code (ECC) error correction. Wherein, the first hard read voltage is one of a plurality of reread voltages having a certain offset from the initial read voltage; the second hard read voltage is the initial read voltage or a reread voltage other than the first hard read voltage among the plurality of reread voltages.

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