Chip filter circuit, integrated chip and electronic equipment

Abstract

The invention discloses a chip filter circuit, an integrated chip and electronic equipment, and belongs to the technical field of electronic equipment. The chip filter circuit comprises a signal source, a blocking capacitor, a filter circuit and a power amplifier, the blocking capacitor is arranged between the signal source and the filter circuit; the filter circuit is arranged between the blocking capacitor and the signal input end of the power amplifier; the filter circuit comprises at least one filter unit; the filter circuit supports filtering of at least one frequency point.

Description

Technical Field

[0001] The present application belongs to the technical field of electronic equipment, and specifically relates to a chip filter circuit, an integrated chip and electronic equipment. Background Art

[0002] With the continuous innovation of the degree of technological process, the integration of integrated circuits (ICs) is getting higher and higher. For example, a power amplifier (PA) can be integrated with modules such as switches, analog-to-digital (AD) conversion or virtual data optimizer (VDO).

[0003] As the number of integrated modules in IC increases, the anti-interference ability between modules in IC decreases. For the PA integrated in IC, if there is interference signal on its power line and signal input line, it will cause the signal amplification waveform to be distorted, resulting in poor performance of IC. Therefore, the anti-interference ability of the PA integrated in IC is very important.

[0004] In the related art, a capacitor is connected in parallel to the power supply pin of the PA outside the IC to filter out specific interference signals on the PA power supply. However, this method can only filter out interference signals on the PA power line, but cannot filter out interference signals on the PA signal input line. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a chip filter circuit, an integrated chip and an electronic device, which can solve the problem of being unable to filter out interference signals on the signal input line of a power amplifier.

[0006] In a first aspect, an embodiment of the present application provides a chip filter circuit, comprising: a signal source, a DC blocking capacitor, a filter circuit, and a power amplifier;

[0007] The DC blocking capacitor is placed between the signal source and the filter circuit;

[0008] The filter circuit is arranged between the DC blocking capacitor and the signal input terminal of the power amplifier;

[0009] The filter circuit includes at least one filter unit;

[0010] The filter circuit supports filtering at at least one frequency point.

[0011] In a second aspect, an embodiment of the present application provides an integrated chip, including:

[0012] The chip filter circuit provided in the embodiment of the present application.

[0013] In a third aspect, an embodiment of the present application provides an electronic device, the electronic device comprising:

[0014] An integrated chip is provided in an embodiment of the present application.

[0015] In the embodiment of the present application, the chip filter circuit includes a signal source, a DC blocking capacitor, a filter circuit and a power amplifier; the DC blocking capacitor is arranged between the signal source and the filter capacitor; the filter circuit is arranged between the DC blocking capacitor and the signal input terminal of the power amplifier; the filter circuit includes at least one filter unit; the filter circuit supports filtering at at least one frequency point. In this way, the chip filter circuit can filter out the interference signal on the signal input line of the power amplifier, ensure that the signal amplification waveform is not distorted, and improve the performance of the integrated chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of a structure for filtering interference signals on a power line of a power amplifier provided in the related art;

[0017] Figure 2 This is a first structural schematic diagram of a chip filter circuit provided in an embodiment of the present application;

[0018] Figure 3 This is a second structural schematic diagram of the chip filter circuit provided in an embodiment of the present application;

[0019] Figure 4 This is a third structural schematic diagram of the chip filter circuit provided in the embodiment of the present application;

[0020] Figure 5 This is a fourth structural schematic diagram of the chip filter circuit provided in the embodiment of the present application;

[0021] Figure 6 This is a fifth structural schematic diagram of the chip filter circuit provided in the embodiment of the present application;

[0022] Figure 7 This is a sixth structural schematic diagram of the chip filter circuit provided in the embodiment of the present application;

[0023] Figure 8 This is a seventh structural schematic diagram of the chip filter circuit provided in the embodiment of the present application;

[0024] Fig. 9 This is an eighth structural schematic diagram of the chip filter circuit provided in the embodiment of the present application;

[0025] Fig.10 This is a ninth structural schematic diagram of the chip filter circuit provided in the embodiment of the present application;

[0026] Fig.11 This is a tenth structural schematic diagram of a chip filter circuit provided in an embodiment of the present application;

[0027] Fig.12 It is a specific structural schematic diagram of a chip filter circuit provided in an embodiment of the present application;

[0028] Fig.13 is another specific structural schematic diagram of the chip filter circuit provided in an embodiment of the present application;

[0029] Fig.14 It is a schematic diagram of the hardware structure of the electronic device provided in the embodiment of the present application. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0031] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way are interchangeable where appropriate, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0032] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0033] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0034] For ease of understanding, some contents involved in the embodiments of the present application are described below.

[0035] With the continuous innovation of technological process, the integration of integrated chips is getting higher and higher, and power amplifiers are gradually integrated with switches, analog-to-digital conversion modules, virtual data optimizers and other modules, which reduces the anti-interference ability between modules within the integrated chip. In addition, the interference occurring within the integrated chip is usually difficult to filter out.

[0036] The filtering solutions in the related art are to connect capacitors in parallel to the power supply pins of the integrated chip of the integrated power amplifier to achieve filtering of specific interference frequency bands. Figure 1 As shown, Figure 1 The figure is a schematic diagram of a structure for filtering interference signals on the power line of a power amplifier provided in the related art. Figure 1 In the invention, the interference signal on the power line of the power amplifier is filtered out by a filter capacitor. However, the filter capacitor cannot filter out the interference signal on the signal input line of the power amplifier (the wiring from the signal source to the power amplifier). Based on this, an embodiment of the present application provides a chip filter circuit, which includes: a signal source, a DC blocking capacitor, a filter circuit and a power amplifier; the DC blocking capacitor is arranged between the signal source and the filter circuit; the filter circuit is arranged between the DC blocking capacitor and the signal input terminal of the power amplifier; the filter circuit includes at least one filter unit; the filter circuit supports filtering of at least one frequency point. The DC blocking capacitor is used to prevent the transmission of direct current, ensuring that the conversion of the level during the transmission of the signal will not affect the signal input terminal of the power amplifier.

[0037] like Figure 2 As shown, Figure 2 This is a schematic diagram of the first structure of the chip filter circuit provided in the embodiment of the present application. Figure 2In the chip filter circuit 100, a power amplifier 10, a filter circuit 20, a signal source 30 and a DC blocking capacitor 40. One end of the DC blocking capacitor 40 is electrically connected to the signal source 30, the other end of the DC blocking capacitor 40 is electrically connected to one end of the filter circuit 20, and the other end of the filter circuit 20 is electrically connected to the signal input terminal 11 of the power amplifier 10. That is, the DC blocking capacitor 40 is arranged between the signal source 30 and the filter circuit 20, and the filter circuit 20 is arranged between the DC blocking capacitor 40 and the signal input terminal 11 of the power amplifier 10. The filter circuit 20 can filter out interference signals on the signal input line of the power amplifier 10, thereby improving the anti-interference performance of the power amplifier.

[0038] Figure 3 This is a second structural diagram of the chip filter circuit provided in an embodiment of the present application.

[0039] exist Figure 3 In the embodiment, the chip filter circuit 100 includes a power amplifier 10, a filter circuit 20, a signal source 30 and a DC blocking capacitor 40. The filter circuit 20 includes a first filter unit 21, and the first filter unit 21 includes a first inductor L1 and a first capacitor C1, and the first inductor L1 and the first capacitor C1 are connected in parallel, wherein the first end of the first inductor L1 is electrically connected to the DC blocking capacitor 40, the second end of the first inductor L1 is electrically connected to the first end of the first capacitor C1 and the signal input terminal 11 of the power amplifier 10, respectively, and the second end of the first capacitor C1 is grounded.

[0040] In some possible implementations of the embodiments of the present application, the switch of the power amplifier is in the form of a triode, and the signal input terminal of the power amplifier is the base of the triode, but this does not limit the form of the switch of the power amplifier. In some embodiments, the switch of the power amplifier is in the form of a metal oxide semiconductor field effect transistor (MOS tube), and the signal input terminal of the power amplifier is the gate of the MOS tube. Figure 4 As shown, Figure 4 This is a third structural schematic diagram of the chip filter circuit provided in the embodiment of the present application.

[0041] exist Figure 4In the chip filter circuit 100, a power amplifier 10, a filter circuit 20, a signal source 30 and a DC blocking capacitor 40 are included. The filter circuit 20 includes a first filter unit 21. The first filter unit 21 includes the power amplifier 10 including a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a transistor G; the first filter unit 21 includes a first inductor L1 and a first capacitor C1; the first inductor L1 and the first capacitor C1 are connected in parallel. The base of the transistor G serves as the signal input end of the power amplifier 10, which is electrically connected to one end of the first inductor L1 and one end of the first capacitor C1 respectively, the other end of the first inductor L1 is electrically connected to the DC blocking capacitor 40, and the other end of the first capacitor C1 is grounded. The power supply end of the power amplifier 10 is electrically connected to the power supply VDD.

[0042] Since the capacitor has a resonant frequency, when the interference frequency is near the capacitor resonant frequency, the capacitor is in a low impedance state, and the transmission signal will propagate along the low impedance path, and the interference frequency signal can be introduced to the ground through the shortest path to achieve a filtering effect. However, the capacitor resonant frequency is relatively single (it can only filter a single frequency), so Figure 3 and Figure 4 The chip filter circuit 100 shown supports filtering at one frequency point.

[0043] In some possible implementations of the embodiments of the present application, the filtering frequency point can be understood as the frequency point of the interference signal that is filtered out.

[0044] When there are multiple interference signals at the signal input end of the power amplifier, a single capacitor cannot filter out the multiple interference signals. Therefore, the chip filter circuit needs to support filtering at least two frequency points to improve the filtering capability of the chip filter circuit.

[0045] In some possible implementations of the embodiments of the present application, the chip filter circuit can support filtering of one frequency point at a time, and then switch the filtering frequency point to achieve filtering of multiple frequency points. In this way, compared with the chip filter circuit that only supports filtering of one frequency point, the chip filter circuit that supports filtering of at least two frequency points can expand the filtering frequency point range, thereby improving the anti-interference performance of the power amplifier.

[0046] In some possible implementations of the present application, the chip filter circuit can support filtering of at least two frequency points at the same time. The at least two frequency points can be continuous or discontinuous. In the case of continuity, the chip filter circuit can perform bandpass filtering to achieve filtering of a wide frequency band.

[0047] In some possible implementations of the embodiments of the present application, the chip filter circuit may be a mirror filter circuit that performs bandpass filtering. In this case, two frequency points are used to determine a frequency band, and the frequency points and the frequency bands have a two-to-one correspondence. The chip filter circuit supports filtering of at least two frequency points, which can be understood as: the chip filter circuit supports filtering out at least one interference signal of a passband, wherein one passband corresponds to two frequency points, and the cutoff frequency of the passband is the two frequency points corresponding to the passband.

[0048] Exemplarily, assuming that the chip filter circuit supports filtering of frequency point x and frequency point y, it can be expressed as: the chip filter circuit supports filtering of passbands with cutoff frequencies of frequency point x and frequency point y.

[0049] In the embodiment of the present application, the chip filter circuit can perform bandpass filtering, which can filter out wide-band interference signals, thereby improving the anti-interference performance of the power amplifier.

[0050] In some possible implementations of the embodiments of the present application, the chip filter circuit in the embodiments of the present application may include a second filter unit and a third filter unit. The second filter unit includes a second inductor and a second capacitor; the third filter unit includes a third inductor and a third capacitor; the first end of the second capacitor is electrically connected to the DC blocking capacitor, and the second end of the second capacitor is electrically connected to the first end of the second inductor, the first end of the third capacitor, and the first end of the third inductor respectively; the second end of the third inductor is electrically connected to the signal input end of the power amplifier; the second end of the second inductor and the second end of the third capacitor are grounded. Figure 5 As shown, Figure 5 This is a fourth structural schematic diagram of the chip filter circuit provided in the embodiment of the present application.

[0051] exist Figure 5 In the embodiment, the chip filter circuit 100 includes a power amplifier 10, a filter circuit 20, a signal source 30 and a DC blocking capacitor 40. The power amplifier 10 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a transistor G; the base of the transistor G serves as a signal input terminal of the power amplifier 10.

[0052] The filter circuit 20 may include a second filter unit 501 and a third filter unit 502. The second filter unit 501 includes a second inductor L2 and a second capacitor C2; the third filter unit 502 includes a third inductor L3 and a third capacitor C3.

[0053] The first end of the second capacitor C2 is electrically connected to the DC blocking capacitor 40, and the second end of the second capacitor C2 is electrically connected to the first end of the second inductor L2, the first end of the third capacitor C3 and the first end of the third inductor L3 respectively; the second end of the third inductor L3 is electrically connected to the base of the transistor G; the second end of the second inductor L2 and the second end of the third capacitor C3 are grounded. The power supply terminal of the power amplifier 10 is electrically connected to the power supply VDD.

[0054] Figure 5 The chip filter circuit in the embodiment can perform bandpass filtering, but the suppression and attenuation of the adjacent frequency interference signal beside the bandpass is poor, and it is difficult to achieve rapid attenuation of the interference signal in the adjacent band. Based on this, further, by adding an inductor connected in parallel with the second capacitor C2 in the second filtering unit 501, the resonant structure of the mirror filter circuit can be increased, so that a pole can be added in the adjacent frequency region near the bandpass of the mirror filter circuit, and rapid attenuation of the out-of-band signal can be achieved, further improving the anti-interference performance of the power amplifier.

[0055] In some possible implementations of the embodiment of the present application, the second filtering unit in the embodiment of the present application may further include a fourth inductor; the fourth inductor is connected in parallel with the second capacitor. Figure 6 As shown, Figure 6 This is a fifth structural diagram of the chip filter circuit provided in the embodiment of the present application.

[0056] exist Figure 6 In the embodiment, the chip filter circuit 100 includes a power amplifier 10, a filter circuit 20, a signal source 30 and a DC blocking capacitor 40. The power amplifier 10 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a transistor G; the base of the transistor G serves as a signal input terminal of the power amplifier 10.

[0057] The filter circuit 20 may include a second filter unit 501 and a third filter unit 502. The second filter unit 501 includes a second inductor L2, a second capacitor C2 and a fourth inductor L4; the third filter unit 502 includes a third inductor L3 and a third capacitor C3.

[0058] The first end of the second capacitor C2 is electrically connected to the DC blocking capacitor 40, the second end of the second capacitor C2 is electrically connected to the first end of the second inductor L2, the first end of the third capacitor C3 and the first end of the third inductor L3 respectively; the second end of the third inductor L3 is electrically connected to the base of the transistor G; the second end of the second inductor L2 and the second end of the third capacitor C3 are grounded, and the fourth inductor L4 is connected in parallel with the second capacitor C2. The power supply terminal of the power amplifier 10 is electrically connected to the power supply VDD.

[0059] In the embodiment of the present application, the fourth inductor and the second capacitor form a resonant structure, which can add a pole in the adjacent frequency region near the passband of the mirror filter circuit, thereby achieving rapid attenuation of out-of-band signals and further improving the anti-interference performance of the power amplifier.

[0060] In some possible implementations of the present application, out-of-band suppression can be improved by adding poles, but when the capacitor or inductor is not properly selected, the frequency of the resonant pole may be close to the passband frequency, which will affect the in-band signal. Based on this, further, the adjacent frequency suppression capability can be improved by introducing a switch at the resonant pole and controlling whether to add a pole by the switch.

[0061] In some possible implementations of the embodiment of the present application, the second filtering unit in the embodiment of the present application may further include a first switch; the first switch is connected in series with the fourth inductor. Figure 7 As shown, Figure 7 This is a sixth structural diagram of the chip filter circuit provided in an embodiment of the present application.

[0062] exist Figure 7 In the embodiment, the chip filter circuit 100 includes a power amplifier 10, a filter circuit 20, a signal source 30 and a DC blocking capacitor 40. The power amplifier 10 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a transistor G; the base of the transistor G serves as a signal input terminal of the power amplifier 10.

[0063] The filter circuit 20 may include a second filter unit 501 and a third filter unit 502. The second filter unit 501 includes a second inductor L2, a second capacitor C2, a fourth inductor L4 and a first switch SW1; the third filter unit 502 includes a third inductor L3 and a third capacitor C3.

[0064] The first end of the second capacitor C2 is electrically connected to the DC blocking capacitor 40, the second end of the second capacitor C2 is electrically connected to the first end of the second inductor L2, the first end of the third capacitor C3 and the first end of the third inductor L3 respectively; the second end of the third inductor L3 is electrically connected to the base of the transistor G; the second end of the second inductor L2 and the second end of the third capacitor C3 are grounded, and the fourth inductor L4 and the first switch SW1 are connected in series and then connected in parallel with the second capacitor C2. The power supply end of the power amplifier 10 is electrically connected to the power supply VDD.

[0065] In the embodiment of the present application, a switch is introduced at the resonant pole formed by the fourth inductor and the second capacitor, and the adjacent frequency suppression capability is improved by controlling whether to add the pole through the switch.

[0066] In some possible implementations of the embodiment of the present application, the second capacitor C2 is an adjustable capacitor, and the fourth inductor L4 is an adjustable inductor.

[0067] In the embodiment of the present application, the pole can be frequency-shifted by means of adjustable capacitance and adjustable inductance, thereby achieving adjustability of adjacent frequency suppression capability while ensuring the passband performance.

[0068] In some possible implementations of the embodiments of the present application, the second filtering unit may further include: a fifth inductor; and the second capacitor is electrically connected to the DC blocking capacitor via the fifth inductor. Figure 8 As shown, Figure 8 This is a seventh structural schematic diagram of the integrated chip provided in the embodiment of the present application.

[0069] exist Figure 8 In the embodiment, the chip filter circuit 100 includes a power amplifier 10, a filter circuit 20, a signal source 30 and a DC blocking capacitor 40. The power amplifier 10 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a transistor G; the base of the transistor G serves as a signal input terminal of the power amplifier 10.

[0070] The filter circuit 20 may include a second filter unit 501 and a third filter unit 502. The second filter unit 501 includes a second inductor L2, a second capacitor C2 and a fifth inductor L5; the third filter unit 502 includes a third inductor L3 and a third capacitor C3.

[0071] The first end of the fifth inductor L5 is electrically connected to the DC blocking capacitor 40, the second end of the fifth inductor L5 is electrically connected to the first end of the second capacitor C2, the second end of the second capacitor C2 is electrically connected to the first end of the second inductor L2, the first end of the third capacitor C3 and the first end of the third inductor L3 respectively; the second end of the third inductor L3 is electrically connected to the base of the transistor G; the second end of the second inductor L2 and the second end of the third capacitor C3 are grounded. The power supply terminal of the power amplifier 10 is electrically connected to the power supply VDD.

[0072] In the embodiment of the present application, the fifth inductor can further improve the filtering effect of the filtering circuit and improve the anti-interference performance of the power amplifier.

[0073] Figure 5 The chip filter circuit in the embodiment can perform bandpass filtering, but the suppression and attenuation of the adjacent frequency interference signal beside the bandpass is poor, and it is difficult to achieve rapid attenuation of the interference signal in the adjacent band. Based on this, further, by adding an inductor in series with the third capacitor C3 in the third filtering unit 502, the resonant structure of the mirror filter circuit can be increased, so that a pole can be added in the adjacent frequency region near the bandpass of the mirror filter circuit, and rapid attenuation of the out-of-band signal can be achieved, thereby further improving the anti-interference performance of the power amplifier.

[0074] In some possible implementations of the embodiments of the present application, the third filtering unit may further include: a sixth inductor; and the second end of the third capacitor is grounded through the sixth inductor. Fig. 9 As shown, Fig. 9 This is the eighth structural schematic diagram of the integrated chip provided in the embodiment of the present application.

[0075] exist Fig. 9 In the embodiment, the chip filter circuit 100 includes a power amplifier 10, a filter circuit 20, a signal source 30 and a DC blocking capacitor 40. The power amplifier 10 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a transistor G; the base of the transistor G serves as a signal input terminal of the power amplifier 10.

[0076] The filter circuit 20 may include a second filter unit 501 and a third filter unit 502. The second filter unit 501 includes a second inductor L2 and a second capacitor C2; the third filter unit 502 includes a third inductor L3, a third capacitor C3 and a sixth inductor L6.

[0077] The first end of the second capacitor C2 is electrically connected to the DC blocking capacitor 40, the second end of the second capacitor C2 is electrically connected to the first end of the second inductor L2, the first end of the third capacitor C3 and the first end of the third inductor L3 respectively; the second end of the third inductor L3 is electrically connected to the base of the transistor G; the second end of the third capacitor C3 is electrically connected to the first end of the sixth inductor L6, and the second end of the second inductor L2 and the second end of the sixth inductor L6 are grounded. The power supply terminal of the power amplifier 10 is electrically connected to the power supply VDD.

[0078] In the embodiment of the present application, the sixth inductor and the third capacitor form a resonant structure, which can add a pole in the adjacent frequency region near the passband of the mirror filter circuit, thereby achieving rapid attenuation of out-of-band signals and further improving the anti-interference performance of the power amplifier.

[0079] In some possible implementations of the present application, out-of-band suppression can be improved by adding poles, but when the capacitor or inductor is not properly selected, the frequency of the resonant pole may be close to the passband frequency, which will affect the in-band signal. Based on this, further, the adjacent frequency suppression capability can be improved by introducing a switch at the resonant pole and controlling whether to add a pole by the switch.

[0080] In some possible implementations of the embodiments of the present application, the third filtering unit may further include: a seventh inductor and a second switch; the second switch is connected in series with the sixth inductor or the seventh inductor. Fig.10 As shown, Fig.10 This is the ninth structural schematic diagram of the chip filter circuit provided in the embodiment of the present application.

[0081] exist Fig.10In the embodiment, the chip filter circuit 100 includes a power amplifier 10, a filter circuit 20, a signal source 30 and a DC blocking capacitor 40. The power amplifier 10 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a transistor G; the base of the transistor G serves as a signal input terminal of the power amplifier 10.

[0082] The filter circuit 20 may include a second filter unit 501 and a third filter unit 502. The second filter unit 501 includes a second inductor L2 and a second capacitor C2; the third filter unit 502 includes a third inductor L3, a third capacitor C3, a sixth inductor L6, a seventh inductor L7 and a second switch SW2.

[0083] The first end of the second capacitor C2 is electrically connected to the DC blocking capacitor 40, the second end of the second capacitor C2 is electrically connected to the first end of the second inductor L2, the first end of the third capacitor C3 and the first end of the third inductor L3 respectively; the second end of the third inductor L3 is electrically connected to the base of the transistor G; the second end of the third capacitor C3 is electrically connected to the first end of the sixth inductor L6, the seventh inductor L7 and the second switch SW2 are connected in series and then connected in parallel with the sixth inductor L6, and the second end of the second inductor L2 and the second end of the sixth inductor L6 are grounded. The power supply end of the power amplifier 10 is electrically connected to the power supply VDD.

[0084] In the embodiment of the present application, a switch is introduced at the resonant pole formed by the sixth inductor and the third capacitor, and the adjacent frequency suppression capability is improved by controlling whether to add the pole through the switch.

[0085] In some possible implementations of the embodiment of the present application, the third capacitor is an adjustable capacitor, and the sixth inductor and the seventh inductor are adjustable inductors.

[0086] In the embodiment of the present application, the pole can be frequency-shifted by means of adjustable capacitance and adjustable inductance, thereby achieving adjustability of adjacent frequency suppression capability while ensuring the passband performance.

[0087] In some possible implementations of the embodiments of the present application, the third filtering unit may further include: a fourth capacitor; and the third inductor is electrically connected to the signal input terminal of the power amplifier via the fourth capacitor. Fig.11 As shown, Fig.11 This is the tenth structural schematic diagram of the integrated chip provided in the embodiment of the present application.

[0088] exist Fig.11 In the embodiment, the chip filter circuit 100 includes a power amplifier 10, a filter circuit 20, a signal source 30 and a DC blocking capacitor 40. The power amplifier 10 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a transistor G; the base of the transistor G serves as a signal input terminal of the power amplifier 10.

[0089] The filter circuit 20 may include a second filter unit 501 and a third filter unit 502. The second filter unit 501 includes a second inductor L2 and a second capacitor C2; the third filter unit 502 includes a third inductor L3, a third capacitor C3 and a fourth capacitor C4.

[0090] The first end of the second capacitor C2 is electrically connected to the DC blocking capacitor 40, and the second end of the second capacitor C2 is electrically connected to the first end of the second inductor L2, the first end of the third capacitor C3 and the first end of the third inductor L3 respectively; the second end of the third inductor L3 is electrically connected to the first end of the fourth capacitor C4, and the second end of the fourth capacitor C4 is electrically connected to the base of the transistor G; the second end of the second inductor L2 and the second end of the third capacitor C3 are grounded. The power supply terminal of the power amplifier 10 is electrically connected to the power supply VDD.

[0091] In the embodiment of the present application, the fourth capacitor can further improve the filtering effect of the filtering circuit and improve the anti-interference performance of the power amplifier.

[0092] Fig.12 It is a specific structural diagram of the chip filter circuit provided in an embodiment of the present application.

[0093] exist Fig.12 In the embodiment, the chip filter circuit 100 includes a power amplifier 10, a filter circuit 20, a signal source 30 and a DC blocking capacitor 40. The power amplifier 10 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a transistor G; the base of the transistor G serves as a signal input terminal of the power amplifier 10.

[0094] The filter circuit 20 may include a second filter unit 501 and a third filter unit 502. The second filter unit 501 includes a second inductor L2, a fifth inductor L5 and a second capacitor C2; the third filter unit 502 includes a third inductor L3, a third capacitor C3 and a fourth capacitor C4.

[0095] The first end of the DC blocking capacitor 40 is electrically connected to the signal source 30, the second end of the DC blocking capacitor 40 is electrically connected to the first end of the fifth inductor L5, the second end of the fifth inductor L5 is electrically connected to the first end of the second capacitor C2, the second end of the second capacitor C2 is electrically connected to the first end of the second inductor L2, the first end of the third capacitor C3 and the first end of the third inductor L3 respectively; the second end of the third inductor L3 is electrically connected to the first end of the fourth capacitor C4, the second end of the fourth capacitor C4 is electrically connected to the base of the transistor G; the second end of the second inductor L2 and the second end of the third capacitor C3 are grounded. The power supply end of the power amplifier 10 is electrically connected to the power supply VDD.

[0096] exist Fig.12In the figure, the second inductor L2, the fifth inductor L5, the second capacitor C2, the third inductor L3, the third capacitor C3 and the fourth capacitor C4 are combined into a T-type mirror filter circuit, but this does not limit the shape of the mirror filter circuit and the number of capacitors and inductors included in the second filtering unit 501 and the third filtering unit 502. They can be set according to actual needs and are not limited in the embodiments of the present application.

[0097] Fig.12 The chip filter circuit in the embodiment can perform bandpass filtering, but the suppression and attenuation of adjacent-band interference signals beside the passband is poor, and it is difficult to achieve rapid attenuation of interference signals in the adjacent band. Based on this, further, by adding an inductor in parallel with the second capacitor C2 in the second filter unit 501, or by adding an inductor in series with the third capacitor C3 in the third filter unit 502, the resonant structure of the mirror filter circuit can be increased, so that poles can be added in the adjacent-band region near the passband of the mirror filter circuit, and rapid attenuation of out-of-band signals can be achieved, further improving the anti-interference performance of the power amplifier. Fig.13 As shown, Fig.13 It is another specific structural schematic diagram of the chip filter circuit provided in an embodiment of the present application.

[0098] exist Fig.13 In the embodiment, the chip filter circuit 100 includes a power amplifier 10, a filter circuit 20, a signal source 30 and a DC blocking capacitor 40. The power amplifier 10 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a transistor G; the base of the transistor G serves as a signal input terminal of the power amplifier 10.

[0099] The filter circuit 20 may include a second filter unit 501 and a third filter unit 502. The second filter unit 501 includes a second inductor L2, a fourth inductor L4, a fifth inductor L5, a first switch SW1 and a second capacitor C2; the third filter unit 502 includes a third inductor L3, a sixth inductor L6, a seventh inductor L7, a third capacitor C3, a fourth capacitor C4 and a second switch SW2.

[0100] The first end of the DC blocking capacitor 40 is electrically connected to the signal source 30, the second end of the DC blocking capacitor 40 is electrically connected to the first end of the fifth inductor L5, the second end of the fifth inductor L5 is electrically connected to the first end of the second capacitor C2, the second end of the second capacitor C2 is electrically connected to the first end of the second inductor L2, the first end of the third capacitor C3 and the first end of the third inductor L3 respectively; the fourth inductor L4 is connected in series with the first switch SW1 and then connected in parallel with the second capacitor C2; the second end of the third inductor L3 is electrically connected to the first end of the fourth capacitor C4, and the second end of the fourth capacitor C4 is electrically connected to the base of the transistor G; the second end of the third capacitor C3 is electrically connected to the first end of the sixth inductor L6, and the second end of the second inductor L2 and the second end of the sixth inductor L6 are grounded. The seventh inductor L7 is connected in series with the second switch SW2 and then connected in parallel with the sixth inductor L6; the power supply end of the power amplifier 10 is electrically connected to the power supply VDD.

[0101] In an embodiment of the present application, by adding a pole in the adjacent frequency region near the passband of the mirror filter circuit, rapid attenuation of out-of-band signals is achieved, thereby further improving the anti-interference performance of the power amplifier; in addition, by introducing a switch at the resonant pole, the adjacent frequency suppression capability is improved by controlling whether to add the pole through the switch; the pole can be frequency-shifted through adjustable capacitance and adjustable inductance, thereby achieving the adjustability of the adjacent frequency suppression capability while ensuring the passband performance.

[0102] In some possible implementations of the embodiments of the present application, the first switch and the second switch in the embodiments of the present application can be any electronic switches, such as: triodes, transistors, relays, field effect transistors, etc., which can be specifically set according to actual needs, and the embodiments of the present application are not limited here.

[0103] The embodiment of the present application also provides an integrated chip, which includes the chip filter circuit provided in the embodiment of the present application.

[0104] An embodiment of the present application also provides an electronic device, which includes the integrated chip provided in the embodiment of the present application.

[0105] The electronic device in the embodiment of the present application may be a terminal, or may be other devices other than a terminal. For example, the electronic device may be a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted electronic device, a mobile Internet device (MID), an augmented reality (AR) / virtual reality (VR) device, a robot, a wearable device, an ultra-mobile personal computer (UMPC), a netbook or a personal digital assistant (PDA), etc., and may also be a server, a network attached storage (NAS), a personal computer (PC), a television (TV), a teller machine or a self-service machine, etc., which is not specifically limited in the embodiment of the present application.

[0106] The electronic device in the embodiment of the present application may be an electronic device having an operating system. The operating system may be an Android operating system, an iOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0107] Fig.14 It is a schematic diagram of the hardware structure of the electronic device provided in the embodiment of the present application.

[0108] The electronic device 1400 includes but is not limited to: a radio frequency unit 1401, a network module 1402, an audio output unit 1403, an input unit 1404, a sensor 1405, a display unit 1406, a user input unit 1407, an interface unit 1408, a memory 1409, and a processor 1410 and other components.

[0109] Those skilled in the art will appreciate that the electronic device 1400 may also include a power source (such as a battery) for supplying power to each component, and the power source may be logically connected to the processor 1410 through a power management system, thereby implementing functions such as managing charging, discharging, and power consumption management through the power management system. Fig.14 The electronic device structure shown in the figure does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently, which will not be described in detail here.

[0110] Among them, the electronic device 1400 also includes the integrated chip provided in the embodiment of the present application.

[0111] It should be understood that in the embodiment of the present application, the input unit 1404 may include a graphics processor (Graphics Processing Unit, GPU) 14041 and a microphone 14042, and the graphics processor 14041 processes the image data of the static picture or video obtained by the image capture device (such as a camera) in the video capture mode or the image capture mode. The display unit 1406 may include a display panel 14061, and the display panel 14061 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc. The user input unit 1407 includes a touch panel 14071 and at least one of other input devices 14072. The touch panel 14071 is also called a touch screen. The touch panel 14071 may include two parts: a touch detection device and a touch controller. Other input devices 14072 may include, but are not limited to, a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and a joystick, which will not be repeated here.

[0112] The memory 1409 can be used to store software programs and various data. The memory 1409 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, an application program or instructions required for at least one function (such as a sound playback function, an image playback function, etc.), etc. In addition, the memory 1409 may include a volatile memory or a non-volatile memory, or the memory 1409 may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDRSDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synchronous link dynamic random access memory (SLDRAM) and a direct memory bus random access memory (DRRAM). The memory 1409 in the embodiment of the present application includes but is not limited to these and any other suitable types of memory.

[0113] The processor 1410 may include one or more processing units; optionally, the processor 1410 integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to an operating system, a user interface, and application programs, and the modem processor mainly processes wireless communication signals, such as a baseband processor. It is understandable that the modem processor may not be integrated into the processor 1410.

[0114] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0115] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A chip filter circuit, characterized in that: The chip filter circuit comprises: a signal source, a DC blocking capacitor, a filter circuit and a power amplifier; The DC blocking capacitor is arranged between the signal source and the filter circuit; The filter circuit is arranged between the DC blocking capacitor and the signal input terminal of the power amplifier; The filtering circuit comprises at least one filtering unit; The filtering circuit supports filtering at at least one frequency point.

2. The chip filter circuit according to claim 1, characterized in that: The filtering circuit comprises a first filtering unit, wherein the first filtering unit comprises a first inductor and a first capacitor; The first inductor and the first capacitor are connected in parallel.

3. The chip filter circuit according to claim 1, characterized in that: The filtering circuit includes a second filtering unit and a third filtering unit; The second filtering unit includes a second inductor and a second capacitor; The third filtering unit includes a third inductor and a third capacitor; The first end of the second capacitor is electrically connected to the DC blocking capacitor, and the second end of the second capacitor is electrically connected to the first end of the second inductor, the first end of the third capacitor, and the first end of the third inductor respectively; The second end of the third inductor is electrically connected to the signal input end of the power amplifier; A second end of the second inductor and a second end of the third capacitor are grounded.

4. The chip filter circuit according to claim 3, characterized in that: The second filtering unit further includes: a fourth inductor; The fourth inductor is connected in parallel with the second capacitor.

5. The chip filter circuit according to claim 4, characterized in that: The second filtering unit further includes: a first switch; The first switch is connected in series with the fourth inductor.

6. The chip filter circuit according to claim 4 or 5, characterized in that: The second capacitor is an adjustable capacitor, and the fourth inductor is an adjustable inductor.

7. The chip filter circuit according to claim 3, characterized in that: The second filtering unit further includes: a fifth inductor; The second capacitor is electrically connected to the DC blocking capacitor through the fifth inductor.

8. The chip filter circuit according to claim 3, characterized in that: The third filtering unit further includes: a sixth inductor; The second end of the third capacitor is grounded through the sixth inductor.

9. The chip filter circuit according to claim 8, characterized in that: The third filtering unit further includes: a seventh inductor and a second switch; The seventh inductor is connected in parallel with the sixth inductor; The second switch is connected in series with the sixth inductor or the seventh inductor.

10. The chip filter circuit according to claim 9, characterized in that: The sixth inductor and the seventh inductor are adjustable inductors, and the third capacitor is an adjustable capacitor.

11. The chip filter circuit according to claim 3, characterized in that: The third filtering unit further includes: a fourth capacitor; The third inductor is electrically connected to the signal input terminal of the power amplifier through the fourth capacitor.

12. An integrated chip, characterized in that: The integrated chip comprises: The chip filter circuit according to any one of claims 1 to 11.

13. An electronic device, characterized in that: The electronic device comprises: The integrated chip as claimed in claim 12.

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