Error code block marking method, electronic equipment and computer readable storage medium

Abstract

The invention provides an error code block marking method, electronic equipment and a computer readable storage medium, and the method comprises the steps: carrying out the first processing of a code stream received from an Ethernet interface, and obtaining a first code stream, the first processing at least comprises the decoding of a first forward error correction code (FEC), and the first code stream is a 257B code stream; for FEC uncorrectable errors occurring in the FEC decoding process, performing error marking on n 257B code blocks in the first code stream to obtain a second code stream, n being an integer greater than or equal to 1; and performing second processing on the second code stream so as to map the second code stream into a signal container of an optical transport network OTN. According to the embodiment of the invention, the method can solve a problem that an OTN node cannot achieve an error marking function for an Ethernet service employing a 257B reference point, and can improve the MTTFPA problem.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to an error code block marking method, an electronic device, and a computer-readable storage medium. Background Art

[0002] Optical Transport Network (OTN) refers to a transmission network that implements the transmission, multiplexing, routing, and monitoring of service signals in the optical domain, and guarantees its performance indicators and survivability. With the rapid growth of network service throughput, the bandwidth demand of communication equipment has also increased rapidly. OTN has been upgraded from 400 Gigabit Ethernet (GE) to support access transmission of 800GE services. Compared with Ethernet services at 400GE rates and below (400GE / 200GE / 100GE / 10GE), in order to save transmission bandwidth, narrow the gap between Ethernet service rates and OTN rates, and increase the possibility of using the same module for Ethernet services and OTN rates, the mapping reference point from 800GE to OTN has been changed from 66B code stream to 257B code stream. However, the current error marking function of the OTN Ethernet interface is for 66B code streams. When the mapping reference point is changed to 257B code streams, the error marking function of the OTN Ethernet interface cannot take effect on the 257B code stream and will cause the mean time to false package acceptance (MTTFPA) problem. Summary of the invention

[0003] The embodiments of the present application provide an error code block marking method, an electronic device, and a computer-readable storage medium, which are intended to solve the problem that an OTN node cannot implement an error marking function for Ethernet services using a 257B reference point.

[0004] In a first aspect, an embodiment of the present application provides a method for marking an error code block, the method comprising:

[0005] Performing a first process on a code stream received from an Ethernet interface to obtain a first code stream, wherein the first process includes first forward error correction code FEC decoding, and the first code stream is a 257B code stream;

[0006] In response to an FEC uncorrectable error occurring during the FEC decoding process, marking n 257B code blocks in the first code stream as errors to obtain a second code stream, where n is an integer greater than or equal to 1;

[0007] The second code stream is subjected to a second processing so as to map the second code stream into a signal container of an optical transport network OTN.

[0008] In a second aspect, an embodiment of the present application provides an error code block marking device, the device comprising:

[0009] A first processing module, configured to perform a first processing on a code stream received from an Ethernet interface to obtain a first code stream, wherein the first processing includes first forward error correction code FEC decoding, and the first code stream is a 257B code stream;

[0010] an error marking module, configured to mark the n 257B code blocks in the first code stream as errors in response to an FEC uncorrectable error occurring during the FEC decoding process, so as to obtain a second code stream, wherein n is an integer greater than or equal to 1;

[0011] The second processing module is used to perform second processing on the second code stream to map the second code stream into a signal container of an optical transport network OTN.

[0012] In a third aspect, an embodiment of the present application provides an electronic device, including:

[0013] one or more processors;

[0014] A memory having one or more programs stored thereon, when the one or more programs are executed by the one or more processors, the one or more processors implement the error code block marking method as described in the first aspect above.

[0015] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon, and when the program is executed by a processor, the error code block marking method as described in the first aspect above is implemented.

[0016] In an embodiment of the present application, a code stream received from an Ethernet interface is first processed to obtain a first code stream using 257B encoding, wherein the first processing includes FEC decoding; in response to an FEC uncorrectable error occurring during the FEC decoding process, n 257B code blocks in the first code stream are error marked to obtain a second code stream carrying an error mark; the second code stream is then mapped to a signal container of an optical transport network OTN, so that the second code stream can be transmitted to an Ethernet sink node through the OTN, thereby solving the problem that the OTN node cannot implement an error marking function for Ethernet services using a 257B reference point, and can improve the MTTFPA problem. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the process of transmitting 400GE services to the opposite Ethernet node through OTN in the related technology;

[0018] Figure 2It is a schematic diagram of the process of transmitting 800GE services to the opposite Ethernet node through OTN in the related technology;

[0019] Figure 3 It is a flowchart of an error code block marking method provided in an embodiment of the present application;

[0020] Figure 4a It is a format diagram of a type A 257B error code block provided in an embodiment of the present application;

[0021] Figure 4b It is a format diagram of a type B 257B error code block provided in an embodiment of the present application;

[0022] Figure 5 This is an optional flow diagram of transmitting an 800GE service to a peer Ethernet node through an OTN provided in an embodiment of the present application;

[0023] Figure 6 This is an optional flow diagram of transmitting an 800GE service to a peer Ethernet node through an OTN provided in an embodiment of the present application;

[0024] Figure 7 It is a schematic diagram of an error marking processing method for an 800GE service transmitted to a peer Ethernet node through an OTN provided in an embodiment of the present application;

[0025] Figure 8 is a schematic diagram of an error code block marking device provided in an embodiment of the present application;

[0026] Fig. 9 It is a schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] In order to enable those skilled in the art to better understand the technical solution of the present application, the error code block marking method, electronic device and computer-readable storage medium provided by the present application are described in detail below in conjunction with the accompanying drawings.

[0028] Hereinafter, example embodiments will be described more fully in conjunction with the accompanying drawings, but the described example embodiments may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, the purpose of providing these embodiments is to make this application thorough and complete, and will enable those skilled in the art to fully understand the scope of this application.

[0029] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0030] The terms used herein are only used to describe specific embodiments and are not intended to limit the present application. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded.

[0031] In the description of the embodiments of the present application, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it can be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0032] In the description of the embodiments of the present application, any embodiment or design scheme of "exemplary", "for example" or "for example" should not be understood as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary", "for example" or "for example" is intended to present related concepts in a specific way.

[0033] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. The terms "include", "comprises", "has" and their variations all mean "including but not limited to", unless otherwise specifically emphasized.

[0034] In order to facilitate understanding of the solutions of the embodiments of the present application and to provide a clear and concise description of the following embodiments, a brief introduction to the relevant technology is first given.

[0035] (1) Optical Transport Network (OTN) refers to a transmission network that implements the transmission, multiplexing, routing, and monitoring of service signals in the optical domain and ensures their performance indicators and survivability.

[0036] OTN is divided into client signal layer, Optical Payload Unit (OPU), Optical Data Unit (ODU), Optical Transport Unit (OTU), Optical Channel layer (OCh), Optical Multiplex Section layer (OMS), Optical Transmission Section layer (OTS). The former is the client layer of the latter, and the latter is the service layer of the former. Among them, the client signal layer refers to the signal to be carried by the OTN network, such as SDHQ, Ethernet, IP services, etc.; the optical channel payload unit OPU is mainly used to adapt the client signal to make it suitable for transmission on the optical channel, that is: a "container" that carries the client signal. The overhead of this layer is mainly used to indicate the process of mapping the client signal to the OTN signal; the optical channel data unit ODU is composed of the OPU layer and the ODU layer related overhead. The overhead of this layer can support end-to-end detection of the transmission signal quality; the optical channel transport unit OTU is the basic unit structure for transmitting information on the optical path, which is composed of the ODU layer and the OTU layer related overhead; the optical channel layer OCh is an optical signal with a specific wavelength and a special frame format, where the special frame format is defined by the OTU layer; the optical multiplexing section layer OMS is a multi-wavelength optical signal that has been processed by multiplexing; the optical transmission section layer OTS is an optical signal processed by the amplifier OA, etc.

[0037] When an Ethernet data packet arrives at OTN, OTN will encapsulate and convert the data packet. The specific processing flow includes: at the sending end, the Ethernet data packet is connected to OTN through the client board and converted into OPU, that is, the Ethernet data packet is encapsulated into an OPU optical signal. OPU is the most basic transmission unit in OTN, which includes data packets and some control information; next, OTN further encapsulates the OPU optical signal and converts it into ODU optical signal. The ODU optical signal is connected and converted into OTU optical signal through the line board, and multiple OTU optical signals are multiplexed together through the combiner and transmitted on the same optical fiber; the optical signal is regenerated and amplified through the OA optical amplifier on the optical fiber transmission path to ensure that the optical signal can be transmitted over long distances; at the receiving end, the optical signal is demultiplexed through the splitter to separate multiple optical signals, which are processed by the line board and the client board to output Ethernet service signals.

[0038] (2) Forward Error Correction (FEC) refers to the pre-coding of signals before they are transmitted. Coding means that the sender sends a code that can correct errors. The receiver automatically corrects errors that occur during transmission based on the received code and decoding rules, so as to find and correct the error codes. Forward error correction methods include Reed-Solomon Forward Error Correction (RS-FEC). The RS-FEC solution can be used for the coding schemes of 100GE, 200GE, 400GE, and 800GE Ethernet services.

[0039] (3) Mean Time to False Package Acceptance (MTTFPA) refers to the average time before failure. MTTF can be used to measure the probability and frequency of system failure. Generally speaking, the longer the MTTF, the higher the stability of the system.

[0040] (4) 66B code stream refers to a code stream using the 66B encoding format, which is composed of multiple 66-bit blocks (66B blocks). Each 66-bit block contains 66 bits and uses the 64B / 66B encoding format. The first two bits of the 66-bit block can be called a synchronization header. A 66-bit block with a synchronization header of 01 can be called a 64B / 66B data coding block, indicating that the last 64 bits of the 66-bit block are all data information; a 66-bit block with a synchronization header of 10 can be called a 64B / 66B control coding block, indicating that the last 64 bits of the 66-bit block are a mixture of data information and control information, or are all control information. When the values ​​of the two bits in the synchronization header are the same (the synchronization header is 00 or 11), the synchronization header is an invalid synchronization header, and the 66-bit block with an invalid synchronization header is an error code block.

[0041] (5) 257B code stream refers to a code stream using the 257B encoding format, which consists of multiple 257-bit blocks (257B blocks). Each 257-bit block contains 257 bits.

[0042] With the rapid growth of network service throughput, the bandwidth demand of communication equipment has also increased rapidly. OTN has been upgraded from 400GE to support the access and transmission of 800GE services. When services below 400G (including 400GE, 200GE, 100GE and 10GE services) are mapped to OTN, the OTN reference point is 66B code stream; for services above 400G, the embodiment of this application refers to 800GE services, when mapped to OTN, the OTN reference point is 257B code stream.

[0043] See also Figure 1 , Figure 1 It is a schematic diagram of the process of transmitting 400GE services to the opposite Ethernet node through OTN in the related technology. Figure 1 The network shown includes Ethernet node 1, OTN node 1, OTN node 2 and Ethernet node 2. Ethernet node 1 is connected to OTN node 1 via a 400G Attachment Unit Interface (AUI), OTN node 2 is connected to Ethernet node 2 via a 400G AUI, and OTN node 1 is connected to OTN node 2 via an OTN link (OTNlink), which may include multiple OTN nodes. Figure 1 In this example, the 800G Ethernet service code stream needs to be transmitted from Ethernet node 1 to Ethernet node 2 via the OTN link. After Ethernet node 1 performs RS-FEC encoding on the 400G Ethernet service code stream, it sends the RS-FEC-encoded code stream to OTN node 1 through the 400G AUI. Since the mapping reference point of the 400GE service in OTN is a 66B code stream, after OTN node 1 receives the 400G code stream from the 400G AUI interface, it first performs RS-FEC decoding and 257B to 66B transcoding on the code stream. When an uncorrectable error occurs during the FEC decoding process, during the 257B to 66B transcoding process, the 66B code block corresponding to the 20*257B code block involved in the RS-FEC codeword is marked as an error. The error marking method can be to replace the synchronization header of the 66B code block with an invalid synchronization header (the synchronization header after replacement is 00 or 11); next, the 66B code stream is mapped to the signal container ODU flex and transmitted to the OTN node 2 through the OTN link. After receiving the 66B code stream, the OTN node 2 performs 66B synchronization positioning of the 66B code block to demap the 66B code block from the ODU flex frame, where the marked invalid 66B code block is converted into an Ethernet local fault (Local False, LF) code blocks or idle (Idle) code blocks, and perform 66B to 257B transcoding processing, and send 257B code stream Ethernet node 2. During this process, LF code blocks or Idle code blocks will be filtered to ensure that these code blocks that may contain code errors will not be passed to the MAC layer of Ethernet node 2.

[0044] See also Figure 2 , Figure 2 It is a schematic diagram of the process of transmitting 800GE services to the opposite Ethernet node through OTN in the related technology. Figure 1The network shown includes Ethernet node 1, OTN node 1, OTN node 2 and Ethernet node 2. Ethernet node 1 is connected to OTN node 1 via 800G AUI, OTN node 2 is connected to Ethernet node 2 via 800G AUI, and OTN node 1 and OTN node 2 are connected via an OTN link, which may include multiple OTN nodes. Figure 2 In the example, the 800G Ethernet service code stream needs to be transmitted from Ethernet node 1 to Ethernet node 2 via the OTN link. The 800G Ethernet service flow is divided into two 400G code streams for PCS / FEC processing. The relevant technology adopts the FEC error marking method consistent with the 400GE service. In order to avoid MTTFPA problems for MAC, when the 800GAUI interface detects an uncorrectable error during the RS-FEC process, it still uses the FEC error marking method of 400GE to replace the invalid synchronization header when transcoding from 257B to 66B. This method is effective when the Ethernet service does not pass through the OTN link and is only transmitted through the Ethernet link. However, for the case where the Ethernet service needs to be transmitted through the OTN link, the error marking function will be invalid. When 800GE is mapped to ODUflex, 800GE is mapped to the OTN reference point as a 257B code stream. Therefore, OTN node 1 performs RS-FEC decoding and 257B to 66B transcoding on the two service code streams at the 800GAUI interface, and replaces the synchronization header of the 66B code block with an invalid synchronization header in accordance with the FEC error marking method consistent with the 400GE service, and then transcodes the 66B code stream into a 257B code stream to map it to ODU flex. However, the 66B code block marked invalid cannot be transcoded to 275B. In this way, the 66B code block marked invalid will not be transmitted to the OTN link. In other words, the existing FEC error marking function of Ethernet cannot guarantee an effective error marking function, so that this Ethernet link path will introduce the MTTFPA problem.

[0045] For 1.6TE services, they are also distributed through 257B code blocks. After the 1.6TE service code stream is output by MAC, it is divided into 4 400G 257B code streams at the PCS layer. Because the 257B code stream has a more compressed overhead ratio than the 66B code stream, its robustness is not as good as the 66B code stream. When the 257B code stream passes through a physical interface that may cause bit errors, it is necessary to consider supporting the error marking function. Among them, the FEC error marking function of the Ethernet interface is completed by replacing the 66B code block with an invalid synchronization header when transcoding from 257B to 66B. The mapping reference point of B400G Ethernet service (800GE / 1.6TE) to OTN is changed from the original 66B to 257B, which inevitably makes the error marking function of the Ethernet interface unable to take effect when the B400G Ethernet service is carried through the OTN link, resulting in MTTFPA problems.

[0046] In view of this, the embodiments of the present application provide an error code block marking method, an electronic device, and a computer-readable storage medium, which are suitable for error marking of services (including 800GE and 1.6TE services) mapped to OTN using 257B as a reference point, and are intended to solve the problem that OTN nodes cannot implement the error marking function for Ethernet services using a 257B reference point.

[0047] See also Figure 3 , Figure 3 1 is a flow chart of an error code block marking method provided in an embodiment of the present application. The error code block marking method is applied in an OTN node, and includes the following steps:

[0048] In step S110, the OTN node performs a first process on the code stream received from the Ethernet interface to obtain a first code stream, wherein the first process at least includes first forward error correction code FEC decoding, and the first code stream is a 257B code stream.

[0049] In an exemplary embodiment, Ethernet node 1 (such as a routing device or a gateway device) sends a code stream of an 800GE service to OTN node 1 through an Ethernet interface, so as to transmit the 800GE service to the Ethernet node 2 at the opposite end through OTN. The code stream of the 800GE service is divided into two parallel 400G code streams at the PCS layer and enters OTN node 1, and the two parallel 400G code streams are both code streams in 275B format. After receiving the two parallel 400G code streams from the Ethernet interface, OTN node 1 performs a first processing on each code stream to obtain a first code stream after the first processing.

[0050] It should be noted that the first processing in the embodiment of the present application at least includes FEC decoding. In addition to FEC decoding, the first processing may also include one or more of the following processing: multi-channel alignment, alignment marker AM locking, channel de-skew, channel sorting and FEC codeword deinterleaving.

[0051] In an exemplary embodiment, after the code stream enters the OTN node through the Ethernet interface, the following first processing steps are performed in sequence: multi-channel alignment, AM locking, channel de-skew, channel sorting, FEC codeword deinterleaving and FEC decoding.

[0052] Step S120: The OTN node marks n 257B code blocks in the first code stream as errors in response to an FEC uncorrectable error that occurs during the FEC decoding process, to obtain a second code stream, where n is an integer greater than or equal to 1.

[0053] It should be noted that, when the OTN node decodes the code stream by FEC, if an FEC uncorrectable error occurs (i.e., the FEC codeword cannot be corrected), the n 257B code blocks in the first code stream are marked as errors, and the specific value of n is determined by the number of different FEC codewords and whether the related codewords affect each other. After the first code stream is marked as an error, the second code stream can be obtained.

[0054] In an exemplary embodiment, in response to an FEC uncorrectable error occurring during FEC decoding, n 257B code blocks in the first code stream may be replaced with 257B error code blocks to obtain a second code stream. In other words, n 257B code blocks in the first code stream may be directly replaced with 257B error code blocks.

[0055] See also Figure 4a , Figure 4a FIG. 2 shows a schematic diagram of the format of a type A 257B error code block provided in an embodiment of the present application. Figure 4a As shown, the A-type 257B error code block includes 257 bits, wherein the 0th bit is 0, the 1st bit to the 4th bit are 0xF (i.e., 0b1111), and the 5th bit to the 256th bit are 252 bits of information. The 252 bits of information may be any information, and the embodiment of the present application does not specifically limit the information content contained in the 252 bits of information.

[0056] See also Figure 4b , Figure 4b FIG. 2 shows a format diagram of a type B 257B error code block provided by an embodiment of the present application. Figure 4bAs shown, the B-type 257B error code block includes 257 bits, wherein the value of the 0th bit of the B-type 257B error code block is 0, the 1st bit to the 4th bit are all 0, the 5th bit to the 8th bit are 0xE, the 1st bit to the 8th bit are 0x0E (i.e., 0b00001110), the 9th bit to the 64th bit are 56 bits of information, the 65th bit to the 72nd bit are 0x1E (i.e., 0b00011110), the 73rd bit to the 128th bit are 56 bits of information, the 129th bit to the 136th bit are 0x1E (i.e., 0b00011110), the 137th bit to the 192th bit are 56 bits of information, the 193rd bit to the 200th bit are 0x1E (i.e., 0b00011110), and the 201st bit to the 256th bit are 56 bits of information. The 56-bit information may be any information, and the embodiment of the present application does not specifically limit the information content contained in the 56-bit information. In one example, the 56-bit information includes an error control code block / E / .

[0057] It should be noted that, in a specific implementation process, the n 257B code blocks in the first code stream may be replaced by any one of the above-mentioned type A 257B error code blocks and type B 257B error code blocks.

[0058] In an exemplary embodiment, the first code stream can be transcoded from 257B to 66B to obtain a third code stream, wherein the third code stream is a 66B code stream; in response to an FEC uncorrectable error occurring during FEC decoding, m 66B code blocks in the third code stream are replaced with 66B invalid code blocks to obtain a fourth code stream, wherein m is greater than or equal to 4 and m is a multiple of 4; the fourth code stream is transcoded from 66B to 257B, and every 4 66B invalid code blocks in the fourth code stream are replaced with 1 257B error code block to obtain a second code stream.

[0059] That is, the first code stream in 275B format is transcoded into the third code stream in 66B format, and then in view of the FEC uncorrectable error that occurs during the FEC decoding process, the m 66B code blocks of the n 257B code blocks that need to be marked as errors in the third code stream are marked as errors, and the error marking method of the 66B code blocks is to set the synchronization header of the 66B code blocks to "00" or "11", that is, the relevant 66B code blocks are replaced with 66B invalid code blocks, thereby obtaining a fourth code stream; then the fourth code stream is transcoded from 66B to 257B, and in the transcoding process, every 4 66B invalid code blocks are replaced with 1 257B error code block to obtain a second code stream.

[0060] In an exemplary embodiment, each of the four 66B invalid code blocks is replaced with one 257B error code block, including: each of the four 66B invalid code blocks is replaced with one A-type 257B error code block. Specifically, the 0th bit of the corresponding 257B code block can be set to 0 (a total of 1 bit), the 1st bit to the 4th bit can be set to 0xF (i.e., Ob1111, a total of 4 bits), the values ​​of the 2nd bit to the 5th bit and the 10th bit to the 65th bit of the 1st 66B code block are placed in the 5th bit to the 64th bit of the 257B code block (a total of 60 bits), and the 2nd bit to the 65th bit of the 2nd, 3rd, and 4th 66B code blocks are placed in the 65th bit to the 256th bit of the 257B code block (a total of 192 bits).

[0061] In an exemplary embodiment, each of the four 66B invalid code blocks is replaced with one 257B error code block, including: each of the four 66B invalid code blocks is replaced with one B-type 257B error code block. Specifically, the 0th bit of the corresponding 257B code block can be set to 0, the 1st bit to the 8th bit of the 257B code block can be set to 0x0E (i.e., 0b00001110), the 56-bit information of the first 66B invalid code block can be placed in the 9th bit to the 64th bit of the 257B code block, the 65th bit to the 72nd bit of the 257B code block can be set to 0x1E (i.e., 0b00011110), and the 56-bit information of the second 66B invalid code block can be placed in the 73rd bit of the 257B code block. The 129th to 136th bits of the 257B code block are set to 0x1E (i.e. 0b00011110), the 56-bit information of the third 66B invalid code block is placed at the 137th to 192th bits of the 257B code block, the 193rd to 200th bits of the 257B code block are set to 0x1E (i.e. 0b00011110), and the 56-bit information of the fourth 66B invalid code block is placed at the 201st to 256th bits of the 257B code block.

[0062] In an exemplary embodiment, an error mark enable signal may be output for FEC uncorrectable errors occurring during FEC decoding; during the duration of the error mark enable signal, a 257B code block in the first code stream is replaced with a 257B error code block to obtain a second code stream.

[0063] For example, when it is detected that the FEC decoding contains uncorrectable errors, an error mark enable signal is set to indicate all 257B blocks involved in the FEC codeword, and the duration of the error mark enable signal is aligned with the 257B codeword. When the error mark enable signal is effective, the corresponding 257B code block is replaced by a 257B error code block.

[0064] It should be noted that the 257B code block is replaced by a 257B error code block, which can be specifically replaced by a type A 257B error code block or a type B 257B error code block.

[0065] In an exemplary embodiment, the first code stream can be transcoded from 257B to 66B to obtain a third code stream, wherein the third code stream is a 66B code stream; in response to an FEC uncorrectable error occurring during the FEC decoding process, an error mark enable signal is output; within the duration of the error mark enable signal, the 66B code blocks in the third code stream are replaced with 66B invalid code blocks; the third code stream is transcoded from 66B to 257B, and every 4 66B invalid code blocks in the third code stream are replaced with 1 257B error code block to obtain a second code stream.

[0066] For example, a first code stream in 257B format is transcoded to obtain a third code stream in 66B format; during the transcoding process, an error mark enable signal is set for the uncorrectable 275 code blocks involved in FEC decoding, so that during the effective period of the error mark enable signal, the relevant 275 code blocks are converted into four 66B invalid code blocks respectively; next, the third code stream with error marking is transcoded to obtain a second code stream in 275B format, and each four 66B invalid code blocks in the third code stream are replaced by one 257B error code block to obtain a second code stream.

[0067] In an exemplary embodiment, each of four 66B invalid code blocks is replaced with one 257B error code block, including: each of four 66B invalid code blocks is replaced with one A-type 257B error code block. Specifically, the 0th bit of the corresponding 257B code block can be set to 0 (a total of 1 bit), the 1st bit to the 4th bit can be set to 0xF (a total of 4 bits), the values ​​of the 2nd bit to the 5th bit and the 10th bit to the 65th bit of the 1st 66B code block are placed in the 5th bit to the 64th bit of the 257B code block (a total of 60 bits), and the 2nd bit to the 65th bit of the 2nd, 3rd, and 4th 66B code blocks are placed in the 65th bit to the 256th bit of the 257B code block (a total of 192 bits).

[0068] In an exemplary embodiment, each of the four 66B invalid code blocks is replaced with one 257B error code block, including: each of the four 66B invalid code blocks is replaced with one B-type 257B error code block. Specifically, the 0th bit of the corresponding 257B code block can be set to 0, the 1st bit to the 8th bit of the 257B code block can be set to 0x0E (i.e., 0b00001110), the 56-bit information of the first 66B invalid code block can be placed in the 9th bit to the 64th bit of the 257B code block, the 65th bit to the 72nd bit of the 257B code block can be set to 0x1E (i.e., 0b00011110), and the 56-bit information of the second 66B invalid code block can be placed in the 73rd bit of the 257B code block. The 129th to 136th bits of the 257B code block are set to 0x1E (i.e. 0b00011110), the 56-bit information of the third 66B invalid code block is placed at the 137th to 192th bits of the 257B code block, the 193rd to 200th bits of the 257B code block are set to 0x1E (i.e. 0b00011110), and the 56-bit information of the fourth 66B invalid code block is placed at the 201st to 256th bits of the 257B code block.

[0069] Step S130: The OTN node performs a second process on the second code stream to map the second code stream into a signal container of the optical transport network OTN.

[0070] In an exemplary embodiment, the second process includes code stream interleaving and rate compensation.

[0071] In an exemplary embodiment, the second code stream is subjected to a second processing to map the second code stream to a signal container of an optical transport network OTN, specifically including: interleaving the second code stream with one or three fifth code streams to obtain one sixth code stream; and rate compensating the sixth code stream and mapping it to the signal container of the OTN, wherein the fifth code stream and the sixth code stream are both 257B code streams.

[0072] For example, 800GE services are divided into two code streams, flow0 and flow1. Flow0 and flow1 enter the OTN node through the Ethernet interface. The OTN node performs the first processing on flow0 and flow1 respectively to obtain flow0' and flow1'. In the FEC decoding process included in the first processing, flow0 has an uncorrectable error, so flow0' is marked as an error and flow0", and flow1 has no uncorrectable error in the FEC decoding process. Flow0" and flow1' are interleaved to form a code stream, and the code stream formed by the interleaving of flow0" and flow1' is rate compensated to adapt to the rate of the OTN signal container, and then the rate-compensated code stream is mapped to the OTN signal container.

[0073] For example, 1.6TE service is divided into 4 code streams flow0, flow1, flow2 and flow3, and enters the OTN node through the Ethernet interface. The OTN node performs the first processing on flow0, flow1, flow2 and flow3 respectively to obtain flow0', flow1', flow2' and flow3'; among them, flow0 has an uncorrectable error in the FEC decoding process included in the first processing, so flow0' is marked as an error and flow0", flow1, flow2 and flow3 do not have uncorrectable errors in the FEC decoding process; flow0" is interleaved with flow1', flow2', flow3 to form a code stream; the interleaved code stream is rate compensated to adapt to the rate of the OTN signal container; the rate-compensated code stream is mapped to the OTN signal container.

[0074] It should be noted that the signal container of OTN refers to an OTN transmission frame, and the OTN transmission frame may be a flexible optical service unit frame (OSU flex) frame, or the OTN transmission frame may also be an optical data unit k (ODUk), ODUCn, ODUflex, or an optical channel transmission unit k (OTUk), OTUCn, or a flexible OTN (FlexO) frame, etc. In the following description, the signal container will take ODUflex as an example.

[0075] It should be noted that rate compensation for the code stream can be achieved by adding / deleting idle code blocks, so that the transmission rate of the code stream finally mapped to ODUflex matches the rate of the payload area of ​​ODUflex.

[0076] The solution provided in the embodiments of the present application is described in detail below through specific examples.

[0077] Example 1

[0078] See also Figure 5 , Figure 5 This is an optional flow diagram of transmitting an 800GE service to a peer Ethernet node through an OTN provided in an embodiment of the present application. This embodiment includes the following steps:

[0079] Step S1001, Ethernet node 1 sends an 800GE service code stream to OTN node 1 through 800GE AUI. The 800GE service code stream is divided into two 400G rate code streams and enters OTN node 1. Here, the two code streams are recorded as flow 0 and flow 1. Both flow 0 and flow 1 are 257B code streams.

[0080] Step S1002, OTN node 1 performs multi-channel alignment, AM locking, channel de-skew, channel sorting, FEC codeword de-interleaving and FEC decoding on flow 0 and flow 1 respectively;

[0081] Step S1003: When an uncorrectable error occurs in flow 0 during FEC decoding, OTN node 1 replaces the relevant uncorrectable 275B code block in flow 0 with a type A 275B error code block or a type B 275B error code block;

[0082] Step S1004: an uncorrectable error occurs in flow 1 during the FEC decoding process, and OTN node 1 replaces the relevant uncorrectable 275B code block in flow 1 with a type A 275B error code block or a type B 275B error code block;

[0083] Step S1005, OTN node 1 interleaves flow 0 and flow 1 that have undergone the first processing and error marking into one 275B code stream, and performs rate compensation on the interleaved code stream and maps it into ODUflex, and ODUflex is transmitted to OTN node 2 via the OTN link;

[0084] Step S1006: OTN node 2 demaps two 257B code streams, flow 0 and flow 1, from ODU flex, and sends flow 0 and flow 1 to Ethernet node 2;

[0085] Step S1007, Ethernet node 2 receives two 275B code streams flow 0 and flow 1, and transcodes flow 0 and flow 1 into 66B code streams respectively, wherein each 275B error code block in flow 0 and flow 1 is converted into four 66B invalid code blocks respectively;

[0086] Step S1008: Ethernet node 2 filters out the 66B invalid code blocks in flow 0 and flow 1 through sequence detection, and then transmits them to the MAC layer.

[0087] Example 2

[0088] See also Figure 6 , Figure 6This is an optional flow diagram of transmitting an 800GE service to a peer Ethernet node through an OTN provided in an embodiment of the present application. This embodiment includes the following steps:

[0089] Step S2001: Ethernet node 1 sends an 800GE service code stream to OTN node 1 through 800GE AUI. The 800GE service code stream is divided into two 400G rate code streams and enters OTN node 1. Here, the two code streams are recorded as flow 0 and flow 1. Both flow 0 and flow 1 are 257B code streams.

[0090] Step S2002, OTN node 1 performs multi-channel alignment, AM locking, channel de-skew, channel sorting, FEC codeword de-interleaving and FEC decoding on flow 0 and flow 1 respectively;

[0091] Step S2003: uncorrectable errors occur in flow 0 during the FEC decoding process. OTN node 1 determines the 275B code blocks that cannot be corrected in flow 0, transcodes flow 0 into a 66B code stream, replaces each 275B code block that cannot be corrected with the corresponding four 66B invalid code blocks, and then transcodes flow 0 into a 275B code stream, and replaces each four 66B invalid code blocks with one B-type 275B error code block.

[0092] Step S2004: uncorrectable errors occur in flow 1 during the FEC decoding process. OTN node 1 determines the 275B code blocks in flow 1 that cannot be corrected, transcodes flow 1 into a 66B code stream, replaces each 275B code block that cannot be corrected with the corresponding four 66B invalid code blocks, and then transcodes flow 0 into a 275B code stream, and replaces each four 66B invalid code blocks with one B-type 275B error code block.

[0093] Step S2005: OTN node 1 interleaves flow 0 and flow 1 into one 275B code stream, performs rate compensation on the interleaved code stream, and maps it into ODUflex. ODUflex is transmitted to OTN node 2 via the OTN link.

[0094] Step S2006: OTN node 2 demaps two 257B code streams, flow 0 and flow 1, from ODU flex, and sends flow 0 and flow 1 to Ethernet node 2.

[0095] Step S2007, Ethernet node 2 receives two 275B code streams flow 0 and flow 1, and transcodes flow 0 and flow 1 into 66B code streams respectively, and each 275B error code block in flow 0 and flow 1 is converted into four 66B invalid code blocks respectively;

[0096] Step S2008: Ethernet node 2 filters out the 66B invalid code blocks in flow 0 and flow 1 through sequence detection, and then transmits them to the MAC layer.

[0097] Example 3

[0098] See also Figure 7 , Figure 7 The present invention provides a schematic diagram of an error marking processing method for an 800GE service transmitted to a peer Ethernet node via an OTN. OTN node 1 receives two code streams of an 800GE service from Ethernet node 1 from an Ethernet interface, and performs a first processing and an OTN FEC error marking on the two code streams. The two code streams after the error marking are as follows: Figure 7 As shown in flow 0 and flow 1, two code streams are interleaved to form one code stream after error-marked code streams flow 0 and flow 1 and mapped into ODUflex; ODUflex is transmitted to OTN node 2 through OTN link, OTN node 2 performs cyclic redundancy check (CRC) on ODUflex, and performs CRC error mark on ODUflex in CRC to obtain ODUflex'; OTN node 2 demaps two code streams flow 0' and flow 1' from ODUflex', and flow 0' and flow 1' have both OTN FEC error mark and CRC error mark; Ethernet node 2 receives flow 0' and flow 1' through OTN interface, and performs FEC decoding on flow 0' and flow 1', and finds that both flow 0' and flow 1' have uncorrectable errors during FEC decoding, and performs Ethernet FEC error mark on flow 0' and flow 1' to obtain flow 0" and flow 1", and some OTN The FEC error mark is replaced by the Ethernet FEC error mark. In this way, the possible error code blocks introduced by the source Ethernet interface, the OTN interface and the sink Ethernet interface link will be correctly marked and will not conflict. In other words, even if the error marking function of the OTN link segment is turned on, it will not affect the error code block marking method of the embodiment of the present application, and ultimately ensure the complete error marking function of the entire Ethernet source interface link, OTN link and Ethernet sink interface link.

[0099] Example 4

[0100] In an optional implementation of transmitting the 1.6TE service provided in the embodiment of the present application to the opposite Ethernet node through the OTN, the following steps are included:

[0101] Step S4001: Ethernet node 1 sends a 1.6TE service code stream to OTN node 1 through a 1.6TE Ethernet interface. The 800GE service code stream is divided into four 400G rate code streams and enters OTN node 1. The four code streams are recorded as flow 0, flow 1, flow 2, and flow 3. Flow 0, flow 1, flow 2, and flow 3 are all 257B code streams.

[0102] Step S4002: OTN node 1 performs multi-channel alignment, AM locking, channel de-skew, channel sorting, FEC codeword deinterleaving and OTN FEC decoding on flow 0, flow 1, flow 2 and flow 3 respectively. Uncorrectable errors occur in flow 0 and flow 1 during the OTN FEC decoding process, while uncorrectable errors do not occur in flow 2 and flow 3 during the OTN FEC decoding process.

[0103] Step S4003: in response to the uncorrectable error in flow 0 during the OTN FEC decoding process, OTN node 1 determines the 275B code blocks that cannot be corrected in flow 0, transcodes flow 0 into a 66B code stream, replaces the 275B code blocks that cannot be corrected with the corresponding four 66B invalid code blocks, then transcodes flow 0 into a 275B code stream, and replaces every four 66B invalid code blocks in flow 0 with type B 275B error code blocks;

[0104] Step S4004: in response to the uncorrectable error in flow 1 during the OTN FEC decoding process, OTN node 1 determines the 275B code blocks that cannot be corrected in flow 1, transcodes flow 1 into a 66B code stream, replaces the 275B code blocks that cannot be corrected with corresponding 4 66B invalid code blocks, then transcodes flow 1 into a 275B code stream, and replaces every 4 66B invalid code blocks in flow 1 with B-type 275B error code blocks;

[0105] Step S4005: OTN node 1 interleaves flow 0, flow 1, flow 2, and flow 3 into one 275B code stream, and performs rate compensation on the interleaved code stream and maps it into ODUflex, which is then transmitted to OTN node 2 via the OTN link.

[0106] Step S4006: OTN node 2 performs CRC detection on ODUflex, and performs CRC error marking on ODUflex for error code blocks found by CRC detection, demaps four 257B code streams flow 0, flow 1, flow 2, and flow 3 from ODUflex, and sends flow 0, flow 1, flow 2, and flow 3 to Ethernet node 2;

[0107] Step S4007, Ethernet node 2 receives four 275B code streams flow 0, flow 1, flow 2 and flow 3, and performs Ethernet FEC decoding and 275B to 66B transcoding on flow 0, flow 1, flow 2 and flow 3 respectively. During the transcoding process, for the uncorrectable errors in Ethernet FEC decoding, the relevant 275B code blocks in the code stream are converted into four 66B invalid code blocks. It is worth noting that the 275B code blocks that cannot be corrected in the Ethernet FEC decoding process may overlap with the 275B code blocks that cannot be corrected in the previous OTN FEC decoding process. However, no matter under what circumstances the 275B code blocks cannot be corrected, they will eventually be converted into four 66B invalid code blocks and filtered out before entering the MAC layer, ensuring the complete error marking function of the entire Ethernet source interface link, OTN link and Ethernet sink interface link.

[0108] It should be noted that although the operations are described in a specific order in some embodiments and drawings in the embodiments of the present application, it should not be understood as requiring that the operations be performed in the specific order or serial order shown, or requiring that all the operations shown be performed to obtain the desired results. In certain environments, multitasking and parallel processing may be advantageous.

[0109] According to the solution of the embodiment of the present application, the problem that the OTN node cannot implement the error marking function for the Ethernet service using the 257B reference point can be effectively solved, and the MTTFPA problem can be improved.

[0110] See also Figure 8 , Figure 8 Schematic diagram of an error code block marking device provided in an embodiment of the present application. Figure 8 As shown, the error code block marking device 200 includes:

[0111] The first processing module 201 is used to perform a first processing on the code stream received from the Ethernet interface to obtain a first code stream, wherein the first processing at least includes first forward error correction code FEC decoding, and the first code stream is a 257B code stream;

[0112] An error marking module 202 is used to mark n 257B code blocks in the first code stream for errors in the FEC decoding process to obtain a second code stream, where n is an integer greater than or equal to 1;

[0113] The second processing module 203 is used to perform a second processing on the second code stream to map the second code stream into a signal container of the optical transport network OTN.

[0114] In a possible embodiment, the error marking module 202 specifically includes a code block replacement unit, which is used to: when an FEC uncorrectable error occurs during FEC decoding, replace n 257B code blocks in the first code stream with 257B error code blocks to obtain a second code stream.

[0115] In a possible embodiment, the error marking module 202 specifically includes an enabling unit and a code block replacement unit, wherein the enabling unit is used to output an error marking enable signal for FEC uncorrectable errors occurring during the FEC decoding process; the code block replacement unit is used to replace the 257B code blocks in the first code stream with 257B error code blocks within the duration of the error marking enable signal to obtain a second code stream.

[0116] In a possible embodiment, replacing the 257B code block with a 257B error code block specifically includes: replacing the 257B code block with a type A 257B error code block or a type B 257B error code block; wherein, the value of the 0th bit of the type A 257B error code block is 0, the 1st to 4th bits are 0xF, and the 5th to 256th bits are 252 bits of information; the value of the 0th bit of the type B 257B error code block is 0, the 1st to 8th bits are 0x0E, the 9th to 64th bits are 56 bits of information, the 65th to 72nd bits are 0x1E, the 73rd to 128th bits are 56 bits of information, the 129th to 136th bits are 0x1E, the 137th to 192nd bits are 56 bits of information, the 193rd to 200th bits are 0x1E, and the 201st to 256th bits are 56 bits of information.

[0117] In a possible embodiment, the error marking module 202 specifically includes a 66B transcoding unit, a 275B transcoding unit and a code block replacement unit, wherein the 66B transcoding unit is used to perform 257B to 66B transcoding processing on the first code stream to obtain a third code stream, wherein the third code stream is a 66B code stream; the code block replacement unit is used to replace m 66B code blocks in the third code stream with 66B invalid code blocks in response to an FEC uncorrectable error occurring during FEC decoding, and obtain a fourth code stream, wherein m is greater than or equal to 4 and m is a multiple of 4; the 275B transcoding unit is used to perform 66B to 257B transcoding processing on the fourth code stream, and replace every 4 66B invalid code blocks in the fourth code stream with 1 257B error code block to obtain a second code stream.

[0118] In a possible embodiment, the error marking module 202 specifically includes an enabling unit, a 66B transcoding unit, a 275B transcoding unit and a code block replacement unit, wherein the 66B transcoding unit is used to perform 257B to 66B transcoding processing on the first code stream to obtain a third code stream, wherein the third code stream is a 66B code stream; the enabling unit is used to output an error marking enable signal for an FEC uncorrectable error occurring during the FEC decoding process; the code block replacement unit is used to replace the 66B code blocks in the third code stream with 66B invalid code blocks within the duration of the error marking enable signal; the 275B transcoding unit is used to perform 66B to 257B transcoding processing on the third code stream, and replace every 4 66B invalid code blocks in the third code stream with 1 257B error code block to obtain a second code stream.

[0119] In a possible embodiment, each of the four 66B invalid code blocks in the fourth code stream is replaced with one 257B error code block, specifically including: each of the four 66B invalid code blocks in the fourth code stream is replaced with one A-type 257B error code block or one B-type 257B error code block; wherein the A-type 257B error code block is obtained by converting four 66B error code blocks, the 0th bit of the A-type 257B error code block is 0, the 1st to 4th bits are 0xF, and the 5th to 256th bits are 252-bit. Special information: The value of the 0th bit of the B-type 257B error code block is 0, the 1st bit to the 8th bit is 0x0E, the 9th bit to the 64th bit is 56 bits of information, the 65th bit to the 72nd bit is 0x1E, the 73rd bit to the 128th bit is 56 bits of information, the 129th bit to the 136th bit is 0x1E, the 137th bit to the 192th bit is 56 bits of information, the 193th bit to the 200th bit is 0x1E, and the 201st bit to the 256th bit is 56 bits of information.

[0120] In a possible embodiment, the first process further includes one or more of the following processes: multi-channel alignment, alignment marker AM locking, channel de-skew, channel sorting, and FEC codeword de-interleaving.

[0121] In a possible embodiment, the second code stream is subjected to a second processing to map the second code stream to a signal container of an optical transport network OTN, including: interleaving the second code stream with one or three fifth code streams to obtain one sixth code stream; and rate compensating the sixth code stream and mapping it to the signal container of the OTN, wherein the fifth code stream and the sixth code stream are both 257B code streams.

[0122] It should be noted that the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of the present application. Their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0123] See also Fig. 9 , Fig. 9 900 is a schematic diagram of an electronic device provided in an embodiment of the present application. The electronic device 900 includes but is not limited to:

[0124] at least one processor 901;

[0125] At least one memory 902, used to store at least one program;

[0126] When at least one program is executed by at least one processor 901, the error code block marking method described in any of the above embodiments is executed.

[0127] It should be understood that the processor 901 and the memory 902 may be connected via a bus or other means.

[0128] It should be understood that the processor 901 may be a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc. Alternatively, the processor 901 may be one or more integrated circuits for executing related programs to implement the technical solutions provided in the embodiments of the present application.

[0129] The memory 902 is a non-transitory computer-readable storage medium that can be used to store non-transitory software programs and non-transitory computer executable programs, such as the error code block marking method described in any embodiment of the present application. The processor 901 implements the above-mentioned error code block marking method by running the non-transitory software program and instructions stored in the memory 902.

[0130] The memory 902 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store and execute the above-mentioned error code block marking method. In addition, the memory 902 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 902 may optionally include a memory remotely arranged relative to the processor 901, and these remote memories may be connected to the processor 901 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0131] The non-transient software programs and instructions required to implement the above-mentioned error code block marking method are stored in the memory 902. When executed by one or more processors 901, the error code block marking method provided by any embodiment of the present application is executed.

[0132] An embodiment of the present application also provides a computer-readable storage medium, which stores a program executable by a processor. When the program executable by the processor is executed by the processor, it is used to implement the error code block marking method described in any of the above embodiments.

[0133] The computer storage medium of the embodiment of the present application can adopt any combination of one or more computer-readable media. Computer-readable media can be computer-readable signal media or computer-readable storage media. Computer-readable storage media can be, for example, but not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any combination of the above. More specific examples (non-exhaustive lists) of computer-readable storage media include: electrical connections with one or more wires, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above. In this document, computer-readable storage media can be any tangible medium containing or storing a program, which can be used by an instruction execution system, device or device or used in combination with it.

[0134] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, which carry computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0135] The program code embodied on the computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0136] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0137] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above implementation. Those skilled in the art can make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the present application.

Claims

1. A method for marking an error code block, the method comprising: Performing a first processing on a code stream received from an Ethernet interface to obtain a first code stream, wherein the first processing at least includes first forward error correction code FEC decoding, and the first code stream is a 257B code stream; In response to an FEC uncorrectable error occurring during the FEC decoding process, marking n 257B code blocks in the first code stream as errors to obtain a second code stream, where n is an integer greater than or equal to 1; The second code stream is subjected to a second processing so as to map the second code stream into a signal container of an optical transport network OTN.

2. The method according to claim 1, characterized in that The method of marking the n 257B code blocks in the first code stream for an FEC uncorrectable error in the FEC decoding process to obtain a second code stream includes: In response to an FEC uncorrectable error occurring during the FEC decoding process, the n 257B code blocks in the first code stream are replaced with 257B error code blocks to obtain the second code stream.

3. The method according to claim 1, characterized in that The method of marking the n 257B code blocks in the first code stream for an FEC uncorrectable error in the FEC decoding process to obtain a second code stream includes: Outputting an error flag enable signal in response to an FEC uncorrectable error occurring during the FEC decoding process; During the duration of the error mark enable signal, the 257B code blocks in the first code stream are replaced with 257B error code blocks to obtain the second code stream.

4. The method according to claim 2 or 3, characterized in that: Replacing the 257B code block with a 257B error code block includes: replacing the 257B error code block with an A-type 257B error code block or a B-type 257B error code block; wherein, The value of the 0th bit of the A-type 257B error code block is 0, the 1st to 4th bits are 0xF, and the 5th to 256th bits are 252 bits of information; The value of the 0th bit of the B-type 257B error code block is 0, the 1st to 4th bits are all 0, the 5th to 8th bits are 0xE, the 9th to 64th bits are 56 bits of information, the 65th to 72nd bits are 0x1E, the 73rd to 128th bits are 56 bits of information, the 129th to 136th bits are 0x1E, the 137th to 192th bits are 56 bits of information, the 193rd to 200th bits are 0x1E, and the 201st to 256th bits are 56 bits of information.

5. The method according to claim 1, characterized in that: The method of marking the n 257B code blocks in the first code stream for an FEC uncorrectable error in the FEC decoding process to obtain a second code stream includes: Performing 257B to 66B transcoding on the first bitstream to obtain a third bitstream, wherein the third bitstream is a 66B bitstream; In response to an FEC uncorrectable error occurring during the FEC decoding process, m of the 66B code blocks in the third code stream are replaced with 66B invalid code blocks to obtain a fourth code stream, wherein m is greater than or equal to 4 and is a multiple of 4; The fourth code stream is transcoded from 66B to 257B, and every four 66B invalid code blocks in the fourth code stream are replaced with one 257B error code block to obtain the second code stream.

6. The method according to claim 1, characterized in that The method of marking the n 257B code blocks in the first code stream for an FEC uncorrectable error in the FEC decoding process to obtain a second code stream includes: Performing 257B to 66B transcoding on the first bitstream to obtain a third bitstream, wherein the third bitstream is a 66B bitstream; Outputting an error flag enable signal in response to an FEC uncorrectable error occurring during the FEC decoding process; During the duration of the error flag enable signal, replacing the 66B code block in the third code stream with a 66B invalid code block; The third code stream is transcoded from 66B to 257B, and every four 66B invalid code blocks in the third code stream are replaced with one 257B error code block to obtain the second code stream.

7. The method according to claim 5 or 6, characterized in that: The replacing each of the four 66B invalid code blocks in the fourth code stream with one 257B error code block includes: replacing each of the four 66B invalid code blocks in the fourth code stream with one A-type 257B error code block or one B-type 257B error code block; The A-type 257B error code block is obtained by converting four of the 66B error code blocks, the 0th bit of the A-type 257B error code block is 0, the 1st to 4th bits are 0xF, and the 5th to 256th bits are 252 bits of information; The 0th bit of the B-type 257B error code block is 0, the 1st bit to the 4th bit are all 0, the 5th bit to the 8th bit are 0xE, the 9th bit to the 64th bit are 56 bits of information, the 65th bit to the 72nd bit are 0x1E, the 73rd bit to the 128th bit are 56 bits of information, the 129th bit to the 136th bit are 0x1E, the 137th bit to the 192nd bit are 56 bits of information, the 193rd bit to the 200th bit are 0x1E, and the 201st bit to the 256th bit are 56 bits of information.

8. The method according to claim 1, characterized in that The first processing also includes one or more of the following processing: multi-channel alignment, alignment marker AM locking, channel de-skew, channel sorting and FEC codeword de-interleaving.

9. The method according to claim 1, characterized in that: The performing a second processing on the second code stream to map the second code stream to a signal container of an optical transport network OTN includes: Interleaving the second code stream with one or three fifth code streams to obtain one sixth code stream; The sixth code stream is rate compensated and then mapped into the signal container of the OTN, wherein both the fifth code stream and the sixth code stream are 257B code streams.

10. An error code block marking device, the device comprising: A first processing module, configured to perform a first processing on a code stream received from an Ethernet interface to obtain a first code stream, wherein the first processing at least includes first forward error correction code FEC decoding, and the first code stream is a 257B code stream; an error marking module, configured to mark the n 257B code blocks in the first code stream as errors in response to an FEC uncorrectable error occurring during the FEC decoding process, so as to obtain a second code stream, wherein n is an integer greater than or equal to 1; The second processing module is used to perform second processing on the second code stream to map the second code stream into a signal container of an optical transport network OTN.

11. An electronic device, comprising: one or more processors; A memory having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the error code block marking method as described in any one of claims 1-9.

12. A computer-readable storage medium having a computer program stored thereon, wherein when the program is executed by a processor, the error code block marking method according to any one of claims 1 to 9 is implemented.

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