Semiconductor device and manufacturing method thereof, electronic device

Abstract

A semiconductor device includes: a plurality of transistors distributed in different layers stacked along a vertical substrate direction; a word line extending along the vertical substrate direction through the different layers; a first insulating layer and a first conductive layer alternately distributed in order from bottom to top along the vertical substrate direction; a via hole penetrating each of the first insulating layer and the first conductive layer, the word line being arranged in the via hole, a second sub-hole of the first conductive layer being located in the via hole, a first sub-hole of the first insulating layer being located in the via hole, a projection of the second sub-hole of the first conductive layer on the substrate being located in a projection of the first sub-hole of the first insulating layer on the substrate; the transistor includes a semiconductor layer surrounding a sidewall of the word line; and the plurality of semiconductor layers of the plurality of transistors are spaced apart. The scheme provided by the embodiment removes the semiconductor layer between the layers, eliminates the parasitic transistor, and reduces the leakage current.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing thereof in the technical field of semiconductor, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. BACKGROUND

[0002] Semiconductor storage can be divided into volatile memory (RAM, including DRAM and SRAM, etc.) and non-volatile memory (ROM and non- ROM) in terms of application.

[0003] Taking DRAM as an example, the conventional known DRAM has multiple repeated “memory cells”, each of which has a capacitor and a transistor. The capacitor can store 1 bit of data, and after charging and discharging, the amount of charge stored in the capacitor can correspond to binary data “1” and “0” respectively. The transistor is a switch that controls the charging and discharging of the capacitor.

[0004] In order to reduce the cost of products as much as possible, people want to make as many memory cells as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs. SUMMARY

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] Embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, and an electronic device, which eliminate parasitic transistors.

[0007] Embodiments of the present disclosure provide a semiconductor device, comprising:

[0008] A plurality of transistors distributed in different layers stacked along a vertical substrate direction;

[0009] A word line extending along the vertical substrate direction through the different layers;

[0010] A first insulating layer and a first conductive layer alternately distributed in order from bottom to top along the vertical substrate direction; a via hole penetrating each of the first insulating layer and the first conductive layer, the word line being arranged in the via hole, and a second sub-hole of the via hole located in the first conductive layer falling within a normal projection of a first sub-hole of the via hole located in the first insulating layer on the substrate;

[0011] The transistor comprises a first electrode, a second electrode, and a semiconductor layer surrounding a sidewall of the word line; the first electrode and the second electrode are arranged in the first conductive layer;

[0012] The plurality of semiconductor layers of the plurality of transistors are arranged at intervals, and are distributed in different regions of the sidewall of the word line.

[0013] In some embodiments, the plurality of semiconductor layers are distributed in the via in sequence from inside to outside, the word line, a gate insulating layer surrounding the sidewall of the word line, the plurality of semiconductor layers extending along the vertical substrate direction in different regions of the sidewall of the gate insulating layer.

[0014] The sidewall of the via includes a first sidewall of a first sub-hole and a second sidewall of a second sub-hole connected to the first sidewall, the first sidewall forms a groove relative to the second sidewall, and the groove includes a sub-sidewall extending in a direction perpendicular to the substrate, the semiconductor layer continuously extends on the second sidewall and continuously extends from the second sidewall to the sub-sidewall of the groove extending in a direction perpendicular to the substrate, and is not distributed on the sub-sidewall so that the plurality of semiconductor layers are disconnected at the sub-sidewall.

[0015] In some embodiments, the semiconductor layer is connected to the sidewall of the first electrode and the second electrode, and is connected to at least one of the upper surface and the lower surface of the first electrode and the second electrode.

[0016] In some embodiments, the first insulating layer only exposes the sidewall in the via, and the first conductive layer exposes the sidewall and part of the upper and lower surfaces in the via.

[0017] The semiconductor layer is distributed at least on the sidewall of the first conductive layer.

[0018] In some embodiments, the semiconductor layer is also distributed on the upper and lower surfaces of the first conductive layer exposed in the via and is not distributed on the sidewall of the first insulating layer.

[0019] In some embodiments, the semiconductor layer includes a first sidewall and a second sidewall arranged opposite along a first direction, and the first direction is perpendicular to the extension direction of the substrate and the first electrode.

[0020] The via further includes a barrier layer arranged on the first sidewall and the second sidewall of the plurality of semiconductor layers away from the word line.

[0021] In some embodiments, the barrier layers of the semiconductor layers of different layers are spaced apart from each other.

[0022] In some embodiments, the barrier layer is not distributed on the sidewall of the first insulating layer exposed in the via, and is not distributed on the sidewall, the upper surface and the lower surface of the first conductive layer exposed in the via.

[0023] In some embodiments, gate insulating layers of a plurality of transistors of different layers are connected to form an integrated structure.

[0024] The embodiments of the present disclosure provide an electronic device including the semiconductor device of any of the above embodiments.

[0025] The embodiments of the present disclosure provide a manufacturing method of a semiconductor device including a plurality of transistors stacked in a direction perpendicular to a substrate, a word line extending in the direction perpendicular to the substrate through different layers, the transistors including a first electrode and a second electrode, the manufacturing method including:

[0026] A substrate is provided, and a first insulating film and a first conductive film are alternately deposited on the substrate in sequence to form a plurality of stacked structures; each of the stacked structures includes a stack of first insulating layers and first conductive layers arranged alternately, and the first conductive layers include a preset electrode pattern, the preset electrode pattern including a first conductive part extending in a second direction, the first conductive part including a first electrode and a second electrode of the transistors to be formed;

[0027] The first conductive layers are etched laterally in a first direction, so that a footprint of the first conductive part in the first direction on the substrate falls within a footprint of the first insulating layers on the substrate;

[0028] A barrier layer covering side walls of the first conductive part and side walls of the first insulating layers is formed;

[0029] The stacked structures are etched to form first through holes through each of the first conductive layers and each of the first insulating layers of the stacked structures in a direction perpendicular to the substrate, side walls of the first through holes exposing each of the first insulating layers, the first insulating layers being etched laterally by wet etching and the barrier layer not being etched, so that, in a plane parallel to the substrate, a footprint of the first through holes of the first conductive layers falls within a footprint of the first through holes of the first insulating layers, and the first through holes disconnect the first electrode and the second electrode in the preset electrode pattern;

[0030] Semiconductor films, gate insulating films, and gate electrode films are deposited in the first through holes in sequence to form semiconductor layers, gate insulating layers, and word lines of the plurality of transistors, the word lines filling the through holes;

[0031] The stacked structures are etched to form second through holes through the stacked structures in the direction perpendicular to the substrate, the second through holes exposing side walls of semiconductor layers extending in parallel to the second direction in the first through holes of the first insulating layers;

[0032] The semiconductor layer located in the first via of the first insulating layer is removed by etching through the second via.

[0033] In some embodiments, the second via also exposes a portion of a sidewall of the semiconductor layer located in the first via of the first insulating layer and extending in parallel to the first direction.

[0034] In some embodiments, before sequentially depositing a semiconductor thin film, a gate insulating thin film and a gate electrode thin film in the first via, the method further comprises: the barrier layer is silicon nitride, and the barrier layer in the first via is removed by etching.

[0035] In some embodiments, after removing the semiconductor layer located in the first via of the first insulating layer by etching through the second via, the method further comprises: depositing an insulating thin film to fill the second via.

[0036] Embodiments of the present disclosure include a semiconductor device and a manufacturing method thereof, and an electronic device. The semiconductor device includes: a plurality of transistors distributed in different layers stacked along a vertical substrate direction; a word line extending along the vertical substrate direction through the different layers; a first insulating layer and a first conductive layer alternately distributed from bottom to top along the vertical substrate direction; a via penetrating through each of the first insulating layer and the first conductive layer, the word line being disposed in the via, and a second sub-hole of the via in the first conductive layer being located in a projection of the first sub-hole of the via in the first insulating layer on the substrate; the transistor including a first electrode, a second electrode, and a semiconductor layer surrounding a sidewall of the word line; the first electrode and the second electrode being disposed in the first conductive layer; and a plurality of semiconductor layers of the plurality of transistors being spaced apart, the plurality of semiconductor layers being distributed in different regions of the sidewall of the word line. The semiconductor device provided by the embodiments can eliminate parasitic transistors between layers, reduce leakage current, and improve device stability by spacing apart semiconductor layers of transistors in different layers. In addition, the first via has a difference in aperture between different layers, which can be used to stagger the semiconductor layer of the first conductive layer and the semiconductor layer in the first insulating layer when manufacturing the semiconductor device. The structure of the semiconductor device of the embodiments of the present disclosure is advantageous in the following structure and process: the structure of the semiconductor device can be used to perform hole removal to remove parasitic transistors outside the hole of the via where the word line is located, thereby effectively removing semiconductor layers between layers without affecting the effective channel region (semiconductor layer of the first conductive layer) of the transistor, and ensuring the removal of parasitic transistors without affecting the channel while realizing a relatively simple process.

[0037] Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be apparent from the description, or can be learned by practice of the disclosure. The objectives and advantages of the disclosure will be realized and attained by the structure particularly pointed out in the description.

[0038] Other aspects can become apparent to those of ordinary skill in the art upon reading and understanding the detailed description and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0039] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used to explain the technical solutions together with the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions.

[0040] Figure 1A A top view of a semiconductor device according to an example embodiment;

[0041] Figure 1B A cross-sectional view along the AA direction; Figure 1A

[0042] Figure 1C A cross-sectional view along the BB direction; Figure 1A

[0043] Figure 1D A cross-sectional view along the AA direction of a semiconductor device according to another example embodiment;

[0044] Figure 1E A cross-sectional view along the BB direction of a semiconductor device according to another example embodiment;

[0045] Figure 2 A perspective view of a semiconductor device after forming a stack structure according to an example embodiment;

[0046] Figure 3A A perspective view of a semiconductor device after forming a predetermined pattern according to an example embodiment;

[0047] Figure 3B A cross-sectional view of a first conductive layer 12 along a direction parallel to a substrate according to an example embodiment;

[0048] Figure 3C A cross-sectional view along the AA direction of a semiconductor device after forming a predetermined pattern according to an example embodiment;

[0049] Figure 3D A cross-sectional view along the BB direction of a semiconductor device after forming a predetermined pattern according to an example embodiment;

[0050] Figure 4A A perspective view of a semiconductor device after reducing the width of a first conductive portion along the AA direction according to an example embodiment;

[0051] ​​Figure 4B A cross-sectional view along the AA direction after reducing the width of the first conductive portion 121 along the AA direction is provided for an exemplary embodiment;

[0052] Figure 4C A cross-sectional view along the BB direction after reducing the width of the first conductive portion 121 along the AA direction is provided for an exemplary embodiment;

[0053] Figure 5A A perspective view after forming a barrier layer is provided for an exemplary embodiment;

[0054] Figure 5B A cross-sectional view along the AA direction after forming a barrier layer is provided for an exemplary embodiment;

[0055] Figure 5C A cross-sectional view along the BB direction after forming a barrier layer is provided for an exemplary embodiment;

[0056] Figure 6A A perspective view after forming a second insulating layer is provided for an exemplary embodiment;

[0057] Figure 6B A cross-sectional view along the AA direction after forming a second insulating layer is provided for an exemplary embodiment;

[0058] Figure 6C A cross-sectional view along the BB direction after forming a second insulating layer is provided for an exemplary embodiment;

[0059] Figure 7A A perspective view after forming a first via is provided for an exemplary embodiment;

[0060] Figure 7B A plan view after forming a first via is provided for an exemplary embodiment;

[0061] Figure 7C A cross-sectional view along the AA direction after forming a first via is provided for an exemplary embodiment;

[0062] Figure 7D A cross-sectional view along the BB direction after forming a first via is provided for an exemplary embodiment;

[0063] Figure 8A A cross-sectional view along the AA direction after expanding a first sub-hole is provided for an exemplary embodiment;

[0064] Figure 8B A cross-sectional view along the BB direction after expanding a first sub-hole is provided for an exemplary embodiment;

[0065] Figure 9A A perspective view after etching a barrier layer is provided for an exemplary embodiment;

[0066] Figure 9B A plan view of the etching stopper layer after etching is provided for an exemplary embodiment;

[0067] Figure 9C A cross-sectional view along the AA direction after etching the etching stopper layer is provided for an exemplary embodiment;

[0068] Figure 9D A cross-sectional view along the BB direction after etching the etching stopper layer is provided for an exemplary embodiment;

[0069] Figure 10A A perspective view of the formation of the semiconductor layer, the gate insulating layer, and the word line is provided for an exemplary embodiment;

[0070] Figure 10B A plan view of the formation of the semiconductor layer, the gate insulating layer, and the word line is provided for an exemplary embodiment;

[0071] Figure 10C A cross-sectional view along the AA direction of the formation of the semiconductor layer, the gate insulating layer, and the word line is provided for an exemplary embodiment;

[0072] Figure 10D A cross-sectional view along the BB direction of the formation of the semiconductor layer, the gate insulating layer, and the word line is provided for an exemplary embodiment;

[0073] Figure 11A A perspective view of the formation of the second via hole is provided for an exemplary embodiment;

[0074] Figure 11B A plan view of the formation of the second via hole is provided for an exemplary embodiment;

[0075] Figure 11B' A plan view of the formation of the second via hole is provided for another exemplary embodiment;

[0076] Figure 11C A cross-sectional view along the AA direction of the formation of the second via hole is provided for an exemplary embodiment;

[0077] Figure 11D A cross-sectional view along the BB direction of the formation of the second via hole is provided for an exemplary embodiment;

[0078] Figure 12A A perspective view of the etching of the semiconductor layer in the first insulating layer is provided for an exemplary embodiment;

[0079] Figure 12B A plan view of the etching of the semiconductor layer in the first insulating layer is provided for an exemplary embodiment;

[0080] Figure 12CA cross-sectional view along the AA direction after etching the semiconductor layer in the first insulating layer is provided for an exemplary embodiment;

[0081] Figure 12D A cross-sectional view along the BB direction after etching the semiconductor layer in the first insulating layer is provided for an exemplary embodiment;

[0082] Figure 13A A plan view after forming the third insulating layer is provided;

[0083] Figure 13B A cross-sectional view along the AA direction after forming the third insulating layer is provided;

[0084] Figure 13C A cross-sectional view along the BB direction after forming the third insulating layer is provided;

[0085] Figure 14 A cross-sectional view along the AA direction after forming the semiconductor layer, the gate insulating layer, and the word line is provided for another exemplary embodiment;

[0086] Figure 15 A cross-sectional view along the AA direction after forming the second via is provided for another exemplary embodiment;

[0087] Figure 16 A cross-sectional view along the AA direction after etching the semiconductor layer in the first insulating layer is provided for another exemplary embodiment;

[0088] Figure 17 A cross-sectional view along the AA direction after forming the second insulating layer is provided for another exemplary embodiment. DETAILED DESCRIPTION

[0089] The embodiments of the present disclosure will be described in detail hereinafter with reference to the drawings. The features of the embodiments of the present disclosure and the embodiments can be arbitrarily combined with each other unless they conflict.

[0090] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning understood by a person of ordinary skill in the art to which the present disclosure pertains.

[0091] The embodiments of the present disclosure are not necessarily limited to the shapes or values shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the actual proportions.

[0092] The ordinal numbers "first", "second", "third", and so on in the present disclosure are used to avoid confusion between components, and do not represent any order, number, or importance.

[0093] In the present disclosure, words of a positional relation or a positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings for the sake of convenience, and are used only to facilitate the description of the present specification and to simplify the description, and thus are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, the words described in the present disclosure are not limited, and can be appropriately replaced according to the situation.

[0094] In the present disclosure, unless explicitly specified and limited otherwise, the terms "mount", "connect", and "connection" are to be broadly interpreted. For example, it can be a physical connection or a signal connection, it can be a contact connection or an integral connection; it can be directly connected, or indirectly connected through an intermediate, or communication within two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific situation.

[0095] In the present disclosure, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region through which current mainly flows.

[0096] In the present disclosure, it can be that the first electrode is the drain electrode and the second electrode is the source electrode, or it can be that the first electrode is the source electrode and the second electrode is the drain electrode. In the case of using a transistor with opposite polarity, or in the case of changing the direction of current in the circuit operation, the functions of "source electrode" and "drain electrode" are sometimes exchanged with each other. Therefore, in the present disclosure, "source electrode" and "drain electrode" can be exchanged with each other.

[0097] In the present disclosure, "connection" includes the case where the components are connected together through an element having a certain electrical effect. The element having a certain electrical effect is not particularly limited as long as it can perform the transmission and reception of electrical signals between the connected components. Examples of the element having a certain electrical effect include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.

[0098] In the present disclosure, "parallel" means approximately parallel or almost parallel, such as a state in which the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes a state in which the angle is -5° or more and 5° or less. In addition, "perpendicular" means approximately perpendicular, such as a state in which the angle formed by two straight lines is 80° or more and 100° or less, and thus also includes a state in which the angle is 85° or more and 95° or less.

[0099] In the present disclosure, "A and B are integrated" can mean that there is no obvious fault or gap, or other obvious boundary interface in the microstructure. Generally, the connected film layers are integrated on a film layer. For example, A and B use the same material to form a film layer and are simultaneously formed by the same patterning process.

[0100] In the present disclosure, "the orthographic projection of B is located within the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A.

[0101] The embodiments of the present disclosure are based on a vertically stacked string of mutually isolated transistors, and the semiconductor layers of each transistor are simultaneously formed in a via hole by one process. The semiconductor layers of each transistor of this type of structure are connected to each other, and there is a parasitic transistor (referred to as a parasitic MOS) between adjacent transistors. In the process, the parasitic MOS is removed while minimizing the impact on the channel region, ensuring the stability of the transistor communication performance. The embodiments of the present disclosure propose a structural improvement and a corresponding process implementation process based on the above status, to remove the parasitic MOS while minimizing the impact on the channel region.

[0102] Figure 1A A top view of a semiconductor device according to an example embodiment, Figure 1B A cross-sectional view along the AA direction in FIG. Figure 1A A cross-sectional view along the BB direction in FIG. Figure 1C A cross-sectional view along the BB direction in FIG. Figure 1A The semiconductor device can be a transistor, a memory cell including a transistor, a memory cell array including a memory cell, a 3D stacked structure including a memory cell array, a memory including a transistor or a memory cell array, etc.

[0103] As shown in FIGS. Figure 1A , Figure 1B and Figure 1C The semiconductor device provided by the embodiments can include:

[0104] a plurality of transistors stacked along the vertical substrate 1 direction in different layers;

[0105] a word line 40 extending along the vertical substrate 1 direction through the different layers;

[0106] a first insulating layer 10 and a first conductive layer 12 are alternately arranged along a direction perpendicular to the substrate 1 from bottom to top; a first via hole K1 is formed through each of the first insulating layer 10 and the first conductive layer 12, the word line 40 is arranged in the first via hole K1, and the first via hole K1 located in the first sub-hole of the first insulating layer 10 has a projection on the substrate 1 falling within the projection of the second sub-hole of the first conductive layer 12 on the substrate 1;

[0107] The transistor comprises a first electrode 51, a second electrode 52, and a semiconductor layer 23 surrounding the sidewall of the word line 40; the first electrode 51 and the second electrode 52 are arranged in the first conductive layer 12.

[0108] The plurality of semiconductor layers 23 of the plurality of transistors are arranged at intervals, and the plurality of semiconductor layers 23 are arranged in different regions of the sidewall of the word line 40.

[0109] The semiconductor device provided by the embodiment can eliminate the parasitic transistor between layers, reduce the leakage current, improve the stability of the device, and the projection of the first via hole of the first conductive layer 12 is located within the projection of the first via hole of the first insulating layer 10, that is, the first via hole has a hole diameter difference between different layers. In the manufacturing of the semiconductor device, the hole diameter difference can be used to stagger the semiconductor layer of the first conductive layer 12 and the semiconductor layer in the first insulating layer 10, so as to remove the semiconductor layer between layers without affecting the semiconductor layer of the first conductive layer 12 (that is, without affecting the effective channel region), improve the performance of the device, and the process is simple.

[0110] In some embodiments, the transistor can further comprise a gate insulating layer 24 surrounding the word line 40.

[0111] In some embodiments, the semiconductor layer 23 can be a full-surrounding type, that is, the semiconductor layer 23 fully surrounds the sidewall of the word line 40, and the cross section of the semiconductor layer 23 along the direction parallel to the substrate 1 is a closed loop. For example, the semiconductor layer 23 is annular, and the annular shape is adapted to the cross-sectional outer contour shape of the word line 40. For example, the cross section of the word line 40 is a circular, elliptical, square, or other structure.

[0112] In some embodiments, along the direction perpendicular to the substrate 1, the first electrode 51 and the second electrode 52 can be located in the same conductive film layer. It can be understood that the first electrode 51 and the second electrode 52 are formed by patterning the same conductive film layer. In some embodiments, the conductive film layer is approximately parallel to the upper surface of the substrate.

[0113] In some embodiments, the semiconductor layer 23 is broken between the intervals, and the gate insulating layer 24 is exposed.

[0114] In some embodiments, the transistor further includes a gate electrode 26, and the gate electrode 26 of different layers of transistors can be part of the word line 40. It can be understood that the gate electrode does not need to be separately made before and after the formation of the word line, and after the formation of the word line, part of the word line functions as the gate electrode. The local topography of the word line is not limited here, and the word line as a whole extends in the direction perpendicular to the substrate. Locally, the gate electrode of the region corresponding to each transistor can extend in the horizontal direction and the vertical direction, but the semiconductor layer is formed on the sidewall of the word line, and the region of the sidewall of the word line that wraps the semiconductor layer can be a main surface of the film layer that includes extension in the direction perpendicular to the substrate, or a region that includes extension in the horizontal direction in addition to the region that includes vertical extension.

[0115] In some embodiments, the semiconductor device can be a memory cell array including a plurality of memory cells including transistors. As shown in Figure 1A The same layer of transistors forms a memory cell array respectively distributed in a first direction X and a second direction Y, and each layer can further include a bit line 30 connected to the second electrode 52 of the transistors in the same column in the layer. Figure 1A As shown in FIG. 1, each layer includes three rows and two columns, but embodiments of the present disclosure are not limited thereto, and each layer can include memory cells of other row and column numbers, such as only one memory cell. The AA direction can be parallel to the first direction X, and the BB direction can be parallel to the second direction Y.

[0116] In some embodiments, the second electrodes 52 of the transistors of the memory cells in two adjacent columns are connected to the same bit line 30.

[0117] In some embodiments, the second electrode 52 of the transistor can be part of the bit line 30 to which the second electrode 52 is connected. For example, the bit line 30 is a straight line, and the sidewall of the straight line is connected to the semiconductor layer 23, or the bit line 30 has a branch with an integrated design, and the branch is connected to the semiconductor layer 23, wherein the extension direction of the branch intersects the extension direction of the bit line 30, such as approximately perpendicular.

[0118] The branch can be a plurality of branches on one sidewall of the bit line, or a plurality of branches on both sidewalls, and each branch corresponds to a transistor or a memory cell to be formed.

[0119] In some embodiments, the bit line 30 can extend in the first direction X.

[0120] In some embodiments, the first electrode 51 can extend along the second direction Y.

[0121] In some embodiments, the first via hole K1 has the word line 40, the gate insulating layer 24 surrounding the sidewall of the word line 40, and the plurality of semiconductor layers 23 extending along the vertical substrate direction and discontinuous at the sidewall of the first insulating layer 10, sequentially distributed from inside to outside.

[0122] The plurality of semiconductor layers 23 extend along the vertical substrate direction and are discontinuous at the sidewall of the first insulating layer 10.

[0123] In some embodiments, the sidewall of the first via hole K1 includes a first sidewall of a first sub-hole and a second sidewall of a second sub-hole connected to the first sidewall, the first sidewall forms a groove relative to the second sidewall, and the groove includes a sub-sidewall extending along the vertical substrate direction, the semiconductor layer 23 continuously extends on the second sidewall and continuously extends from the second sidewall to the sub-sidewall of the groove extending along the vertical substrate direction, and is not distributed on the sub-sidewall so that the plurality of semiconductor layers 23 are discontinuous at the sub-sidewall. That is, the cross section of the semiconductor layer 23 along the vertical substrate direction can be two U-shaped distributed on both sides of the word line 40, and the opening direction of the U-shaped is away from the word line 40.

[0124] In some embodiments, the semiconductor layer 23 is connected to the sidewall of the first electrode 51 and the second electrode 52, and at least one of the upper surface and the lower surface of the first electrode 51 and the second electrode 52. The upper surface of the first electrode 51 and the second electrode 52 is the surface away from the substrate, the lower surface of the first electrode 51 and the second electrode 52 is the surface towards the substrate, and the sidewall of the first electrode 51 and the second electrode 52 is the surface connecting the upper surface and the lower surface. The scheme provided in this embodiment, the semiconductor layer 23 contacts the sidewall and at least one of the upper and lower surfaces of the first electrode 51 and the second electrode 52, compared with the scheme that the semiconductor layer 23 only contacts the sidewall, can increase the contact area and reduce the contact resistance between the first electrode 51 and the second electrode 52 and the semiconductor layer 23.

[0125] In some embodiments, the first insulating layer 10 only exposes the sidewall in the first via hole K1, and the first conductive layer 12 exposes the sidewall and the partial region of the upper and lower surfaces in the first via hole K1.

[0126] The semiconductor layer 23 is at least distributed on the sidewall of the first conductive layer 12, that is, on the sidewall of the first conductive layer 12 exposed in the first via hole K1.

[0127] In some embodiments, the semiconductor layer 23 can also be distributed on both upper and lower surfaces of the first conductive layer 12 exposed in the first via K1 and not distributed on the sidewall of the first insulating layer 10.

[0128] In some embodiments, the semiconductor device can further include a third insulating layer 15 including a vertical portion extending in a direction perpendicular to the substrate and a surrounding portion surrounding the semiconductor layer 23 in a first region of the first via.

[0129] Figure 1D A cross-sectional view of a semiconductor device along AA direction provided for another exemplary embodiment, Figure 1E A cross-sectional view of a semiconductor device along BB direction provided for another exemplary embodiment. In this embodiment, a barrier layer is provided on the outer sidewall of the semiconductor layer 23 (the semiconductor layer 23 can include an inner sidewall and an outer sidewall, and the inner sidewall is in contact with the gate insulating layer 24). In some embodiments, as shown in Figure 1D 、 Figure 1E The semiconductor layer 23 can include a first sidewall and a second sidewall oppositely arranged along a first direction X, and the first direction X is perpendicular to the extension direction of the substrate and the first electrode 51 (i.e., a second direction Y);

[0130] The first via K1 can further include a barrier layer 13 provided on the first sidewall and the second sidewall of the plurality of semiconductor layers 23 away from the word line. The barrier layer 13 is used to limit the size of the first via K1 when the first via K1 is formed, so as to realize accurate control of the first via K1.

[0131] In some embodiments, the barrier layers 13 of the semiconductor layer 23 surfaces of different layers are spaced apart from each other.

[0132] In some embodiments, the barrier layer 13 is not distributed on the sidewall of the first insulating layer 10 exposed in the first via K1, and is not distributed on the sidewall, upper surface and lower surface of the first conductive layer 12 exposed in the first via K1. As shown in Figure 1E there is no barrier layer 13 in the BB direction.

[0133] In some embodiments, the gate insulating layers 24 of the plurality of transistors of different layers can be connected to form an integrated structure. However, the embodiments of the present disclosure are not limited thereto, and the gate insulating layers 24 of the plurality of transistors of different layers can be disconnected.

[0134] The technical solution of the present embodiment is further illustrated by the manufacturing process of the semiconductor device of the present embodiment. The "patterning process" in the present embodiment includes deposition of a film, coating of photoresist, mask exposure, development, etching, stripping of photoresist, etc. and is a mature manufacturing process in the related art. The "lithography process" in the present embodiment includes coating of a film, mask exposure and development and is a mature manufacturing process in the related art. Deposition can employ known processes such as sputtering, evaporation, chemical vapor deposition, etc., coating can employ known coating processes, and etching can employ known methods, and no specific limitation is made herein. In the description of the present embodiment, it is to be understood that "film" refers to a film of a certain material made on a substrate by deposition or coating. If the "film" does not need to be subjected to a patterning process or a lithography process during the entire manufacturing process, the "film" can also be referred to as a "layer". If the "film" needs to be subjected to a patterning process or a lithography process during the entire manufacturing process, the "film" is referred to as a "film" before the patterning process and as a "layer" after the patterning process. The "layer" after the patterning process or the lithography process contains at least one "pattern".

[0135] In an embodiment, the manufacturing process of the semiconductor device can include:

[0136] 101) Depositing a first insulating film and a first conductive film on a substrate 1 in sequence to form a stack structure including first insulating layers 10 and first conductive layers 12 arranged alternately, as shown in Figure 2 Figure 2 is a schematic perspective view of the stack structure after formation provided for an exemplary embodiment. A hard mask layer 8 is provided on the topmost first conductive layer 12.

[0137] The first insulating layers 10 and the first conductive layers 12 overlap in orthographic projection in a direction parallel to the substrate.

[0138] In some embodiments, the first insulating film can be an insulating material including but not limited to silicon oxide such as silicon dioxide (SiO2), aluminum oxide (Al2O3), etc.

[0139] In some embodiments, the first conductive film can be a conductive material including but not limited to:

[0140] For example, a metal including tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; or an alloy including a metal among the aforementioned metals.

[0141] ​Alternatively, it can be a metal oxide, a metal nitride, a metal silicide, a metal carbide, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), an oxide of indium (InO), and other metal oxide materials with high conductivity; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), and other metal nitride materials.

[0142] Alternatively, it can be a polysilicon material, a conductive doped semiconductor material, etc., such as conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, and other materials that exhibit conductivity.

[0143] In some embodiments, the hard mask layer 8 includes, but is not limited to, at least one of the following: carbon, polysilicon, silicon oxide, etc.

[0144] Figure 2 The stack structure shown in FIG. 1 includes three layers of first insulating layers 10 and three layers of first conductive layers 12, which are merely examples, and in other embodiments, the stack structure can include more or fewer film layers.

[0145] 102) patterning the stack structure so that the stack structure forms a preset pattern;

[0146] The patterning of the stack structure can include:

[0147] The stack structure is etched from the top layer to the bottom layer (excluding the substrate) using dry etching to form a plurality of first trenches, which cause the first conductive layers 12 to form a preset pattern, which can include first conductive portions 121 and second conductive portions 122, wherein the first conductive portions 121 can extend along the second direction Y, and the second conductive portions 122 can extend along the first direction X, as shown in Figure 3A 、 Figure 3B 、 Figure 3C 、 Figure 3D wherein, Figure 3A is a three-dimensional schematic view after the preset pattern is formed, Figure 3B is a cross-sectional view of the first conductive layer 12 along a direction parallel to the substrate direction, Figure 3C is a cross-sectional view along the AA direction after the preset pattern is formed, Figure 3D is a cross-sectional view along the BB direction after the preset pattern is formed. The preset pattern and the pattern of the plurality of first trenches are complementary, i.e., the combination of the pattern of the preset pattern and the pattern of the first trenches is the shape of the first conductive layer 12 in step 1). The first direction X and the second direction Y can intersect. In some embodiments, the first direction X and the second direction Y can be perpendicular.

[0148] The first conductive part 121 can form a first electrode 51 of a transistor, the second conductive part 122 can form a second electrode 52 of the transistor, and a bit line 30.

[0149] Alternatively, the first conductive part 121 can form a first electrode 51 and a second electrode 52 of a transistor, and the second conductive part 122 can form a bit line 30.

[0150] Figure 3B The preset pattern shown is only an example, and the preset pattern can be other shapes.

[0151] In this step, the size of the first conductive part 121 along the AA direction can be greater than the size of the finally formed first electrode 51 along the AA direction.

[0152] When a word line is subsequently formed, a first via hole K1 is formed, which has different hole diameters in the first insulating layer 10 and the first conductive layer 12, wherein the hole diameter of the first via hole K1 in the first insulating layer 10 is a first hole diameter d1, and the hole diameter of the first conductive layer 12 is a second hole diameter d2. In this step, the size d of the first conductive part 121 along the AA direction can be the first hole diameter d1. In some embodiments, the difference between d1 and d2 can be 10 nanometers to 50 nanometers.

[0153] 103) reducing the width of the first conductive part 121 along the AA direction;

[0154] The reduction of the width of the first conductive part 121 along the AA direction can include: passing etching liquid into the first trench to selectively etch the first conductive layer 12 and the first insulating layer 10 by wet etching, that is, etching the first conductive layer 12 and substantially no etching the first insulating layer 10, so that the size of the first conductive part 121 along the AA direction is reduced, and the orthographic projection of the first conductive part 121 along the AA direction falls within the orthographic projection of the first insulating layer 10, as shown in Figure 4A 、 Figure 4B 、 Figure 4C as shown, wherein, Figure 4A is a three-dimensional schematic view after the width of the first conductive part 121 along the AA direction is reduced, Figure 4B is a cross-sectional view along the AA direction after the width of the first conductive part 121 along the AA direction is reduced, Figure 4C is a cross-sectional view along the BB direction after the width of the first conductive part 121 along the AA direction is reduced. In the AA direction, the cross section of the first conductive layer 12 falls within the orthographic projection of the cross section of the first insulating layer 10 on the substrate. In this step, the size of the first conductive part 121 along the AA direction can be the hole diameter of the subsequently formed first via hole K1 in the first conductive layer 12, that is, the second hole diameter d2.

[0155] 104) forming a barrier layer 13;

[0156] The forming of the barrier layer 13 can include depositing a barrier layer thin film on the substrate 1 with the aforementioned structure, forming the barrier layer 13, as shown in Figure 5A 、 Figure 5B 、 Figure 5C wherein, Figure 5A is a perspective view after the barrier layer 13 is formed, Figure 5B is a cross-sectional view along the AA direction after the barrier layer 13 is formed, Figure 5C is a cross-sectional view along the BB direction after the barrier layer 13 is formed. The barrier layer 13 covers the upper surface of the hard mask layer 8 and the sidewall, lower surface exposed in the first trench, and covers the sidewall of the first conductive layer 12 exposed in the first trench, and covers the upper surface and lower surface of the first insulating layer 10 exposed in the first trench. The barrier layer 13 can protect the insulating thin film in the same layer as the first conductive layer 12 during subsequent etching of the first insulating layer 10, i.e., the second insulating layer 14 formed subsequently in the same layer as the first conductive layer 12.

[0157] In some embodiments, the barrier layer thin film is a material with high etching selectivity to the first insulating thin film, facilitating the protection of the first conductive layer 12 during subsequent etching of the first insulating layer 10.

[0158] In some embodiments, the barrier layer 13 can be a single layer or multiple layers.

[0159] In some embodiments, the barrier layer thin film can include but is not limited to at least one of the following: silicon nitride (Si3N4), aluminum trioxide (Al2O3), etc.

[0160] 105) forming a second insulating layer 14;

[0161] The forming of the second insulating layer 14 can include depositing a second insulating thin film on the substrate 1 with the aforementioned structure, forming the second insulating layer 14 filling the first trench;

[0162] polishing to remove the hard mask layer 8 and the upper surface of the hard mask layer 8, so that the upper surface of the second insulating layer 14 is flush with the upper surface of the first conductive layer 12 in the top layer, as shown in Figure 6A 、 Figure 6B and Figure 6C wherein, Figure 6A is a perspective view after the second insulating layer 14 is formed, Figure 6B is a cross-sectional view along the AA direction after the second insulating layer 14 is formed, Figure 6C is a cross-sectional view along the BB direction after the second insulating layer 14 is formed. The second insulating layer 14 fills the first trench.

[0163] In some embodiments, the planarization can be performed by chemical mechanical polishing (CMP).

[0164] In some embodiments, the second insulating film can be the same as or different from the first insulating film material.

[0165] In some embodiments, the second insulating film can be an insulating material, including but not limited to silicon oxide, such as silicon dioxide (SiO2), aluminum oxide (Al2O3), etc.

[0166] 106) forming a first via K1;

[0167] The forming of the first via K1 can include etching the stack structure by dry etching to form a plurality of first vias K1 penetrating through the stack structure, the sidewall of the first via K1 exposing each of the first conductive layer 12 and the first insulating layer 10, and the first via K1 having a substantially consistent aperture size at different layers, i.e., the aperture size of the first via K1 at the first insulating layer 10 is consistent with the aperture size of the first via K1 at the first conductive layer 12, and the first via K1 disconnects the first conductive layer 12 to form the first electrode 51 and the second electrode 52 disconnected from each other, as shown in Figure 7A 、 Figure 7B 、 Figure 7C and Figure 7D Figure 7A is a perspective view after the forming of the first via K1, Figure 7B is a top view after the forming of the first via K1, Figure 7C is a sectional view along the direction of AA after the forming of the first via K1, Figure 7D is a sectional view along the direction of BB after the forming of the first via K1.

[0168] The first via K1 can include a first sub-via K11 located at the first insulating layer 10 and a second sub-via K12 located at the first conductive layer 12. In this step, the aperture size of the second sub-via K12 can be equal to the aperture size of the first sub-via 11.

[0169] In some embodiments, the first via K1 can extend along a direction perpendicular to the substrate 1.

[0170] In some embodiments, the orthographic projection of the first via K1 on a plane parallel to the substrate 1 can be a square, but is not limited thereto and can be other shapes, such as a circle, a hexagon, an ellipse, etc.

[0171] 107) expanding the aperture size of the first sub-via K11;

[0172] ​The method for expanding the aperture of the first sub-hole K11 can comprise: introducing etching liquid into the first through-hole K1, and expanding the aperture of the first sub-hole K11 by wet etching the first insulating layer 10 in a lateral direction, so that the orthogonal projection of the second sub-hole K12 on the substrate 1 falls within the orthogonal projection of the first sub-hole K11 on the substrate 1, as shown in Figure 8A 、 Figure 8B wherein, Figure 8A is a sectional view of the first sub-hole K11 in the rear direction AA after the aperture is expanded, Figure 8B is a sectional view of the first sub-hole K11 in the rear direction BB after the aperture is expanded. It can be seen that, in the AA direction, the orthogonal projection of the second sub-hole K12 on the substrate 1 falls within the orthogonal projection of the first sub-hole K11 on the substrate 1; in the BB direction, the orthogonal projection of the second sub-hole K12 on the substrate 1 falls within the orthogonal projection of the first sub-hole K11 on the substrate 1. After the etching liquid is introduced into the first through-hole K1, the second insulating layer 14 in the same layer as the first conductive layer 12 is protected by the blocking layer 13 and is prevented from being etched by the etching liquid, as shown in Figure 8A , the side wall of the second sub-hole K12 in the AA direction is distributed with the blocking layer 13, so as to prevent the second insulating layer 14 from being etched, and the side wall of the first sub-hole K11 is distributed with the blocking layer 13, so as to limit the aperture of the first sub-hole K11 after the aperture is expanded. The scheme provided in the embodiment can accurately control the expansion size through the blocking layer 13, and the controllability and accuracy of the process are ensured.

[0173] After the semiconductor layer is subsequently deposited in the first through-hole K1, in the direction perpendicular to the substrate 1, since the aperture of the first through-hole K1 located in the first insulating layer 10 is different from the aperture of the first through-hole K1 located in the first conductive layer 12, the semiconductor layer located in the first insulating layer 10 and the semiconductor layer located in the first conductive layer 12 are staggered with each other, so as to facilitate the removal of the semiconductor layer located in the first insulating layer 10. In some embodiments, the difference between the aperture of the first through-hole K1 located in the first insulating layer 10 and the aperture of the first through-hole K1 located in the first conductive layer 12 can be 10 nm to 50 nm, so that the distance by which the semiconductor layer located in the first insulating layer 10 and the semiconductor layer located in the first conductive layer 12 are staggered can be 5 nm to 25 nm. However, the embodiments of the present disclosure are not limited thereto, and can be set to other values as needed.

[0174] 108) etching to remove the blocking layer 13 distributed on the side wall of the first through-hole K1;

[0175] The etching to remove the blocking layer 13 distributed on the side wall of the first through-hole K1 can comprise: introducing etching liquid into the first through-hole K1, and removing the blocking layer 13 located on the side wall of the first through-hole K1 by wet etching, as shown in Figure 9A 、 Figure 9B 、 Figure 9C and Figure 9D wherein, Figure 9A is a three-dimensional schematic view after the blocking layer 13 is etched,Figure 9B is a plan view after etching the etching stop layer 13, Figure 9C is a sectional view along the AA direction after etching the etching stop layer 13, Figure 9D is a sectional view along the BB direction after etching the etching stop layer 13. In this step, only the etching stop layer 13 is etched and removed, and the first insulating layer 10 and the second insulating layer 14 are not etched.

[0176] 109) forming a semiconductor layer 23, a gate insulating layer 24 and a word line 40;

[0177] The forming of the semiconductor layer 23, the gate insulating layer 24 and the word line 40 can include:

[0178] forming a semiconductor layer 23, a gate insulating layer 24 and a word line 40 on the substrate 1 having the above structure by sequentially depositing a semiconductor thin film, a gate insulating thin film and a gate electrode thin film, and planarizing; as shown in FIGS. 1-4, wherein, Figure 10A 、 Figure 10B 、 Figure 10C and Figure 10D the semiconductor layer 23, the gate insulating layer 24 and the word line 40 are formed, and Figure 10A is a perspective view after forming the semiconductor layer 23, the gate insulating layer 24 and the word line 40, Figure 10B is a plan view after forming the semiconductor layer 23, the gate insulating layer 24 and the word line 40, Figure 10C is a sectional view along the AA direction after forming the semiconductor layer 23, the gate insulating layer 24 and the word line 40, Figure 10D is a sectional view along the BB direction after forming the semiconductor layer 23, the gate insulating layer 24 and the word line 40. The gate electrode 26 of each transistor is part of the word line 40.

[0179] After planarizing, the surface of the semiconductor layer 23, the gate insulating layer 24 and the word line 40 away from the substrate 1 side is made flush with the surface of the topmost first conductive layer 12 away from the substrate 1 side.

[0180] The semiconductor layer 23 can cover the bottom wall and the sidewall of the first via K1, the word line 40 fills the first via K1, and the gate insulating layer 24 is arranged between the semiconductor layer 23 and the word line 40 to insulate the semiconductor layer 23 and the word line 40.

[0181] In some embodiments, the semiconductor thin film, the gate insulating thin film and the gate electrode thin film can be deposited by ALD.

[0182] In exemplary embodiments of the present disclosure, the material of the semiconductor layer 23 can be silicon or polycrystalline silicon or the like material with a band gap less than 2eV, or can be a wide band gap material such as a metal oxide material with a band gap greater than 2eV.

[0183] For example, the material of the metal oxide semiconductor layer or channel can include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, and the like. Of course, the metal oxide can also include compounds containing other elements, such as N, Si, and the like; and can also include other small amounts of doped elements.

[0184] In some embodiments, the material of the metal oxide semiconductor layer or channel can include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), and the like, as long as the leakage current of the transistor meets the requirements, and the specific material can be adjusted according to the actual situation.

[0185] The band gap of these materials is wide, and the leakage current is low. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A. Thus, the working performance of the dynamic memory can be improved.

[0186] The material of the metal oxide semiconductor layer or channel described above only emphasizes the element type of the material, and does not emphasize the atomic percentage in the material and the film quality of the material.

[0187] In the exemplary embodiments of the present disclosure, the material of the gate insulating layer 24 can include one or more layers of High-K dielectric material. In some embodiments, one or more oxides of hafnium, aluminum, lanthanum, zirconium, and the like can be included. For example, at least one of the following high-K materials can be included, but is not limited to: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and the like.

[0188] In some embodiments, the gate electrode thin film can be one or more of the following different types of materials:

[0189] For example, containing tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt and other metals; can be a metal alloy containing the metals mentioned above;

[0190] Alternatively, it can be a metal oxide, a metal nitride, a metal silicide, a metal carbide, etc., such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), aluminum-doped zinc oxide (AZO), and other high-conductivity metal oxide materials; for example, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), and other metal nitride materials;

[0191] Alternatively, it can be a polysilicon material, a conductive doped semiconductor material, etc., such as conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc.; other materials that exhibit conductivity, etc.

[0192] 110) Forming a second via K2;

[0193] The forming of the second via K2 can include etching the stack structure from the top layer to the bottom layer (excluding the substrate 1) by dry etching to form a plurality of second vias K2, the second vias K2 exposing the semiconductor layer 23 in the first insulating layer 10 in the AA direction, and not exposing the semiconductor layer 23 in the first conductive layer 12 in the AA direction, and not exposing the semiconductor layer 23 in the first conductive layer 12 in the BB direction, as shown in Figure 11A 、 Figure 11B 、 Figure 11C and Figure 11D wherein Figure 11A is a perspective view after forming the second via K2, Figure 11B is a top view after forming the second via K2, Figure 11C is a cross-sectional view along the AA direction after forming the second via K2, Figure 11D is a cross-sectional view along the BB direction after forming the second via K2. In this step, the second insulating layer 14 is etched to form the second via K2.

[0194] In some embodiments, the second via K2 is located outside the projection of the first conductive layer 12 in the projection of the substrate 1.

[0195] As shown in Figure 11C , the semiconductor layer 23 in the first insulating layer 10 in the AA direction is completely exposed, and the semiconductor layer 23 in the first conductive layer 12 in the AA direction is protected by the second insulating layer 14, i.e., the two sides of the semiconductor layer 23 in the first insulating layer 10 arranged in the AA direction are exposed by the two second vias K2, facilitating subsequent etching of the semiconductor layer 23 by etching liquid in the second via K2.

[0196] Figure 11B The size of the second through hole K2 described above is merely an example. In another exemplary embodiment, the size of the second through hole along the BB direction can be reduced to expose the semiconductor layer 23 located in the first insulating layer 10 along the AA direction. The larger the size of the second through hole K2 along the BB direction, the more semiconductor layer 23 is exposed, which in turn speeds up the subsequent etching of the semiconductor layer 23 and facilitates the etching of the semiconductor layer 23.

[0197] In another exemplary embodiment, Figure 11B' As shown, the second through hole K2 may include two sub-through holes: a first sub-through hole K21 and a second sub-through hole K22. The first sub-through hole K21 extends along the BB direction, exposing the side wall of the semiconductor layer 23 extending parallel to the second direction Y in the first through hole K1 of the first insulating layer 10; the second sub-through hole K22 extends along the AA direction, exposing part of the side wall of the semiconductor layer 23 extending parallel to the first direction X in the first through hole K1 of the first insulating layer 10, that is, the two side surfaces of the semiconductor layer 23 arranged along the BB direction in the first insulating layer 10 are exposed by the two second sub-through holes K22, and each second sub-through hole K22 is divided into two parts, respectively located on both sides of the electrically conductive portion 121. The solution provided in this embodiment can expose more semiconductor layers 23, so that the semiconductor layers 23 can be etched and removed faster. In the subsequent steps, the second through hole K2 is used as the Figure 11B The shape shown is used as an example for explanation.

[0198] 111) etching the semiconductor layer 23 in the first insulating layer 10;

[0199] The etching of the semiconductor layer 23 in the first insulating layer 10 may include: introducing an etching solution into the second through hole K2 to etch away the semiconductor layer 23 in the first insulating layer 10, without etching other film layers, such as the second insulating layer 14, the gate insulating layer 24, etc. Figure 12A 、 12B , 12C and 12D, Figure 12A This is a three-dimensional schematic diagram after etching the semiconductor layer 23 located in the first insulating layer 10. Figure 12B This is a top view after etching the semiconductor layer 23 located in the first insulating layer 10. Figure 12C This is a cross-sectional view along the AA direction after etching the semiconductor layer 23 located in the first insulating layer 10. Figure 12D It is a cross-sectional view along the BB direction after etching the semiconductor layer 23 located in the first insulating layer 10 .

[0200] When etching the semiconductor layer 23 in the first insulating layer 10, the semiconductor layer 23 in the first insulating layer 10 that surrounds the word line 40 is etched away.Figure 12C and 12D As shown in FIG. 9, it can be seen that the semiconductor layer 23 in the first insulating layer 10 is etched away, and the gate insulating layer 24 is exposed in the second through hole K2.

[0201] In this step, the semiconductor layer 23 in the first insulating layer 10 is etched away, and the semiconductor layer 23 between the transistors of adjacent layers is disconnected, eliminating the parasitic transistor.

[0202] 112) forming a third insulating layer 15;

[0203] The forming of the third insulating layer 15 can include: depositing a third insulating film on the substrate 1 of the foregoing structure to fill the second through hole K2 and the area where the etched semiconductor layer 23 is located, forming the third insulating layer 15, as shown in FIG. 10. Figure 13A 、 Figure 13B and Figure 13C As shown in FIG. 10, Figure 13A is a top view after forming the third insulating layer 15, Figure 13B is a sectional view along the AA direction after forming the third insulating layer 15, Figure 13C is a sectional view along the BB direction after forming the third insulating layer 15.

[0204] In some embodiments, the third insulating film can be an insulating material, including but not limited to silicon oxide, such as silicon dioxide (SiO2), aluminum oxide (Al2O3), etc.

[0205] In another embodiment, a material that has a barrier effect on hydrogen (H) and oxygen (O) and has little effect on the semiconductor layer 23 can be used to form the barrier layer 13, so that the barrier layer 13 can be preserved. The manufacturing process of the semiconductor device can include:

[0206] Steps 201 to 207, steps 101 to 107;

[0207] 208) forming a semiconductor layer 23, a gate insulating layer 24 and a word line 40;

[0208] The forming of the semiconductor layer 23, the gate insulating layer 24 and the word line 40 can include:

[0209] Depositing a semiconductor film, a gate insulating film and a gate electrode film on the substrate 1 of the foregoing structure in sequence, grinding, forming the semiconductor layer 23, the gate insulating layer 24 and the word line 40; as shown in FIG. 8, Figure 14 As shown in FIG. 8, Figure 14This is a cross-sectional view along the AA direction after the semiconductor layer 23, gate insulating layer 24 and word line 40 are formed. The gate electrode 26 of each layer of transistors is part of the word line 40. In this embodiment, the first through hole K1 is sequentially distributed with the barrier layer 13, semiconductor layer 23, gate insulating layer 24 and word line 40 from the outside to the inside in the AA direction. Figure 10D , no more details.

[0210] The semiconductor layer 23 may cover the bottom wall and sidewalls of the first through hole K1 . The word line 40 fills the first through hole K1 . The gate insulating layer 24 is disposed between the semiconductor layer 23 and the word line 40 to insulate the semiconductor layer 23 from the word line 40 .

[0211] 209) forming a second through hole K2;

[0212] The forming of the second through holes K2 may include: etching the stacked structure from the top layer to the bottom layer (excluding the substrate 1) by dry etching to form a plurality of second through holes K2, wherein the second through holes K2 expose the semiconductor layer 23 in the first insulating layer 10 in the AA direction, and do not expose the semiconductor layer 23 in the first conductive layer 12 in the AA direction, and do not expose the semiconductor layer 23 in the first conductive layer 12 in the BB direction, as shown in FIG. Figure 15 As shown, Figure 15 The cross-sectional view along the AA direction after the second through hole K2 is formed. Figure 11D In another embodiment, the second through hole K2 may be similar to Figure 11B' The shape of the second through hole K2.

[0213] In this embodiment, the second insulating layer 14 and a portion of the barrier layer 13 are removed by etching to form the second through hole K2 .

[0214] In some embodiments, the orthographic projection of the second through hole K2 on the substrate 1 is located outside the orthographic projection of the first conductive layer 12 .

[0215] like Figure 15 As shown, the semiconductor layer 23 located in the first insulating layer 10 in the AA direction is completely exposed, and the semiconductor layer 23 located in the first conductive layer 12 in the AA direction is protected by the second insulating layer 14, that is, the semiconductor layer 23 located on two side surfaces distributed along the AA direction in the first insulating layer 10 is exposed by two second through holes K2, which facilitates the subsequent etching of the semiconductor layer 23 by passing the etching solution into the second through holes K2.

[0216] 210) etching the semiconductor layer 23 in the first insulating layer 10 to form a third insulating layer 15;

[0217] Referring to steps 111-112, etching the semiconductor layer 23 in the first insulating layer 10 in the AA direction to form the third insulating layer 15 can include: introducing an etching liquid into the plurality of second through holes K2, etching to remove the semiconductor layer 23 in the first insulating layer 10, and not etching other film layers such as the second insulating layer 14, the gate insulating layer 24, etc., as shown in Figure 16 . Figure 16 The cross-sectional view along the AA direction after etching the semiconductor layer 23 in the first insulating layer 10 is shown in Figure 12D .

[0218] Depositing a third insulating film to fill the second through holes K2 and the region where the semiconductor layer 23 is etched to form the third insulating layer 15, as shown in Figure 17 . Figure 17 The cross-sectional view along the AA direction after forming the third insulating layer 15 is shown in Figure 13C .

[0219] In this embodiment, the first through holes K1 in the AA direction, from the outside to the inside, are sequentially distributed with the blocking layer 13, the semiconductor layer 23, the gate insulating layer 24, and the word line 40 in the first conductive layer 12.

[0220] In this embodiment, the blocking layer 13 can be a material such as Al2O3 that has an isolating effect on H and O and does not react with the semiconductor layer 23 to affect the performance of the transistor. Therefore, the blocking layer 13 can be retained, thereby reducing the number of etching processes, reducing costs, and avoiding residues caused by etching, and improving device performance.

[0221] The present disclosure provides a manufacturing method of a semiconductor device, the semiconductor device including a plurality of transistors stacked in a direction perpendicular to a substrate, a word line extending in the direction perpendicular to the substrate and penetrating through different layers, the transistors including a first electrode and a second electrode, the manufacturing method of the semiconductor device can include:

[0222] providing a substrate, depositing a first insulating film and a first conductive film alternately on the substrate, and performing patterning to form a plurality of stacked structures; each of the stacked structures includes a stack of the first insulating layer and the first conductive layer arranged alternately, the first conductive layer includes a preset electrode pattern, the preset electrode pattern includes a first conductive part extending in a second direction, the first conductive part includes the first electrode and the second electrode of the transistor to be formed;

[0223] laterally etching the first conductive layer in a first direction, so that the first conductive part in the first direction falls within the orthographic projection of the first insulating layer on the substrate;

[0224] forming a barrier layer covering the sidewall of the first conductive layer and the sidewall of the first insulating layer;

[0225] etching the stack structure to form a first via penetrating each first conductive layer and each first insulating layer of the stack structure in a direction perpendicular to the substrate, a sidewall of the first via exposing each first insulating layer, the first via being formed by wet etching laterally etching the first insulating layer without etching the barrier layer, such that in a plane parallel to the substrate, a footprint of the first via in the first conductive layer falls within a footprint of the first via in the first insulating layer, and the first via disconnects the first electrode and the second electrode in the pre-set electrode pattern;

[0226] sequentially depositing a semiconductor thin film, a gate insulating thin film and a gate electrode thin film in the first via to form a multi-layer semiconductor layer, a gate insulating layer and a word line of the transistor, the word line filling the via;

[0227] etching the stack structure to form a second via penetrating the stack structure in a direction perpendicular to the substrate, the second via exposing a sidewall of the semiconductor layer in the first via in the first insulating layer extending in a second direction;

[0228] removing the semiconductor layer in the first via in the first insulating layer by etching through the second via.

[0229] The method for manufacturing a semiconductor device provided by the embodiments of the present disclosure removes the parasitic transistor outside the hole of the via where the word line is located, effectively removes the semiconductor layer between layers, and does not affect the effective channel region (the semiconductor layer of the first conductive layer) of the transistor, ensuring that the parasitic transistor is removed without affecting the channel while realizing a relatively simple process.

[0230] In some embodiments, the second via also exposes a partial sidewall of the semiconductor layer in the first via in the first insulating layer extending in a first direction.

[0231] In some embodiments, before sequentially depositing a semiconductor thin film, a gate insulating thin film and a gate electrode thin film in the first via, the method further comprises: when the barrier layer is silicon nitride, etching to remove the barrier layer in the first via.

[0232] In some embodiments, after removing the semiconductor layer in the first via in the first insulating layer by etching through the second via, the method further comprises: depositing an insulating thin film to fill the second via.

[0233] The embodiments of the present disclosure also provide an electronic device comprising the semiconductor device of any of the preceding embodiments. The electronic device can be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, or the like. The storage device can include a memory in a computer, and the like, which is not limited herein.

[0234] Although the embodiments of the present disclosure are disclosed as above, the content described is only the embodiments adopted for the purpose of facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure. The patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a plurality of transistors stacked along a vertical substrate direction in different layers; a word line extending along the vertical substrate direction through the different layers; a first insulating layer and a first conductive layer alternately arranged along the vertical substrate direction from bottom to top; a via hole through each of the first insulating layer and the first conductive layer, the word line being arranged in the via hole, a second sub-hole of the first conductive layer being located in the via hole, a first sub-hole of the first insulating layer being located in the via hole, a projection of the second sub-hole on the substrate falling within a projection of the first sub-hole on the substrate; the transistor comprising a first electrode, a second electrode, and a semiconductor layer surrounding a sidewall of the word line; the first electrode and the second electrode being arranged in the first conductive layer; a plurality of semiconductor layers of the plurality of transistors being arranged at intervals, the plurality of semiconductor layers being arranged in different regions of the sidewall of the word line; the via hole comprising, from inside to outside, the word line, a gate insulating layer surrounding the sidewall of the word line, and the plurality of semiconductor layers surrounding different regions of the sidewall of the gate insulating layer; a sidewall of the via hole comprising a first sidewall of a first sub-hole and a second sidewall of a second sub-hole connected to the first sidewall, the first sidewall forming a groove relative to the second sidewall, the groove comprising a sub-sidewall extending along a direction perpendicular to the substrate, the semiconductor layer continuously extending on the second sidewall and continuously extending from the second sidewall to the sub-sidewall of the groove extending along the direction perpendicular to the substrate, and not being arranged on the sub-sidewall so that the plurality of semiconductor layers are disconnected on the sub-sidewall.

2. The semiconductor device according to claim 1, wherein the semiconductor layer being connected to a sidewall of the first electrode and the second electrode, and being connected to at least one of an upper surface and a lower surface of the first electrode and the second electrode.

3. The semiconductor device of claim 1, wherein the first insulating layer only exposing a sidewall in the via hole, and the first conductive layer exposing a sidewall and a partial region of an upper surface and a lower surface in the via hole; the semiconductor layer being arranged at least on the sidewall of the first conductive layer.

4. The semiconductor device of claim 1, wherein the semiconductor layer being further arranged on the upper surface and the lower surface of the first conductive layer exposed in the via hole and not being arranged on the sidewall of the first insulating layer exposed in the via hole.

5. The semiconductor device of claim 1, wherein the semiconductor layer comprising a first sidewall and a second sidewall arranged opposite along a first direction, the first direction being perpendicular to an extension direction of the substrate and the first electrode; the via hole further comprising a barrier layer arranged on the first sidewall and the second sidewall of the plurality of semiconductor layers away from the word line.

6. The semiconductor device according to claim 5, wherein the barrier layers of the semiconductor layers of different layers being spaced apart from each other.

7. The semiconductor device of claim 5, wherein the barrier layer not being arranged on the sidewall of the first insulating layer exposed in the via hole, and not being arranged on the sidewall, the upper surface, and the lower surface of the first conductive layer exposed in the via hole.

8. The semiconductor device of claim 1, wherein, gate insulating layers of the plurality of transistors in different layers being connected to form an integrated structure.

9. An electronic device, comprising: The semiconductor device comprises:

10. A method of manufacturing a semiconductor device, characterized by a plurality of transistors stacked along a vertical substrate direction in different layers; a word line extending along the vertical substrate direction through the different layers; a first insulating layer and a first conductive layer alternately arranged along the vertical substrate direction from bottom to top; a via hole through each of the first insulating layer and the first conductive layer, the word line being arranged in the via hole, a second sub-hole of the first conductive layer being located in the via hole, a first sub-hole of the first insulating layer being located in the via hole, a projection of the second sub-hole on the substrate falling within a projection of the first sub-hole on the substrate; the transistor comprising a first electrode, a second electrode, and a semiconductor layer surrounding a sidewall of the word line; the first electrode and the second electrode being arranged in the first conductive layer; a plurality of semiconductor layers of the plurality of transistors being arranged at intervals, the plurality of semiconductor layers being arranged in different regions of the sidewall of the word line; the via hole comprising, from inside to outside, the word line, a gate insulating layer surrounding the sidewall of the word line, and the plurality of semiconductor layers surrounding different regions of the sidewall of the gate insulating layer; a sidewall of the via hole comprising a first sidewall of a first sub-hole and a second sidewall of a second sub-hole connected to the first sidewall, the first sidewall forming a groove relative to the second sidewall, the groove comprising a sub-sidewall extending along a direction perpendicular to the substrate, the semiconductor layer continuously extending on the second sidewall and continuously extending from the second sidewall to the sub-sidewall of the groove extending along the direction perpendicular to the substrate, and not being arranged on the sub-sidewall so that the plurality of semiconductor layers are disconnected on the sub-sidewall. the semiconductor layer being connected to a sidewall of the first electrode and the second electrode, and being connected to at least one of an upper surface and a lower surface of the first electrode and the second electrode. the first insulating layer only exposing a sidewall in the via hole, and the first conductive layer exposing a sidewall and a partial region of an upper surface and a lower surface in the via hole; the semiconductor layer being arranged at least on the sidewall of the first conductive layer. the semiconductor layer being further arranged on the upper surface and the lower surface of the first conductive layer exposed in the via hole and not being arranged on the sidewall of the first insulating layer exposed in the via hole. the semiconductor layer comprising a first sidewall and a second sidewall arranged opposite along a first direction, the first direction being perpendicular to an extension direction of the substrate and the first electrode; the via hole further comprising a barrier layer arranged on the first sidewall and the second sidewall of the plurality of semiconductor layers away from the word line. the barrier layers of the semiconductor layers of different layers being spaced apart from each other. the barrier layer not being arranged on the sidewall of the first insulating layer exposed in the via hole, and not being arranged on the sidewall, the upper surface, and the lower surface of the first conductive layer exposed in the via hole. gate insulating layers of the plurality of transistors in different layers being connected to form an integrated structure. The semiconductor device comprises: a plurality of transistors stacked along a vertical substrate direction in different layers; a word line extending along the vertical substrate direction through the different layers; a first insulating layer and a first conductive layer alternately arranged along the vertical substrate direction from bottom to top; a via hole through each of the first insulating layer and the first conductive layer, the word line being arranged in the via hole, a second sub-hole of the first conductive layer being located in the via hole, a first sub-hole of the first insulating layer being located in the via hole, a projection of the second sub-hole on the substrate falling within a projection of the first sub-hole on the substrate; the transistor comprising a first electrode, a second electrode, and a semiconductor layer surrounding a sidewall of the word line; the first electrode and the second electrode being arranged in the first conductive layer; a plurality of semiconductor layers of the plurality of transistors being arranged at intervals, the plurality of semiconductor layers being arranged in different regions of the sidewall of the word line; the via hole comprising, from inside to outside, the word line, a gate insulating layer surrounding the sidewall of the word line, and the plurality of semiconductor layers surrounding different regions of the sidewall of the gate insulating layer; a sidewall of the via hole comprising a first sidewall of a first sub-hole and a second sidewall of a second sub-hole connected to the first sidewall, the first sidewall forming a groove relative to the second sidewall, the groove comprising a sub-sidewall extending along a direction perpendicular to the substrate, the semiconductor layer continuously extending on the second sidewall and continuously extending from the second sidewall to the sub-sidewall of the groove extending along the direction perpendicular to the substrate, and not being arranged on the sub-sidewall so that the plurality of semiconductor layers are disconnected on the sub-sidewall. the semiconductor layer being connected to a sidewall of the first electrode and the second electrode, and being connected to at least one of an upper surface and a lower surface of the first electrode and the second electrode. the first insulating layer only exposing a sidewall in the via hole, and the first conductive layer exposing a sidewall and a partial region of an upper surface and a lower surface in the via hole; the semiconductor layer being arranged at least on the sidewall of the first conductive layer. the semiconductor layer being further arranged on the upper surface and the lower surface of the first conductive layer exposed in the via hole and not being arranged on the sidewall of the first insulating layer exposed in the via hole. the semiconductor layer comprising a first sidewall and a second sidewall arranged opposite along a first direction, the first direction being perpendicular to an extension direction of the substrate and the first electrode; the via hole further comprising a barrier layer arranged on the first sidewall and the second sidewall of the plurality of semiconductor layers away from the word line. the barrier layers of the semiconductor layers of different layers being spaced apart from each other. the barrier layer not being arranged on the sidew A substrate is provided, on which a first insulating thin film and a first conductive thin film are sequentially and alternately deposited to form a plurality of stack structures by patterning; each of the stack structures comprises a stack of first insulating layers and first conductive layers arranged alternately, the first conductive layers comprising a preset electrode pattern, the preset electrode pattern comprising first conductive portions extending along a second direction, the first conductive portions comprising first electrodes and second electrodes of the transistors to be formed; The first conductive layers are etched laterally along a first direction, so that the first conductive portions in the first direction fall within the orthographic projection of the first insulating layers on the substrate; A barrier layer is formed covering the sidewalls of the first conductive portions and the sidewalls of the first insulating layers; The stack structures are etched to form first through holes penetrating each of the first conductive layers and each of the first insulating layers of the stack structures in a direction perpendicular to the substrate, the sidewalls of the first through holes exposing each of the first insulating layers, the first insulating layers being etched laterally by wet etching and the barrier layer not being etched, so that in a plane parallel to the substrate, the orthographic projection of the first through holes in the first conductive layers falls within the orthographic projection of the first through holes in the first insulating layers, and the first through holes disconnect the first electrodes and the second electrodes in the preset electrode pattern; Semiconductor thin films, gate insulating thin films and gate electrode thin films are sequentially deposited in the first through holes to form a plurality of semiconductor layers, gate insulating layers and word lines of the transistors, the word lines filling the through holes; The stack structures are etched to form second through holes penetrating the stack structures in a direction perpendicular to the substrate, the second through holes exposing the sidewalls of the semiconductor layers extending along the second direction within the first through holes of the first insulating layers; The semiconductor layers within the first through holes of the first insulating layers are removed by etching through the second through holes.

11. The method of manufacturing a semiconductor device according to Claim 10, wherein The second through holes also expose part of the sidewalls of the semiconductor layers extending along the first direction within the first through holes of the first insulating layers.

12. The method of manufacturing a semiconductor device according to Claim 10 or 11, wherein Before the semiconductor thin films, the gate insulating thin films and the gate electrode thin films are sequentially deposited in the first through holes, the barrier layer is silicon nitride, and the barrier layer within the first through holes is removed by etching.

13. The method of manufacturing a semiconductor device according to claim 10 or 11, wherein After the semiconductor layers within the first through holes of the first insulating layers are removed by etching through the second through holes, an insulating thin film is deposited to fill the second through holes.

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