Semiconductor device and method of manufacturing the same, electronic device

Abstract

A method for manufacturing a semiconductor device includes: alternately depositing a first insulating film and a second insulating film on a substrate to form a stacked structure; etching the stacked structure to form a first via hole that penetrates the stacked structure in a direction perpendicular to the substrate; forming a sacrificial layer that fills the first via hole; etching and removing the second insulating film; depositing a first conductive film to form a first electrode and a second electrode of a plurality of transistors, the first electrode and the second electrode of the transistors being separated by the sacrificial layer; etching a portion of the sacrificial layer in the first via hole to form a second via hole that penetrates the sacrificial layer in a direction perpendicular to the substrate; sequentially forming a semiconductor layer, a gate insulating line layer, and a word line of the plurality of transistors in the second via hole; etching the sacrificial layer around the second via hole to expose at least a portion of the semiconductor layer in an interlayer region of adjacent layers; and etching and removing the exposed semiconductor layer to separate the semiconductor layers of the transistors of the adjacent layers.

Description

TECHNICAL FIELD

[0001] The present document relates to, but is not limited to, the field of device design and manufacture of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same, and an electronic device. BACKGROUND

[0002] Semiconductor memory can be classified into volatile memory (RAM, including DRAM and SRAM, etc.) and non-volatile memory (ROM and non- ROM) in terms of application. Taking DRAM as an example, the conventional known DRAM has a plurality of repeated memory cells, each memory cell having a capacitor and a transistor. The capacitor can store 1 bit of data, and after charging and discharging, the amount of charge stored in the capacitor can correspond to binary data “0” and “1”, respectively. The transistor is a switch that controls the charging and discharging of the capacitor.

[0003] In order to reduce the cost of products as much as possible, people want to make as many memory cells as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs. SUMMARY

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, and an electronic device.

[0006] In one aspect, the embodiments provide a method for manufacturing a semiconductor device. The semiconductor device includes a plurality of transistors stacked along a direction perpendicular to a substrate and periodically distributed in different layers, and a word line extending through the different layers along the direction perpendicular to the substrate. The transistor includes a first electrode, a second electrode, a gate electrode extending along the direction perpendicular to the substrate, a semiconductor layer arranged around a sidewall of the gate electrode and insulated from the gate electrode, and a gate insulating layer arranged between the gate electrode and the semiconductor layer. The method for manufacturing the semiconductor device includes providing a substrate, depositing a first insulating film and a second insulating film alternately on the substrate to form a stack structure, etching the stack structure to form a first via hole extending through the stack structure along the direction perpendicular to the substrate, forming a sacrificial layer filling the first via hole, etching and removing the second insulating film, depositing a first conductive film to form a first conductive layer, the first conductive layer including at least the first electrode and the second electrode of the plurality of transistors, the first electrode and the second electrode of the transistor being separated by the sacrificial layer, etching part of the sacrificial layer in the first via hole to form a second via hole extending through the sacrificial layer along the direction perpendicular to the substrate, the sidewall of the second via hole exposing the first electrode and the second electrode of the transistor, and the sidewall of the second via hole in an interlayer region of adjacent layers exposing the sacrificial layer, depositing a semiconductor film, a gate insulating film, and a third conductive film in the second via hole to form a semiconductor layer, a gate insulating layer, and a third conductive layer of the plurality of transistors, the third conductive layer including the word line and the gate electrode of the plurality of transistors, the plurality of transistors in the same layer being connected to the same word line, the gate electrode of each transistor in the plurality of transistors being part of the word line, and the semiconductor layer of the transistor being in contact with the first electrode and the second electrode of the transistor, and etching the sacrificial layer around the second via hole to expose at least part of the semiconductor layer in the interlayer region of adjacent layers, and etching and removing the exposed semiconductor layer to separate the semiconductor layer of the transistors in adjacent layers.

[0007] In some example embodiments, the etching the stack structure to form the first via hole extending through the stack structure along the direction perpendicular to the substrate includes forming a hard mask layer on a side of the stack structure away from the substrate, etching the first insulating film and the second insulating film of the stack structure using the hard mask layer to form a first initial via hole in the first insulating film and a second via hole in the second insulating film, the first initial via hole and the second via hole being aligned and connected in the direction perpendicular to the substrate, and wet-etching the first insulating film to expand the first initial via hole to a first via hole.

[0008] In some example embodiments, the depositing a first conductive thin film to form a first conductive layer comprises: depositing a first conductive thin film, etching the first conductive thin film by dry etching such that the edge of the etched first conductive thin film is flush with the edge of the first insulating thin film; etching the first conductive thin film by wet etching such that the edge of the first conductive thin film is recessed inwardly of the edge of the first insulating thin film, and the first conductive thin film on both sides of the sacrificial layer is disconnected to form the first electrode and the second electrode of the transistor.

[0009] In some example embodiments, the thickness of the wet etching for the first insulating thin film is the same as the thickness of the wet etching for the first conductive thin film. In some example embodiments, the semiconductor device further comprises: a plurality of capacitors, the capacitors comprising a first plate and a second plate, the second electrode of the transistor and the first plate of the connected capacitor being an integrated structure. After forming the first conductive layer and before etching the partial sacrificial layer in the first via, the preparation method further comprises: depositing a first insulating thin film to cover the first conductive layer; etching part of the first insulating thin film to expose part of the surface of the first electrode and the second electrode of the plurality of transistors and part of the surface of the sacrificial layer facing the first electrode; sequentially depositing a third insulating thin film and a second conductive thin film in the area where the first insulating thin film is removed to form a third insulating layer and a second conductive layer, the second conductive layer comprising: the second plate of the capacitor, the third insulating layer being between the first plate and the second plate of the capacitor.

[0010] In some example embodiments, after etching the partial sacrificial layer in the first via to form a second via penetrating the sacrificial layer in a direction perpendicular to the substrate, the preparation method further comprises: etching the sacrificial layer in the second via to increase the size of the second via and thin the sacrificial layer on the periphery of the second via.

[0011] In some example embodiments, the etching the sacrificial layer on the periphery of the second via to expose at least part of the semiconductor layer in the interlayer region of the adjacent layer and etching the exposed semiconductor layer such that the semiconductor layers of the transistors of the adjacent layers are spaced apart comprises: etching the first insulating thin film by dry etching and wet etching in sequence to expose the sacrificial layer in the interlayer region of the adjacent layer, etching the sacrificial layer to expose at least part of the semiconductor layer in the interlayer region of the adjacent layer; etching the exposed semiconductor layer by wet etching such that the semiconductor layers of the transistors of different layers are spaced apart.

[0012] In some example embodiments, the sacrificial layer is made of a material that has a selectivity ratio with the wet etching of the semiconductor layer.

[0013] In some example embodiments, the material of the sacrificial layer comprises aluminum oxide.

[0014] In another aspect, the embodiments provide a semiconductor device, including: a word line and a plurality of transistors. The plurality of transistors are stacked along a direction perpendicular to a substrate and periodically distributed in different layers; the word line extends through the different layers and along the direction perpendicular to the substrate. The transistors include: a gate electrode extending along the direction perpendicular to the substrate, a semiconductor layer disposed around a sidewall of the gate electrode and insulated from the gate electrode, a gate insulating layer disposed between the gate electrode and the semiconductor layer; a plurality of transistors are connected to the same word line along the direction perpendicular to the substrate, the gate electrode of each transistor of the plurality of transistors is a part of the word line; the semiconductor layers of the plurality of transistors are spaced apart. The word line in an interlayer region of adjacent layers is surrounded by the gate insulating layer, and the gate insulating layer in the interlayer region of adjacent layers is surrounded by a first insulating layer.

[0015] In some example embodiments, at least part of the gate insulating layer in the interlayer region of adjacent layers is in contact with an independent semiconductor layer, and the semiconductor layer in the interlayer region of adjacent layers is in contact with a sacrificial layer; the semiconductor layer in the interlayer region of adjacent layers is disconnected from the semiconductor layer of the transistor.

[0016] In some example embodiments, the material of the sacrificial layer includes: aluminum oxide.

[0017] In some example embodiments, the word line includes: a first main body portion and a second main body portion extending along the direction perpendicular to the substrate and alternately connected, the first main body portion serving as the gate electrode of the transistor, and the second main body portion being located in the interlayer region of adjacent layers; a footprint of the first main body portion on the substrate is within a footprint of the second main body portion on the substrate.

[0018] In some example embodiments, the gate insulating layer includes: a first insulating portion and a second insulating portion extending along the direction perpendicular to the substrate and alternately connected, the first insulating portion being located between the semiconductor layer and the gate electrode of the transistor, and the second insulating portion being located in the interlayer region of adjacent layers, the second insulating portion forming a step on a surface of the first insulating portion in a plane parallel to the substrate; the semiconductor layer of the transistor is distributed on a sidewall of the first insulating portion and the step.

[0019] In another aspect, the embodiments provide an electronic device including the semiconductor device as described above.

[0020] Other aspects can become apparent after reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0021] The accompanying drawings are used to provide an understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.

[0022] FIG. 1 A perspective view of a semiconductor device according to at least one embodiment of the present disclosure;

[0023] FIG. 2 A perspective view of a semiconductor device according to at least one embodiment of the present disclosure; FIG. 1 A top view of a semiconductor device according to at least one embodiment of the present disclosure;

[0024] FIG. 3 A perspective view of a semiconductor device according to at least one embodiment of the present disclosure; FIG. 1 A sectional view of the semiconductor device along the AA' direction according to at least one embodiment of the present disclosure;

[0025] FIG. 4 A perspective view of a semiconductor device according to at least one embodiment of the present disclosure; FIG. 1 A perspective view of a semiconductor device according to at least one embodiment of the present disclosure, in which the first insulating layer is omitted;

[0026] FIG. 5 A perspective view of a semiconductor device according to at least one embodiment of the present disclosure, in which the first insulating layer is omitted; FIG. 4 A partial enlarged view of the dashed area according to at least one embodiment of the present disclosure;

[0027] FIG. 6A A perspective view of a laminated structure according to at least one embodiment of the present disclosure;

[0028] FIG. 6B A perspective view of a laminated structure according to at least one embodiment of the present disclosure; FIG. 6A A sectional view of the laminated structure according to at least one embodiment of the present disclosure in a plane where the first direction and the third direction are located;

[0029] FIG. 7A A perspective view of a laminated structure according to at least one embodiment of the present disclosure after forming a first via;

[0030] FIG. 7B A sectional view of the laminated structure according to at least one embodiment of the present disclosure along the AA' direction after one etching;

[0031] FIG. 7C A sectional view of the laminated structure according to at least one embodiment of the present disclosure along the AA' direction after forming the first via;

[0032] FIG. 7D A sectional view of the laminated structure according to at least one embodiment of the present disclosure along the BB' direction after forming the first via;

[0033] FIG. 7E A sectional view of the second insulating film according to at least one embodiment of the present disclosure parallel to the plane where the substrate is located after forming the first via;

[0034] FIG. 7F A sectional view of the first insulating film according to at least one embodiment of the present disclosure parallel to the plane where the substrate is located after forming the first via;

[0035] FIG. 8AA perspective view of a layer structure after forming a sacrificial layer for at least one embodiment of the present disclosure;

[0036] FIG. 8B A perspective view of a layer structure after forming a first insulating film for at least one embodiment of the present disclosure; FIG. 8A A cross-sectional view along the AA' direction in the middle;

[0037] FIG. 8C A perspective view of a layer structure after forming a first insulating film for at least one embodiment of the present disclosure; FIG. 8A A cross-sectional view along the AA' direction in the middle;

[0038] FIG. 9A A perspective view of a layer structure after forming a groove for at least one embodiment of the present disclosure;

[0039] FIG. 9B A perspective view of a layer structure after forming a groove for at least one embodiment of the present disclosure; FIG. 9A A cross-sectional view along the AA' direction in the middle;

[0040] FIG. 10A A perspective view of a layer structure after forming a support layer for at least one embodiment of the present disclosure;

[0041] FIG. 10B A perspective view of a layer structure after forming a support layer for at least one embodiment of the present disclosure; FIG. 10A A cross-sectional view along the AA' direction in the middle;

[0042] FIG. 10C A perspective view of a layer structure after forming a support layer for at least one embodiment of the present disclosure; FIG. 10A A plan view of a layer structure in the middle;

[0043] FIG. 11A A perspective view of a layer structure after forming a first hollow part and a second hollow part for at least one embodiment of the present disclosure;

[0044] FIG. 11B A perspective view of a layer structure after forming a first hollow part and a second hollow part for at least one embodiment of the present disclosure; FIG. 11A A cross-sectional view along the BB' direction in the middle;

[0045] FIG. 11C A plan view of a layer structure in the middle; FIG. 11A A plan view of a layer structure in the middle;

[0046] FIG. 12A A perspective view of a layer structure after removing a second insulating film for at least one embodiment of the present disclosure;

[0047] FIG. 12B A perspective view of a layer structure after removing a second insulating film for at least one embodiment of the present disclosure; FIG. 12A A cross-sectional view along the AA' direction in the middle;

[0048] FIG. 12C A cross-sectional view along the BB' direction in the middle; FIG. 12A A cross-sectional view along the BB' direction in the middle;

[0049] FIG. 13A A perspective view of a layer structure after depositing a first conductive film for at least one embodiment of the present disclosure;

[0050] FIG. 13B for FIG. 13A A cross-sectional view of the first insulating film in a plane parallel to the substrate;

[0051] FIG. 14A is a three-dimensional schematic diagram of a stacked structure after the first conductive film is etched once in at least one embodiment of the present disclosure;

[0052] FIG. 14B for FIG. 14A Cross-sectional view along BB' direction;

[0053] FIG. 14C for FIG. 14A Schematic top view of the laminated structure;

[0054] FIG. 15A is a three-dimensional schematic diagram of a stacked structure after the first conductive film is etched twice in at least one embodiment of the present disclosure;

[0055] FIG. 15B for FIG. 15A Cross-sectional view along AA' direction;

[0056] FIG. 15C for FIG. 15A Cross-sectional view along BB' direction;

[0057] FIG. 16A A three-dimensional schematic diagram of a stacked structure after the first insulating film is deposited again according to at least one embodiment of the present disclosure;

[0058] FIG. 16B for FIG. 16A Schematic top view of the laminated structure;

[0059] FIG. 17A is a three-dimensional schematic diagram of the stacked structure after the sixth hollow portion and the seventh hollow portion are formed in at least one embodiment of the present disclosure;

[0060] FIG. 17B for FIG. 17A Cross-sectional view along AA' direction;

[0061] FIG. 17C for FIG. 17A Schematic top view of the laminated structure;

[0062] FIG. 18A A three-dimensional schematic diagram of a stacked structure after forming a second electrode plate of a capacitor according to at least one embodiment of the present disclosure;

[0063] FIG. 18B for FIG. 18A Cross-sectional view along AA' direction;

[0064] FIG. 18C for FIG. 18Aa top view of the stack structure in the embodiment of the present disclosure;

[0065] FIG. 19A a perspective view of the stack structure after etching the sacrificial layer in at least one embodiment of the present disclosure;

[0066] FIG. 19B a perspective view of the stack structure after etching the sacrificial layer in at least one embodiment of the present disclosure; FIG. 19A a cross-sectional view along the direction of AA' in the embodiment of the present disclosure;

[0067] FIG. 19C a cross-sectional view along the direction of AA' in the embodiment of the present disclosure; FIG. 9A a top view of the stack structure in the embodiment of the present disclosure;

[0068] FIG. 19A a cross-sectional view along the direction of AA' of the stack structure after widening the second via in at least one embodiment of the present disclosure;

[0069] FIG. 19B a top view of the stack structure after widening the second via in at least one embodiment of the present disclosure;

[0070] FIG. 20A a perspective view of the stack structure after forming the semiconductor layer, the gate insulating layer and the third conductive layer in at least one embodiment of the present disclosure;

[0071] FIG. 20B a perspective view of the stack structure after forming the semiconductor layer, the gate insulating layer and the third conductive layer in at least one embodiment of the present disclosure; FIG. 21A a cross-sectional view along the direction of AA' in the embodiment of the present disclosure;

[0072] FIG. 21B a cross-sectional view along the direction of AA' in the embodiment of the present disclosure; FIG. 21A a top view of the stack structure in the embodiment of the present disclosure;

[0073] FIG. 21C a perspective view of the stack structure after etching the first insulating film in at least one embodiment of the present disclosure;

[0074] FIG. 21A a perspective view of the stack structure after etching the first insulating film in at least one embodiment of the present disclosure; FIG. 22A

[0075] FIG. 22B a perspective view of the stack structure after etching the sacrificial layer in at least one embodiment of the present disclosure;

[0076] FIG. 22A a perspective view of the stack structure after etching the sacrificial layer in at least one embodiment of the present disclosure; FIG. 23A a cross-sectional view along the direction of AA' in the embodiment of the present disclosure;

[0077] FIG. 23B a cross-sectional view along the direction of AA' in the embodiment of the present disclosure; FIG. 23A a top view of the stack structure in the embodiment of the present disclosure;

[0078] FIG. 23C a perspective view of the stack structure after etching the exposed semiconductor layer in at least one embodiment of the present disclosure;

[0079] ​FIG. 23A FIG. 1 is a schematic plan view of a semiconductor device according to one embodiment of the present disclosure. FIG. 24A FIG. 2 is a schematic cross-sectional view of the semiconductor device of FIG. 1 along the direction of AA'.

[0080] FIG. 24B FIG. 3 is a schematic plan view of a semiconductor device according to another embodiment of the present disclosure. FIG. 24A FIG. 4 is a schematic cross-sectional view of the semiconductor device of FIG. 3 along the direction of AA'.

[0081] FIG. 24C FIG. 5 is a schematic cross-sectional view of another semiconductor device according to one embodiment of the present disclosure along the direction of AA'. DETAILED DESCRIPTION

[0082] Embodiments of the present disclosure will be described below with reference to the accompanying drawings. The embodiments can be implemented in various forms. It is readily apparent to those skilled in the art that the embodiments and features thereof can be changed or replaced without departing from the gist of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the following embodiments. The embodiments and features in the present disclosure can be combined with each other as long as they are not inconsistent with each other.

[0083] In the drawings, the size, the layer thickness, or the region of one or more of the constituent elements can sometimes be exaggerated for the sake of explanation. Thus, one embodiment of the present disclosure is not necessarily limited by the size, the shape, or the relative arrangement of the components illustrated in the drawings. The drawings are schematic illustrations used for explanation of the principle of the present disclosure, and the shape, the numerical value, and the like are not limited to those illustrated in the drawings.

[0084] In this specification, ordinal terms such as "first", "second", and "third" are used merely to avoid confusion with one another, and do not necessarily limit the number or order of an execution sequence. In the present disclosure, "a plurality of" means two or more.

[0085] In this specification, terms of direction or position relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the components with reference to the drawings, and are merely for convenience of the description of the specification and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be construed as limiting the present disclosure. The positional relationship of the components is appropriately changed according to the direction of the components described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed depending on the situation.

[0086] In this specification, unless otherwise explicitly specified and limited, the terms "mount", "connected", "connection" should be interpreted broadly. For example, it can be fixed connection, or detachable connection, or integral connection; can be physical connection or signal connection; can be direct connection, or indirect connection through intermediate parts, or internal connection of two elements. For those skilled in the art, the meaning of the above terms in this disclosure can be understood according to the circumstances.

[0087] In this specification, "connection" or "electric connection" can include the case where the constituent elements are connected together through an element having some electrical effect. The element having some electrical effect is not particularly limited as long as it can perform transmission of electrical signals between the constituent elements to be connected. Examples of the element having some electrical effect include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.

[0088] In this specification, a transistor can include a gate (also referred to as a gate electrode), a channel, a first electrode, and a second electrode. In this specification, the first electrode can be a drain electrode, and the second electrode can be a source electrode, or the first electrode can be a source electrode, and the second electrode can be a drain electrode. The source electrode can also be referred to as a source electrode terminal, a source region, or a source. The drain electrode can also be referred to as a drain electrode terminal, a drain region, or a drain. In the case of using a transistor whose polarity is reversed, or in the case where the direction of current flowing in a circuit is changed, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Thus, in this specification, the "source electrode" and the "drain electrode" can be interchanged.

[0089] In this specification, "parallel" means a state where an angle formed by two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus, a state where the angle is greater than or equal to -5° and less than or equal to 5° is also included. In addition, "perpendicular" means a state where an angle formed by two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus, a state where the angle is greater than or equal to 85° and less than or equal to 95° is also included.

[0090] In this specification, "A and B are provided in the same layer" includes a case where the same material or different materials are formed into a film layer. For example, A and B are formed into the same film layer by the same material and then formed by the same patterning process or different patterning processes. A and B provided in the same layer can be located on the same horizontal plane but do not necessarily have to be located on the same film layer, or can be located in different regions of the same film layer but do not necessarily have to be located on the same horizontal plane.

[0091] In the embodiments of the present disclosure, “A and B are an integrated structure connected to each other” can include that the connected film layers are integrated by patterning on one film layer. For example, A and B are structures connected to each other formed by using the same material on one film layer and by the same patterning process.

[0092] In the embodiments of the present disclosure, “substrate” means and includes a base material or structure on which materials such as vertical field effect transistors are formed. The substrate can be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. The substrate can be a conventional silicon substrate or other bulk substrate including a layer of semiconductor material.

[0093] The embodiments provide a semiconductor device and a preparation method thereof, and an electronic device, which can effectively reduce or eliminate a parasitic MOS (referred to as a parasitic MOS) under the premise of ensuring the size of the semiconductor device.

[0094] The embodiments provide a semiconductor device, comprising: a word line (WL, World Line) and a plurality of transistors. The plurality of transistors are stacked along a direction perpendicular to a substrate and periodically distributed in different layers; the word line extends along a direction perpendicular to the substrate and penetrates through the different layers. The transistor comprises: a gate electrode extending along a direction perpendicular to the substrate, a semiconductor layer arranged around a sidewall of the gate electrode and insulated from the gate electrode, and a gate insulating layer arranged between the gate electrode and the semiconductor layer. The plurality of transistors arranged along a direction perpendicular to the substrate are connected to the same word line, the gate electrode of each transistor in the plurality of transistors is part of the word line; the semiconductor layers of the plurality of transistors are arranged at intervals; the word line in the interlayer region of the adjacent layers is surrounded by the gate insulating layer, and the gate insulating layer in the interlayer region of the adjacent layers is surrounded by a first insulating layer.

[0095] The semiconductor device of the embodiments can effectively reduce or eliminate the parasitic MOS in at least part of the interlayer region by arranging the semiconductor layers of the plurality of transistors at intervals, thereby improving the stability of the device.

[0096] In some example embodiments, the channel between the first electrode and the second electrode of the transistor is a horizontal channel. The horizontal channel is a channel in which the direction of carrier transport is overall in a plane parallel to the substrate.

[0097] In some example embodiments, at least part of the gate insulating layer in the interlayer region of the adjacent layer is in contact with the independent semiconductor layer, the semiconductor layer in the interlayer region of the adjacent layer is in contact with the sacrificial layer; the semiconductor layer in the interlayer region of the adjacent layer is disconnected from the semiconductor layer of the transistor. In some examples, the material of the sacrificial layer comprises: aluminum oxide. In some examples, during the preparation of the semiconductor device, the semiconductor layer in the interlayer region is removed by sequentially exposing the sacrificial layer and the semiconductor layer in the interlayer region, and under the limitation of process conditions, when the sacrificial layer remains, the semiconductor layer protected by the sacrificial layer can be partially remained, so that the semiconductor layer disconnected from the semiconductor layer of the transistor remains outside the gate insulating layer in the interlayer region. The present example achieves the reduction of the parasitic MOS in the interlayer region by etching away the small range of semiconductor layer exposed by the sacrificial layer.

[0098] In some example embodiments, the word line can comprise: a first main body portion and a second main body portion which are connected alternately and extend in a direction perpendicular to the substrate, the first main body portion can serve as the gate electrode of the transistor, and the second main body portion can be located in the interlayer region of the adjacent layer; the orthographic projection of the first main body portion on the substrate can be located within the orthographic projection range of the second main body portion on the substrate. In the present example, the cross-sectional size of the word line at different positions in the extension direction can be different. For example, the cross-sectional size of the first main body portion of the word line serving as the gate electrode of the transistor can be smaller than the cross-sectional size of the second main body portion of the word line located in the interlayer region. However, the present embodiment is not limited thereto. In other examples, the cross-sectional size of the word line at different positions in the extension direction can be the same.

[0099] In some example embodiments, the gate insulating layer can comprise: a first insulating portion and a second insulating portion which are connected alternately and extend in a direction perpendicular to the substrate, the first insulating portion can be located between the semiconductor layer and the gate electrode of the transistor, and the second insulating portion can be located in the interlayer region of the adjacent layer, and the second insulating portion protrudes from the surface of the first insulating portion to form a step in a plane parallel to the substrate; the semiconductor layer of the transistor is distributed on the sidewall of the first insulating portion and the step. In the present example, the topography of the word line can make the gate insulating layer form a step, and through the step, the semiconductor layer damaged in the interlayer region can be prevented from extending to the layer where the transistor is located, so as to ensure the performance of the transistor.

[0100] The scheme of the present embodiment is exemplified below through some examples.

[0101] FIG. 24A A perspective schematic view of a semiconductor device of at least one embodiment of the present disclosure. FIG. 25 A perspective schematic view of a semiconductor device. FIG. 1 A top view schematic view of a semiconductor device. FIG. 2 A top view schematic view of a semiconductor device. FIG. 1 A cross-sectional view along the direction of AA' in the above-described semiconductor device. FIG. 3 A cross-sectional view along the direction of AA' in the above-described semiconductor device. FIG. 1Schematic diagram of a three-dimensional semiconductor device after omitting the first insulating layer. FIG. 4 for FIG. 1 A partial enlarged schematic diagram of the dashed area. This example uses three layers of memory cells stacked perpendicular to the substrate as an example. Each layer of memory cells may include multiple memory cells arranged in an array along a first direction D1 and a second direction D2, for example, six memory cells arranged in a 2×3 array.

[0102] In some examples, the plane in which the first direction D1 and the second direction D2 lie can be parallel to the plane in which the substrate 100 lies, and the third direction D3 can be perpendicular to the plane in which the substrate 100 lies. The first direction D1 and the second direction D2 can intersect; for example, the first direction D1 can be perpendicular to the second direction D2. Within a plane parallel to the substrate, a plurality of memory cells arranged along the first direction D1 can be referred to as a row of memory cells, and a plurality of memory cells arranged along the second direction D2 can be referred to as a column of memory cells. In this example, in each layer, two columns of memory cells can be arranged along the first direction D1, and three rows of memory cells can be arranged along the second direction D2.

[0103] In some examples, such as FIG. 5 As shown, the semiconductor device may include: layer regions 300 and interlayer regions 400 alternately arranged along a third direction D3. The layer region 300 may include a plurality of memory cells arranged in an array. The memory cell may include: a transistor and a capacitor. The transistor may include: a first electrode 31, a second electrode 32, a gate electrode 33, and a semiconductor layer 34. The capacitor may include: a first plate 41 and a second plate 42. The first electrode 31 of the transistor of the memory cell is connected to the first plate 41 of the capacitor. For example, the first electrode 31 of the transistor and the first plate 41 of the connected capacitor may be an integrated structure connected to each other. Multiple memory cells (for example, six memory cells) located in the same layer may be electrically connected to the same bit line 22. For example, the bit line 22 may extend along the second direction D2. The second electrodes 32 of the transistors of two adjacent columns of memory cells may be connected to the same bit line 22. For example, the second electrodes 32 of the transistors of two adjacent columns of the same layer may be connected to the same bit line 22.

[0104] In some examples, such as FIG. 4As shown, the gate electrodes 33 of the transistors of the multiple memory cells arranged along the third direction D3 can be connected to the same word line 21, and the gate electrodes 33 of the multiple transistors and the word line 21 can be an integrated structure connected to each other. The gate electrode 33 of the transistor can be insulated from the semiconductor layer 34. The semiconductor layer 34 extends on the sidewall of the gate electrode 33 to form a ring structure extending along the third direction D3. The semiconductor layer 34 can completely surround the gate electrode 33. For example, the semiconductor layer 34 surrounding the gate electrode 33 can be a closed ring in a cross section parallel to the plane where the substrate is located. In other examples, the semiconductor layer 34 can partially surround the gate electrode 33, and the semiconductor layer 34 surrounding the gate electrode 33 can not be closed in a cross section parallel to the plane where the substrate is located, but can have an open ring.

[0105] In some examples, such as FIG. 1 to FIG. 3 and FIG. 1 to FIG. 3 As shown, a gate insulating layer 35 can be provided around the sidewalls of the wordline 21. The gate insulating layer 35 directly contacts the wordline 21 and extends along the sidewalls of the wordline 21 to form a ring-shaped structure extending along the third direction D3. The gate insulating layer 35 can include a first insulating portion 351 located in the layer region 300 and a second insulating portion 352 located in the interlayer region 400. The first insulating portion 351 and the second insulating portion 352 can be an interconnected, integral structure. The first insulating portion 351 is located between the semiconductor layer 34 and the gate electrode 33 of the transistor and directly contacts the semiconductor layer 34 and the gate electrode 33 to ensure insulation between the semiconductor layer 34 and the gate electrode 33. The interlayer region 400 may not include a semiconductor layer, allowing the semiconductor layers 34 of adjacent layer regions 300 to be separated and spaced apart. The second insulating portion 352 of the gate insulating layer 35 in the interlayer region 400 can be in direct contact with the first insulating layer 51. The first insulating layer 51 can surround the second insulating portion 352, and the second insulating portion 352 can surround the wordline 21.

[0106] In some examples, such as FIG. 1 As shown, the word line 21 may include a first main portion 211 and a second main portion 212 extending along a third direction D3 and alternately connected. The first main portion 211 may be located in the layer region 300 and may serve as the gate electrode 33 of the transistor. The second main portion 212 may be located in the interlayer region 400. The first main portion 211 and the second main portion 212 are an integral structure connected to each other. The orthographic projection of the first main portion 211 on the substrate 100 may be located within the orthographic projection of the second main portion 212 on the substrate 100. For example, if the cross-sectional shape of the first and second main portions 211, 212 of the word line 21 is a square when parallel to the substrate, the side length of the first main portion 211 may be smaller than the side length of the second main portion 212.

[0107] In some examples, such as FIG. 3As shown, due to the different sizes of the first body portion 211 and the second body portion 212 of the word line 21, a step 200 can be formed between the first insulating portion 351 and the second insulating portion 352 of the gate insulating layer 35. The step 200 can be formed on the surface of the second insulating portion 352 that protrudes from the first insulating portion 351 parallel to the plane of the substrate. The semiconductor layer 34 of the transistor can be distributed on the sidewalls of the first insulating portion 351 and on the step 200. The formation of the step 200 prevents the semiconductor layer damaged in the interlayer region from extending to the layer region 300, thereby ensuring the performance of the transistor.

[0108] In some examples, such as FIG. 3 As shown, the first electrode 31 of the transistor and the first plate 41 of the capacitor can be an integrated structure connected to each other. The integrated structure of the first electrode 31 and the first plate 41 can extend in a plane parallel to the substrate. The first electrode 31 and the second electrode 32 of the transistor can be in direct contact with the semiconductor layer 34. The second plate 42 of the capacitor can be located on the side of the first plate 31 away from the gate electrode. FIG. 3 to FIG. 5 and FIG. 3 As shown, for two columns of memory cells arranged along the first direction D1, the second plates of the capacitors of the first column of memory cells can be located on the side of the connected word line 21 opposite to the first direction D1, and the second plates of the capacitors of the second column of memory cells can be located on the side of the connected word line 21 in the first direction D1. The second plates of the capacitors of multiple memory cells can be interconnected and integrally formed. A third insulating layer 52 can be disposed between the second plate 42 of the capacitor and the first plate 41.

[0109] The technical solution of this embodiment is further explained below through the preparation process of the semiconductor device of this embodiment. The "composition process" mentioned in this embodiment includes processes such as depositing a film layer, applying a photoresist, mask exposure, development, etching, and stripping the photoresist, and is a mature preparation process in the relevant technology. The "photolithography process" mentioned in this embodiment includes coating a film layer, mask exposure and development, and is a mature preparation process in the relevant technology. Deposition can adopt known processes such as sputtering, evaporation, and chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not limited here.

[0110] In some examples, a semiconductor device fabrication process may include the following steps. In this example, a cross-sectional view along the AA' direction refers to a cross-sectional view passing through the AA' direction and perpendicular to the plane of the substrate, and a cross-sectional view along the BB' direction refers to a cross-sectional view passing through the BB' direction and perpendicular to the plane of the substrate.

[0111] (1) A first insulating film 11 and a second insulating film 12 are alternately deposited on a substrate 100 to form a stacked structure 10. FIG. 1A perspective view of a stack structure according to at least one embodiment of the present disclosure. FIG. 3 A perspective view of a stack structure according to at least one embodiment of the present disclosure. FIG. 6A A cross-sectional view of the stack structure shown in FIG. 1 along the AA' direction.

[0112] In some examples, the substrate 100 can be a semiconductor substrate, such as a silicon substrate. The material of the first insulating film 11 can include an oxide, such as silicon dioxide (SiO2), etc. The material of the second insulating film 12 can include a nitride. A nitride refers to a class of compound materials composed of nitrogen and metal elements (such as aluminum, gallium, titanium, etc.).

[0113] In some examples, the stack structure 10 can include four first insulating films 11 and three second insulating films 12 arranged alternately. The number of first insulating films 11 and second insulating films 12 included in the stack structure according to the present embodiment is not limited. In some examples, the thickness of the first insulating film 11 closest to the substrate 100 and the thickness of the first insulating film 11 farthest from the substrate 100 can be substantially the same, and can be greater than the thickness of the first insulating film 11 sandwiched by the two second insulating films 12.

[0114] In some examples, the first insulating film 11 and the second insulating film 12 can cover the substrate 100. The orthographic projection of the first insulating film 11 on the substrate 100 can coincide with the orthographic projection of the second insulating film 12 on the substrate 100, for example, the orthographic projection shape can be a rectangle, and the orthographic projection of the first insulating film 11 on the substrate 100 can coincide with the substrate 100.

[0115] (2) Forming a hard mask layer (HM) 13 on the stack structure by a patterning process, and performing twice etching on the stack structure by using the hard mask layer 13 to form a plurality of first through holes K1 penetrating the stack structure in the third direction D3.

[0116] FIG. 6B A perspective view of a stack structure after forming the first through holes according to at least one embodiment of the present disclosure. FIG. 6A A cross-sectional view of the stack structure along the AA' direction after once etching. FIG. 7A A cross-sectional view of the stack structure along the AA' direction after forming the first through holes. FIG. 7B A cross-sectional view of the stack structure along the BB' direction after forming the first through holes. FIG. 7C A cross-sectional view of the second insulating film parallel to the plane in which the substrate is located after forming the first through holes. FIG. 7D A cross-sectional view of the first insulating film parallel to the plane in which the substrate is located after forming the first through holes.

[0117] In some examples, a hard mask film is coated on the surface of the first insulating film 11 farthest from the substrate 100, and a hard mask layer 13 with a mask pattern is formed by an ATH lithography process. The hard mask layer 13 can use materials such as silicon dioxide (SiO2), silicon nitride (Si3N4), titanium nitride (TiN), amorphous carbon (ACHM), etc., and is mainly used in multiple exposure processes, etc.

[0118] Subsequently, the laminated structure is etched twice. In this step, the laminated structure can be etched once using the hard mask layer 13, and a plurality of first initial vias K11a are formed in the first insulating film 11 and a plurality of second vias K12 are formed in the second insulating film 12. The first initial vias K11a and the second vias K12 are aligned and communicated in the third direction D3, as shown in FIG. 1C. The first initial vias K11a and the second vias K12 can coincide in the orthographic projection of the substrate 100, for example, the orthographic projection shapes can both be rectangular. Subsequently, the first insulating film 11 is etched twice to form the first vias K11 by expanding the first initial vias K11a. For example, the first insulating film 11 is etched twice by wet etching (such as oxide wet etching), in which an acid solution with a relatively high etching selectivity for the first insulating film 11 and the second insulating film 12 can be selected, and the first insulating film 11 is etched laterally in the direction away from the center of the first initial via K11a by a certain thickness (for example, the thickness of wet etching is L3) to make the part of the first insulating film 11 around the first initial via K11a be etched away, exposing the surface of the second insulating film 12 parallel to the plane of the substrate, forming the first via K11, as shown in FIG. 1D. FIG. 7E FIG. 7F In some examples, as shown in FIG. 1E, the first via K1 of the laminated structure can include the first via K11 and the second via K12 which are through and alternately communicated in the third direction D3. As shown in FIG. 1F, the orthographic projection of the first via K11 in the substrate 100 can be a rectangle with rounded or chamfered corners. As shown in FIG. 1G, the orthographic projection of the second via K12 in the substrate 100 can be a rectangle with rounded or chamfered corners.

[0119] In some examples, as shown in FIG. 1E, the first via K1 of the laminated structure can include the first via K11 and the second via K12 which are through and alternately communicated in the third direction D3. As shown in FIG. 1F, the orthographic projection of the first via K11 in the substrate 100 can be a rectangle with rounded or chamfered corners. As shown in FIG. 1G, the orthographic projection of the second via K12 in the substrate 100 can be a rectangle with rounded or chamfered corners. FIG. 7B FIG. 7F In some examples, as shown in FIG. 1E, the first via K1 of the laminated structure can include the first via K11 and the second via K12 which are through and alternately communicated in the third direction D3. As shown in FIG. 1F, the orthographic projection of the first via K11 in the substrate 100 can be a rectangle with rounded or chamfered corners. As shown in FIG. 1G, the orthographic projection of the second via K12 in the substrate 100 can be a rectangle with rounded or chamfered corners. FIG. 7C ​​As shown, the second via K12 can have a substantially rectangular shape in the orthographic projection of the substrate 100. The first via K11 can cover the orthographic projection of the second via K12 in the orthographic projection of the substrate 100. The center positions of the first via K11 and the second via K12 can coincide in the orthographic projection of the substrate 100. The sidewall of the second via K12 exposes the second insulating film 12, and the sidewall of the first via K11 exposes the first insulating film 11 and the portion of the second insulating film 12 away from or close to the surface of the substrate.

[0120] In some examples, as shown, the first via K1 can have a square shape in the cross section parallel to the substrate. The length of the side of the first via K1 in the first insulating film 11 can be L1, and the length of the side of the second via K2 in the second insulating film 12 can be L2. L1 can be equal to L2+2*L3. For example, the etching thickness L3 can be 15 nanometers (nm) to 30 nm, such as about 25 nm or 30 nm. FIG. 7F

[0121] The first via formed by twice etching in the present example has different sizes in the first insulating film and the second insulating film, which is beneficial to control the morphology of the word line in the subsequent manufacturing process.

[0122] (3) Depositing a sacrificial film on the substrate 100 to form a sacrificial layer 15 filling the plurality of first vias, so that the surface of the stack structure away from the substrate 100 is flush. In some examples, after depositing the sacrificial film in the first via of the stack structure, the surface of the stack structure away from the substrate 100 can be made flat by chemical mechanical polishing (CMP).

[0123] FIG. 7E A perspective view of the stack structure after forming the sacrificial layer for at least one embodiment of the present disclosure. FIG. 7C A cross-sectional view along the direction AA' in FIG. 8A A cross-sectional view along the direction AA' in FIG. 8B A cross-sectional view along the direction AA' in FIG. 8A A cross-sectional view along the direction AA' in

[0124] In some examples, as shown, the sacrificial layer 15 can include a plurality of filling columns 151 extending along the third direction D3, and one filling column 151 can fill one corresponding first via K1. The plurality of filling columns 151 can be arranged as two columns along the first direction D1 and three rows along the second direction D2. FIG. 8C

[0125] ​​In some examples, the sacrificial layer 15 can adopt a material that has a selectivity ratio with wet etching of the semiconductor layer, for example, the material of the sacrificial layer 15 can include aluminum oxide (Al2O3).

[0126] The sacrificial layer of the present example can protect the semiconductor layer of the transistor in subsequent processes, and etch the semiconductor layer of the interlayer region by selectively removing the sacrificial layer in a small range, so as to reduce or eliminate the parasitic MOS while ensuring the stability of the mechanical structure.

[0127] (3) Etching the first insulating film 11 and the second insulating film 12 of the stack structure formed with the aforementioned pattern, forming grooves Q1 arranged opposite to each other in the first direction D1, and depositing a support material in the grooves Q1 to form a support layer 16.

[0128] FIG. 8A A perspective view of the stack structure after forming the grooves for at least one embodiment of the present disclosure. FIG. 8A to FIG. 8C A FIG. 9A sectional view along the AA' direction. FIG. 9B A perspective view of the stack structure after forming the support layer for at least one embodiment of the present disclosure. FIG. 9A A FIG. 10A sectional view along the AA' direction. FIG. 10B A FIG. 10A top view of the stack structure.

[0129] In some examples, as shown in FIG. 10C and FIG. 10A , etching the stack structure can remove the two side edges of the first insulating film 11 and the second insulating film 12 in the first direction D1 to form two grooves Q1, which can expose the two side end portions of the first insulating film 11 and the second insulating film 12 in the first direction D1, and a part of the surface of the substrate 100 close to the first insulating film 11. Subsequently, as shown in FIG. 9A , a support material is deposited in the two grooves Q1 to form a support layer 16. The support layer 16 can cover the two side end surface of the first insulating film 11 and the second insulating film 12 in the first direction D1, and a part of the surface of the substrate 100 close to the first insulating film 11. The edge of the support layer 16 can be flush with the edge of the substrate 100 by CMP. The orthographic projection of the support layer 16 on the substrate 100 can be within the range of the substrate 100.

[0130] In some examples, the support layer 16 can adopt silicon oxynitride (SiON) or other insulating materials. The support layer 16 adopting insulating materials can avoid generating capacitance with the second plate of the capacitor formed subsequently, and can ensure the performance of the semiconductor device.

[0131] (4) Etch the first insulating film 11 and the second insulating film 12 of the stacked structure forming the foregoing pattern to form a plurality of first hollow portions 171 and a plurality of second hollow portions 172.

[0132] FIG. 9B This is a three-dimensional schematic diagram of the stacked structure after forming the first hollow portion and the second hollow portion in at least one embodiment of the present disclosure. FIG. 10A to FIG. 10C It is FIG. 11A The cross-sectional view along the BB' direction in FIG. 11B It is FIG. 11A The top view schematic diagram of the stacked structure in

[0133] In some examples, as FIG. 11C shown, a photolithography process can be used to etch the stacked structure to form a plurality of first hollow portions 171 and a plurality of second hollow portions 172. In a plane parallel to the substrate, the first hollow portion 171 can be located between adjacent filling columns of the sacrificial layer 15 in the second direction D2, and the second hollow portion 172 can be adjacent to one filling column in the second direction D2. The orthographic projections of the first hollow portion 171 and the second hollow portion 172 on the substrate 100 can be generally rectangular. The orthographic projection of the etched stacked structure on the substrate 100 can be generally in the shape of the Chinese character "丰". The sides of the first hollow portion 171 and the second hollow portion 172 can expose the first insulating film 11 and the second insulating film 12. In the first direction D1, adjacent first hollow portions 171 are separated by the first insulating film 11 and the second insulating film 12, and in the second direction D2, adjacent first hollow portions 171 are separated by the first insulating film 11, the second insulating film 12, and the sacrificial layer 15. In the first direction D1, adjacent second hollow portions 172 are separated by the first insulating film 11 and the second insulating film 12, and in the second direction D2, adjacent first hollow portions 171 and second hollow portions 172 are separated by the first insulating film 11, the second insulating film 12, and the sacrificial layer 15.

[0134] (5) Etch the second insulating film of the stacked structure forming the foregoing pattern to completely remove the second insulating film, and form a plurality of third hollow portions 173 connecting the first hollow portion 171 and the second hollow portion 172. Subsequently, deposit a first conductive film on the stacked structure and perform two etchings on the first conductive film to form a first conductive layer, and the first conductive layer includes: the first electrodes and the second electrodes of a plurality of transistors, and bit lines. The first conductive film in this example can fill the area where the removed second insulating film is located.

[0135] FIG. 11A This is a three-dimensional schematic diagram of the stacked structure after removing the second insulating film in at least one embodiment of the present disclosure. FIG. 11A to FIG. 11C It is FIG. 12A The cross-sectional view along the AA' direction in FIG. 12B It is <00,00429>A cross-sectional view along the direction of BB'.

[0136] In some examples, as shown in FIG. 1 1, the second insulating film 12 in the stack structure can be etched clean by dry etching, exposing part of the surface of the filling column 151 of the sacrificial layer 15. In the third direction D3, the third hollow part 173 can be located between the adjacent first insulating films 1 1, and the third hollow part 173 can communicate the first hollow part 171 and the second hollow part 172. The first insulating film in the present example can ensure the structural stability in the plane parallel to the substrate, the sacrificial layer can ensure the structural stability in the plane perpendicular to the substrate, and the present example can ensure the stability of the mechanical structure during the preparation process. FIG. 12C

[0137] A perspective view of the stack structure after deposition of the first conductive film in at least one embodiment of the present disclosure. FIG. 12A A perspective view of the stack structure after deposition of the first conductive film in at least one embodiment of the present disclosure. FIG. 12A to FIG. 12C A cross-sectional view along the direction of BB' in FIG. 1 1. FIG. 13A A cross-sectional view along the direction of BB' in FIG. 1 1.

[0138] In some examples, as shown in FIG. 1 1, the second insulating film 12 in the stack structure can be etched clean by dry etching, exposing part of the surface of the filling column 151 of the sacrificial layer 15. In the third direction D3, the third hollow part 173 can be located between the adjacent first insulating films 1 1, and the third hollow part 173 can communicate the first hollow part 171 and the second hollow part 172. The first insulating film in the present example can ensure the structural stability in the plane parallel to the substrate, the sacrificial layer can ensure the structural stability in the plane perpendicular to the substrate, and the present example can ensure the stability of the mechanical structure during the preparation process. FIG. 13B FIG. 13A In some examples, as shown in FIG. 1 1, the second insulating film 12 in the stack structure can be etched clean by dry etching, exposing part of the surface of the filling column 151 of the sacrificial layer 15. In the third direction D3, the third hollow part 173 can be located between the adjacent first insulating films 1 1, and the third hollow part 173 can communicate the first hollow part 171 and the second hollow part 172. The first insulating film in the present example can ensure the structural stability in the plane parallel to the substrate, the sacrificial layer can ensure the structural stability in the plane perpendicular to the substrate, and the present example can ensure the stability of the mechanical structure during the preparation process.

[0139] In some examples, the first conductive film can be made of metal material.

[0140] FIG. 13A A perspective view of the stack structure after deposition of the first conductive film in at least one embodiment of the present disclosure. FIG. 13B A perspective view of the stack structure after deposition of the first conductive film in at least one embodiment of the present disclosure. FIG. 14A A cross-sectional view along the direction of BB' in FIG. 1 1. FIG. 14B A cross-sectional view along the direction of BB' in FIG. 1 1. FIG. 14A A top view of the stack structure in FIG. 1 1.

[0141] In some examples, as shown in FIG. 1 1, the second insulating film 12 in the stack structure can be etched clean by dry etching, exposing part of the surface of the filling column 151 of the sacrificial layer 15. In the third direction D3, the third hollow part 173 can be located between the adjacent first insulating films 1 1, and the third hollow part 173 can communicate the first hollow part 171 and the second hollow part 172. The first insulating film in the present example can ensure the structural stability in the plane parallel to the substrate, the sacrificial layer can ensure the structural stability in the plane perpendicular to the substrate, and the present example can ensure the stability of the mechanical structure during the preparation process. FIG. 14C ​As shown, a dry etching process can be used to etch the first conductive thin film 180 to form a plurality of fourth hollow portions 174 and a plurality of fifth hollow portions 175. The orthographic projection of the dry-etched first conductive thin film 180 on the substrate 100 can be within the orthographic projection range of the first insulating thin film 11 on the substrate 100. The edges of the dry-etched first conductive thin film 180 and the edges of the first insulating thin film 11 can be flush. In a plane parallel to the substrate 100, the fourth hollow portions 174 can be located between adjacent filling columns 151 of the sacrificial layer 15 in the second direction D2, and the fifth hollow portions 175 can be adjacent to one filling column 151 in the second direction D2. The orthographic projections of the fourth hollow portions 174 and the fifth hollow portions 175 on the substrate 100 can be generally rectangular. The orthographic projection of the stacked structure after etching on the substrate 100 can be generally in the shape of the Chinese character "丰".

[0142] FIG. 14A This is a three-dimensional schematic diagram of a stacked structure after secondary etching of the first conductive thin film in at least one embodiment of the present disclosure. FIG. 14A to FIG. 14C is FIG. 15A the cross-sectional view along the AA' direction in FIG. 15B is FIG. 15A the cross-sectional view along the BB' direction in

[0143] In some examples, as FIG. 15C shown, a wet etching process is used to etch the first conductive thin film 180 to form the first conductive layer 18. In the wet etching of the first conductive thin film, the first conductive thin film can be etched transversely by a certain thickness, so that the edges of the wet-etched first conductive thin film 180 in the second direction D2 can indent inwardly towards the edges of the first insulating thin film 11, and the first conductive thin film 180 on both sides of the filling column 151 of the sacrificial layer can be disconnected, thereby forming the first electrode 31 and the second electrode 32 of the transistor. The first conductive layer 18 can include: the first electrodes 31 and the second electrodes 32 of a plurality of transistors, and the bit lines 22. The second electrodes 32 of the transistors located in the same layer and adjacent in the first direction D1 can be an integrally connected structure. The second electrodes 32 of two adjacent columns of transistors located in the same layer can be electrically connected to the same bit line 22. The bit lines 22 can extend in the second direction D2. The first electrodes 31 and the second electrodes 32 of the transistors can be located on both sides of the filling column 151 of the sacrificial layer 15 in the first direction D1. Two side surfaces of the filling column 151 in the second direction D2 can be exposed and not covered by the first insulating thin film 11.

[0144] In some examples, the thickness of the wet etching for the first conductive film can be substantially the same as the thickness of the wet etching for the first insulating film in the foregoing step. For example, the wet etching thickness for the first conductive film can be 15 nm to 30 nm, such as about 25 nm or 30 nm. The present example can ensure that the sacrificial layer is exposed in the wet etching process of the first conductive film to form the first electrode and the second electrode of the first transistor by setting the same wet etching thickness.

[0145] The present example can achieve the outward expansion of the first via by twice etching the first insulating film, and the inward contraction of the first conductive film by twice etching the first conductive film. Through the two processes, the size difference between the first conductive layer and the first insulating film can be formed to be uneven, which is beneficial to control the morphology of the transistor.

[0146] FIG. 15A A perspective view of the stack structure after the first insulating film is deposited again for at least one embodiment of the present disclosure. FIG. 15A to FIG. 15C A FIG. 16A A top view of the stack structure.

[0147] In some examples, as FIG. 16B and FIG. 16A shown, after the first conductive layer is formed, the first insulating film 11 is deposited again, and the first insulating film 11 can fill the fourth hollow part 174 and the fifth hollow part 175. Through CMP, the first insulating film 11 on the two sides in the second direction D2 can be flush with the side surface of the substrate 100, and the surface of the first insulating film 11 away from the substrate 100 can remain flat.

[0148] (6) Etching the first insulating film of the stack structure forming the foregoing pattern to form a sixth hollow part and a seventh hollow part to expose part of the surface of the first electrode and the second electrode of the plurality of transistors and part of the side surface of the filling column of the sacrificial layer. Subsequently, a third insulating film and a second conductive film are sequentially deposited in the sixth hollow part and the seventh hollow part to form a third insulating layer and a second conductive layer.

[0149] FIG. 16A A perspective view of the stack structure after the sixth hollow part and the seventh hollow part are formed for at least one embodiment of the present disclosure. FIG. 16B A FIG. 17A A cross-sectional view along the AA' direction. FIG. 17B A FIG. 17A A top view of the stack structure.

[0150] In some examples, as FIG. 17CAs shown, the first insulating film 11 can be etched using a photolithography process to form a sixth hollow portion 176 and a seventh hollow portion 177. The sixth hollow portion 176 and the seventh hollow portion 177 can be located on both sides of the plurality of filling pillars 151 along the first direction D1. The first insulating film within the sixth hollow portion 176 and the seventh hollow portion 177 is removed, exposing the side of the support layer 16 facing the first electrode 31 of the transistor, portions of the surface of the first electrodes 31 of the plurality of transistors, and portions of the side of the filling pillars 151 facing the support layer 16 and the first electrode 31.

[0151] FIG. 17A This is a three-dimensional schematic diagram of a stacked structure after forming the second plate of a capacitor according to at least one embodiment of the present disclosure. FIG. 17A to FIG. 17C for FIG. 18A Cross-sectional view along AA' direction. FIG. 18B for FIG. 18A Schematic top view of the stacked structure.

[0152] In some examples, such as FIG. 18C As shown, a third insulating film and a second conductive film are sequentially deposited in the sixth hollow portion 176 and the seventh hollow portion 177 to form a third insulating layer 52 and a second conductive layer. The third insulating layer 52 can cover the first electrodes of the multiple transistors exposed by the sixth hollow portion 176 and the seventh hollow portion 177 and the side of the sacrificial layer. The third insulating layer 52 can be located between the second conductive layer and the first conductive layer, so that the first conductive layer and the second conductive layer are insulated. The third insulating layer 52 can serve as a dielectric layer between the two plates of the capacitor. The second conductive layer may include: a second plate 42 of the capacitor. The second plates 42 of the capacitors of the multiple storage units can be an integrated structure connected to each other.

[0153] In some examples, the third insulating film and the second conductive film may be deposited by atomic layer deposition (ALD).

[0154] In some examples, the third insulating layer may be made of a high-k dielectric material, such as a dielectric material with a dielectric constant K≥3.9. The High-k dielectric material may include, but is not limited to, at least one of the following: silicon oxide and hafnium oxide.

[0155] In some examples, the second conductive film may be made of metal material.

[0156] (7) The sacrificial layer of the stacked structure forming the aforementioned pattern is etched to form a plurality of second through holes K2 penetrating the sacrificial layer 15 in the third direction D3.

[0157] FIG. 18A This is a three-dimensional schematic diagram of the stacked structure after etching the sacrificial layer according to at least one embodiment of the present disclosure.FIG. 18A to FIG. 18C for FIG. 19A Cross-sectional view along AA' direction. FIG. 19B for FIG. 19A Schematic top view of the laminated structure.

[0158] In some examples, such as FIG. 19C As shown, a photolithography process can be used to etch the sacrificial layer 15 within the first through hole to form a second through hole K2. Each filling pillar 151 can form a corresponding second through hole K2. The second through hole K2 can penetrate the sacrificial layer 15 along the third direction D3. The orthographic projection of the second through hole K2 on the substrate 100 can be roughly rectangular, and the orthographic projection of the second through hole K2 on the substrate is located within the orthographic projection of the first through hole K1 on the substrate. Because the first through hole K1 has different dimensions in the first insulating film and the first conductive layer, by providing a second through hole K2 with a smaller size than the first through hole K1, the sacrificial layer 15 between the first electrode 31 and the second electrode 32 of the transistor can be removed. This allows the second through hole K2 to expose a portion of the surface of the first electrode 31 and the second electrode 32 of the transistor, and the sidewalls of the second through hole K2 located in the interlayer region between adjacent layers expose the sacrificial layer 15. In the interlayer region between adjacent layers, the sacrificial layer 15 located between the sidewalls of the first through hole K1 and the sidewalls of the second through hole K2 can be retained. For example, the etched sacrificial layer can surround the second through hole K2.

[0159] In some examples, the sacrificial layer 15 may be further etched within the second through hole K2 to increase the size of the second through hole K2 and thin the sacrificial layer 15 around the second through hole K2 .

[0160] FIG. 9A This is a cross-sectional view of the stacked structure along the AA′ direction after the second through hole is widened according to at least one embodiment of the present disclosure. FIG. 19A to FIG. 19B Schematic top view of the stacked structure after the second through hole is widened according to at least one embodiment of the present disclosure.

[0161] In some examples, such as FIG. 20A and FIG. 20B As shown, the remaining sacrificial layer 15 can be laterally etched within the second through hole K2, and the sacrificial layer 15 around the second through hole K2 can be thinned, so that the size of the second through hole K2 in the interlayer region between adjacent layers can be larger than the size between the first electrode and the second electrode. The second through hole K2 in the interlayer region can expose a portion of the surface of the sacrificial layer 15 and the first and second electrodes of the transistor that is parallel to the plane of the substrate.

[0162] In this example, by etching the sacrificial layer 15 twice, the sizes of the second through hole K2 in the layer region and the interlayer region can be different, which is beneficial for controlling the morphology of the word line and the gate insulation layer in subsequent processes.

[0163] (8) A semiconductor film, a gate insulating film, and a third conductive film are sequentially deposited in the second through hole K2 of the stacked structure forming the aforementioned pattern to form a semiconductor layer, a gate insulating layer, and a third conductive layer for multiple transistors. The third conductive layer includes: word lines and gate electrodes for multiple transistors.

[0164] FIG. 21A This is a three-dimensional schematic diagram of a stacked structure after forming a semiconductor layer, a gate insulating layer, and a third conductive layer according to at least one embodiment of the present disclosure. FIG. 21B for FIG. 21A Cross-sectional view along AA' direction. FIG. 21C for FIG. 21A Schematic top view of the stacked structure.

[0165] In some examples, such as FIG. 21A to FIG. 21C As shown, a semiconductor film, a gate insulating film, and a third conductive film can be sequentially deposited within the second through hole K2 using ALD to form a semiconductor layer 34, a gate insulating layer 35, and a third conductive layer. For example, within the second through hole K2, the semiconductor film, the gate insulating film, and the third conductive film are sequentially deposited from the edge toward the center. The third conductive layer may include word lines 21 and gate electrodes for multiple transistors. The word lines 21 located in the layer region can serve as gate electrodes for the transistors. Because the dimensions of the second through hole K2 differ between the layer region 300 and the interlayer region 400, the dimensions of the word lines 21 in the layer region 300 and the interlayer region 400 can differ. The gate insulating layer 35 can be disposed around the sidewalls of the word lines 21, and the semiconductor layer 34 can be disposed around the sidewalls of the gate insulating layer 35. In the layer region 300, the semiconductor layer 34 can be in direct contact with the first and second electrodes 31 and 32 of the transistors. In the interlayer region 400, the semiconductor layer 34 is in contact with the remaining sacrificial layer 15.

[0166] In some examples, the semiconductor layer 34 may be made of a metal oxide material, such as indium gallium zinc oxide (IGZO). When the semiconductor layer is made of IGZO, the leakage current of the transistor is small (the leakage current is less than or equal to 10 -15A), thereby ensuring a low refresh rate of the dynamic memory. However, the present embodiment is not limited thereto. In other examples, the metal oxide material can include ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, and the like, as long as the leakage current of the transistor can meet the requirements, which can be adjusted according to actual conditions.

[0167] In some examples, the gate insulating layer 35 can adopt a High-K dielectric material, such as a dielectric material with a dielectric constant K≥3.9. For example, the High-K dielectric material can include at least one of silicon oxide and hafnium oxide.

[0168] In some examples, the material of the third conductive layer can include at least one of indium tin oxide (ITO), TiN / W, aluminum-doped zinc oxide (AZO), and indium zinc oxide (IZO).

[0169] (9) etching the stack structure formed in the foregoing to expose the sacrificial layer at the periphery of the second via hole K2, and etching the exposed sacrificial layer to expose at least part of the semiconductor layer in the interlayer region of the adjacent layer, and etching to remove the exposed semiconductor layer, so that the semiconductor layers of the transistors of the adjacent layers are arranged in a spaced manner.

[0170] In some examples, the first insulating film of the stack structure can be etched twice to expose the sacrificial layer 15 at the periphery of the second via hole K2.

[0171] FIG. 22A A perspective view of the stack structure after etching the first insulating film in at least one embodiment of the present disclosure. FIG. 22B A perspective view of the stack structure after etching the first insulating film in at least one embodiment of the present disclosure. FIG. 22A A top view of the stack structure after etching the first insulating film in at least one embodiment of the present disclosure.

[0172] In some examples, as shown in FIG. 6A, the first insulating film 10 can be etched twice to expose the sacrificial layer 15 at the periphery of the second via hole K2. FIG. 22A and FIG. 22BAs shown, the first insulating film 11 can be etched using dry etching to form an eighth hollow portion 178 and a ninth hollow portion 179. The first insulating film 11 within the eighth hollow portion 178 and the ninth hollow portion 179 can be removed. In a plane parallel to the substrate, the eighth hollow portion 178 can be located between adjacent word lines 21 in the second direction D2, and the ninth hollow portion 179 can be adjacent to a word line 21 in the second direction D2. The orthographic projections of the eighth hollow portion 178 and the ninth hollow portion 179 on the substrate 100 can both be substantially rectangular. The sides of the eighth hollow portion 178 and the ninth hollow portion 179 can be surrounded by the first insulating film 11 and the third insulating layer 52. In this example, the eighth hollow portion 178 and the ninth hollow portion 179 may not expose the surface of the sacrificial layer 15. This is not a limitation in this embodiment. In other examples, the sides of the eighth hollow portion and the ninth hollow portion may expose portions of the surface of the sacrificial layer 15.

[0173] In some examples, after dry etching the first insulating film 11 , wet etching may be performed on the first insulating film 11 to expose the sacrificial layer 15 located around the second through hole.

[0174] FIG. 23A 3D schematic diagram of the stacked structure after etching the sacrificial layer in at least one embodiment of the present disclosure. FIG. 23B for FIG. 23A Cross-sectional view along AA' direction. FIG. 23C for FIG. 23A Schematic top view of the stacked structure.

[0175] In some examples, such as FIG. 23A to FIG. 23C As shown, after the sacrificial layer 15 is exposed by etching the first insulating film 11, the exposed sacrificial layer 15 can be etched to expose the semiconductor layer 34. Since the exposed sacrificial layer 15 is located in the interlayer region 400, the semiconductor layer 34 in the interlayer region 400 can be exposed after the sacrificial layer 15 is etched. This step can completely etch away the remaining portion of the sacrificial layer 15. In some examples, due to process conditions, some sacrificial layer 15 may remain.

[0176] FIG. 24A FIG. 1 is a perspective schematic diagram of a stacked structure after etching to expose the semiconductor layer in at least one embodiment of the present disclosure. FIG. 24B for FIG. 24A Cross-sectional view along AA' direction. FIG. 24C for FIG. 24A Schematic top view of the stacked structure.

[0177] In some examples, such as FIG. 24A to FIG. 24CAs shown, the semiconductor layer 34 in the interlayer region 400 exposed by the wet etching can be etched away, so that the semiconductor layers of the transistors in the adjacent layers are spaced apart. In this example, the semiconductor layer in the interlayer region 400 is removed, which can effectively reduce or remove the parasitic MOS, without affecting the effective channel length of the transistor, and can enhance the stability of the device.

[0178] In some examples, after etching the semiconductor layer in the interlayer region 400, the first insulating film can be deposited again, and the edge of the first insulating film is made flush with the edge of the substrate by CMP, and the surface of the first insulating film away from the substrate is kept flat, thereby forming the first insulating layer 51. The semiconductor device prepared in this example can be as shown. FIG. 1

[0179] The preparation method of the semiconductor device provided in this example can form a first through hole in the stacked structure, deposit a sacrificial layer in the first through hole, form a second through hole in the sacrificial layer, and deposit a semiconductor layer, a gate insulating layer and a gate electrode of a transistor in the second through hole. In the preparation process, the sacrificial layer can be arranged around the semiconductor layer in the interlayer region, and the sacrificial layer and the semiconductor layer in the interlayer region can be etched in sequence by exposing the sacrificial layer, which can effectively reduce or remove the parasitic MOS while ensuring the size of the device. The preparation method in this example exposes and etches the sacrificial layer and the local semiconductor layer in sequence, selectively removes the sacrificial layer and the local semiconductor layer in a small range, without exposing the complete semiconductor layer to cause the structure to be suspended. This example can ensure the stability of the mechanical structure, and is conducive to the miniaturization of the device.

[0180] Moreover, this example realizes the outward expansion of the first through hole by twice etching of the first insulating film, and realizes the inward contraction of the first conductive film by twice etching of the first conductive film, so that the size difference between the first conductive layer and the first insulating film can be formed by the two processes, which is conducive to controlling the morphology of the transistor. The morphology of the word line in this example can form a step in the gate insulating layer at the junction between the layer region and the interlayer region, which can avoid the damaged semiconductor layer in the interlayer region extending to the layer region, thereby ensuring the performance of the transistor.

[0181] FIG. 25 Another semiconductor device according to at least one embodiment of the present disclosure is shown in a cross-sectional view along the AA' direction. In some examples, as shown in FIG. 25 ​As shown, the word line 21 can be a strip structure extending along the third direction D3. The cross-sectional size of the word line 21 at different positions in the extending direction can be the same. The size of the word line 21 in the layer region 300 and the interlayer region 400 can be the same. In the manufacturing method of the present example, after the second via hole is formed by etching the sacrificial layer, no further etching is performed in the second via hole, so that the size of the second via hole in the layer region and the interlayer region can be the same. The manufacturing method of the semiconductor device of the present example can refer to the description of the foregoing embodiments, and thus will not be described here again.

[0182] The present embodiment also provides a manufacturing method of a semiconductor device, which includes: a plurality of transistors stacked along a direction perpendicular to a substrate and periodically distributed in different layers, a word line extending through the different layers and along a direction perpendicular to the substrate; the transistor includes: a first electrode, a second electrode, a gate electrode extending along a direction perpendicular to the substrate, a semiconductor layer arranged around a sidewall of the gate electrode and insulated from the gate electrode, and a gate insulating layer arranged between the gate electrode and the semiconductor layer. The manufacturing method of the semiconductor device includes: providing a substrate, sequentially and alternately depositing a first insulating film and a second insulating film on the substrate to form a laminated structure; etching the laminated structure to form a first via hole extending through the laminated structure in a direction perpendicular to the substrate; forming a sacrificial layer filling the first via hole; etching and removing the second insulating film; depositing a first conductive film to form a first conductive layer, the first conductive layer at least including: the first electrode and the second electrode of the plurality of transistors, the first electrode and the second electrode of the transistor being separated by the sacrificial layer; etching part of the sacrificial layer in the first via hole to form a second via hole extending through the sacrificial layer in a direction perpendicular to the substrate, the sidewall of the second via hole exposing the first electrode and the second electrode of the transistor, and the sidewall of the second via hole in the interlayer region of the adjacent layer exposing the sacrificial layer; sequentially depositing a semiconductor film, a gate insulating film and a third conductive film in the second via hole to form the semiconductor layer, the gate insulating layer and the third conductive layer of the plurality of transistors, the third conductive layer including: the word line and the gate electrode of the plurality of transistors, the plurality of transistors being connected to the same word line along a direction perpendicular to the substrate, the gate electrode of each transistor in the plurality of transistors being part of the word line; the semiconductor layer of the transistor being in contact with the first electrode and the second electrode of the transistor; etching the sacrificial layer around the second via hole to expose at least part of the semiconductor layer in the interlayer region of the adjacent layer, etching and removing the exposed semiconductor layer so that the semiconductor layers of the transistors in the adjacent layers are spaced apart.

[0183] In some example embodiments, the etching the stack structure to form the first via through the stack structure in a direction perpendicular to the substrate includes: forming a hard mask layer on a side of the stack structure away from the substrate; etching the first insulating film and the second insulating film of the stack structure using the hard mask layer to form a first initial via in the first insulating film and a second via in the second insulating film, the first initial via and the second via being aligned and connected in a direction perpendicular to the substrate; wet-etching the first insulating film to expand the first initial via to a first via; and the first via and the second via being connected to form the first via, a projection of the second via on the substrate being within a projection of the first via on the substrate.

[0184] In some example embodiments, the depositing the first conductive film to form the first conductive layer includes: depositing the first conductive film, dry-etching the first conductive film to make an edge of the etched first conductive film flush with an edge of the first insulating film; and wet-etching the first conductive film to make the edge of the first conductive film recede inwardly of the edge of the first insulating film, and the first conductive film on both sides of the sacrificial layer being disconnected to form the first electrode and the second electrode of the transistor.

[0185] In some example embodiments, a thickness of the wet-etching for the first insulating film is the same as a thickness of the wet-etching for the first conductive film.

[0186] In some example embodiments, the semiconductor device further includes a plurality of capacitors, each of the capacitors including a first plate and a second plate, and the second electrode of the transistor and the first plate of the connected capacitor being an integrated structure. After the first conductive layer is formed and before the part of the sacrificial layer in the first via is etched, the preparation method further includes: depositing a first insulating film to cover the first conductive layer; etching part of the first insulating film to expose part of surfaces of the first electrode and the second electrode of the plurality of transistors and part of surfaces of the sacrificial layer facing the first electrode; and sequentially depositing a third insulating film and a second conductive film in areas where the first insulating film is removed to form a third insulating layer and a second conductive layer, the second conductive layer including the second plate of the capacitor, and the third insulating layer being between the first plate and the second plate of the capacitor.

[0187] In some example embodiments, after the etching the part of the sacrificial layer in the first via to form the second via through the sacrificial layer in a direction perpendicular to the substrate, the preparation method further includes: etching the sacrificial layer in the second via to increase the second via and thin the sacrificial layer around the second via.

[0188] In some example embodiments, the etching the sacrificial layer around the second via to expose at least part of the semiconductor layer at the interlayer region of the adjacent layer, and etching away the exposed semiconductor layer so that the semiconductor layers of the transistors of the adjacent layers are spaced apart, comprises: etching the first insulating film by dry etching and wet etching in sequence to expose the sacrificial layer at the interlayer region of the adjacent layer, and etching the sacrificial layer to expose at least part of the semiconductor layer at the interlayer region of the adjacent layer; and etching the exposed semiconductor layer by wet etching so that the semiconductor layers of the transistors of different layers are spaced apart.

[0189] In some example embodiments, the sacrificial layer is made of a material that has a selectivity ratio with respect to wet etching of the semiconductor layer.

[0190] In some example embodiments, the material of the sacrificial layer comprises aluminum oxide.

[0191] The preparation method of the semiconductor device of the present embodiment can refer to the description of the foregoing embodiments, and thus will not be described here in detail.

[0192] The present embodiment also provides an electronic device comprising the semiconductor device of any one of the foregoing embodiments. The electronic device can comprise a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence, a wearable device, a mobile power supply, or a smart mobile terminal, etc. The storage device can comprise a memory in a computer, etc., and the present embodiment is not limited thereto.

[0193] The drawings in the present disclosure only relate to the structures involved in the present disclosure, and other structures can refer to the usual design. In the case of no conflict, the features in the embodiments of the present disclosure, i.e., the features in the embodiments, can be combined with each other to obtain new embodiments. It should be noted that the above-mentioned embodiments or example embodiments are only exemplary and are not restrictive. Therefore, the present disclosure is not limited to the details shown and described herein. Various modifications, replacements or omissions can be made to the forms and details without departing from the scope of the present disclosure.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The semiconductor device comprises: a plurality of transistors stacked along a direction perpendicular to a substrate and periodically distributed in different layers, and a word line extending through the different layers along a direction perpendicular to the substrate; the transistor comprises: a first electrode, a second electrode, a gate electrode extending along a direction perpendicular to the substrate, a semiconductor layer arranged around a sidewall of the gate electrode and insulated from the gate electrode, and a gate insulating layer arranged between the gate electrode and the semiconductor layer; The method for manufacturing the semiconductor device comprises: providing a substrate, and alternately depositing a first insulating film and a second insulating film on the substrate to form a laminated structure; etching the laminated structure to form a first via hole extending through the laminated structure along a direction perpendicular to the substrate; forming a sacrificial layer to fill the first via hole; etching and removing the second insulating film; depositing a first conductive film to form a first conductive layer, the first conductive layer comprising at least the first electrode and the second electrode of the plurality of transistors, the first electrode and the second electrode of the transistor being separated by the sacrificial layer; etching part of the sacrificial layer in the first via hole to form a second via hole extending through the sacrificial layer along a direction perpendicular to the substrate, the sidewall of the second via hole exposing the first electrode and the second electrode of the transistor, and the sidewall of the second via hole exposing the sacrificial layer in an interlayer region of adjacent layers; sequentially depositing a semiconductor film, a gate insulating film and a third conductive film in the second via hole to form a semiconductor layer, a gate insulating layer and a third conductive layer of the plurality of transistors, the third conductive layer comprising the word line and the gate electrode of the plurality of transistors, the plurality of transistors in each layer being connected to the same word line, the gate electrode of each transistor being part of the word line, and the semiconductor layer of the transistor being in contact with the first electrode and the second electrode of the transistor; etching the sacrificial layer around the second via hole to expose at least part of the semiconductor layer in the interlayer region of adjacent layers, and etching and removing the exposed semiconductor layer so that the semiconductor layers of the transistors in adjacent layers are spaced apart.

2. The method of producing a semiconductor device according to claim 1, wherein The etching of the laminated structure to form a first via hole extending through the laminated structure along a direction perpendicular to the substrate comprises: forming a hard mask layer on a side of the laminated structure away from the substrate; etching the first insulating film and the second insulating film of the laminated structure using the hard mask layer to form a first initial via hole in the first insulating film and a second via hole in the second insulating film, the first initial via hole and the second via hole being aligned and connected in a direction perpendicular to the substrate; extending the first initial via hole to a first via hole by wet etching the first insulating film, the first via hole and the second via hole being connected to form the first via hole, and a projection of the second via hole on the substrate being located within a projection range of the first via hole on the substrate.

3. The method of producing a semiconductor device according to claim 2, wherein The deposition of a first conductive film to form a first conductive layer comprises: depositing a first conductive film, and dry etching the first conductive film so that the edge of the etched first conductive film is flush with the edge of the first insulating film. The first conductive film is etched by wet etching, so that the edge of the first conductive film is recessed inwardly from the edge of the first insulating film, and the first conductive film on both sides of the sacrificial layer is disconnected to form the first electrode and the second electrode of the transistor.

4. The method of producing a semiconductor device according to claim 3, wherein The thickness of the wet etching for the first insulating film is the same as the thickness of the wet etching for the first conductive film.

5. The method of producing a semiconductor device according to Claim 1, wherein The semiconductor device further comprises: a plurality of capacitors, each capacitor comprising a first plate and a second plate, the second electrode of the transistor and the first plate of the connected capacitor being an integrated structure; After the first conductive layer is formed, before the part of the sacrificial layer in the first via is etched, the preparation method further comprises: depositing a first insulating film to cover the first conductive layer; etching part of the first insulating film to expose part of the surface of the first electrode and the second electrode of the plurality of transistors and part of the surface of the sacrificial layer facing the first electrode; depositing a third insulating film and a second conductive film in the area where the first insulating film is removed in sequence to form a third insulating layer and a second conductive layer, the second conductive layer comprising: the second plate of the capacitor, the third insulating layer being located between the first plate and the second plate of the capacitor.

6. The method of producing a semiconductor device according to Claim 1, wherein After the part of the sacrificial layer in the first via is etched to form a second via penetrating the sacrificial layer in the direction perpendicular to the substrate, the preparation method further comprises: etching the sacrificial layer in the second via to increase the size of the second via and thin the sacrificial layer around the second via.

7. The method of producing a semiconductor device according to claim 6, wherein The etching of the sacrificial layer around the second via exposes at least part of the semiconductor layer in the interlayer region of the adjacent layer, and the exposed semiconductor layer is etched to separate the semiconductor layers of the transistors in the adjacent layers, comprising: exposing the sacrificial layer in the interlayer region of the adjacent layer by etching the first insulating film in sequence by dry etching and wet etching, and etching the sacrificial layer to expose at least part of the semiconductor layer in the interlayer region of the adjacent layer; exposing the semiconductor layer by wet etching to separate the semiconductor layers of the transistors in different layers.

8. The method of producing a semiconductor device according to Claim 7, wherein The sacrificial layer is made of a material that has a selectivity ratio with the wet etching of the semiconductor layer.

9. The method of producing a semiconductor device according to Claim 8, wherein The material of the sacrificial layer comprises aluminum oxide.

10. A semiconductor device, characterized by comprising: Comprising: a plurality of transistors stacked in the direction perpendicular to the substrate and periodically distributed in different layers; a word line penetrating the different layers and extending in the direction perpendicular to the substrate; The transistor comprises: a gate electrode extending in the direction perpendicular to the substrate, a semiconductor layer arranged around the sidewall of the gate electrode and insulated from the gate electrode, and a gate insulating layer arranged between the gate electrode and the semiconductor layer; The plurality of transistors arranged in the direction perpendicular to the substrate are connected to the same word line, and the gate electrode of each transistor in the plurality of transistors is part of the word line; the semiconductor layers of the plurality of transistors are separated; the word line in the interlayer region of the adjacent layers is surrounded by the gate insulating layer, and the gate insulating layer in the interlayer region of the adjacent layers is surrounded by the first insulating layer; at least part of the gate insulating layer in the interlayer region of the adjacent layers is in contact with an independent semiconductor layer; The gate insulating layer includes: first insulating portions and second insulating portions which are alternately connected and extend in a direction perpendicular to the substrate, the first insulating portions being located between the semiconductor layer and the gate electrode of the transistor, the second insulating portions being located in the interlayer region of the adjacent layer; A portion of the semiconductor layer extends in a direction away from the first insulating portion of the gate insulating layer.

11. The semiconductor device of claim 10, wherein, The semiconductor layer of the interlayer region of the adjacent layer is in contact with the sacrificial layer; the semiconductor layer of the interlayer region of the adjacent layer is disconnected from the semiconductor layer of the transistor.

12. The semiconductor device of claim 11, wherein, The material of the sacrificial layer includes: aluminum oxide.

13. The semiconductor device of claim 10, wherein, The word line includes: first main body portions and second main body portions which are alternately connected and extend in a direction perpendicular to the substrate, the first main body portions serving as the gate electrode of the transistor, the second main body portions being located in the interlayer region of the adjacent layer; a projection of the first main body portion on the substrate is located within a projection range of the second main body portion on the substrate.

14. The semiconductor device of claim 13, wherein, The second insulating portion forms a step from a surface of the first insulating portion in a direction parallel to a plane in which the substrate lies; the semiconductor layer of the transistor is distributed on a sidewall of the first insulating portion and the step.

15. An electronic device, comprising: A semiconductor device including any one of the semiconductor devices according to claims 10 to 14.

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