Laminated ceramic electronic component and mounting structure for laminated ceramic electronic component

Abstract

Provided is a laminated ceramic electronic component that prevents an increase in insulation resistance while ensuring moisture resistance reliability. A laminated ceramic electronic component according to the present invention is provided with: a laminated body (12) including a plurality of laminated ceramic layers (14) and a plurality of internal electrode layers (16) laminated on the ceramic layers (14), the first main surface (12a) and the second main surface (12b) face each other in the lamination direction (x); the first side surface (12c) and the second side surface (12d) face each other in the width direction (y) orthogonal to the lamination direction (x); and the first end surface (12e) and the second end surface (12f) face each other in the length direction (z) orthogonal to the lamination direction (x) and the width direction (y). And a plurality of external electrodes (30), characterized in that the plurality of internal electrode layers (16) are provided with: first internal electrode layers (16a) which are alternately laminated with the plurality of ceramic layers (14) and which are exposed on the first end surface (12e) and the second end surface (12f); and second internal electrode layers (16b) alternately laminated with the plurality of ceramic layers (14) and exposed on the first side surface (12c) and the second side surface (12d), the plurality of external electrodes (30) being provided with: a first external electrode (30a) and a second external electrode (30b) connected to the first internal electrode layer (16a); and a third external electrode (30c) and a fourth external electrode (30d) connected to the second internal electrode layer (16b), the first external electrode (30a) and the second external electrode (30b) each having a base electrode layer (32a, 32b), the base electrode layers (32a, 32b) having dense regions (40a, 40b) in which the area ratio of conductive components is high and sparse regions (42) in which the area ratio of conductive components is lower than that of the dense regions (40). The dense region (40) is positioned closer to the laminate (12) than the sparse region (42).

Description

Technical Field

[0001] The present invention relates to a laminated ceramic electronic component and a mounting structure of the laminated ceramic electronic component. Background Art

[0002] In recent years, with the improvement of the performance of mobile phones such as smart phones, there is a demand for miniaturization of laminated ceramic electronic components. In addition, with the miniaturization of laminated ceramic electronic components, the thickness of external electrodes is also getting thinner, so ensuring moisture-resistant reliability has become a problem.

[0003] For example, Patent Document 1 discloses a laminated ceramic electronic component. The laminated ceramic electronic component of Patent Document 1 includes a ceramic body (laminated body) including a dielectric layer (ceramic layer) and first and second internal electrodes laminated mutually with the dielectric layer sandwiched therebetween, a first external electrode connected to the first internal electrode of the ceramic body, and a second internal electrode connected to the ceramic body, the first external electrode including a first base electrode layer arranged in contact with the ceramic body, a first glass layer arranged on the first base electrode layer, and a first resin electrode layer arranged on the first glass layer, and the second external electrode including a second base electrode layer arranged in contact with the ceramic body, a second glass layer arranged on the second base electrode layer, and a second resin electrode layer arranged on the second glass layer. In Patent Document 1, moisture resistance reliability is ensured by providing the first and second glass layers on the first and second base electrode layers, and providing the first and second resin electrode layers on the first and second glass layers.

[0004] Prior Art Literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2022-62671 Summary of the invention

[0007] Problem that the invention aims to solve

[0008] However, as in Patent Document 1, if the first and second glass layers are provided as external electrodes on the first and second base electrode layers, and the first and second resin electrode layers are provided on the first and second glass layers, there is a problem of increased insulation resistance because the first and second glass layers and the first and second resin electrode layers have higher resistance values ​​than the first and second base electrode layers.

[0009] Therefore, an object of the present invention is to provide a multilayer ceramic electronic component that prevents an increase in insulation resistance while ensuring moisture-resistant reliability.

[0010] Technical solutions to solve problems

[0011] The laminated ceramic electronic component of the present invention comprises a laminate and a plurality of external electrodes, wherein the laminate comprises a plurality of laminated ceramic layers and a plurality of internal electrode layers laminated on the ceramic layers, and comprises a first main surface and a second main surface opposite to each other in a laminated direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the laminated direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the laminated direction and the width direction, and is characterized in that the plurality of internal electrode layers comprises: a first internal electrode layer alternately laminated with the plurality of ceramic layers, The second end face is exposed; and the second internal electrode layer is alternately stacked with multiple ceramic layers and exposed on the first side and the second side, and multiple external electrodes include: the first external electrode and the second external electrode, which are connected to the first internal electrode layer; and the third external electrode and the fourth external electrode, which are connected to the second internal electrode layer, the first external electrode and the second external electrode respectively have a base electrode layer, the base electrode layer has a dense area with a high area ratio of the conductive component and a sparse area with a lower area ratio of the conductive component than the dense area, and the dense area is located on the stacked body side than the sparse area.

[0012] The present invention relates to a laminated ceramic electronic component having a base electrode layer in each of the first external electrode and the second external electrode, wherein the base electrode layer has a dense region with a high area ratio of a conductive component and a sparse region with a lower area ratio of the conductive component than the dense region, and the dense region is located closer to the laminate than the sparse region, so that the contact between the internal electrode layer and the conductive component in the external electrode is increased, and the insulation resistance can be reduced. In addition, by having the dense region in a portion close to the laminate, the moisture resistance reliability can be improved.

[0013] The mounting structure of a stacked ceramic electronic component of the present invention comprises: a mounting substrate; and a stacked ceramic electronic component mounted on the mounting substrate, the stacked ceramic electronic component comprising a stacked body and a plurality of external electrodes, the stacked body comprising a plurality of stacked ceramic layers and a plurality of stacked internal electrode layers, and comprising a first main surface and a second main surface opposite to each other in a stacking direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the stacking direction and the width direction, characterized in that the plurality of internal electrode layers comprise: a first internal electrode layer alternately stacked with the plurality of ceramic layers and exposed at the first end surface and the second end surface; and a second internal electrode layer alternately stacked with the plurality of ceramic layers and exposed at the first side surface and the second side surface, and the plurality of external electrodes comprise: a first external electrode and The second external electrode is connected to the first internal electrode layer; and the third external electrode and the fourth external electrode are connected to the second internal electrode layer, the first external electrode and the second external electrode respectively have a base electrode layer, the base electrode layer has a dense area with a high area ratio of the conductive component and a sparse area with a lower area ratio of the conductive component than the dense area, the dense area is located on the side of the stacked body than the sparse area, the mounting substrate has: a core material of the substrate; a first connecting conductor, arranged on the core material and connected to the first external electrode; a second connecting conductor, arranged on the core material and connected to the second external electrode; a third connecting conductor, arranged on the core material and connected to the third external electrode; and a fourth connecting conductor, arranged on the core material and connected to the fourth external electrode, in the stacked ceramic electronic component, the first external electrode and the second external electrode having the dense area and the sparse area are connected to the anode.

[0014] The mounting structure of the multilayer ceramic electronic component involved in the present invention is mounted on a mounting substrate so that the second main surface of the multilayer ceramic capacitor is opposite to the mounting surface on the substrate side, and the first external electrode and the second external electrode having a dense area and a sparse area are connected to the anode, so that the current distance becomes shorter, and it is possible to prevent the increase of insulation resistance while ensuring moisture resistance reliability.

[0015] The laminated ceramic electronic component of the present invention comprises a laminated body and a plurality of external electrodes, wherein the laminated body comprises a plurality of laminated ceramic layers and a plurality of laminated internal electrode layers, and comprises a first main surface and a second main surface opposite to each other in a laminating direction, a first side surface and a second side surface opposite to each other in a width direction orthogonal to the laminating direction, and a first end surface and a second end surface opposite to each other in a length direction orthogonal to the laminating direction and the width direction, and is characterized in that the plurality of internal electrode layers comprises: a first internal electrode layer alternately laminated with the plurality of ceramic layers, The end face is exposed; and the second internal electrode layer is alternately stacked with multiple ceramic layers and exposed on the first side and the second side, and the multiple external electrodes include: the first external electrode and the second external electrode, which are connected to the first internal electrode layer; and the third external electrode and the fourth external electrode, which are connected to the second internal electrode layer, the third external electrode and the fourth external electrode respectively have a base electrode layer, the base electrode layer has a dense area with a high area ratio of the conductive component and a sparse area with a lower area ratio of the conductive component than the dense area, and the dense area is located on the stacked body side than the sparse area.

[0016] The laminated ceramic electronic component of the present invention has a base electrode layer at the third external electrode and the fourth external electrode respectively, and the base electrode layer has a dense region with a high area ratio of a conductive component and a sparse region with a lower area ratio of the conductive component than the dense region. The dense region is located closer to the laminate than the sparse region, so the contact between the internal electrode layer and the conductive component in the external electrode is increased, and the insulation resistance can be reduced. In addition, by having a dense region in a portion close to the laminate, the moisture resistance reliability can be improved.

[0017] The mounting structure of a stacked ceramic electronic component of the present invention comprises: a mounting substrate; and a stacked ceramic electronic component mounted on the mounting substrate, the stacked ceramic electronic component comprising a stacked body and a plurality of external electrodes, the stacked body comprising a plurality of stacked ceramic layers and a plurality of stacked internal electrode layers, and comprising a first main surface and a second main surface opposite to each other in a stacking direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the stacking direction and the width direction, characterized in that the plurality of internal electrode layers comprise: a first internal electrode layer alternately stacked with the plurality of ceramic layers and exposed at the first end surface and the second end surface; and a second internal electrode layer alternately stacked with the plurality of ceramic layers and exposed at the first side surface and the second side surface, and the plurality of external electrodes comprise: a first external electrode and The second external electrode is connected to the first internal electrode layer; and the third external electrode and the fourth external electrode are connected to the second internal electrode layer, the third external electrode and the fourth external electrode respectively have a base electrode layer, the base electrode layer has a dense area with a high area ratio of the conductive component and a sparse area with a lower area ratio of the conductive component than the dense area, the dense area is located on the side of the stacked body than the sparse area, the mounting substrate has: a core material of the substrate; a first connecting conductor, arranged on the core material and connected to the first external electrode; a second connecting conductor, arranged on the core material and connected to the second external electrode; a third connecting conductor, arranged on the core material and connected to the third external electrode; and a fourth connecting conductor, arranged on the core material and connected to the fourth external electrode, in the stacked ceramic electronic component, the third external electrode and the fourth external electrode having the dense area and the sparse area are connected to the anode.

[0018] The mounting structure of the multilayer ceramic electronic component involved in the present invention is mounted on a mounting substrate so that the second main surface of the multilayer ceramic capacitor is opposite to the mounting surface on the substrate side, and the third external electrode and the fourth external electrode having a dense area and a sparse area are connected to the anode, so that the current distance becomes shorter, and it is possible to prevent the increase of insulation resistance while ensuring moisture resistance reliability.

[0019] Effects of the Invention

[0020] According to the present invention, it is possible to provide a multilayer ceramic electronic component and a mounting structure of the multilayer ceramic electronic component that prevent an increase in insulation resistance while ensuring moisture-resistant reliability.

[0021] The above objects, other objects, features and advantages of the present invention will become more apparent from the following description of specific embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a perspective view showing the appearance of a multilayer ceramic capacitor as an example of a multilayer ceramic electronic component according to the first embodiment of the present invention.

[0023] Figure 2 It is a plan view showing a multilayer ceramic capacitor as an example of the multilayer ceramic electronic component according to the first embodiment of the present invention.

[0024] Figure 3 It is a front view showing a multilayer ceramic capacitor as an example of the multilayer ceramic electronic component according to the first embodiment of the present invention.

[0025] Figure 4 yes Figure 1 A cross-sectional view is concerned along line IV-IV.

[0026] Figure 5 yes Figure 1 The cross-sectional view is taken along line VV.

[0027] Figure 6 yes Figure 4 A cross-sectional view taken along line VI-VI is involved.

[0028] Figure 7 yes Figure 4 The cross-sectional view refers to the line VII-VII.

[0029] Figure 8 yes Figure 4 Enlarged view of the involved section A.

[0030] Fig. 9 It is an LT cross-sectional view showing an example of the mounting structure of the multilayer ceramic electronic component according to the first embodiment of the present invention.

[0031] Fig.10 It is a WT cross-sectional view showing an example of the mounting structure of the multilayer ceramic electronic component according to the first embodiment of the present invention.

[0032] Fig.11 This is a perspective view showing the appearance of a multilayer ceramic capacitor as an example of a multilayer ceramic electronic component according to a second embodiment of the present invention.

[0033] Fig.12 It is a plan view showing a multilayer ceramic capacitor as an example of a multilayer ceramic electronic component according to a second embodiment of the present invention.

[0034] Fig.13 It is a front view showing a multilayer ceramic capacitor as an example of a multilayer ceramic electronic component according to a second embodiment of the present invention.

[0035] Fig.14 yes Fig.11 The cross-sectional view refers to the line XIV-XIV.

[0036] Fig.15 yes Fig.11 The cross-sectional view refers to the line XV-XV.

[0037] Fig.16 yes Fig.14 The cross-sectional view refers to the line XVI-XVI.

[0038] Fig.17 yes Fig.14 The cross-sectional view refers to the line XVII-XVII.

[0039] Fig.18 yes Fig.14 Enlarged view of the involved part B.

[0040] Fig.19 It is an LT cross-sectional view showing an example of a mounting structure of a multilayer ceramic electronic component according to a second embodiment of the present invention.

[0041] Fig. 20 It is a WT cross-sectional view showing an example of the mounting structure of the multilayer ceramic electronic component according to the second embodiment of the present invention. DETAILED DESCRIPTION

[0042] A. First Embodiment

[0043] 1. Laminated ceramic electronic components

[0044] A multilayer ceramic capacitor 10 is described as an example of a multilayer ceramic electronic component according to a first embodiment of the present invention. Figure 1 This is a perspective view showing the appearance of a multilayer ceramic capacitor as an example of a multilayer ceramic electronic component according to the first embodiment of the present invention. Figure 2 It is a plan view showing a multilayer ceramic capacitor as an example of the multilayer ceramic electronic component according to the first embodiment of the present invention. Figure 3 It is a front view showing a multilayer ceramic capacitor as an example of the multilayer ceramic electronic component according to the first embodiment of the present invention. Figure 4 yes Figure 1 A cross-sectional view is concerned along line IV-IV. Figure 5 yes Figure 1 The cross-sectional view is taken along line VV. Figure 6 yes Figure 4 A cross-sectional view taken along line VI-VI is involved. Figure 7 yes Figure 4 A cross-sectional view is concerned along line VII-VII. Figure 8 yes Figure 4 Enlarged view of the involved section A.

[0045] The stacked ceramic capacitor 10 comprises: a stacked body 12 having a plurality of stacked ceramic layers 14 and a plurality of stacked internal electrode layers 16, including a first main surface 12a and a second main surface 12b opposite to each other in a stacking direction x, a first side surface 12c and a second side surface 12d opposite to each other in a width direction y perpendicular to the stacking direction x, and a first end surface 12e and a second end surface 12f opposite to each other in a length direction z perpendicular to the stacking direction x and the width direction y; and a plurality of external electrodes 30.

[0046] The dimension of the multilayer ceramic capacitor 10 including the multilayer body 12 and the external electrode 30 in the longitudinal direction z is represented by L. M Size: L M The dimension is preferably 0.4 mm or more and 1.6 mm or less. The dimension in the width direction y of the multilayer ceramic capacitor 10 including the multilayer body 12 and the external electrode 30 is denoted by W. M Dimensions. W M The dimension is preferably 0.2 mm or more and 1.0 mm or less. The dimension of the multilayer ceramic capacitor 10 including the multilayer body 12 and the external electrode 30 in the stacking direction x is denoted as T. M Size. M The size is preferably 0.2 mm or more and 1.0 mm or less.

[0047] (Laminated body)

[0048] The laminate 12 has a plurality of laminated ceramic layers 14 and a plurality of internal electrode layers 16. Furthermore, the laminate 12 has a first main surface 12a and a second main surface 12b opposite to each other in a stacking direction x, a first side surface 12c and a second side surface 12d opposite to each other in a width direction y orthogonal to the stacking direction x, and a first end surface 12e and a second end surface 12f opposite to each other in a length direction z orthogonal to the stacking direction x and the width direction y.

[0049] The laminate 12 has a rectangular parallelepiped shape. In addition, the laminate 12 preferably has rounded corners and ridges. In addition, the so-called corner is a portion where three adjacent faces of the laminate 12 intersect, and the so-called ridge is a portion where two adjacent faces of the laminate 12 intersect. In addition, concavities and convexities may be formed on part or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f.

[0050] The stack 12 comprises: an effective layer portion 15a, in which a plurality of internal electrode layers 16 are arranged opposite to each other with ceramic layers 14 interposed therebetween in a stacking direction x connecting the first main surface 12a and the second main surface 12b to each other; a first outer layer portion 15b1, formed by a plurality of ceramic layers 14 located between the first main surface 12a and the internal electrode layer 16 which is closest to the first main surface 12a among the plurality of internal electrode layers 16; and a second outer layer portion 15b2, formed by a plurality of ceramic layers 14 located between the second main surface 12b and the internal electrode layer 16 which is closest to the second main surface 12b among the plurality of internal electrode layers 16.

[0051] The first outer layer portion 15 b 1 is located on the first principal surface 12 a side of the laminate 12 , and is an aggregate of a plurality of ceramic layers 14 located between the first principal surface 12 a and the internal electrode layer 16 closest to the first principal surface 12 a .

[0052] The second outer layer portion 15 b 2 is located on the second main surface 12 b side of the laminate 12 , and is an aggregate of a plurality of ceramic layers 14 located between the second main surface 12 b and the internal electrode layer 16 closest to the second main surface 12 b .

[0053] Furthermore, a region sandwiched between the first outer layer portion 15b1 and the second outer layer portion 15b2 is the effective layer portion 15a.

[0054] In addition, the stack 12 has side portions (W gap) 24a, 24b of the stack 12 which are located between one end of the width direction y of the first opposing portion 18a of the first internal electrode layer 16a described later and the second opposing portion 18b of the second internal electrode layer 16b and the first side surface 12c, and between one end of the width direction y of the first opposing portion 18a of the first internal electrode layer 16a described later and the second opposing portion 18b of the second internal electrode layer 16b and the second side surface 12d, and include the first extension portion 22a and the second extension portion 22b of the second internal electrode layer 16b.

[0055] In addition, the stack 12 has end portions (L gap) 26a, 26b of the stack 12 located between one end of the length direction z of the first opposing portion 18a of the first internal electrode layer 16a described later and the second opposing portion 18b of the second internal electrode layer 16b and the first end face 12e, and between one end of the length direction z of the first opposing portion 18a of the first internal electrode layer 16a described later and the second opposing portion 18b of the second internal electrode layer 16b and the second end face 12f, and including the first lead portion 20a and the second lead portion 20b of the first internal electrode layer 16a.

[0056] The number of stacked ceramic layers 14 is not particularly limited, but is preferably 4 or more and 1000 or less including the first outer layer portion 15b1 and the second outer layer portion 15b2. The thickness of the ceramic layer 14 is preferably 0.4 μm or more and 1.0 μm or less.

[0057] The ceramic layer 14 may be made of a dielectric material, for example. For example, dielectric ceramics containing main components such as BaTiO3, CaTiO3, SrTiO3, and CaZrO3 may be used as the dielectric material. In addition, materials containing secondary components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds added to these main components may also be used.

[0058] The size of the laminate 12 is not particularly limited, but the size of the laminate 12 in this embodiment is the size obtained by removing the thickness of the external electrode 30 from the size of the laminated ceramic capacitor 10. The dimension in the length direction z connecting the first end face 12e and the second end face 12f of the laminate 12 is set to L dimension. The L dimension is preferably 0.4 mm or more and 1.6 mm or less. The dimension in the width direction y connecting the first side face 12c and the second side face 12d of the laminate 12 is set to W dimension. The W dimension is preferably 0.2 mm or more and 1.0 mm or less. The dimension in the stacking direction x connecting the first main face 12a and the second main face 12b of the laminate 12 is set to T dimension. The T dimension is preferably 0.2 mm or more and 1.0 mm or less.

[0059] (Internal electrode layer)

[0060] The internal electrode layer 16 includes a first internal electrode layer 16 a and a second internal electrode layer 16 b .

[0061] The first internal electrode layer 16a is disposed on the surface of the ceramic layer 14. The first internal electrode layer 16a includes a first opposing portion 18a located inside the stacked body 12, a first lead portion 20a connected to the first opposing portion 18a and led to the first end surface 12e, and a second lead portion 20b led to the second end surface 12f.

[0062] The shape of the first opposing portion 18a of the first internal electrode layer 16a is not particularly limited, but is preferably a rectangular shape when viewed from above. However, the corners when viewed from above may be rounded, or the corners may be formed to be inclined (conical) when viewed from above. In addition, the shape may be a conical shape when viewed from above that is inclined in a certain direction.

[0063] The shapes of the first lead portion 20a and the second lead portion 20b of the first internal electrode layer 16a are not particularly limited, but are preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed to be inclined (conical) in plan view. In addition, the shape may be a cone in plan view that is inclined toward a certain direction.

[0064] The second internal electrode layer 16b is arranged on the surface of a ceramic layer 14 different from the ceramic layer 14 on which the first internal electrode layer 16a is arranged. The second internal electrode layer 16b has a second opposing portion 18b opposed to the first internal electrode layer 16a, a first extended portion 22a connected to the second opposing portion 18b and extended to the first side surface 12c, and a second extended portion 22b extended to the second side surface 12d.

[0065] The shape of the second opposing portion 18b of the second internal electrode layer 16b is not particularly limited, but is preferably a rectangular shape when viewed from above. However, the corners when viewed from above may be rounded, or the corners may be formed to be inclined (conical) when viewed from above. In addition, the shape may be a conical shape when viewed from above that is inclined in a certain direction.

[0066] The shapes of the first extension 22a and the second extension 22b of the second internal electrode layer 16b are not particularly limited, but are preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed to be inclined (conical) in plan view. In addition, the shape may be a cone in plan view that is inclined in a certain direction.

[0067] The first internal electrode layer 16 a and the second internal electrode layer 16 b can be formed of an appropriate conductive material such as a metal such as Ni, Cu, Ag, Pd, Au, or an alloy containing at least one of these metals such as an Ag—Pd alloy.

[0068] The number of the first internal electrode layers 16a is not particularly limited, but is preferably, for example, 1 or more and 500 or less. The number of the second internal electrode layers 16b is not particularly limited, but is preferably, for example, 1 or more and 500 or less. The total number of the first internal electrode layers 16a and the second internal electrode layers 16b is preferably 2 or more and 1000 or less.

[0069] The thickness of the first internal electrode layer 16 a is not particularly limited, but is preferably, for example, not less than 0.4 μm and not more than 0.8 μm.

[0070] The thickness of the second internal electrode layer 16 b is not particularly limited, but is preferably, for example, not less than 0.4 μm and not more than 0.8 μm.

[0071] In the present embodiment, the first opposing portion 18a of the first internal electrode layer 16a and the second opposing portion 18b of the second internal electrode layer 16b face each other via the ceramic layer 14, thereby forming capacitance and exhibiting capacitor characteristics.

[0072] When piezoelectric ceramics are used in the laminated body 12, the laminated ceramic electronic component functions as a ceramic piezoelectric element. Specific examples of piezoelectric ceramic materials include, for example, PZT (lead zirconate titanate)-based ceramic materials.

[0073] When semiconductor ceramics are used in the laminated body 12, the laminated ceramic electronic component functions as a thermistor element. Specific examples of semiconductor ceramic materials include spinel ceramic materials and the like.

[0074] In addition, when magnetic ceramics are used in the laminated body 12, the laminated ceramic electronic component functions as an inductor element. In addition, when it functions as an inductor element, the internal electrode layer becomes a coil-shaped conductor. As specific examples of magnetic ceramic materials, for example, ferrite ceramic materials can be cited.

[0075] That is, the multilayer ceramic electronic component according to the present embodiment can appropriately function not only as the multilayer ceramic capacitor 10 but also as a ceramic piezoelectric element, a thermistor element, or an inductor element by appropriately changing the material and structure of the multilayer body 12 .

[0076] (External Electrode)

[0077] The external electrode 30 includes a plurality of external electrodes 30 connected to the first internal electrode layer 16a and the second internal electrode layer 16b. The external electrode 30 includes a first external electrode 30a, a second external electrode 30b, a third external electrode 30c, and a fourth external electrode 30d.

[0078] The first external electrode 30a is disposed on the first end surface 12e and connected to the first internal electrode layer 16a. The first external electrode 30a may also be disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d.

[0079] The second external electrode 30b is disposed on the second end surface 12f and connected to the first internal electrode layer 16a. The second external electrode 30b may also be disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d.

[0080] The third external electrode 30c is disposed on the first side surface 12c and is connected to the second internal electrode layer 16b. In addition, the third external electrode 30c may be disposed on a portion of the first main surface 12a and a portion of the second main surface 12b.

[0081] The fourth external electrode 30d is disposed on the second side surface 12d and connected to the second internal electrode layer 16b. The fourth external electrode 30d may be disposed on a portion of the first main surface 12a and a portion of the second main surface 12b.

[0082] It is preferable that each of the first external electrode 30 a , the second external electrode 30 b , the third external electrode 30 c , and the fourth external electrode 30 d includes a base electrode layer 32 and a plating layer 34 .

[0083] In other words, the first external electrode 30a preferably includes the first base electrode layer 32a and the first plating layer 34a. The second external electrode 30b preferably includes the second base electrode layer 32b and the second plating layer 34b. The third external electrode 30c preferably includes the third base electrode layer 32c and the third plating layer 34c. The fourth external electrode 30d preferably includes the fourth base electrode layer 32d and the fourth plating layer 34d.

[0084] Furthermore, the first base electrode layer 32a of the first external electrode 30a and the second base electrode layer 32b of the second external electrode 30b have a dense region 40 where the area ratio of the conductive component 48 is high and a sparse region 42 where the area ratio of the conductive component 48 is lower than that of the dense region 40 .

[0085] In more detail, the first base electrode layer 32a includes a dense region 40a having a high area ratio of the conductive component 48 and a sparse region 42a having a lower area ratio of the conductive component 48 than the dense region 40a. In addition, the second base electrode layer 32b includes a dense region 40b having a high area ratio of the conductive component 48 and a sparse region 42b having a lower area ratio of the conductive component 48 than the dense region 40b. The dense region 40 is composed of the dense region 40a of the first base electrode layer 32a and the dense region 40b of the second base electrode layer 32b. Similarly, the sparse region 42 is composed of the sparse region 42a of the first base electrode layer 32a and the sparse region 42b of the second base electrode layer 32b.

[0086] In addition, the dense region 40 is located on the laminate 12 side relative to the sparse region 42. Since the dense region 40 is located on the laminate 12 side relative to the sparse region 42, the contact between the first internal electrode layer 16a and the conductive component 48 in the first external electrode 30a or the second external electrode 30b is increased, resulting in a decrease in insulation resistance. In addition, since the dense region 40 having a high area ratio of the conductive component 48 is provided in the portion close to the laminate 12, moisture resistance reliability is also improved.

[0087] Furthermore, the area ratio of the conductive component 48 to the area of ​​the dense region 40 is preferably 80% or more and 85% or less. If the area ratio of the conductive component 48 to the area of ​​the dense region 40 becomes less than 80%, the area ratio of the dense region 40 where the area ratio of the voids to the conductive component 48 is high increases, thereby causing a decrease in moisture resistance reliability. In addition, if the area ratio of the conductive component 48 to the area of ​​the dense region 40 becomes more than 85%, the content of the non-conductive component that ensures the connection with the stacked body 12 decreases, thereby increasing the risk of the first external electrode 30a or the second external electrode 30b peeling off.

[0088] In addition, the area ratio of the conductive component 48 to the area of ​​the sparse region 42 is preferably 75% or more and 80% or less. If the area ratio of the conductive component 48 to the area of ​​the sparse region 42 becomes less than 75%, the area ratio of the sparse region 42 where the area ratio of the void to the conductive component 48 is low increases, thereby causing a decrease in moisture resistance reliability. In addition, if the area ratio of the conductive component 48 to the area of ​​the sparse region 42 becomes more than 80%, the compressive stress of the sparse region 42 increases, which may cause structural defects.

[0089] The thickness l1 of the stack 12 in the dense region 40 in the length direction z is preferably 30% or more and 50% or less of the thickness l2 of the stack 12 in the length direction z of the first base electrode layer 32a and the second base electrode layer 32b. If the thickness l1 of the stack 12 in the dense region 40 in the length direction z becomes less than 30% of the thickness l2 of the stack 12 in the length direction z of the first base electrode layer 32a and the second base electrode layer 32b, the area ratio of the sparse region 42 to the dense region 40 increases, thereby causing a decrease in moisture resistance reliability. In addition, if the thickness l1 of the stack 12 in the dense region 40 in the length direction z becomes greater than 50% of the thickness l2 of the stack 12 in the length direction z of the first base electrode layer 32a and the second base electrode layer 32b, the area ratio of the sparse region 42 to the dense region 40 decreases, so that the stress relaxation effect cannot be fully obtained, which may cause structural defects.

[0090] Here, regarding the method for measuring the area ratio of the conductive component 48 in the dense region 40 and the sparse region 42 of the first foundation electrode layer 32a and the second foundation electrode layer 32b, first, the dimension W in the width direction y of the multilayer ceramic capacitor 10 is calculated. MThe cross section is polished to 1 / 2 of the stacking direction x of the stack 12 (1 / 2LT cross section). Next, the measurement is performed using a secondary electron image or a reflected electron image of a scanning electron microscope (SEM). The measurement portion of the dense area 40 is set on the polished surface as 1 / 2 of the stacking direction x of the stack 12 and 30% of the thickness (l2) of the stack 12 in the length direction z of the first base electrode layer 32a and the second base electrode layer 32b from the first end face 12e and the second end face 12f. In addition, the measurement portion of the sparse area 42 is set on the polished surface as 1 / 2 of the stacking direction x of the stack 12 and 80% of the thickness (l2) of the stack 12 in the length direction z of the first base electrode layer 32a and the second base electrode layer 32b from the first end face 12e and the second end face 12f. Next, using HALCON of MVTec, the conductive part and the non-conductive part are binarized to calculate the area ratio of the conductive component 48.

[0091] The base electrode layer 32 includes at least one selected from a sintered layer, a conductive resin layer, a thin film layer, etc. When the first base electrode layer 32a and the second base electrode layer 32b are provided with a dense region 40 and a sparse region 42, the first base electrode layer 32a and the second base electrode layer 32b preferably include at least one selected from a sintered layer and a conductive resin layer.

[0092] First, the case where the base electrode layer 32 is formed by a sintered layer is described. The sintered layer contains a metal component and a glass component. The glass component contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. In addition, as the metal component of the sintered layer, for example, at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. is contained. In the case of the sintered layer, the metal component functions as a conductive component 48. Furthermore, the sintered layer may also be a multilayer.

[0093] The sintered layer is obtained by applying a conductive paste containing a glass component and a metal component to the stacked body 12 and sintering it. The sintered layer may be obtained by simultaneously sintering the stacked small pieces having the internal electrode layer 16 and the ceramic layer 14 and the conductive paste applied to the stacked small pieces, or may be obtained by sintering the stacked small pieces having the internal electrode layer 16 and the ceramic layer 14 to obtain the stacked body 12, and then applying the conductive paste and sintering it. In addition, when the stacked small pieces having the internal electrode layer 16 and the ceramic layer 14 and the conductive paste applied to the stacked small pieces are sintered simultaneously, it is preferable to add a ceramic component instead of the glass component, or to add both of them to form the sintered layer.

[0094] The thickness of the first sintered layer and the second sintered layer located at the central part of the stacking direction x connecting the first main surface 12a and the second main surface 12b, and the thickness of the first sintered layer and the second sintered layer in the longitudinal direction z connecting the first end surface 12e and the second end surface 12f (end surface center thickness) is preferably greater than 5 μm and less than 30 μm, for example.

[0095] In addition, when a base electrode layer (sintered layer) is also provided on a portion of the first principal surface 12a or a portion of the second principal surface 12b, the thickness of the first sintered layer and the second sintered layer located on the first principal surface 12a or the second principal surface 12b in the central portion of the longitudinal direction z connecting the first end surface 12e and the second end surface 12f, and in the stacking direction x connecting the first principal surface 12a and the second principal surface 12b, is preferably, for example, greater than 5 μm and less than 10 μm.

[0096] Next, the case where the base electrode layer 32 is formed by the conductive resin layer is described. The conductive resin layer is arranged on the sintered layer to cover the sintered layer, or it can be arranged directly on the laminate 12 without providing the sintered layer. In addition, the conductive resin layer can completely cover the sintered layer, or it can cover a part of the sintered layer. Furthermore, the conductive resin layer can also be a multilayer.

[0097] The conductive resin layer includes a thermosetting resin and a metal. Since the conductive resin layer includes a thermosetting resin, it is more flexible than, for example, a plated film or a sintered layer including a sintered product of a conductive paste. Therefore, even when a physical impact or an impact caused by a thermal cycle is applied to the multilayer ceramic capacitor 10, the conductive resin layer functions as a buffer layer and can prevent cracks from being generated in the multilayer ceramic capacitor 10.

[0098] As the metal contained in the conductive resin layer, Ag, Cu, Ni, Sn, Bi or alloys containing them can be used. In addition, metal powder coated with Ag on the surface of the metal powder can also be used. When using metal powder coated with Ag on the surface of the metal powder, Cu, Ni, Sn, Bi or alloy powders thereof are preferably used as the metal powder. The reason for using Ag as the conductive metal is that Ag has the lowest resistivity among metals and is therefore suitable for electrode materials, and Ag is a noble metal and therefore does not oxidize and has high weather resistance. In addition, it is because the metal of the base material can be made cheap while maintaining the above-mentioned characteristics of Ag. In the case of the conductive resin layer, the conductive metal acts as a conductive component 48.

[0099] Furthermore, as the metal contained in the conductive resin layer, metals subjected to oxidation resistance treatment may be used for Cu and Ni. In addition, as the metal contained in the conductive resin layer, metal powders obtained by coating the surface of Sn, Ni, or Cu may be used. When using metal powders obtained by coating the surface of Sn, Ni, or Cu, it is preferred that Ag, Cu, Ni, Sn, Bi, or alloy powders thereof be used as the metal powder.

[0100] The metal contained in the conductive resin layer is mainly responsible for the conductivity of the conductive resin layer. Specifically, the conductive fillers are in contact with each other, thereby forming a conductive path inside the conductive resin layer.

[0101] The metal contained in the conductive resin layer may be a spherical metal, a flat metal, or the like, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0102] As the resin of the conductive resin layer, various known thermosetting resins such as epoxy resin, phenolic resin, urethane resin, silicone resin, polyimide resin, etc. can be used. Among them, epoxy resin is one of the most suitable resins because of its excellent heat resistance, moisture resistance, adhesion, etc.

[0103] In addition, the conductive resin layer preferably contains a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol, amine, anhydride, imidazole, active ester, and amide-imide can be used as the curing agent for the epoxy resin.

[0104] The thickness of the thickest portion of the conductive resin layer is preferably, for example, 5 μm or more and 30 μm or less.

[0105] Any one or each of the third external electrode 30c and the fourth external electrode 30d may be a thin film layer formed on the surface of the stacked body 12 as the base electrode layer 32. When a thin film layer is provided as the base electrode layer 32, the thin film layer is a layer of 1 μm or less formed by a thin film forming method such as sputtering or evaporation and depositing metal particles.

[0106] (Plating layer)

[0107] The plating layer 34 includes a first plating layer 34a configured to cover the first base electrode layer 32a, a second plating layer 34b configured to cover the second base electrode layer 32b, a third plating layer 34c configured to cover the third base electrode layer 32c, and a fourth plating layer 34d configured to cover the fourth base electrode layer 32d.

[0108] The plating layer 34 includes, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, and the like.

[0109] In addition, the plating layer 34 may be formed of multiple layers. The plating layer 34 is preferably a two-layer structure in the order of Ni plating and Sn plating. The Ni plating layer can prevent the base electrode layer 32 from being corroded by the solder when the multilayer ceramic capacitor 10 is mounted. In addition, the Sn plating layer can improve the wettability of the solder when the multilayer ceramic capacitor 10 is mounted, and can be easily mounted.

[0110] Furthermore, the thickness of each of the plating layers 34 is preferably 4 μm or more and 10 μm or less.

[0111] The plating layer 34 may be formed directly on the surface of the laminate 12 for either or both of the third external electrode 30c and the fourth external electrode 30d. That is, the laminated ceramic capacitor 10 may include a plating layer 34 that is directly electrically connected to the second internal electrode layer 16b. In such a case, the plating layer 34 may be formed directly after a catalyst is disposed on the surface of the laminate 12 as a pretreatment.

[0112] When the plating layer 34 is formed directly on the laminate 12 , the height can be reduced, that is, the thickness can be reduced, or the thickness can be converted to the thickness of the laminate 12 , that is, the thickness of the effective layer portion 15 a , thereby increasing the degree of freedom in designing a thin chip.

[0113] When the plated layer 34 is formed directly on the laminate 12 , the plated layer 34 preferably includes a lower plated electrode formed on the surface of the laminate 12 and an upper plated electrode formed on the surface of the lower plated electrode.

[0114] Preferably, the lower plated electrode and the upper plated electrode each contain at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing the metal.

[0115] In addition, for example, when the first internal electrode layer 16a and the second internal electrode layer 16b are formed using Ni, the lower plated electrode is preferably formed using Cu having good bonding properties with Ni. In addition, the upper plated electrode may be formed as required, and the third external electrode 30c and the fourth external electrode 30d may also be composed of only the lower plated electrode.

[0116] When the plated layer 34 is formed directly on the laminate 12 , the plated layer 34 may have an upper plated electrode as the outermost layer, or another plated electrode may be further formed on the surface of the upper plated electrode.

[0117] When the plating layer 34 is formed directly on the laminate 12 , the thickness of each plating layer 34 is preferably 1 μm or more and 15 μm or less.

[0118] When the plating layer 34 is formed directly on the laminate 12, the plating layer 34 preferably does not contain glass. In addition, the metal ratio per unit volume of the plating layer 34 is preferably 99 volume % or more.

[0119] according to Figure 1 The multilayer ceramic capacitor 10 shown in the figure has base electrode layers 32a and 32b in the first external electrode 30a and the second external electrode 30b, respectively. The base electrode layers 32a and 32b have a dense region 40 with a high area ratio of the conductive component 48 and a sparse region 42 with a lower area ratio of the conductive component 48 than the dense region 40. The dense region 40 is located closer to the laminate 12 than the sparse region 42. As a result, the contact between the internal electrode layer 16 and the conductive component 48 in the external electrode 30 is increased, and the insulation resistance can be reduced. In addition, by having the dense region 40 in the portion close to the laminate 12, the moisture resistance reliability can be improved.

[0120] according to Figure 1 In the multilayer ceramic capacitor 10 shown, the thickness l1 of the multilayer body 12 in the length direction z of the dense region 40 is preferably 30% or more and 50% or less of the thickness l2 of the multilayer body 12 in the length direction z of the first base electrode layer 32a and the second base electrode layer 32b. As a result, the contact between the internal electrode layer 16 and the conductive component 48 in the external electrode 30 is increased, the insulation resistance can be reduced, and the moisture resistance reliability can be improved.

[0121] according to Figure 1 In the illustrated multilayer ceramic capacitor 10, the area ratio of the conductive component 48 in the dense region 40 is preferably 80% or more and 85% or less relative to the area of ​​the dense region 40. This further increases the contact between the conductive component 48 in the internal electrode layer 16 and the external electrode 30, which can reduce the insulation resistance and improve the moisture resistance reliability.

[0122] according to Figure 1 In the illustrated multilayer ceramic capacitor 10, the area ratio of the conductive component 48 in the sparse region 42 is preferably 75% or more and 80% or less relative to the area of ​​the sparse region 42. This can further improve the moisture resistance reliability.

[0123] 2. Mounting structure of multilayer ceramic electronic components

[0124] Next, a mounting structure 60 of the multilayer ceramic capacitor 10 as an example of the multilayer ceramic electronic component according to the first embodiment of the present invention will be described.

[0125] like Fig. 9 as well as Fig.10As shown, the mounting structure 60 of the multilayer ceramic capacitor involved in the present embodiment includes the multilayer ceramic capacitor 10 involved in the present embodiment and the mounting substrate 50. The mounting substrate 50 includes a core material 51 of the substrate and a conductor connection land 52. The core material 51 of the substrate is, for example, a substrate including a material in which a base material mixed with glass cloth (fiber cloth) and glass non-woven cloth is impregnated with epoxy resin or polyimide resin, or a ceramic substrate manufactured by sintering a sheet material mixed with ceramic and glass. In addition, the core material 51 of the substrate may be a substrate including a single layer, or may be a substrate formed by stacking multiple layers.

[0126] The thickness of the core material 51 of the substrate is not particularly limited, but is preferably set to, for example, 200 μm or more and 800 μm or less.

[0127] One main surface of the core material 51 of the substrate constitutes a substrate-side mounting surface 51 a on which the conductor lands 52 are arranged and on which the multilayer ceramic capacitor 10 is mounted.

[0128] The conductor land 52 includes a first conductor land 52a, a second conductor land 52b, a third conductor land 52c, and a fourth conductor land 52d.

[0129] The first conductor land 52a is a portion electrically connected and mechanically joined to the first external electrode 30a of the multilayer ceramic capacitor 10 via the bonding material 54. The second conductor land 52b is a portion electrically connected and mechanically joined to the second external electrode 30b of the multilayer ceramic capacitor 10 via the bonding material 54. The third conductor land 52c is a portion electrically connected and mechanically joined to the third external electrode 30c of the multilayer ceramic capacitor 10 via the bonding material 54. The fourth conductor land 52d is a portion electrically connected and mechanically joined to the fourth external electrode 30d of the multilayer ceramic capacitor 10 via the bonding material 54.

[0130] In addition, the conductor land 52 may be provided on the main surface of the core material 51 of the substrate on the opposite side to the substrate-side mounting surface 51 a .

[0131] The material of the conductor land 52 is not particularly limited, and for example, metals such as copper, gold, palladium, and platinum can be used. In addition, the thickness of the conductor land 52, that is, the dimension in the stacking direction x, is not particularly limited, and for example, is preferably set to be greater than 20 μm and less than 200 μm. For example, a high heat-resistant epoxy adhesive can be used as the bonding material 54.

[0132] In the above description, the mounting substrate 50 is equivalent to the mounting substrate of the present invention. The core material 51 of the substrate is equivalent to the core material of the substrate of the present invention. The substrate side mounting surface 51a is equivalent to the mounting surface of the present invention. The plurality of conductor connection pads 52 are equivalent to the plurality of connection conductors of the present invention. However, the connection conductor of the present invention is not limited to other uses, functions, shapes, names, etc. as long as it is a conductor provided between the multilayer ceramic capacitor and the mounting substrate and capable of electrically connecting the two, in addition to the so-called connection pads.

[0133] Fig. 9 as well as Fig.10 The mounting structure 60 of the multilayer ceramic capacitor shown is mounted on the mounting substrate 50 so that the second main surface 12b of the multilayer ceramic capacitor 10 faces the substrate-side mounting surface 51a. Furthermore, the first external electrode 30a and the second external electrode 30b having the dense area 40 and the sparse area 42 are connected to the anode. As a result, the current distance is shortened, and it is possible to prevent an increase in insulation resistance while ensuring moisture resistance reliability.

[0134] 3. Method for manufacturing multilayer ceramic electronic component

[0135] Hereinafter, a method for manufacturing the multilayer ceramic capacitor 10 as an example of the multilayer ceramic electronic component according to the first embodiment of the present invention will be described.

[0136] First, a dielectric sheet and a conductive paste for internal electrodes are prepared. The conductive paste for the dielectric sheet and the internal electrodes contains a binder and a solvent. As the binder and the solvent, known binders and solvents can be used.

[0137] Next, a conductive paste for the internal electrode is printed on the dielectric sheet in a given pattern, for example, by screen printing, gravure printing, etc. Thus, a dielectric sheet having a pattern of the first internal electrode layer and a dielectric sheet having a pattern of the second internal electrode layer are prepared. More specifically, a screen plate for printing the first internal electrode layer and a screen plate for printing the second internal electrode layer can be prepared separately, and the internal electrode layer 16 of the present invention can be printed using a printer capable of printing the two screen plates separately. Here, the portion that becomes the effective layer portion 15a is formed by stacking the sheets printed with the first internal electrode layer and the second internal electrode layer so as to obtain the desired structure. In the present embodiment, a screen plate is used to print the internal electrode pattern.

[0138] Next, a portion that will become the first outer layer portion 15b1 on the first main surface 12a side is formed by laminating a predetermined number of dielectric sheets on which the pattern of the internal electrode layer is not printed. Then, a portion that will become the effective layer portion 15a prepared as described above is laminated, and a predetermined number of dielectric sheets on which the pattern of the internal electrode layer is not printed are laminated on the portion that will become the effective layer portion 15a, thereby forming a portion that will become the second outer layer portion 15b2 on the second main surface 12b side. In this way, a laminated sheet can be produced.

[0139] Next, the laminated sheets are pressed in the laminating direction by isostatic pressing or the like to produce a laminated block.

[0140] Next, the stacked block is cut into a given size to obtain stacked small pieces. At this time, the corners and ridges of the stacked small pieces may be rounded by barrel grinding or the like.

[0141] Next, the stacked small pieces are fired to produce the stacked body 12. The firing temperature depends on the materials of the ceramic and the internal electrodes, but is preferably 900°C or higher and 1400°C or lower.

[0142] The first base electrode layer 32a of the first external electrode 30a and the second base electrode layer 32b of the second external electrode 30b are formed on the first end face 12e and the second end face 12f of the fired laminate 12. In addition, the third base electrode layer 32c of the third external electrode 30c and the fourth base electrode layer 32d of the fourth external electrode 30d are formed on the first side face 12c and the second side face 12d of the fired laminate 12.

[0143] When a sintered layer is formed as the base electrode layer 32 , a conductive paste containing a glass component and a metal is applied and then sintered to form the base electrode layer 32 .

[0144] More specifically, first, the third foundation electrode layer 32c of the third external electrode 30c and the fourth foundation electrode layer 32d of the fourth external electrode 30d are formed on the first side surface 12c and the second side surface 12d of the fired laminated body 12.

[0145] Here, various methods can be used as a method for forming the third base electrode layer 32c and the fourth base electrode layer 32d. For example, a method of applying the conductive paste by extruding it from a slit can be used. In the case of this method, by increasing the amount of conductive paste extruded, the third base electrode layer 32c and the fourth base electrode layer 32d can be formed not only on the first side surface 12c and the second side surface 12d, but also on a part of the first main surface 12a and a part of the second main surface 12b.

[0146] In addition, the roller transfer method can also be used for formation. In the case of the roller transfer method, when the third base electrode layer 32c and the fourth base electrode layer 32d are formed not only on the first side surface 12c and the second side surface 12d, but also on a part of the first main surface 12a and a part of the second main surface 12b, the third base electrode layer 32c and the fourth base electrode layer 32d can be formed on a part of the first main surface 12a and a part of the second main surface 12b by increasing the pressing pressure during the roller transfer.

[0147] Next, the first base electrode layer 32a of the first external electrode 30a and the second base electrode layer 32b of the second external electrode 30b are formed on the first end face 12e and the second end face 12f of the laminate 12 obtained by firing. At this time, the conductive paste that will become the dense area 40 is applied to the first end face 12e and the second end face 12f of the laminate 12. Next, the conductive paste that will become the sparse area 42 is applied so as to cover a part or all of the dense area 40 formed as described above. Then, the base electrode layer 32 is fired at a firing temperature of 700° C. to 900° C. and a firing time of 10 minutes to 60 minutes. At this time, the atmosphere is preferably reduced at the 1st position and oxidized at the 10th position when observed at the equilibrium oxygen partial pressure of Ni / NiO. Here, the conductive paste that will become the dense area 40 has a higher Cu ratio than the conductive paste that will become the sparse area 42, thereby forming the dense area 40 and the sparse area 42.

[0148] Here, various methods can be used as a method for forming the first foundation electrode layer 32a and the second foundation electrode layer 32b. For example, a method such as dipping can be used to form the first foundation electrode layer 32a and the second foundation electrode layer 32b not only on the first end surface 12e and the second end surface 12f, but also to extend to a portion of the first main surface 12a and a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d.

[0149] In this embodiment, the first base electrode layer 32a and the second base electrode layer 32b are fired after the third base electrode layer 32c and the fourth base electrode layer 32d are fired, but the first base electrode layer 32a and the second base electrode layer 32b and the third base electrode layer 32c and the fourth base electrode layer 32d may be fired at the same time.

[0150] When the base electrode layer 32 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method: The conductive resin layer may be formed on the surface of the sintered layer, or the conductive resin layer may be formed directly on the laminate without forming a sintered layer.

[0151] As a method for forming a conductive resin layer, a conductive resin paste containing a thermosetting resin and a metal component is applied to a sintered layer or a laminate, and heat-treated at a temperature of 250° C. to 550° C. to thermally cure the resin, thereby forming a conductive resin layer. The atmosphere during the heat treatment is preferably an N2 atmosphere. In addition, in order to prevent the scattering of the resin and the oxidation of various metal components, the oxygen concentration is preferably suppressed to below 100 ppm.

[0152] As a method for applying the conductive resin paste, similar to the method of forming the base electrode layer 32 using a baked layer, for example, a method of applying the conductive paste by squeezing it out from a slit or a roll transfer method can be used.

[0153] Then, as needed, a plating layer 34 is formed on the base electrode layer 32 and on the surface of the laminate 12. In the present embodiment, the plating layer 34 is formed on the surface of the base electrode layer 32. More specifically, a Ni plating layer and a Sn plating layer are formed on the base electrode layer 32. When performing the plating process, either electrolytic plating or electroless plating can be used. However, electroless plating requires pretreatment using a catalyst or the like in order to increase the plating deposition rate, which has the disadvantage of complicating the process. Therefore, electrolytic plating is usually preferred.

[0154] As above, it is possible to produce Figure 1 A multilayer ceramic capacitor 10 described in .

[0155] B. Second Embodiment

[0156] 1. Laminated ceramic electronic components

[0157] Next, a multilayer ceramic capacitor 110 will be described as an example of a multilayer ceramic electronic component according to a second embodiment of the present invention.

[0158] Fig.11 This is a perspective view showing the appearance of a multilayer ceramic capacitor as an example of a multilayer ceramic electronic component according to a second embodiment of the present invention. Fig.12 It is a plan view showing a multilayer ceramic capacitor as an example of a multilayer ceramic electronic component according to a second embodiment of the present invention. Fig.13 It is a front view showing a multilayer ceramic capacitor as an example of a multilayer ceramic electronic component according to a second embodiment of the present invention. Fig.14 yes Fig.11 The cross-sectional view refers to the line XIV-XIV. Fig.15 yes Fig.11 The cross-sectional view refers to the line XV-XV. Fig.16 yes Fig.14 The cross-sectional view refers to the line XVI-XVI. Fig.17 yes Fig.14 The cross-sectional view refers to the line XVII-XVII. Fig.18 yes Fig.14 Enlarged view of the involved part B. Fig.19 It is an LT cross-sectional view showing an example of a mounting structure of a multilayer ceramic electronic component according to a second embodiment of the present invention. Fig. 20 WT is a cross-sectional view showing an example of a mounting structure of a multilayer ceramic electronic component according to a second embodiment of the present invention. However, the same reference numerals are used for the same or corresponding structures as those in the first embodiment, and detailed descriptions of the structures and operations common to those in the first embodiment are omitted.

[0159] The stacked ceramic capacitor 110 comprises: a stacked body 12 having a plurality of stacked ceramic layers 14 and a plurality of stacked internal electrode layers 16, including a first main surface 12a and a second main surface 12b opposite to each other in a stacking direction x, a first side surface 12c and a second side surface 12d opposite to each other in a width direction y perpendicular to the stacking direction x, and a first end surface 12e and a second end surface 12f opposite to each other in a length direction z perpendicular to the stacking direction x and the width direction y; and a plurality of external electrodes 130.

[0160] (External Electrode)

[0161] The external electrode 130 includes a plurality of external electrodes 130 connected to the first internal electrode layer 16a and the second internal electrode layer 16b. The external electrode 130 includes a first external electrode 130a, a second external electrode 130b, a third external electrode 130c, and a fourth external electrode 130d.

[0162] The first external electrode 130a is disposed on the first end surface 12e and connected to the first internal electrode layer 16a. The first external electrode 130a may also be disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d.

[0163] The second external electrode 130b is disposed on the second end surface 12f and connected to the first internal electrode layer 16a. The second external electrode 130b may also be disposed on a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d.

[0164] The third external electrode 130c is disposed on the first side surface 12c and is connected to the second internal electrode layer 16b. In addition, the third external electrode 130c may be disposed on a portion of the first main surface 12a and a portion of the second main surface 12b.

[0165] The fourth external electrode 130d is disposed on the second side surface 12d and connected to the second internal electrode layer 16b. In addition, the fourth external electrode 130d may be disposed on a portion of the first main surface 12a and a portion of the second main surface 12b.

[0166] It is preferable that each of the first external electrode 130 a , the second external electrode 130 b , the third external electrode 130 c , and the fourth external electrode 130 d includes a base electrode layer 132 and a plated layer 134 .

[0167] In other words, the first external electrode 130a preferably includes a first base electrode layer 132a and a first plating layer 134a. The second external electrode 130b preferably includes a second base electrode layer 132b and a second plating layer 134b. The third external electrode 130c preferably includes a third base electrode layer 132c and a third plating layer 134c. The fourth external electrode 130d preferably includes a fourth base electrode layer 132d and a fourth plating layer 134d.

[0168] The third base electrode layer 132c of the third external electrode 130c and the fourth base electrode layer 132d of the fourth external electrode 130d have a dense region 44 where the area ratio of the conductive component 48 is high and a sparse region 46 where the area ratio of the conductive component 48 is lower than that of the dense region 44 .

[0169] In more detail, the third base electrode layer 132c includes a dense region 44a having a high area ratio of the conductive component 48, and a sparse region 46a having a lower area ratio of the conductive component 48 than the dense region 44a. In addition, the fourth base electrode layer 132d includes a dense region 44b having a high area ratio of the conductive component 48, and a sparse region 46b having a lower area ratio of the conductive component 48 than the dense region 44b. The dense region 44 is composed of the dense region 44a of the third base electrode layer 132c and the dense region 44b of the fourth base electrode layer 132d. Similarly, the sparse region 46 is composed of the sparse region 46a of the third base electrode layer 132c and the sparse region 46b of the fourth base electrode layer 132d.

[0170] In addition, the dense region 44 is located on the laminate 12 side relative to the sparse region 46. Since the dense region 44 is located on the laminate 12 side relative to the sparse region 46, the contact between the second internal electrode layer 16b and the conductive component 48 in the third external electrode 130c or the fourth external electrode 130d is increased, resulting in a decrease in insulation resistance. In addition, by having the dense region 44 having a high area ratio of the conductive component 48 in the portion close to the laminate 12, moisture resistance reliability is also improved.

[0171] Furthermore, the area ratio of the conductive component 48 to the area of ​​the dense region 44 is preferably 80% or more and 85% or less. If the area ratio of the conductive component 48 to the area of ​​the dense region 44 becomes less than 80%, the area ratio of the dense region 44 where the area ratio of the voids to the conductive component 48 is high increases, thereby causing a decrease in moisture resistance reliability. In addition, if the area ratio of the conductive component 48 to the area of ​​the dense region 44 becomes greater than 85%, the content of the non-conductive component that ensures the connection with the stacked body 12 decreases, thereby increasing the risk of the third external electrode 130c or the fourth external electrode 130d peeling off.

[0172] In addition, the area ratio of the conductive component 48 to the area of ​​the sparse region 46 is preferably 75% or more and 80% or less. If the area ratio of the conductive component 48 to the area of ​​the sparse region 46 becomes less than 75%, the area ratio of the sparse region 46 where the area ratio of the void to the conductive component 48 is low increases, thereby causing a decrease in moisture resistance reliability. In addition, if the area ratio of the conductive component 48 to the area of ​​the sparse region 46 becomes more than 80%, the compressive stress of the sparse region 46 increases, which may cause structural defects.

[0173] The thickness w1 of the stack 12 in the width direction y of the dense region 44 is preferably 30% or more and 50% or less of the thickness w2 of the stack 12 in the width direction y of the third and fourth base electrode layers 132c, 132d. If the thickness w1 of the stack 12 in the width direction y of the dense region 44 becomes less than 30% of the thickness w2 of the stack 12 in the width direction y of the third and fourth base electrode layers 132c, 132d, the area ratio of the sparse region 46 to the dense region 44 increases, thereby causing a decrease in moisture resistance reliability. In addition, if the thickness w1 of the stack 12 in the width direction y of the dense region 44 becomes greater than 50% of the thickness w2 of the stack 12 in the width direction y of the third and fourth base electrode layers 132c, 132d, the area ratio of the sparse region 46 to the dense region 44 decreases, thereby failing to fully obtain the stress relaxation effect, which may cause structural defects.

[0174] In addition, regarding the method for measuring the area ratio of the conductive component 48 in the dense region 44 and the sparse region 46 of the third foundation electrode layer 132c and the fourth foundation electrode layer 132d, first, the dimension L in the length direction z of the multilayer ceramic capacitor 110 is measured. MThe cross section is polished to 1 / 2 of the stacking direction x of the stack 12 (1 / 2WT cross section). Next, the measurement is performed using a secondary electron image or a reflected electron image of a scanning electron microscope (SEM). The measurement portion of the dense area 44 is set on the polished surface as 1 / 2 of the stacking direction x of the stack 12 and 30% of the thickness (w2) of the third base electrode layer 132c and the fourth base electrode layer 132d in the width direction y of the stack 12. In addition, the measurement portion of the sparse area 46 is set on the polished surface as 1 / 2 of the stacking direction x of the stack 12 and 80% of the thickness (w2) of the third base electrode layer 132c and the fourth base electrode layer 132d in the width direction y of the stack 12. Next, using HALCON of MVTec, the conductive part and the non-conductive part are binarized to calculate the area ratio of the conductive component 48.

[0175] according to Fig.11 The multilayer ceramic capacitor 110 shown in the figure has base electrode layers 132c and 132d in the third external electrode 130c and the fourth external electrode 130d, respectively. The base electrode layers 132c and 132d have a dense region 44 having a high area ratio of the conductive component 48 and a sparse region 46 having a lower area ratio of the conductive component 48 than the dense region 44. The dense region 44 is located closer to the laminate 12 than the sparse region 46. As a result, the contact between the internal electrode layer 16 and the conductive component 48 in the external electrode 130 is increased, and the insulation resistance can be reduced. In addition, by having the dense region 44 in the portion close to the laminate 12, the moisture resistance reliability can be improved.

[0176] 2. Mounting structure of multilayer ceramic electronic components

[0177] Next, a mounting structure 160 of a multilayer ceramic capacitor 110 as an example of a multilayer ceramic electronic component according to a second embodiment of the present invention is described. In addition, the same reference numerals are used for the same or equivalent structures as those in the first embodiment, and detailed descriptions of the structures and operations common to those in the first embodiment are omitted.

[0178] like Fig.19 as well as Fig. 20 As shown, a mounting structure 160 of a multilayer ceramic capacitor according to the present embodiment includes a multilayer ceramic capacitor 110 according to the present embodiment and a mounting substrate 50 .

[0179] Fig.19 as well as Fig. 20The mounting structure 160 of the multilayer ceramic capacitor shown is mounted on the mounting substrate 50 so that the second main surface 12b of the multilayer ceramic capacitor 110 faces the substrate-side mounting surface 51a. Furthermore, the third external electrode 130c and the fourth external electrode 130d having the dense area 44 and the sparse area 46 are connected to the anode. As a result, the current distance is shortened, and it is possible to prevent an increase in insulation resistance while ensuring moisture resistance reliability.

[0180] 3. Method for manufacturing a laminated ceramic electronic component

[0181] Hereinafter, a method for manufacturing a multilayer ceramic capacitor 110 as an example of a multilayer ceramic electronic component according to a second embodiment of the present invention will be described. In addition, the same reference numerals are used for the same or equivalent structures as those in the first embodiment, and detailed descriptions of the structures and operations common to those in the first embodiment will be omitted.

[0182] First, the laminate 12 is produced. The first base electrode layer 132a of the first external electrode 130a and the second base electrode layer 132b of the second external electrode 130b are formed on the first end face 12e and the second end face 12f of the laminate 12 obtained by firing. In addition, the third base electrode layer 132c of the third external electrode 130c and the fourth base electrode layer 132d of the fourth external electrode 130d are formed on the first side face 12c and the second side face 12d of the laminate 12 obtained by firing.

[0183] When a sintered layer is formed as the base electrode layer 132 , a conductive paste containing a glass component and a metal is applied and then sintered to form the base electrode layer 132 .

[0184] In more detail, first, the third base electrode layer 132c of the third external electrode 130c and the fourth base electrode layer 132d of the fourth external electrode 130d are formed on the first side surface 12c and the second side surface 12d of the laminated body 12 obtained by firing. At this time, the conductive paste that will become the dense area 44 is applied to the first side surface 12c and the second side surface 12d of the laminated body 12. Then, the conductive paste that will become the sparse area 46 is applied so as to cover a part or all of the dense area 44 formed above. Then, the third base electrode layer 132c and the fourth base electrode layer 132d are fired at a firing temperature of 700° C. to 900° C. and a firing time of 10 minutes to 60 minutes. At this time, the atmosphere is preferably reduced at the 1st position and oxidized at the 10th position when observed at the equilibrium oxygen partial pressure of Ni / NiO. Furthermore, the conductive paste to be used in dense region 44 has a higher Cu ratio than the conductive paste to be used in sparse region 46 , thereby forming dense region 44 and sparse region 46 .

[0185] Here, various methods can be used as a method for forming the third base electrode layer 132c and the fourth base electrode layer 132d. For example, a method of applying the conductive paste by extruding it from a slit can be used. In the case of this method, by increasing the amount of conductive paste extruded, the third base electrode layer 132c and the fourth base electrode layer 132d can be formed not only on the first side surface 12c and the second side surface 12d, but also on a part of the first main surface 12a and a part of the second main surface 12b.

[0186] In addition, it is also possible to form it using a roller transfer method. In the case of the roller transfer method, when the base electrode layer 132 is formed not only on the first side surface 12c and the second side surface 12d, but also on a part of the first main surface 12a and a part of the second main surface 12b, the third base electrode layer 132c and the fourth base electrode layer 132d can be formed on a part of the first main surface 12a and a part of the second main surface 12b by increasing the pressing pressure during the roller transfer.

[0187] Next, the first foundation electrode layer 132a of the first external electrode 130a and the second foundation electrode layer 132b of the second external electrode 130b are formed on the first end surface 12e and the second end surface 12f of the fired laminated body 12.

[0188] Here, various methods can be used as a method for forming the first base electrode layer 132a and the second base electrode layer 132b. For example, a method such as dipping can be used to form the first base electrode layer 132a and the second base electrode layer 132b not only on the first end surface 12e and the second end surface 12f, but also to extend to a portion of the first main surface 12a and a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d.

[0189] In this embodiment, the first base electrode layer 132a and the second base electrode layer 132b are fired after the third base electrode layer 132c and the fourth base electrode layer 132d are fired, but the first base electrode layer 132a and the second base electrode layer 132b and the third base electrode layer 132c and the fourth base electrode layer 132d may be fired at the same time.

[0190] When the base electrode layer 132 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method: The conductive resin layer may be formed on the surface of the sintered layer, or the conductive resin layer may be formed directly on the laminate without forming the sintered layer.

[0191] As a method for forming a conductive resin layer, a conductive resin paste containing a thermosetting resin and a metal component is applied to a sintered layer or a laminate, and heat-treated at a temperature of 250° C. to 550° C. to thermally cure the resin, thereby forming a conductive resin layer. The atmosphere during the heat treatment is preferably an N2 atmosphere. In addition, in order to prevent the scattering of the resin and the oxidation of various metal components, the oxygen concentration is preferably suppressed to below 100 ppm.

[0192] As a method for applying the conductive resin paste, similar to the method of forming the base electrode layer 132 using a baked layer, for example, a method of applying the conductive paste by squeezing it out from a slit or a roll transfer method can be used.

[0193] Then, as needed, a plating layer 134 is formed on the base electrode layer 132 and on the surface of the laminate 12. In the present embodiment, the plating layer 134 is formed on the surface of the base electrode layer 132. In more detail, a Ni plating layer and a Sn plating layer are formed on the base electrode layer 132. When performing the plating process, either electrolytic plating or electroless plating can be used. However, electroless plating requires pretreatment using a catalyst or the like in order to increase the plating deposition rate, which has the disadvantage of complicating the process. Therefore, electrolytic plating is usually preferred.

[0194] As above, it is possible to produce Fig.11 A multilayer ceramic capacitor 110 described in .

[0195] C. Modification

[0196] In the first embodiment, the first base electrode layer 32a of the first external electrode 30a and the second base electrode layer 32b of the second external electrode 30b have a dense region 40 and a sparse region 42, but the present invention is not limited thereto. In addition, in the second embodiment, the third base electrode layer 132c of the third external electrode 130c and the fourth base electrode layer 132d of the fourth external electrode 130d have a dense region 44 and a sparse region 46, but the present invention is not limited thereto. That is, the first base electrode layer of the first external electrode, the second base electrode layer of the second external electrode, the third base electrode layer of the third external electrode, and the fourth base electrode layer of the fourth external electrode may have a dense region and a sparse region.

[0197] Furthermore, as described above, the embodiments of the present invention are disclosed through the above description, but the present invention is not limited thereto.

[0198] That is, various changes can be made to the above-described embodiment and each modified example with respect to mechanism, shape, material, number, position, arrangement, etc. within the scope not departing from the technical idea and purpose of the present invention, and they are included in the present invention.

[0199] <1>

[0200] A laminated ceramic electronic component comprises a laminate and a plurality of external electrodes, wherein the laminate comprises a plurality of laminated ceramic layers and a plurality of laminated internal electrode layers, and comprises a first main surface and a second main surface opposite to each other in a lamination direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the lamination direction and the width direction, wherein:

[0201] The plurality of internal electrode layers include:

[0202] a first internal electrode layer, which is alternately stacked with the plurality of ceramic layers and is exposed at the first end surface and the second end surface; and

[0203] a second internal electrode layer, which is alternately stacked with the plurality of ceramic layers and exposed on the first side surface and the second side surface;

[0204] The plurality of external electrodes include:

[0205] a first external electrode and a second external electrode connected to the first internal electrode layer; and

[0206] The third external electrode and the fourth external electrode are connected to the second internal electrode layer.

[0207] The first external electrode and the second external electrode each have a base electrode layer, wherein the base electrode layer has a dense region having a high area ratio of a conductive component and a sparse region having a lower area ratio of a conductive component than the dense region.

[0208] The dense region is located closer to the stacked body than the sparse region.

[0209] <2>

[0210] In the multilayer ceramic electronic component according to <1>, a thickness of the multilayer body in the densely populated region in the longitudinal direction is 30% to 50% of a thickness of the multilayer body of the first and second foundation electrode layers in the longitudinal direction.

[0211] <3>

[0212] The multilayer ceramic electronic component according to <1> or <2>, wherein an area ratio of the conductive component in the densely populated region is 80% or more and 85% or less relative to an area of ​​the densely populated region.

[0213] <4>

[0214] The multilayer ceramic electronic component according to any one of <1> to <3>, wherein an area ratio of the conductive component in the sparse region is 75% or more and 80% or less relative to an area of ​​the sparse region.

[0215] <5>

[0216] A mounting structure for a laminated ceramic electronic component, comprising:

[0217] mounting substrate; and

[0218] A multilayer ceramic electronic component is mounted on the mounting substrate.

[0219] The laminated ceramic electronic component comprises a laminate and a plurality of external electrodes, wherein the laminate comprises a plurality of laminated ceramic layers and a plurality of laminated internal electrode layers, and comprises a first main surface and a second main surface opposite to each other in a lamination direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the lamination direction and the width direction.

[0220] The plurality of internal electrode layers include:

[0221] a first internal electrode layer, which is alternately stacked with the plurality of ceramic layers and is exposed at the first end surface and the second end surface; and

[0222] a second internal electrode layer, which is alternately stacked with the plurality of ceramic layers and exposed on the first side surface and the second side surface;

[0223] The plurality of external electrodes include:

[0224] a first external electrode and a second external electrode connected to the first internal electrode layer; and

[0225] The third external electrode and the fourth external electrode are connected to the second internal electrode layer.

[0226] The first external electrode and the second external electrode each have a base electrode layer, wherein the base electrode layer has a dense region having a high area ratio of a conductive component and a sparse region having a lower area ratio of a conductive component than the dense region.

[0227] The dense region is located closer to the stacked body than the sparse region.

[0228] The mounting substrate comprises:

[0229] The core material of the substrate;

[0230] a first connection conductor, disposed on the core material and connected to the first external electrode;

[0231] a second connection conductor disposed on the core material and connected to the second external electrode;

[0232] a third connection conductor disposed on the core material and connected to the third external electrode; and

[0233] a fourth connection conductor disposed on the core material and connected to the fourth external electrode,

[0234] In the multilayer ceramic electronic component, the first external electrode and the second external electrode having the dense region and the sparse region are connected to an anode.

[0235] <6>

[0236] A laminated ceramic electronic component comprises a laminate and a plurality of external electrodes, wherein the laminate comprises a plurality of laminated ceramic layers and a plurality of laminated internal electrode layers, and comprises a first main surface and a second main surface opposite to each other in a lamination direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the lamination direction and the width direction, wherein:

[0237] The plurality of internal electrode layers include:

[0238] a first internal electrode layer, which is alternately stacked with the plurality of ceramic layers and is exposed at the first end surface and the second end surface; and

[0239] a second internal electrode layer, which is alternately stacked with the plurality of ceramic layers and exposed on the first side surface and the second side surface;

[0240] The plurality of external electrodes include:

[0241] a first external electrode and a second external electrode connected to the first internal electrode layer; and

[0242] The third external electrode and the fourth external electrode are connected to the second internal electrode layer.

[0243] The third external electrode and the fourth external electrode each have a base electrode layer, wherein the base electrode layer has a dense region having a high area ratio of a conductive component and a sparse region having a lower area ratio of a conductive component than the dense region.

[0244] The dense region is located closer to the stacked body than the sparse region.

[0245] <7>

[0246] A mounting structure for a laminated ceramic electronic component, comprising:

[0247] mounting substrate; and

[0248] A multilayer ceramic electronic component is mounted on the mounting substrate.

[0249] The laminated ceramic electronic component comprises a laminate and a plurality of external electrodes, wherein the laminate comprises a plurality of laminated ceramic layers and a plurality of laminated internal electrode layers, and comprises a first main surface and a second main surface opposite to each other in a lamination direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the lamination direction and the width direction.

[0250] The plurality of internal electrode layers include:

[0251] a first internal electrode layer, which is alternately stacked with the plurality of ceramic layers and is exposed at the first end surface and the second end surface; and

[0252] a second internal electrode layer, which is alternately stacked with the plurality of ceramic layers and exposed on the first side surface and the second side surface;

[0253] The plurality of external electrodes include:

[0254] a first external electrode and a second external electrode connected to the first internal electrode layer; and

[0255] The third external electrode and the fourth external electrode are connected to the second internal electrode layer.

[0256] The third external electrode and the fourth external electrode each have a base electrode layer, wherein the base electrode layer has a dense region having a high area ratio of a conductive component and a sparse region having a lower area ratio of a conductive component than the dense region.

[0257] The dense region is located closer to the stacked body than the sparse region.

[0258] The mounting substrate comprises:

[0259] The core material of the substrate;

[0260] a first connection conductor, disposed on the core material and connected to the first external electrode;

[0261] a second connection conductor disposed on the core material and connected to the second external electrode;

[0262] a third connection conductor disposed on the core material and connected to the third external electrode; and

[0263] a fourth connection conductor disposed on the core material and connected to the fourth external electrode,

[0264] In the multilayer ceramic electronic component, the third external electrode and the fourth external electrode having the dense region and the sparse region are connected to an anode.

[0265] Industrial Applicability

[0266] The present invention relates to a multilayer ceramic electronic component and can be used as a multilayer ceramic electronic component capable of preventing an increase in insulation resistance while ensuring moisture-resistant reliability.

[0267] Description of Reference Numerals

[0268] 10. Multilayer ceramic capacitors;

[0269] 12 laminate;

[0270] 12a 1st main side;

[0271] 12b 2nd main side;

[0272] 12c 1st side;

[0273] 12d 2nd side;

[0274] 12e 1st end face;

[0275] 12f 2nd end surface;

[0276] 14 Ceramic layer;

[0277] 15a effective layer;

[0278] 15b1 1st outer part;

[0279] 15b2 2nd outer part;

[0280] 16 internal electrode layer;

[0281] 16a first internal electrode layer;

[0282] 16b second internal electrode layer;

[0283] 18a: first opposing portion;

[0284] 18b second opposing portion;

[0285] 20a: first lead-out portion;

[0286] 20b: second lead-out portion;

[0287] 22a 1st extension;

[0288] 22b The second extension;

[0289] 24a, 24b side of the stack (W gap);

[0290] 26a, 26b ends of the stack (L gap);

[0291] 30 external electrodes;

[0292] 30a first external electrode;

[0293] 30b second external electrode;

[0294] 30c 3rd external electrode;

[0295] 30d 4th external electrode;

[0296] 32 base electrode layer;

[0297] 32a: a first base electrode layer;

[0298] 32b: a second base electrode layer;

[0299] 32c: the third base electrode layer;

[0300] 32d 4th base electrode layer;

[0301] 34 coating;

[0302] 34a: first coating layer;

[0303] 34b: second coating layer;

[0304] 34c: 3rd coating layer;

[0305] 34d 4th coating layer;

[0306] 40 Dense area on the end face side;

[0307] 40a: a dense area on the first end surface side;

[0308] 40b: a dense area on the second end surface side;

[0309] 42 Sparse area on the end face side;

[0310] 42a: a sparse region on the first end surface side;

[0311] 42b: a sparse region on the second end surface side;

[0312] 44 Dense areas on the lateral side;

[0313] 44a Dense area on the first lateral side;

[0314] 44b Dense area on the 2nd lateral side;

[0315] 46 sparse areas on the lateral side;

[0316] 46a Sparse area on the 1st lateral side;

[0317] 46b Sparse area on the 2nd lateral side;

[0318] 48 conductive components;

[0319] 50 Install the base plate;

[0320] 51 core material;

[0321] 51a substrate side mounting surface;

[0322] 52 connecting conductor (connecting plate);

[0323] 54 Joining materials (solder);

[0324] x stacking direction;

[0325] y width direction;

[0326] z length direction;

[0327] L M The length dimension of the multilayer ceramic capacitor;

[0328] W M The width dimension of the multilayer ceramic capacitor;

[0329] T M The dimensions of a stacked ceramic capacitor in the stacking direction;

[0330] L is the length dimension of the laminate;

[0331] W is the width dimension of the laminate;

[0332] T is the dimension of the stack in the stacking direction;

[0333] l1: the thickness of the dense area of ​​the first end surface and the second end surface in the length direction;

[0334] l2 thickness of the first base electrode layer and the second base electrode layer in the length direction;

[0335] w1 is the thickness in the width direction of the dense area of ​​the first side and the second side;

[0336] w2: thickness of the third foundation electrode layer and the fourth foundation electrode layer in the width direction.

Claims

1. A laminated ceramic electronic component, comprising a laminate and a plurality of external electrodes, the laminate comprising a plurality of laminated ceramic layers and a plurality of laminated internal electrode layers, and comprising a first main surface and a second main surface opposite to each other in a lamination direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the lamination direction and the width direction, wherein: The plurality of internal electrode layers include: a first internal electrode layer, which is alternately stacked with the plurality of ceramic layers and is exposed at the first end surface and the second end surface; and a second internal electrode layer, which is alternately stacked with the plurality of ceramic layers and exposed on the first side surface and the second side surface; The plurality of external electrodes include: a first external electrode and a second external electrode connected to the first internal electrode layer; and The third external electrode and the fourth external electrode are connected to the second internal electrode layer. The first external electrode and the second external electrode each have a base electrode layer, wherein the base electrode layer has a dense region having a high area ratio of a conductive component and a sparse region having a lower area ratio of a conductive component than the dense region. The dense region is located closer to the stacked body than the sparse region.

2. The multilayer ceramic electronic component according to claim 1, wherein The thickness of the stacked body in the densely populated area in the longitudinal direction is 30% or more and 50% or less of the thickness of the stacked body in the longitudinal direction of the first foundation electrode layer and the second foundation electrode layer.

3. The multilayer ceramic electronic component according to claim 1 or 2, wherein: An area ratio of the conductive component in the densely populated region is 80% or more and 85% or less relative to an area of ​​the densely populated region.

4. The multilayer ceramic electronic component according to any one of claims 1 to 3, wherein An area ratio of the conductive component in the sparse region is 75% or more and 80% or less relative to an area of ​​the sparse region.

5. A mounting structure of a laminated ceramic electronic component, comprising: mounting substrate; and A multilayer ceramic electronic component is mounted on the mounting substrate. The laminated ceramic electronic component comprises a laminate and a plurality of external electrodes, wherein the laminate comprises a plurality of laminated ceramic layers and a plurality of laminated internal electrode layers, and comprises a first main surface and a second main surface opposite to each other in a lamination direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the lamination direction and the width direction. The plurality of internal electrode layers include: a first internal electrode layer, which is alternately stacked with the plurality of ceramic layers and is exposed at the first end surface and the second end surface; and a second internal electrode layer, which is alternately stacked with the plurality of ceramic layers and exposed on the first side surface and the second side surface; The plurality of external electrodes include: a first external electrode and a second external electrode connected to the first internal electrode layer; and The third external electrode and the fourth external electrode are connected to the second internal electrode layer. The first external electrode and the second external electrode each have a base electrode layer, wherein the base electrode layer has a dense region having a high area ratio of a conductive component and a sparse region having a lower area ratio of a conductive component than the dense region. The dense region is located closer to the stacked body than the sparse region. The mounting substrate comprises: The core material of the substrate; a first connection conductor, disposed on the core material and connected to the first external electrode; a second connection conductor disposed on the core material and connected to the second external electrode; a third connection conductor disposed on the core material and connected to the third external electrode; and a fourth connection conductor disposed on the core material and connected to the fourth external electrode, In the multilayer ceramic electronic component, the first external electrode and the second external electrode having the dense region and the sparse region are connected to an anode.

6. A laminated ceramic electronic component comprising a laminate and a plurality of external electrodes, the laminate comprising a plurality of laminated ceramic layers and a plurality of laminated internal electrode layers, and comprising a first main surface and a second main surface opposite to each other in a stacking direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the stacking direction and the width direction, wherein: The plurality of internal electrode layers include: a first internal electrode layer, which is alternately stacked with the plurality of ceramic layers and is exposed at the first end surface and the second end surface; and a second internal electrode layer, which is alternately stacked with the plurality of ceramic layers and exposed on the first side surface and the second side surface; The plurality of external electrodes include: a first external electrode and a second external electrode connected to the first internal electrode layer; and The third external electrode and the fourth external electrode are connected to the second internal electrode layer. The third external electrode and the fourth external electrode each have a base electrode layer, wherein the base electrode layer has a dense region having a high area ratio of a conductive component and a sparse region having a lower area ratio of a conductive component than the dense region. The dense region is located closer to the stacked body than the sparse region.

7. A mounting structure of a laminated ceramic electronic component, comprising: mounting substrate; and A multilayer ceramic electronic component is mounted on the mounting substrate. The laminated ceramic electronic component comprises a laminate and a plurality of external electrodes, wherein the laminate comprises a plurality of laminated ceramic layers and a plurality of laminated internal electrode layers, and comprises a first main surface and a second main surface opposite to each other in a lamination direction, a first side surface and a second side surface opposite to each other in a width direction perpendicular to the lamination direction, and a first end surface and a second end surface opposite to each other in a length direction perpendicular to the lamination direction and the width direction. The plurality of internal electrode layers include: a first internal electrode layer, which is alternately stacked with the plurality of ceramic layers and is exposed at the first end surface and the second end surface; and a second internal electrode layer, which is alternately stacked with the plurality of ceramic layers and exposed on the first side surface and the second side surface; The plurality of external electrodes include: a first external electrode and a second external electrode connected to the first internal electrode layer; and The third external electrode and the fourth external electrode are connected to the second internal electrode layer. The third external electrode and the fourth external electrode each have a base electrode layer, wherein the base electrode layer has a dense region having a high area ratio of a conductive component and a sparse region having a lower area ratio of a conductive component than the dense region. The dense region is located closer to the stacked body than the sparse region. The mounting substrate comprises: The core material of the substrate; a first connection conductor, disposed on the core material and connected to the first external electrode; a second connection conductor disposed on the core material and connected to the second external electrode; a third connection conductor disposed on the core material and connected to the third external electrode; and a fourth connection conductor disposed on the core material and connected to the fourth external electrode, In the multilayer ceramic electronic component, the third external electrode and the fourth external electrode having the dense region and the sparse region are connected to an anode.

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