Method and apparatus for detecting region of interest based on variable rate shading

Abstract

Methods, apparatus, systems, and articles of manufacture for identifying a region of interest of an image based on a variable rate shading (VRS) mask created from a video image. A method for detecting a region may include detecting, with one or more processors, a region of interest of a video image based on a VRS mask generated by a renderer. The method may also include encoding, with the one or more processors, the region of interest of the video image, the encoding including adjusting the quantization parameter to be adapted to encode the region of interest.

Description

Technical Field

[0001] Generally speaking, the present disclosure relates to detecting regions of interest, and more particularly, to methods and apparatus for detecting regions of interest based on variable rate shading (VRS). Background Art

[0002] Region of Interest (ROI) encoding is a feature widely used in the field of computer generated graphics to improve coding quality. Current techniques for detecting regions of interest typically include: i) traditional detectors (e.g., HOG detectors, deformable part-based models (DPMs), etc.) and ii) convolutional neural network (CNN) detectors. ROI encoding is proposed to improve the image quality of objects (or regions) of interest in a graphics scene (e.g., a video scene), while reducing the quality level of less interesting regions in the same video scene. Both techniques are typically applied to each frame in a video sequence. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 is a block diagram of a cloud-based gaming system that streams games to client gaming devices.

[0004] Figure 2 is a block diagram of a configuration for performing variable rate shading (VRS).

[0005] Figure 3 is a flow chart showing how different shading rates based on different shading layers are combined to create a final shading rate.

[0006] Figure 4 is a block diagram of an example pipeline for encoding a video image according to the teachings disclosed herein, the example pipeline including a detector that detects a region of interest in the video image based on a VRS mask generated by a renderer.

[0007] Figure 5 yes Figure 4 Block diagram 500 of an example implementation of a detector and renderer.

[0008] Figure 6 is a schematic diagram of a VRS mask generated for a video image.

[0009] Figure 7 is a schematic diagram of a VRS coding unit (VCU) converted into an important VRS coding unit (IVCU map).

[0010] Figure 8 is a diagram of connected components around which an axis-aligned minimum bounding box has been drawn.

[0011] Fig. 9is a representation that can be executed by an example processor circuit device (circuitry) to implement Figure 5 A flowchart of example machine readable instructions and / or example operations of a detector.

[0012] Fig.10 is a block diagram of an example processing platform including a processor circuit device configured to perform Fig. 9 Example machine readable instructions and / or example operations to implement Figure 5 Detector.

[0013] Fig.11 yes Fig.10 A block diagram of an example implementation of a processor circuit device.

[0014] Fig.12 yes Fig.10 A block diagram of another example implementation of a processor circuit device.

[0015] Generally, the same reference numbers will be used throughout the drawings and accompanying written description to refer to the same or like parts.The drawings are not drawn to scale.

[0016] As used herein, unless otherwise specified, connection references (e.g., attachment, coupling, connection, and engagement) may include intermediate members between elements referenced by the connection reference and / or relative movement between such elements. Thus, a connection reference does not necessarily infer that two elements are directly connected and / or are in a fixed relationship to each other. As used herein, a statement that any part is "in contact with" another part is defined to mean that there are no intermediate parts between the two parts.

[0017] Unless otherwise specifically stated, descriptors such as "first," "second," "third," etc. are used herein without inferring or otherwise indicating any meaning of priority, physical order, arrangement in a list, and / or ordering in any manner, but are used merely as labels and / or arbitrary names to distinguish elements to facilitate understanding of the disclosed examples. In some examples, the descriptor "first" may be used to refer to an element in the detailed description, while the same element may be referred to by a different descriptor (such as "second" or "third") in the claims. In this case, it should be understood that these descriptors are only used to clearly identify those elements that may, for example, otherwise share the same name.

[0018] As used herein, "approximately" and "approximately" modify their subject matter / values ​​to recognize possible variations that occur in real-world applications. For example, "approximately" and "approximately" may modify dimensions that may not be exact due to manufacturing tolerances and / or other real-world imperfections that will be understood by one of ordinary skill in the art. For example, "approximately" and "approximately" may indicate that these dimensions may be within a tolerance range of + / - 10%, unless otherwise stated in the description below. As used herein, "substantially real time" means occurring in a nearly instantaneous manner, recognizing that there may be real-world delays for computation time, transmission, etc. Therefore, unless otherwise stated, "substantially real time" means real time + / - 1 second.

[0019] As used herein, the phrase "in communication" includes variations thereof, including direct communication and / or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or continuous communication, but also includes selective communication at periodic intervals, scheduled intervals, non-periodic intervals and / or one-time events.

[0020] As used herein, "processor circuitry" is defined as including (i) one or more special-purpose circuits that are constructed to perform specific operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and / or (ii) one or more general-purpose semiconductor-based circuits that are programmable with instructions to perform specific operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of processor circuitry include programmable microprocessors, field programmable gate arrays (FPGAs) that can instantiate instructions, central processor units (CPUs), graphics processor units (GPUs), digital signal processors (DSPs), XPUs, or microcontrollers and integrated circuits, such as application-specific integrated circuits (ASICs). For example, an XPU can be implemented by a heterogeneous computing system that includes multiple types of processor circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more DSPs, etc., and / or combinations thereof) and an application programming interface (API) that can assign computing tasks to any one or more of the multiple types of processing circuitry that is best suited to perform the computing tasks. DETAILED DESCRIPTION

[0021] Cloud gaming is a type of online gaming that runs a video game on a remote server and streams the game directly to the user's device (also referred to as a client device and / or gaming device). In a cloud gaming scenario, due to bandwidth limitations, rendered video frames must be encoded before being sent to the client device. Therefore, encoding quality is of great significance in terms of user experience. Although, as mentioned above, region of interest (ROI) encoding is a widely used technique for improving encoding quality, ROI detectors based on traditional or convolutional neural network (CNN) techniques require a lot of computing resources when applied to each frame in a video sequence. In addition, traditional and CNN techniques for performing ROI detection are sensitive to the data sets on which they are trained. A new ROI detection method disclosed herein is based on the use of a variable rate shading (VRS) mask generated by graphics for cloud gaming. This novel VRS mask-based ROI detection technique requires almost negligible computation and is insensitive to data.

[0022] In a traditional cloud gaming pipeline, frames output from a renderer are passed to an encoder, so that the renderer and encoder operate as two independent components. According to the methods, devices, systems, and products disclosed herein, VRS information is shared between the renderer and the encoder as metadata. The encoder uses the VRS information contained in the metadata to achieve improved encoding and decoding efficiency and reduce processing power. Because, as further disclosed herein, only areas of the video frame with rich details require high shading rates, improved efficiency and power savings are achieved. Therefore, more bits are spent on areas with rich details, and fewer bits are spent on other areas. In some examples, the information provided to the encoder enables the encoder to select a quantization parameter (QP) that is more suitable for the encoded image. The quantization parameter (QP) is related to the amount of compression that occurs for each macroblock (MB) in the frame. A large QP value indicates that the corresponding image is encoded using coarser quantization, higher compression, and lower quality. In contrast, an image encoded using a low QP value indicates the opposite. In addition, the methods, devices, systems, and products disclosed herein are insensitive to training data because no training data is used.

[0023] VRS (also known as Coarse Pixel Shading) is a novel architecture for flexibly controlling shading rates in a 3D graphics pipeline that significantly reduces shading costs for a variety of applications. VRS allows rendering performance / power to be allocated at a rate that varies across the rendered image (e.g., allocating more power to render areas of interest and less power to render other areas).

[0024] Figure 1An example cloud gaming system 100 is shown with a set of cloud-based (e.g., remote) gaming servers 102 that run and stream video games to a plurality of different client devices / gaming devices 104A-104E. An example detector for detecting regions of interest based on VRS masks of video images may be used, for example, in the cloud-based gaming servers 102, as described further below.

[0025] Figure 2 Four different configurations are shown in which shading rates may be determined, including a first "1x1" configuration 202, a second "2x1" configuration 204, a third "1x2" configuration 206, and a fourth "2x2" configuration 208. Figure 2 In the first, second, third and fourth configurations of the example, each square represents a pixel and each black dot represents the location where the VRS system's coarse pixel shader performs pixel shader evaluation. Figure 2 ) are then broadcasted to the white points in the render target. Using the coarse pixel shader assumption, all white points / positions will be assigned / assigned the result of the evaluation performed at the location of the corresponding black point. In general, when VRS is used, more time is spent shading the most important pixels (e.g., pixels with richer details), and the shading rate applied to less important pixels is reduced. In addition, more coverage and depth information for each pixel of the render target is retained relative to other software-based techniques.

[0026] In some examples, different shading densities are used to represent different shading intensities (e.g., results of an evaluation) to be applied when shading corresponding pixels (or other sized regions). Each of the different shading densities indicates a different intensity level of detail associated with the object represented by the pixel. In some examples, the highest density of shading represents a high level of shading intensity, while lower density shading represents a lower level of shading intensity.

[0027] Figure 3An example flow 300 is shown by which different types of shading rates are combined to form a final shading rate applied to a pixel. In some such examples, there are 3 layers of shading rate settings. The example first layer 302 is used to set a per-draw shading rate based on a frame. When the first layer 302 is used, the same shading rate is applied to the entire frame. The example second layer 304 is a per-initiated vertex shading rate (or per-primitive shading rate). In further detail, in a rendering pipeline, a VRS system may include different types of shaders, including vertex shaders and geometry shaders. In terms of pixel configuration, a "primitive" consists of multiple vertices, and one of the vertices is designated as a "initiated vertex." The per-initiated vertex shading rate and the per-primitive shading rate are essentially the same because the final shading rate for each initiating vertex / primitive is different. The initiating vertex shading rate comes from the vertex shader, while the primitive shading rate comes from the geometry shader. The example third layer 306 is an image-based shading rate. Image-based shading rate allows creation of a “level of detail (LOD) mask” image that indicates areas of different qualities (e.g., areas that will be covered by motion blur, areas covered by depth of field blur, areas containing transparent objects, or areas affected by elements of a heads-up display user interface).

[0028] Some VRS tools support only one per-draw layer (for example, the first layer), while others support all three layers. Figure 3 As shown in the process 300, the first combiner 308 and the second combiner 310 allow the three layers of shading rates (e.g., per-draw shading rate, triggered vertex shading rate, and image-based shading rate) to be combined to arrive at a final shading rate 312. The final shading rate for each pixel is identified on the VRS mask generated for the corresponding image.

[0029] Figure 4is a block diagram of an example video pipeline 400 having an example detector 402 for detecting regions of interest in a video image based on a VRS mask generated by an example renderer 404 in accordance with the teachings of the present disclosure. In some examples, the video pipeline 400 additionally includes an example frame generator 406 and an example encoder 408. In some such examples, the example renderer 404 provides rendered video to the frame generator 406 and provides the VRS mask to the detector 402. The renderer 404 uses VRS techniques to render the video image and also uses VRS techniques to generate a VRS mask for use by the detector 402. The frame generator uses the rendered image to generate a video frame and then passes the video frame to the encoder 408. The detector 402 uses the VRS mask generated by the renderer 404 to determine a region of interest and then provides the region of interest to the encoder 408. Thus, the VRS technique performed by the renderer has two purposes (e.g., to produce a rendering of the video image and to enable the detector 402 to identify a region of interest). The encoder 408 uses the region of interest information to identify portions of the video frame to be encoded using a greater number of bits, thereby maintaining the level of detail included in these regions. In some examples, the encoder uses the region of interest (ROI) information to adjust the QP value used to encode each MB in the ROI. Thus, the encoder operates faster and more efficiently by using QP values ​​that are appropriate for the content being encoded (e.g., whether a region of interest is being encoded).

[0030] Figure 5 Yes Figure 4 An example detector 402 and Figure 4 An example block diagram 500 of an example renderer 404 of FIG. The renderer 404 includes an example VRS mask generator 502, and the detector 402 includes an example important VRS codec unit (IVCU) searcher 504, an example connected component marker (CCL) 506, an example axis-aligned minimum bounding box (AAMBB) definer 508, an example final score calculator 510, and an example region of interest (ROI) provider 512.

[0031] As described above, the renderer 405 (also referred to as the renderer circuitry 405) includes a VRS mask generator 502 (also referred to as the VRS mask generator circuitry 502) that renders a video image to provide to the example frame generator 406 ( Figure 4). In addition, the renderer 405 provides the VRS mask generated by the VRS mask generator 502 to the IVCU searcher 504 (also referred to as IVCU searcher circuit device 504 and / or searcher circuit device 504) of the detector 402. According to the teachings disclosed herein, the blocks of the detector 402 including the IVCU searcher 504, the CCL 506, the AABMM definer 508, the final score calculator 510 and the ROI provider 512 use the VRS mask to identify the region of interest (ROI) in the corresponding video image. The CCL 506 is also referred to as the marking circuit device 506, the AABMM definer 508 is also referred to as the delimiting circuit device, and the final score calculator 510 is also referred to as the score calculation circuit device 510.

[0032] As mentioned above, Figure 5 is a block diagram of a detector (e.g., detector 402) for detecting a region of interest in a video image based on a mask generated by a VRS generated by an example renderer 404. Either or both of the renderer 404 and the detector 402 may be instantiated (e.g., created as an instance for any length of time, generated for any length of time, materialized, realized, etc.) by a processor circuit device (such as a central processing unit) executing instructions. Additionally or alternatively, Figure 5 The renderer 404 and / or detector 402 may be instantiated by an ASIC or FPGA configured to perform operations corresponding to the instructions (e.g., create an instance of any length of time, generate, implement, realize, etc. for any length of time). It should be understood that, therefore, Figure 5 Some or all of the circuit devices may be instantiated at the same or different times. For example, some or all of the circuit devices may be instantiated in one or more threads that are executed concurrently on the hardware and / or in series on the hardware. In addition, in some examples, Figure 5 Some or all of the circuitry may be implemented by microprocessor circuitry executing instructions to implement one or more virtual machines and / or containers.

[0033] In some examples, the example VRS mask generator 502 is instantiated by a processor circuit device that executes VRS mask generator instructions and / or is configured to perform operations such as by Fig. 9 In some examples, the example important VRS codec unit (IVCU) searcher circuit device is instantiated by a processor circuit device executing IVCU searcher instructions and / or configured to perform operations such as those represented by the flowchart 900. Fig. 9 In some examples, the example connected component marker CCL 506 is instantiated by a processor circuit device that executes connected component marker instructions and / or is configured to perform operations such as those represented by the flowchart 900 of FIG. Fig. 9The operations are those represented by flowchart 900.

[0034] In some examples, the example axis-aligned minimum bounding box (AAMBB) definer 508 is instantiated by a processor circuit device that executes an AAMBB identifier instruction and / or is configured to perform operations such as by Fig. 9 In some examples, the example final score calculator 510 is instantiated by a processor circuit device that executes final score calculation instructions and / or is configured to perform operations such as those represented by the flowchart 900 of FIG. Fig. 9 In some examples, the example region of interest (ROI) provider 512 is instantiated by a processor circuit device that executes region of interest provider instructions and / or is configured to perform operations such as those represented by the flowchart 900. Fig. 9 The operations are those represented by flowchart 900.

[0035] In some examples, the example IVCU searcher 504 operates on a microblock data grid having a size of 16x16 (e.g., the smallest codec unit often used in video coding standards). The IVCU searcher 504 receives the VRS mask from the example VRS mask generator 502 of the example renderer 404. After receiving the VRS mask, the IVCU searcher 504 divides the VRS mask into a plurality of 16x16 blocks. Each 16x16 block is referred to as a VRS codec unit (VCU) and, due to its size, is aligned with the microblock grid. To further illustrate, the example VCU 600 is in Figure 6 is shown in and is also referenced here Figure 5 As provided by the VRS mask generator 502, each VCU (e.g., Figure 6 The pixels represented in the VCU 600 have been assigned different shading rates, represented by different patterns. Figure 6 As shown, the example first region 602, the example second region 604, the example third region 606, and the example fourth region 608 of the example VCU 600 include shading densities from the most dense (the first region 602) to the least dense (the second region 608). In these examples, Figure 6 The shading density in the pixel indicates the strength of the shading rate. The IVCU searcher 504 applies a weight to each pixel included in the VCU based on the strength of the corresponding shading rate. Table 1 below shows example weights assigned to the first region 602, the second region 604, the third region 606, and the fourth region 608 of the VCU 600 based on the corresponding shading rates, where (a>b>c).

[0036] Coloring Rate 1x1 1x2 2x1 2x2 Weight a b b c

[0037] Table 1

[0038] Reference again Figure 5 , the example IVCU searcher 504 finds the VCU (e.g., Figure 6 The weights of each pixel within the example VCU 600 are summed together. The summed weights "w" are then compared according to the example inequality statement denoted as ENQ.1 (shown below).

[0039] ENQ.1

[0040] w≥256c+λ*256(ac)(0≤λ≤1)

[0041] If the value of "w" satisfies the inequality of example ENQ.1 (where "w" represents the sum of weights and λ is a coefficient), the example VCU 600 currently being processed (see Figure 6 ) will be marked as an important VRS codec unit (IVCU). As shown in ENQ.1, the maximum value of "w" is 256a, and the minimum value of "w" is 256c (a>b>c), so the range of "w" can be described as 256*[c+λ(ac)], where 0<λ<1. If λ=0, ENQ.1 becomes w>=256c, which causes all VCUs to be considered as IVCUs. If λ=1, ENQ.1 becomes w>=256a, which causes only those VCUs consisting of only 1x1 shading rate pixels to be considered as IVCUs. In this way, λ is used as a threshold coefficient to identify whether a VCU is an IVCU.

[0042] Also refer to Figure 7 , Figure 7 is an example VRS mask 700A, which includes four different parts of the VRS mask, each forming / representing one of the VCUs. As described above, by the example renderer 404 (see Figure 4 and Figure 5 ) is divided into VCUs of size 16x16. Assuming that when the VRS mask is divided into VCU results in four VCUs (size 16x16) (e.g., the first VCU 702A, the second VCU 704A, the third VCU 706A, and the fourth VCU 708A), the VRS mask provided to the IVCU searcher is 32x32.

[0043] After identifying the IVCU, the example IVCU searcher 504 shrinks the original VRS 700A to 1 / 16 of its original size, resulting in Figure 7IVCU diagram 700B. Since the first VCU 702A and the second VCU 704A of the VRS mask will have relatively high summation weights (as shown by a larger number of pixels with denser colored pixels), the first VCU 702B and the second VCU 704B of the IVCU diagram 700B are marked with dense coloring to indicate that both VCUs qualify as IVCUs. In contrast, the third VCU 706A and the fourth VCU 708A of the VRS mask 700A will have relatively low summation weights (e.g., as shown by the lack of densely colored pixels). Therefore, the third VCU 706B and the second VCU 708B of the IVCU diagram 700B are marked as uncolored and white to indicate that both the third VCU 706B and the fourth VCU 708B do not qualify as IVCUs. Please note that the coloring density used to distinguish between VCUs and IVCUs is only an example, and any other type of coloring, marking, color and / or any other indicator may be used.

[0044] Still reference Figure 5 , the example CCL 506 is used to map the IVCU generated by the example IVCU searcher 504 (see Figure 7 The IVCU diagram 700B of FIG. 700B is operated to mark the connected components. The connected components are defined as the black and connected (or touching) parts of the IVCU diagram. Figure 8 , example grid 800 illustrates an example output of an IVCU searcher (eg, a collection of IVCU maps arranged together where some areas of the IVCU maps are black and other areas are white).

[0045] In some examples, one or more of the connected components (e.g., black squares) are sorted by size, and small connected areas may be filtered out. In some examples, a "top 32" may be used to filter out small connected components. The connected components are labeled by the example connected component labeler 506 and provided to (or otherwise made available to) the example AAMBB definer 508 ( Figure 5 ). The AAMBB definer 508 designates one or more of the connected components as region of interest (ROI) candidates. Generally speaking, connected components with larger pixel sizes are of greater interest. As an example, and referring to Figure 8, three connected components 802, 804, 806 have been marked as ROI candidates for AAMBB definer 508. AAMBB definer 508 creates a boundary around each of the three connected components. In some examples, the boundary around each set of connected components 802, 804, 806 is designed as an axis-aligned minimum bounding box. Define AAMBB for the connected area using the coordinates of each pixel in a specific connected area (e.g., within a specific area with connected components). Check the pixel coordinates to identify the value of each of Xmin, Xmax, Ymin, and Ymax. Then, determine that the coordinates of the four vertices of AAMBB are (Xmin, Ymin), (Xmax, Ymin), (Xmin, Ymax), and (Xmax, Ymax).

[0046] Still reference Figure 5 , the example final score calculator 510 determines ( Figure 8 Which of the AAMBBs 802, 804, 806 (or any other number of AAMBBs) is most effective. Figure 8 , both the first candidate ROI1 (e.g., the first set of connected components 802) and the second candidate ROI2 (e.g., the second set of connected components 804) contain three IVCUs. However, the second candidate ROI2 (e.g., the second set of connected components) is more "effective" than the first candidate ROI1 (the first set of connected components 802) because the second candidate ROI2 has a smaller AAMBB size and is therefore selected instead of candidate ROI1.

[0047] In some examples, the effectiveness (represented by the coefficient β) of each ROI candidate is measured using an equation (see ENQ.2 below) (where “q” represents the size of the AAMBB and “p” refers to the number of IVCUs contained in the same AAMBB).

[0048] ENQ.2

[0049]

[0050] The example final score calculator 510 then uses ENQ.3 to determine a final score for each ROI candidate.

[0051] ENQ.3

[0052] s=β*p

[0053] In some examples, the example final score calculator 510 identifies the sixteen (or any other number) AAMBBs with the highest scores "s" as ROI candidates to provide to the ROI provider 512 for subsequent use by the encoder. The example encoder 408 uses the ROI to adjust the QP distribution to obtain better image quality in these regions of interest. The encoded information (e.g., the encoded image) is provided to the transmitter for use in transmitting the encoded image to the client device / gaming device 104A-104E ( Figure 1 ) received.

[0054] In some examples, detector 402 (see Figure 4 and Figure 5 ) includes a module for generating a VRS mask. For example, the module for generating a VRS mask can be implemented by the example VRS mask generator 502. In some examples, the VRS mask generator 502 can be implemented by a processor circuit device (e.g., Fig.10 For example, the VRS mask generator 502 may be implemented by executing machine executable instructions (e.g., by Fig. 9 At least those instructions implemented by block 902) Fig.11 In some examples, the VRS mask generator 502 may be instantiated by a hardware logic circuit device, which may be an ASIC, XPU, or other processor configured to perform operations corresponding to machine-readable instructions. Fig.12 1200. Additionally or alternatively, the VRS mask generator 502 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the VRS mask generator 502 may be implemented by at least one or more hardware circuits (e.g., processor circuits, discrete and / or integrated analog and / or digital circuits, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.) that are configured to execute some or all of the machine-readable instructions and / or to execute some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are equally applicable.

[0055] In some examples, detector 402 (see Figure 4 and Figure 5 ) includes a module for searching for important VRS codec units. For example, the module for searching for important VRS codec units can be implemented by the example IVCU searcher 504. In some examples, the IVCU searcher 504 can be implemented by a processor circuit device (e.g. Fig.10 For example, the IVCU searcher 504 may be executed by executing machine executable instructions (e.g., by Fig. 9 at least those instructions implemented by blocks 904, 906, 908, 910, and 912) Fig.11 In some examples, the IVCU searcher 504 may be instantiated by a hardware logic circuit device, which may be an ASIC, XPU, or other processor configured to perform operations corresponding to machine-readable instructions. Fig.12 FPGA circuit device 1200. In addition or alternatively, the IVCU searcher 504 may be instantiated by any other combination of hardware, software and / or firmware. For example, the IVCU searcher 504 may be implemented by at least one or more hardware circuits (e.g., processor circuit devices, discrete and / or integrated analog and / or digital circuit devices, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.) that are constructed to execute some or all of the machine-readable instructions and / or to execute some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are equally applicable.

[0056] In some examples, detector 402 (see Figure 4 and Figure 5 ) includes a module for marking connected components. For example, the module for marking connected components can be implemented by the example CCL 506. In some examples, the CCL 506 can be implemented by a processor circuit device (e.g. Fig.10 For example, CCL 506 may be instantiated by executing machine executable instructions (such as those implemented by at least block 914). Fig.11 In some examples, the CCL 506 may be instantiated by a hardware logic circuit device, which may be an ASIC, XPU, or other processor configured to perform operations corresponding to machine-readable instructions. Fig.12 1200. Additionally or alternatively, CCL 506 may be instantiated by any other combination of hardware, software, and / or firmware. For example, CCL 506 may be implemented by at least one or more hardware circuits (e.g., processor circuits, discrete and / or integrated analog and / or digital circuits, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.) that are configured to execute some or all of the machine-readable instructions and / or to perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are equally applicable.

[0057] In some examples, detector 402 (see Figure 4 and Figure 5 ) includes a module for defining AAMBB. For example, the module for defining AAMBB can be implemented by the example AAMBB definer 508. In some examples, the AAMBB definer 508 can be implemented by a processor circuit device (e.g. Fig.10 For example, the AAMBB definer 508 may be instantiated by executing machine executable instructions (such as those implemented by at least blocks 916 and 918). Fig.11 In some examples, the AAMBB definer 508 may be instantiated by a hardware logic circuit device, which may be an ASIC, XPU, or other processor configured to perform operations corresponding to machine-readable instructions. Fig.12 FPGA circuit device 1200 is implemented. In addition or alternatively, AAMBB definer 508 can be instantiated by any other combination of hardware, software and / or firmware. For example, AAMBB definer 508 can be implemented by at least one or more hardware circuits (e.g., processor circuit devices, discrete and / or integrated analog and / or digital circuit devices, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.), which are constructed to execute some or all of the machine-readable instructions and / or perform some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are equally applicable.

[0058] In some examples, detector 402 (see Figure 4 and Figure 5 ) includes a module for calculating a final score. For example, the module for calculating a final score can be implemented by the example final score calculator 510. In some examples, the final score calculator 510 can be implemented by a processor circuit device (e.g. Fig.10 For example, the final score calculator 510 may be instantiated by executing machine executable instructions (such as those implemented by at least blocks 920 and 922). Fig.11 In some examples, the final score calculator 510 may be instantiated by a hardware logic circuit device, which may be an ASIC, an XPU, or a processor configured to perform operations corresponding to machine-readable instructions. Fig.12The final score calculator 510 may be implemented by any other combination of hardware, software, and / or firmware. In addition or alternatively, the final score calculator 510 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the final score calculator 510 may be implemented by at least one or more hardware circuits (e.g., processor circuits, discrete and / or integrated analog and / or digital circuits, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.) that are configured to execute some or all of the machine-readable instructions and / or to execute some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are equally applicable.

[0059] In some examples, detector 402 (see Figure 4 and Figure 5 ) includes a module for providing a ROI to an encoder. For example, the module for providing a ROI to an encoder can be implemented by an example ROI provider 512. In some examples, the ROI provider 512 can be implemented by a processor circuit device (e.g. Fig.10 For example, the ROI provider 512 may be implemented by executing machine executable instructions (such as those implemented by at least block 924). Fig.11 In some examples, the ROI provider 512 may be instantiated by a hardware logic circuit device, which may be an ASIC, an XPU, or a processor configured to perform operations corresponding to machine-readable instructions. Fig.12 1200. Additionally or alternatively, the ROI provider 512 may be instantiated by any other combination of hardware, software, and / or firmware. For example, the ROI provider 512 may be implemented by at least one or more hardware circuits (e.g., processor circuits, discrete and / or integrated analog and / or digital circuits, FPGAs, ASICs, XPUs, comparators, operational amplifiers (op-amps), logic circuits, etc.) that are configured to execute some or all of the machine-readable instructions and / or to execute some or all of the operations corresponding to the machine-readable instructions without executing software or firmware, but other structures are equally applicable.

[0060] Although Figure 5 The implementation is shown in Figure 4 The example method of the detector 402, however Figure 5One or more of the elements, processes and / or devices shown in the example VRS mask generator 502, the example important VRS codec unit (IVCU) searcher 504, the example connected component marker 506, the example axis-aligned minimum bounding box (AAMBB) definer 508, the example final score calculator 510 and the example region of interest provider 512 and / or more generally, Figure 5 The example detector 402 may be implemented by hardware alone, or by hardware in combination with software and / or firmware. Thus, for example, any of the example VRS mask generator 502, the example important VRS codec unit (IVCU) searcher 504, the example connected component marker 506, the example axis-aligned minimum bounding box (AAMBB) definer 508, the example final score calculator 510, and the example region of interest provider 512, and / or more generally, Figure 5 The example detector may be implemented by a processor circuit device, an analog circuit, a digital circuit, a logic circuit, a programmable processor, a programmable microcontroller, a graphics processing unit (GPU), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a programmable logic device (PLD) and / or a field programmable logic device (FPLD) (such as a field programmable gate array (FPGA)). In addition, Figure 5 An example detector 402 may include Figure 5 In addition to or in lieu of those shown in Figure 5 One or more elements, processes and / or devices of those shown in, and / or may include more than one of any or all of the shown elements, processes or devices.

[0061] Fig. 9 A flowchart representing example machine readable instructions that may be executed to configure a processor circuit device to implement Figure 5 The machine-readable instructions may be one or more executable programs or a portion of an executable program for execution by a processor circuit device, such as the following in conjunction with Fig.10 The processor circuitry 1012 shown in the example processor platform 1000 discussed below and / or in conjunction with Fig.11 and / or Fig.12Example processor circuit devices discussed. The program may be embodied in software stored on one or more non-transitory computer-readable storage media such as a compact disk (CD), a floppy disk, a hard disk drive (HDD), a solid-state drive (SSD), a digital versatile disk (DVD), a Blu-ray disk, a volatile memory (e.g., any type of random access memory (RAM), etc.) or a non-volatile memory associated with a processor circuit device located in one or more hardware devices (e.g., an electrically erasable programmable read-only memory (EEPROM), flash memory, HDD, SSD, etc.), but the entire program and / or portions thereof may alternatively be executed by one or more hardware devices other than the processor circuit device and / or embodied in firmware or dedicated hardware. The machine-readable instructions may be distributed across multiple hardware devices and / or executed by two or more hardware devices (e.g., a server and a client hardware device). For example, a client hardware device may be implemented by an endpoint client hardware device (e.g., a hardware device associated with a user) or an intermediate client hardware device (e.g., a radio access network (RAN)) gateway that may facilitate communication between a server and an endpoint client hardware device. Similarly, non-transitory computer-readable storage media may include one or more media located in one or more hardware devices. Fig. 9 The flowchart shown in describes an example program, but many other methods of implementing the example detector X may be used instead. For example, the order of execution of the blocks may be changed, and / or some of the blocks described may be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks may be implemented by one or more hardware circuits (e.g., processor circuit devices, discrete and / or integrated analog and / or digital circuit devices, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) that are configured to perform corresponding operations without executing software or firmware. The processor circuit devices may be distributed at different network locations and / or located locally in one or more hardware devices (e.g., a single-core processor (e.g., a single-core central processing unit (CPU)), a multi-core processor in a single machine (e.g., a multi-core CPU, an XPU, etc.), multiple processors distributed on multiple servers in a server rack, multiple processors distributed on one or more server racks, a CPU and / or FPGA in the same package (e.g., the same integrated circuit (IC) package or in two or more separate housings, etc.).

[0062] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a segmented format, a compiled format, an executable format, a packaged format, etc. The machine-readable instructions as described herein may be stored as data or data structures (e.g., as part of instructions, codes, representations of codes, etc.) that may be used to create, manufacture, and / or generate machine-executable instructions. For example, the machine-readable instructions may be segmented and stored on one or more storage devices and / or computing devices (e.g., servers) located at the same or different locations of a network or a collection of networks (e.g., in the cloud, in edge devices, etc.). The machine-readable instructions may require one or more of installation, modification, adaptation, update, combination, supplementation, configuration, decryption, decompression, unpacking, distribution, redistribution, compilation, etc., so that they are directly readable, interpretable, and / or executable by a computing device and / or other machines. For example, the machine-readable instructions may be stored in multiple parts that are individually compressed, encrypted, and / or stored on separate computing devices, where the parts, when decrypted, decompressed, and / or combined, form a collection of machine-executable instructions that implement one or more operations that may together form a program such as described herein.

[0063] In another example, the machine-readable instructions may be stored in a state where the processor circuitry can read them, but a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., may need to be added in order to execute the machine-readable instructions on a particular computing device or other device. In another example, the machine-readable instructions and / or corresponding programs may need to be configured (e.g., stored settings, data inputs, recorded network addresses, etc.) before they can be executed in whole or in part. Therefore, as used herein, a machine-readable medium may include machine-readable instructions and / or programs regardless of the particular format or state of the machine-readable instructions and / or programs when stored or otherwise at rest or in transmission.

[0064] The machine-readable instructions described herein may be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions may be represented by any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0065] As mentioned above, Fig. 9The example operations of may be implemented using executable instructions (e.g., computer and / or machine readable instructions) stored on one or more non-transitory computer and / or machine readable media (such as optical storage devices, magnetic storage devices, HDDs, flash memory, read-only memory (ROM), CDs, DVDs, caches, any type of RAM, registers) and / or any other storage device or storage disk in which information is stored for any duration (e.g., extended period of time, permanently, transiently, temporarily buffered and / or cached information). As used herein, the terms non-transitory computer readable medium, non-transitory computer readable storage medium, non-transitory machine readable medium, and non-transitory machine readable storage medium are expressly defined to include any type of computer readable storage device and / or storage disk, and to exclude propagating signals and to exclude transmission media. As used herein, the terms "computer readable storage device" and "machine readable storage device" are defined to include any physical (mechanical and / or electrical) structure for storing information, but to exclude propagating signals and to exclude transmission media. Examples of computer-readable storage devices and machine-readable storage devices include any type of random access memory, any type of read-only memory, solid-state memory, flash memory, optical disks, magnetic disks, disk drives, and / or redundant arrays of independent disks (RAID) systems. As used herein, the term "device" refers to a physical structure, such as a mechanical and / or electrical device, hardware, and / or circuitry, that may or may not be configured by computer-readable instructions, machine-readable instructions, etc., and / or is manufactured to execute computer-readable instructions, machine-readable instructions, etc.

[0066] "Including" and "comprising" (and all forms and tenses thereof) are used herein as open-ended terms. Thus, whenever a claim employs any form of "include" or "comprise" (e.g., comprises, includes, comprising, including, having, etc.) as a preamble or within any type of claim recitation, it should be understood that additional elements, terms, etc. may be present without exceeding the scope of the corresponding claim or recitation. As used herein, when the phrase "at least" is used as a transitional term, such as in the preamble of a claim, it is open-ended, just as the terms "comprising" and "including" are open-ended. For example, when used in a form such as A, B, and / or C, the term "and / or" refers to any combination or subset of A, B, and C, such as (1) only A, (2) only B, (3) only C, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C. As used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A and B" is intended to refer to implementations that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A or B" is intended to refer to implementations that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the performance or execution of processes, instructions, actions, activities, and / or steps, the phrase "at least one of A and B" is intended to refer to implementations that include any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the performance or execution of a process, instruction, action, activity, and / or step, the phrase "at least one of A or B" is intended to refer to an implementation that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0067] As used herein, singular references (e.g., "a", "an", "first", "second", etc.) do not exclude a plurality. As used herein, the term "a" or "an" object refers to one or more of the object. The terms "a" (or "an"), "one or more" and "at least one" are used interchangeably herein. In addition, although listed separately, multiple units, elements or method actions may be implemented by, for example, the same entity or object. In addition, although individual features may be included in different examples or claims, these features may be combined, and inclusion in different examples or claims does not mean that the combination of features is not feasible and / or disadvantageous.

[0068] Fig. 9 is a flow diagram representative of example machine-readable instructions and / or example operations 900 that may be executed and / or instantiated by processor circuitry to detect regions of interest in video images using VRS-generated masks. Fig. 9 The machine readable instructions and / or operations 900 of the present invention begin at block 902, where the example renderer 404 ( Figure 4 ) Example VRS Mask Generator 502 ( Figure 5 ) generates a VRS mask based on the video image, and provides the VRS mask to the example detector 402 ( Figure 4 ) of an example IVCU searcher 504 ( Figure 5 ). At block 904, the IVCU searcher 504 divides the VRS mask into a plurality of 16x16 blocks (referred to as VCUs). At block 906, the IVCU searcher 504 assigns a weight to each pixel included in each VCU based on the pixel's corresponding shading rate, as described above with respect to Figure 5 At block 908, the IVCU searcher 504 finds the example VCU 600 (see Figure 6 ) are added together. The IVCU searcher 504 then compares the summed weights "w" (as shown below) using the example inequality statement denoted as ENQ.1 (see block 910).

[0069] ENQ.1

[0070] w≥256c+λ*256(ac)(0≤λ≤1)

[0071] Based on whether the sum (e.g., w) satisfies the inequality, the corresponding VCU is identified as an IVCU (see block 912). If the inequality expressed in ENQ.1 is not satisfied, the IVCU searcher 504 may ignore the corresponding VCU. At block 914, the IVCU is used to identify the corresponding VCU as described above with reference to Figure 5 IVCU maps were generated as described.

[0072] Still reference Fig. 9 , Example CCL 506( Figure 5 ) marks the connected components included on the IVCU map (see block 916). At block 918, the marked connected components are provided (or otherwise made available) to the example AAMBB definer 508 ( Figure 5 ), the example AAMBB definer 508 designates one or more of the connected components as region of interest (ROI) candidates, as described above with reference to Figure 5 described.

[0073] At block 920, the example final score calculator 510 determines AAMBB (see, e.g., Figure 8 ) are most effective. In some examples, and as described above, determining the effectiveness of each of the ROI candidates (represented by coefficient β) includes applying ENQ.2, as described above with reference to Figure 5 described.

[0074] ENQ.2

[0075]

[0076] At block 922 , the example final score calculator 510 determines a final score for each ROI candidate using ENQ.3.

[0077] ENQ.3

[0078] s=β*p

[0079] Based on the result of the final score equation (ENQ.3), the final score calculator 510 identifies the sixteen (or any other number) AAMBBs with the highest scores "s" as ROIs to be provided to the ROI provider 512 (block 924). The ROI provider 512 then provides the ROIs to the encoder (see box 924). Thereafter, the flowchart 900 ends. In some examples, when the next VRS map is received for the next video image, the detector 402 operates to repeat Fig. 9 In some examples, following flowchart 900, the example encoder 408 encodes the ROI before sending the encoded information to a transmitter for reception at a client device / gaming device (see Figure 1 ).

[0080] Fig.10 is a block diagram of an example processor platform 1000 that is configured to execute and / or instantiate Fig. 9 Machine-readable instructions and / or operations to implement Figure 4 and Figure 5The processor platform 1000 may be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cell phone, a smartphone, an iPad, etc.). TM tablet computer), personal digital assistant (PDA), internet appliance, DVD player, CD player, digital video recorder, Blu-ray player, game console, personal video recorder, set-top box, headsets (e.g., augmented reality (AR) headsets, virtual reality (VR) headsets, etc.) or other wearable device, or any other type of computing device.

[0081] The processor platform 1000 of the illustrated example includes a processor circuit device 1012. The processor circuit device 1012 of the illustrated example is hardware. For example, the processor circuit device 1012 can be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs and / or microcontrollers from any desired series or manufacturer. The processor circuit device 1012 can be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the processor circuit device 1012 implements the example VRS mask generator 502, the example IVCU searcher 504, the example CCL 506, the example AAMBB definer 508, the example final score calculator 510 and the example region of interest provider 512.

[0082] The processor circuit device 1012 of the illustrated example includes a local memory 1013 (e.g., cache, registers, etc.). The processor circuit device 1012 of the illustrated example communicates with a main memory including a volatile memory 1014 and a non-volatile memory 1016 via a bus 1018. The volatile memory 1014 may be composed of a synchronous dynamic random access memory (SDRAM), a dynamic random access memory (DRAM), Dynamic Random Access Memory The non-volatile memory 1016 may be implemented by flash memory and / or any other desired type of memory device. Access to the main memory 1014, 1016 of the illustrated example is controlled by a memory controller 1017.

[0083] The processor platform 1000 of the illustrated example also includes an interface circuit device 1020. The interface circuit device 1020 may be implemented by hardware that complies with any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, interface, a near field communication (NFC) interface, a peripheral component interconnect (PCI) interface, and / or a peripheral component interconnect express (PCIe) interface.

[0084] In the example shown, one or more input devices 1022 are connected to the interface circuitry 1020. The input devices 1022 allow a user to input data and / or commands into the processor circuitry 1012. The input devices 1022 may be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, buttons, a mouse, a touch screen, a trackpad, a trackball, an isochronous device, and / or a speech recognition system.

[0085] One or more output devices 1024 are also connected to the interface circuit device 1020 of the illustrated example. The output device 1024 can be implemented, for example, by a display device (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-place switching (IPS) display, a touch screen, etc.), a tactile output device, a printer, and / or a speaker. Therefore, the interface circuit device 1020 of the illustrated example typically includes a graphics driver card, a graphics driver chip, and / or a graphics processor circuit device, such as a GPU.

[0086] The interface circuitry 1020 of the illustrated example also includes communication devices, such as transmitters, receivers, transceivers, modems, residential gateways, wireless access points, and / or network interfaces to facilitate the exchange of data with external machines (e.g., any type of computing device) over the network 1026. The communication may be, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a field wireless system, a cellular telephone system, an optical connection, etc.

[0087] The processor platform 1000 of the illustrated example also includes one or more mass storage devices 1028 for storing software and / or data. Examples of such mass storage devices 1028 include magnetic storage devices, optical storage devices, floppy disk drives, HDDs, CDs, Blu-ray disk drives, redundant arrays of independent disks (RAID) systems, solid-state storage devices such as flash memory devices and / or SSDs, and DVD drives.

[0088] Can be Fig. 9 The machine-readable instructions 1032 implemented by the machine-readable instructions may be stored in the mass storage device 1028, in the volatile memory 1014, in the non-volatile memory 1016, and / or on a removable, non-transitory computer-readable storage medium (such as a CD or DVD).

[0089] Fig.11 yes Fig.10 1012. In this example, Fig.10The processor circuit device 1012 is implemented by the microprocessor 1100. For example, the microprocessor 1100 may be a general-purpose microprocessor (eg, a general-purpose microprocessor circuit device). The microprocessor 1100 executes Fig. 9 Some or all of the machine readable instructions of a flowchart to effectively Figure 5 The circuit device is instantiated as a logic circuit to perform operations corresponding to these machine-readable instructions. In some such examples, Figure 5 The circuit device is instantiated by the hardware circuit of the microprocessor 1100 in combination with instructions. For example, the microprocessor 1100 can be implemented by a multi-core hardware circuit device such as a CPU, DSP, GPU, XPU, etc. Although it can include any number of example cores 1102 (for example, 1 core), the microprocessor 1100 of this example is a multi-core semiconductor device including N cores. The cores 1102 of the microprocessor 1100 can operate independently, or can cooperate to execute machine-readable instructions. For example, the machine code corresponding to a firmware program, an embedded software program, or a software program can be executed by one of the cores in the core 1102, or can be executed by multiple cores in the core 1102 at the same or different times. In some examples, the machine code corresponding to the firmware program, the embedded software program, or the software program is split into threads and executed in parallel by two or more cores in the core 1102. The software program may correspond to a program executed by Fig. 9 A flowchart may represent a portion or all of machine-readable instructions and / or operations.

[0090] The cores 1102 can communicate via a first example bus 1104. In some examples, the first bus 1104 can be implemented via a communication bus to enable communications associated with one or more of the cores 1102. For example, the first bus 1104 can be implemented via at least one of an inter-integrated circuit (I2C) bus, a serial peripheral interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the first bus 1104 can be implemented via any other type of computing or electrical bus. The cores 1102 can obtain data, instructions, and / or signals from one or more external devices via an example interface circuit device 1106. The cores 1102 can output data, instructions, and / or signals to one or more external devices via the interface circuit device 1106. Although the core 1102 of this example includes an example local memory 1120 (e.g., a level 1 (L1) cache that can be divided into an L1 data cache and an L1 instruction cache), the microprocessor 1100 also includes an example shared memory 1110 that can be shared by the cores (e.g., a level 2 (L2 cache)) for high-speed access to data and / or instructions. Data and / or instructions can be transferred (e.g., shared) by writing to and / or reading from the shared memory 1110. The local memory 1120 and the shared memory 1110 of each core in the core 1102 can be a plurality of levels of cache memory and main memory (e.g., Fig.10 Part of a hierarchy of storage devices (main memory 1014, 1016) of the cache. Typically, memory at higher levels in the hierarchy exhibits lower access times and has smaller storage capacity than memory at lower levels. Changes to the various levels of the cache hierarchy are managed (e.g., coordinated) by a cache coherence policy.

[0091] Each core 1102 may be referred to as a CPU, DSP, GPU, etc., or any other type of hardware circuit device. Each core 1102 includes a control unit circuit device 1114, an arithmetic and logic (AL) circuit device (sometimes referred to as an ALU) 1116, a plurality of registers 1118, a local memory 1120, and a second example bus 1122. Other structures may exist. For example, each core 1102 may include a vector unit circuit device, a single instruction multiple data (SIMD) unit circuit device, a load / store unit (LSU) circuit device, a branch / jump unit circuit device, a floating point unit (FPU) circuit device, etc. The control unit circuit device 1114 includes a semiconductor-based circuit that is configured to control (e.g., coordinate) data movement within the corresponding core 1102. The AL circuit device 1116 includes a semiconductor-based circuit that is configured to perform one or more mathematical and / or logical operations on data within the corresponding core 1102. The AL circuit device 1116 of some examples performs integer-based operations. In other examples, the AL circuit device 1116 also performs floating-point operations. In other examples, AL circuitry 1116 may include a first AL circuitry that performs integer-based operations and a second AL circuitry that performs floating-point operations. In some examples, AL circuitry 1116 may be referred to as an arithmetic logic unit (ALU). Registers 1118 are semiconductor-based structures for storing data and / or instructions (such as the results of one or more operations performed by AL circuitry 1116 of a corresponding core 1102). For example, registers 1118 may include vector registers, SIMD registers, general registers, flag registers, segment registers, machine-specific registers, instruction pointer registers, control registers, debug registers, memory management registers, machine check registers, etc. Registers 1118 may be, for example, vector registers, SIMD registers, general registers, flag registers, segment registers, machine-specific registers, instruction pointer registers, control registers, debug registers, memory management registers, machine check registers, etc. Fig.11 The registers 1118 may be arranged in a memory bank as shown. Alternatively, the registers 1118 may be organized in any other arrangement, format, or structure, including being distributed throughout the core 1102 to reduce access time. The second bus 1122 may be implemented by at least one of an I2C bus, an SPI bus, a PCI bus, or a PCIe bus.

[0092] Each core 1102 and / or more generally, the microprocessor 1100 may include additional and / or alternative structures in addition to the structures shown and described above. For example, there may be one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHA), one or more aggregation / common grid stops (CMS), one or more shifters (e.g., barrel shifters) and / or other circuit devices. The microprocessor 1100 is a semiconductor device that is manufactured to include many transistors that are interconnected to implement the structure described above in one or more integrated circuits (ICs) contained in one or more packages. The processor circuit device may include one or more accelerators and / or collaborate with one or more accelerators. In some examples, the accelerator is implemented by a logic circuit device to perform certain tasks faster and / or more efficiently than a general-purpose processor. Examples of accelerators include ASICs and FPGAs, such as those discussed herein. A GPU or other programmable device may also be an accelerator. The accelerator may be on a processor circuit device board, in the same chip package as the processor circuit device, and / or in one or more packages separated from the processor circuit device.

[0093] Fig.12 yes Fig.10 1012 is a block diagram of another example implementation of a processor circuit device 1012. In this example, the processor circuit device 1012 is implemented by an FPGA circuit device 1200. For example, the FPGA circuit device 1200 can be implemented by an FPGA. The FPGA circuit device 1200 can be used, for example, to perform operations that can be performed by a processor that executes corresponding machine-readable instructions. Fig.11 However, once configured, the FPGA circuit device 1200 instantiates the machine-readable instructions in hardware and, therefore, can generally perform operations faster than a general-purpose microprocessor executing corresponding software.

[0094] More specifically, as described above Fig.11 The microprocessor 1100 (which can be programmed to execute Fig. 9 Compared to a general-purpose device that contains some or all of the machine-readable instructions represented by a flowchart, but whose interconnections and logic circuitry are fixed after manufacture, Fig.12 The example FPGA circuit device 1200 includes interconnect and logic circuit devices, which can be configured and / or interconnected in different ways after manufacturing to instantiate, for example, Fig. 9In particular, FPGA circuit device 1200 can be considered to be an array of logic gates, interconnects, and switches. The switches can be programmed to change how the logic gates are interconnected by the interconnects, effectively forming one or more dedicated logic circuits (unless or until FPGA circuit device 1200 is reprogrammed). The configured logic circuits enable the logic gates to cooperate in different ways to perform different operations on data received by the input circuit device. These operations can correspond to the operations performed by Fig. 9 Thus, FPGA circuit device 1200 can be constructed to convert Fig. 9 Some or all of the machine-readable instructions of the flowchart are effectively instantiated as dedicated logic circuits that perform operations corresponding to these software instructions in a dedicated manner similar to an ASIC. Therefore, the FPGA circuit device 1200 can execute operations corresponding to these software instructions faster than a general-purpose microprocessor. Fig. 9 Operations corresponding to some or all of the machine-readable instructions.

[0095] exist Fig.12 In the example of FPGA circuit device 1200, FPGA circuit device 1200 is configured to be programmed (and / or reprogrammed one or more times) by an end user via a hardware description language (HDL) such as Verilog. Fig.12 FPGA circuit device 1200 includes example input / output (I / O) circuit device 1202, which is used to obtain and / or output data to / from example configuration circuit device 1204 and / or external hardware 1206. For example, configuration circuit device 1204 can be implemented by an interface circuit device, which can obtain machine-readable instructions to configure FPGA circuit device 1200 or a portion thereof. In some such examples, configuration circuit device 1204 can obtain machine-readable instructions from a user, a machine (e.g., a hardware circuit device (e.g., a programming or dedicated circuit device) that can implement an artificial intelligence / machine learning (AI / ML) model to generate instructions), etc. In some examples, external hardware 1206 can be implemented by an external hardware circuit device. For example, external hardware 1206 can be implemented by Fig.11 1100. The FPGA circuit device 1200 also includes an array of example logic gate circuit devices 1208, a plurality of example configurable interconnects 1210, and an example storage circuit device 1212. The logic gate circuit devices 1208 and the configurable interconnects 1210 can be configured to instantiate Fig. 9 One or more operations of at least some of the machine-readable instructions and / or other desired operations. Fig.12The logic gate circuit device 1208 shown in is manufactured in the form of groups or blocks. Each block includes a semiconductor-based electrical structure that can be configured as a logic circuit. In some examples, the electrical structure includes a logic gate (e.g., an AND gate, an OR gate, a NOR gate, etc.) that provides a basic building block for the logic circuit. An electrically controlled switch (e.g., a transistor) is present in each logic gate circuit device 1208 to implement the configuration of the electrical structure and / or logic gate to form a circuit that performs the desired operation. The logic gate circuit device 1208 may include other electrical structures, such as a lookup table (LUT), a register (e.g., a flip-flop or a latch), a multiplexer, etc.

[0096] The configurable interconnect 1210 of the illustrated example is a conductive path, trace, via, etc., which may include an electrically controlled switch (e.g., a transistor) whose state can be changed by programming (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more logic gate circuit devices 1208 to program the desired logic circuit.

[0097] The storage circuit device 1212 of the illustrated example is configured to store the results of one or more operations performed by the corresponding logic gates. The storage circuit device 1212 can be implemented by registers, etc. In the illustrated example, the storage circuit device 1212 is distributed between the logic gate circuit devices 1208 to facilitate access and increase execution speed.

[0098] Fig.12 The example FPGA circuit device 1200 also includes an example dedicated operation circuit device 1214. In this example, the dedicated operation circuit device 1214 includes a dedicated circuit device 1216, which can be called to implement common functions to avoid the need to program these functions in the field. Examples of such dedicated circuit devices 1216 include memory (e.g., DRAM) controller circuit devices, PCIe controller circuit devices, clock circuit devices, transceiver circuit devices, memory, and multiplier accumulator circuit devices. Other types of dedicated circuit devices may exist. In some examples, the FPGA circuit device 1200 may also include an example general-purpose programmable circuit device 1218, such as an example CPU 1220 and / or an example DSP 1222. Other general-purpose programmable circuit devices 1218 may exist in addition or alternatively, such as GPUs, XPUs, etc., which can be programmed to perform other operations.

[0099] although Fig.11 and Fig.12 Shows Fig.10 These are two example implementations of the processor circuit device 1012, but many other approaches are contemplated. For example, as described above, a modern FPGA circuit device may include an onboard CPU, such as Fig.12One or more of the example CPUs 1220. Thus, Fig.10 The processor circuit device 1012 may additionally be combined by Figure 1 An example microprocessor 1100 and Fig.12 In some such hybrid examples, the Fig. 9 The first portion of the machine-readable instructions represented by the flowchart may be represented by Fig.11 1102, executed by one or more of the cores 1102 Fig. 9 The second portion of the machine-readable instructions represented by the flowchart may be represented by Fig.12 The FPGA circuit device 1200 is executed, and / or by Fig. 9 The third portion of the machine-readable instructions represented by the flowchart may be executed by the ASIC. It should be understood that, therefore, Figure 5 Some or all of the circuit devices may be instantiated at the same or different times. For example, some or all of the circuit devices may be instantiated in one or more threads that are executed concurrently and / or serially. In addition, in some examples, Figure 5 Some or all of the circuitry of may be implemented within one or more virtual machines and / or containers executing on the microprocessor.

[0100] In some examples, Fig.10 The processor circuit device 1012 can be in one or more packages. For example, Fig.11 The microprocessor 1100 and / or Fig.12 The FPGA circuit device 1200 can be in one or more packages. In some examples, the XPU can be composed of Fig.10 The XPU may be implemented by a processor circuit device 1012, which may be in one or more packages. For example, the XPU may include a CPU in one package, a DSP in another package, a GPU in yet another package, and an FPGA in yet another package.

[0101] As can be appreciated from the foregoing, example systems, methods, apparatus, and articles of manufacture have been disclosed for improving the processing of video images by reducing the number of image pixels that need to be encoded. The disclosed systems, methods, apparatus, and articles of manufacture improve the efficiency of using a computing device by reducing the amount of processing power used by the computing device and reducing the complexity and speed at which the computing device can process images for encoding. Thus, the disclosed systems, methods, apparatus, and articles of manufacture relate to one or more improvements in the operation of a machine such as a computer or other electronic and / or mechanical device.

[0102] Disclosed herein are example methods, apparatus, systems, and articles of manufacture for detecting regions of interest in video images based on a variable rate shading mask generated by a renderer. Disclosed herein are example methods, apparatus, systems, and articles of manufacture for detecting regions of interest in video images based on a variable rate shading mask generated by a renderer. Further examples and combinations thereof include the following: Example 1 includes an apparatus for identifying regions of interest in an image, the apparatus comprising an interface circuit device for receiving a video image and a processor circuit device, the processor circuit device comprising one or more of the following: at least one of a central processing unit, a graphics processing unit, or a digital signal processor, the at least one of the central processing unit, the graphics processing unit, or the digital signal processor having a control circuit device for controlling data movement within the processor circuit device, an arithmetic and logic circuit device for performing one or more first operations corresponding to instructions, and one or more registers for storing results of the one or more first operations, instructions in the device; a field programmable gate array (FPGA), the FPGA comprising a logic gate circuit device, a plurality of configurable interconnects and storage circuits device, a logic gate circuit device and a plurality of configurable interconnections for performing one or more second operations, a storage circuit device for storing results of the one or more second operations; or an application-specific integrated circuit device (ASIC), the ASIC including a logic gate circuit device for performing one or more third operations, a processor circuit device for performing at least one of the first operation, the second operation or the third operation to instantiate: a detector circuit device, which is configured to: be coupled to a renderer circuit device, receive a variable rate shading (VRS) mask based on a video image from the renderer circuit device, and detect a region of interest of the video image based on the VRS mask; and an encoder circuit device for encoding the region of interest of the video image, the encoder circuit device being used to adjust a quantization parameter to encode the region of interest, the quantization parameter being based on the region of interest.

[0103] Example 2 includes the apparatus of Example 1, wherein the detector circuitry includes a searcher circuitry to search the VRS mask to identify partitions in the VRS mask having weights that satisfy a threshold.

[0104] Example 3 includes the apparatus of Example 2, wherein the detector circuit apparatus includes: a marking circuit apparatus for identifying and marking connected components in a VRS mask associated with partitions of the VRS mask having weights that satisfy a threshold; a delimiting circuit apparatus for determining a boundary around each set of marked connected components, thereby producing delimited components; and a score calculation circuit apparatus for determining corresponding scores of corresponding delimited components for the delimited components, and identifying selected delimited components of the delimited components as regions of interest, the selected delimited components of the delimited components being selected based on the corresponding scores of the corresponding delimited components.

[0105] Example 4 includes the apparatus of Example 2, wherein the searcher circuit apparatus is used to i) create partitions of the VRS mask, the partitions comprising pixels, ii) assign corresponding weights to corresponding pixels in the pixels based on a variable shading rate of the pixels, iii) determine corresponding sums of the weights of the pixels in corresponding partitions in the partitions of the VRS mask, and iv) identify the corresponding partition as an important partition when any one of the corresponding sums in the sums satisfies a threshold.

[0106] Example 5 includes a device for detecting a region of interest in a video image, the device comprising at least one memory, machine-readable instructions, and a processor circuit device, the processor circuit device being used to instantiate or execute at least one of the machine-readable instructions to detect a region of interest in the video image based on a variable rate shading (VRS) mask of the video image, the VRS mask being generated by a renderer and encoding the region of interest in the video image.

[0107] Example 6 includes the apparatus of Example 5, wherein the processor circuit means for detecting the region of interest is to search a VRS mask of the video image to identify partitions in the VRS mask having a total weight that satisfies a threshold.

[0108] Example 7 includes the apparatus of Example 6, wherein, to search for a VRS mask, the processing circuit apparatus is used to divide the VRS mask into partitions, the partitions of the VRS mask having pixels, weights are assigned to the pixels based on corresponding variable rate shading provided in the VRS mask, the weights of the pixels of each partition of the VRS mask are summed to determine a total weight for each partition, and when any one of the total weights satisfies a threshold, the partition corresponding to the total weight is identified as an important partition.

[0109] Example 8 includes the apparatus of Example 5, wherein, when it is determined that one or more of the partitions of the VRS mask include potential regions of interest, in order to detect the regions of interest, the processor circuit device is used to determine that the one or more partitions of the VRS mask include potential regions of interest, reduce the size of the entire VRS mask to create a map, mark components in the map that have strong shading rates and are connected to each other, generate boundaries around each of the marked components, and identify any of the marked components and the components around which boundaries have been generated as candidate regions of interest.

[0110] Example 9 includes the apparatus of Example 8, wherein, to detect a region of interest, the processor circuit apparatus is operable to determine a significance value for each of a plurality of components that have been marked and delimited, select a marked and delimited subset of the plurality of components based on the significance value, generate a score for the marked and delimited subset of the plurality of components, select a number of the marked and delimited subset of the plurality of components based on the score, and provide the number of the marked and delimited subsets of the plurality of components as the region of interest to an encoder.

[0111] Example 10 includes the apparatus of Example 5, wherein, to detect regions of interest, the processor circuit apparatus is for determining that a partition of the VRS mask has one or more regions of interest based on a determination that the partition of the VRS mask has one or more regions of interest, reducing a size of the VRS mask, identifying one or more pixel groups associated with strongly variable shading rates and in contact with each other included in the partition of the VRS mask, selecting a subset of one or more of the pixel groups based on a significance value associated with each group of pixels in the pixel groups, calculating a score for each of the one or more pixel groups in the subset, and selecting one or more of the regions of interest to be identified from the subset for use by the encoder.

[0112] Example 11 includes a non-transitory machine-readable storage medium comprising instructions that, when executed, cause a processor circuit device to detect a region of interest of a video image based at least on a variable rate shading (VRS) mask of the video image, the VRS mask of the video image being created by a renderer using variable rate shading (VRS), and encode the region of interest of the video image, wherein a quantization parameter is adjusted to a setting suitable for encoding the region of interest.

[0113] Example 12 includes the non-transitory machine-readable storage medium of Example 11, comprising instructions that, when executed, cause a processor circuit device to search a VRS mask of a video image to identify partitions in the VRS mask having weights that satisfy a threshold.

[0114] Example 13 includes the non-transitory machine-readable storage medium of Example 11, wherein, to search for a VRS mask, the instructions, when executed, cause the processor circuit device to divide the VRS mask of the video image into partitions, the partitions including pixels, assigning corresponding weights to corresponding pixels of the pixels based on variable shading rates of the corresponding pixels, determining, for each of the partitions, a sum of the weights of the pixels included in the partition to obtain a total weight for each of the partitions, and when the total weight of any partition in the partitions satisfies a threshold, identifying the corresponding partition of the VRS mask as an important partition.

[0115] Example 14 includes the transitory machine-readable storage medium of Example 13, comprising instructions that, when executed, cause a processor circuit device to identify and mark sets of connected components included in a significant partition of a VRS mask, determine a boundary around each set of marked connected components to produce sets of marked, delimited components, determine a validity score for a first subset of the sets of marked, delimited components, form a second subset of the first subset of marked, delimited components based on the validity scores, determine a final score for each set in the sets of marked, delimited components in the second subset, select one or more sets in the sets of marked, delimited components in the second subset based on the final scores to form a third subset of marked, delimited components, and identify the third subset of marked, delimited components as a region of interest for an encoder.

[0116] Example 15 includes the transitory machine-readable storage medium of Example 11, wherein, to detect a region of interest, the instructions, when executed, cause a processor circuit device to determine, based on the determination, that a VRS mask includes a potential region of interest, reduce the size of the VRS mask to create a graph, mark components in the graph that have a strong shading rate and are connected to each other, generate boundaries around the marked components, and identify the delimited, marked components as candidate regions of interest.

[0117] Example 16 includes a method for encoding a region of interest of a video image based on a variable rate shading (VRS) mask, the method comprising detecting the region of interest of the video image based on the VRS mask using one or more processors, the VRS mask being generated by a renderer, and encoding the region of interest of the video image using one or more processors, the encoding comprising adjusting a quantization parameter suitable for encoding the region of interest.

[0118] Example 17 includes the method of Example 16, wherein detecting the region of interest comprises searching a VRS mask of the video image to identify regions in the VRS mask having weights that satisfy a threshold.

[0119] Example 18 includes the method of Example 17, wherein searching for the VRS mask includes dividing the VRS mask of the video image into sub-components, the sub-components including pixels, assigning corresponding weights to corresponding pixels in the pixels based on a variable shading rate of the pixels identified in the VRS mask, determining a sum of the weights for each sub-component to identify a total weight, and identifying the VRS mask of the video image as a region of interest candidate when the total weight of any of the sub-components satisfies a threshold.

[0120] Example 19 includes the method of Example 16, wherein detecting the region of interest includes marking connected portions in the VRS mask that have been identified as having high intensity shading rates and that are in contact with each other, determining boundaries around each set of marked connected components to produce marked, delimited components, determining a validity score for a first subset of the marked, delimited components, forming a second subset of the first subset of the marked, delimited components based on the validity scores, determining a final score for each of the marked, delimited components in the second subset, selecting one or more of the marked, delimited components in the second subset based on the final scores to form a third subset of the marked, delimited components, and identifying the third subset of the marked, delimited components as the region of interest.

[0121] Example 20 includes the method of Example 16, wherein detecting the region of interest includes reducing the size of the VRS mask to create a map, marking components in the VRS map that have strong shading rates and are connected to each other, generating boundaries around the marked components, and identifying the demarcated marked components as candidate regions of interest.

[0122] The following claims are incorporated by reference into the detailed description. Although certain example systems, methods, devices, and articles have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, methods, devices, and articles that fully fall within the scope of the claims of this patent.

Claims

1. A device for identifying a region of interest of an image, comprising: An interface circuit device, the interface circuit device is used to receive a video image; as well as A processor circuit arrangement comprising one or more of the following: at least one of a central processor unit, a graphics processor unit, or a digital signal processor, the at least one of the central processor unit, the graphics processor unit, or the digital signal processor having: control circuitry for controlling movement of data within the processor circuitry; arithmetic and logic circuitry for performing one or more first operations corresponding to the instruction; and one or more registers for storing results of said one or more first operations, said instructions in said apparatus; a field programmable gate array (FPGA), the FPGA comprising logic gate circuitry, a plurality of configurable interconnects, and storage circuitry, the logic gate circuitry and the plurality of configurable interconnects being used to perform one or more second operations, the storage circuitry being used to store results of the one or more second operations; or an application specific integrated circuit (ASIC), the ASIC comprising logic gate circuit means for performing one or more third operations; The processor circuit device is configured to perform at least one of the first operation, the second operation, or the third operation to instantiate: a detector circuit device configured to: couple to the renderer circuit device, receive from the renderer circuit device a variable rate shading (VRS) mask based on a video image, and detect a region of interest of the video image based on the VRS mask; as well as An encoder circuit arrangement is provided for encoding the region of interest of the video image, the encoder circuit arrangement being configured to adjust a quantization parameter to encode the region of interest, the quantization parameter being based on the region of interest.

2. The device according to claim 1, wherein: The detector circuitry includes searcher circuitry for searching the VRS mask to identify partitions in the VRS mask having weights that satisfy a threshold.

3. The device according to claim 2, wherein: The detector circuit arrangement comprises: marking circuitry for identifying and marking connected components of the VRS mask associated with the partitions of the VRS mask having the weights that satisfy the threshold; delimiting circuitry for determining a boundary around each set of labeled connected components, thereby producing delimited components; and A score calculation circuit device is used to determine the corresponding score of the corresponding delimited components of the delimited components, and identify the selected delimited components of the delimited components as the region of interest, and the selected delimited components of the delimited components are selected based on the corresponding scores of the corresponding delimited components.

4. The device according to claim 2, wherein: The searcher circuit device is used to i) create partitions of the VRS mask, the partitions including pixels, ii) assign corresponding weights to corresponding pixels in the pixels based on the variable shading rate of the pixels, iii) determine corresponding sums of the weights of the pixels in the corresponding partitions in the partitions of the VRS mask, and iv) when any of the corresponding sums in the sums satisfies the threshold, identify the corresponding partition as an important partition.

5. A device for detecting a region of interest of a video image, comprising: at least one memory; machine-readable instructions; as well as processor circuitry for at least one of instantiating or executing the machine-readable instructions for: detecting the region of interest of the video image based on a variable rate shading (VRS) mask of the video image, the VRS mask being generated by a renderer; and The region of interest of the video image is encoded.

6. The device according to claim 5, wherein: The processor circuitry for detecting the region of interest is configured to search the VRS mask of the video image to identify partitions in the VRS mask having a total weight that satisfies a threshold.

7. The device according to claim 6, wherein: To search the VRS mask, the processing circuit means is configured to: dividing the VRS mask into the partitions, the partitions of the VRS mask having pixels; assigning weights to the pixels based on corresponding variable rate shading provided in the VRS mask; summing the weights of the pixels of each partition of the VRS mask to determine a total weight for each partition; as well as When any one of the total weights satisfies the threshold, the partition corresponding to the total weight is identified as an important partition.

8. The device according to claim 5, wherein: In order to detect the region of interest, the processor circuit arrangement is configured to: determining that one or more partitions of the VRS mask include potential regions of interest; When one or more of the partitions of the VRS mask are determined to include potential regions of interest, reducing the size of the entire VRS mask to create a map; Mark the components in the graph that have strong coloring rates and are connected to each other; generating a boundary around each of the components that are labeled; as well as Any of the components that are marked and around which a boundary has been generated is identified as a candidate region of interest.

9. The device according to claim 8, wherein: In order to detect the region of interest, the processor circuit arrangement is configured to: determining a significance value for each of the plurality of components that have been marked and delimited; selecting a subset of the plurality of components that are marked and delimited based on the significance values; generating a score for the subset of the plurality of components that are labeled and delimited; selecting a subset of a number of the plurality of components that are labeled and delimited based on the scores; as well as The number of subsets of the plurality of components that are marked and delimited are provided to an encoder as regions of interest.

10. The device according to claim 5, wherein: In order to detect the region of interest, the processor circuit arrangement is configured to: determining that a partition of the VRS mask has one or more regions of interest; reducing a size of the VRS mask based on the determination that the partition of the VRS mask has one or more regions of interest; identifying one or more pixel groups included in the partition of the VRS mask, the one or more pixel groups being associated with strong variable shading rates and being in contact with each other; selecting a subset of the one or more of the pixel groups based on a significance value associated with each of the pixel groups; calculating a score for each of the one or more pixel groups in the subset; as well as One or more of the regions of interest identified for an encoder are selected from the subset.

11. A non-transitory machine-readable storage medium comprising instructions that, when executed, cause a processor circuit device to at least: detecting a region of interest of the video image based on a variable rate shading (VRS) mask of the video image, the VRS mask of the video image being created by a renderer using variable rate shading (VRS); and The region of interest of the video image is encoded, wherein: The quantization parameter is adjusted to a setting suitable for encoding the region of interest.

12. The non-transitory machine-readable storage medium of claim 11, comprising instructions that, when executed, cause processor circuitry to search the VRS mask of the video image to identify partitions in the VRS mask having weights that satisfy a threshold.

13. The non-transitory machine-readable storage medium of claim 11, wherein: To search the VRS mask, the instructions, when executed, cause the processor circuitry to: dividing the VRS mask of the video image into the partitions, the partitions comprising pixels, assigning corresponding weights to corresponding pixels among the pixels based on variable shading rates of the corresponding pixels, determining, for each of the partitions, a sum of the weights of the pixels included in the partition to obtain a total weight for each of the partitions, and When the total weight of any one of the partitions satisfies a threshold, the corresponding partition of the VRS mask is identified as an important partition.

14. The transitory machine-readable storage medium of claim 13, comprising instructions that, when executed, cause the processor circuitry to: identifying and marking a set of connected components included in the significant partition of the VRS mask; determining a boundary around each set of labeled connected components, thereby producing sets of labeled, bounded components; determining a validity score for a first subset of the set of labeled, delimited components; forming a second subset of the first subset of the labeled, delimited components based on the validity scores; determining a final score for each of the sets of labeled, delimited components in the second subset; selecting, based on the final scores, one or more of the sets of labeled, delimited components in the second subset to form a third subset of the labeled, delimited components; as well as The third subset of the marked, delimited components identifies a region of interest for an encoder.

15. The transitory machine-readable storage medium of claim 11, wherein: To detect the region of interest, the instructions, when executed, cause the processor circuit device to: determining that the VRS mask includes a potential region of interest; Based on the determination, reducing the size of the VRS mask to create a map; Mark the components in the graph that have strong coloring rates and are connected to each other; generating a boundary around the labeled component; as well as The bounded, labeled components are identified as candidate regions of interest.

16. A method for encoding a region of interest of a video image based on a variable rate shading (VRS) mask, comprising: detecting, using one or more processors, a region of interest of the video image based on the VRS mask, the VRS mask being generated by a renderer; as well as The region of interest of the video image is encoded using one or more processors, the encoding comprising adjusting a quantization parameter suitable for encoding the region of interest.

17. The method according to claim 16, wherein: Detecting the region of interest includes searching the VRS mask of the video image to identify regions in the VRS mask having weights that satisfy a threshold.

18. The method according to claim 17, wherein: Searching the VRS mask includes: dividing the VRS mask of the video image into sub-components, the sub-components comprising pixels, assigning respective weights to respective ones of the pixels based on variable shading rates of the pixels identified in the VRS mask, determining the sum of the weights for each subcomponent to identify a total weight, and When the total weight of any of the subcomponents satisfies a threshold, the VRS mask of the video image is identified as having a region of interest candidate.

19. The method according to claim 16, wherein: Detecting the region of interest includes: Mark the connected parts in the VRS mask that have been identified as having high intensity shading rates and are in contact with each other, determining a boundary around each set of labeled connected components, thereby producing labeled, bounded components; determining a validity score for a first subset of the labeled, delimited components; forming a second subset of the first subset of the labeled, delimited components based on the validity scores; determining a final score for each of the labeled, delimited components in the second subset; selecting, based on the final score, one or more of the labeled, delimited components in the second subset to form a third subset of the labeled, delimited components; and The third subset of the labeled, delimited components is identified as a region of interest.

20. The method according to claim 16, wherein: Detecting the region of interest includes: reducing the size of the VRS mask to create a map; Mark the components in the VRS diagram that have strong coloring rates and are connected to each other; generating a boundary around the labeled component; and The delimited, labeled components are identified as candidate regions of interest.

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