Array substrate and display device

Abstract

The array substrate comprises a plurality of pixel driving circuits. Each pixel driving circuit includes a driving transistor, a data writing transistor, a first capacitor including a first capacitor electrode and a second capacitor electrode, and a second capacitor including a third capacitor electrode and a fourth capacitor electrode. A second capacitor electrode and a third capacitor electrode are coupled to the second electrode of the data write transistor. The array substrate includes a stacked structure of capacitor electrodes. The stacked structure includes: a first capacitor electrode; an insulating layer on the first capacitor electrode; an electrode block including a second capacitor electrode and a third capacitor electrode located on a side of the insulating layer away from the first capacitor electrode; the interlayer dielectric layer is positioned on one side, far away from the insulating layer, of the electrode block; and the fourth capacitor electrode is positioned on the interlayer dielectric layer.

Description

Technical Field

[0001] The present invention relates to display technology, and in particular to an array substrate and a display device. Background Art

[0002] Organic light emitting diode (OLED) display is one of the hot spots in the field of flat panel display research today. Unlike thin film transistor-liquid crystal display (TFT-LCD) that uses a stable voltage to control brightness, OLED is driven by a driving current that needs to be kept constant to control brightness. The OLED display panel includes a plurality of pixel units, which are configured with a pixel driving circuit arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor having a gate terminal connected to a gate line for each row and a drain terminal connected to a data line for each column. When the row in which the pixel unit is selected is turned on, the switching transistor connected to the driving transistor is turned on, and the data voltage is applied to the driving transistor from the data line via the switching transistor, so that the driving transistor outputs a current corresponding to the data voltage to the OLED device. The OLED device is driven to emit light of corresponding brightness. Summary of the invention

[0003] On the one hand, the present disclosure provides an array substrate, comprising a plurality of pixel driving circuits; wherein each of the plurality of pixel driving circuits comprises a driving transistor, a data writing transistor, a first capacitor comprising a first capacitor electrode and a second capacitor electrode, and a second capacitor comprising a third capacitor electrode and a fourth capacitor electrode; wherein the second capacitor electrode and the third capacitor electrode are coupled to the second electrode of the data writing transistor; wherein the array substrate comprises a stacked structure of capacitor electrodes; wherein the stacked structure comprises: the first capacitor electrode; an insulating layer, which is located on the first capacitor electrode; an electrode block comprising the second capacitor electrode and the third capacitor electrode, which is located on a side of the insulating layer away from the first capacitor electrode; an interlayer dielectric layer, which is located on a side of the electrode block away from the insulating layer; and the fourth capacitor electrode, which is located on a side of the interlayer dielectric layer away from the electrode block.

[0004] Optionally, the fourth capacitor electrode is connected to a first voltage supply line.

[0005] Optionally, the first capacitor electrode, the insulating layer and the electrode block form the first capacitor; and the electrode block, the interlayer dielectric layer and the fourth capacitor electrode form at least a portion of the second capacitor.

[0006] Optionally, the array substrate also includes a plurality of first voltage supply line third branches located in the semiconductor material layer; wherein the stacked structure also includes: a gate insulation layer, which is located on the side of the first capacitor electrode away from the insulation layer; and a corresponding first voltage supply line third branch among the plurality of first voltage supply line third branches, which is located on the side of the gate insulation layer away from the first capacitor electrode.

[0007] Optionally, the first capacitor electrode, the insulating layer and the electrode block form the first capacitor; the electrode block, the interlayer dielectric layer and the fourth capacitor electrode form a first part of the second capacitor; and the electrode block, the insulating layer, the gate insulating layer, and a part of the third branch of the corresponding first voltage supply line form a second part of the second capacitor.

[0008] Optionally, the array substrate also includes a first node connection line and a second node connection line located in the first signal line layer; wherein, each pixel driving circuit also includes a compensation transistor, a first reset transistor and a second reset transistor; the first node connection line connects the first capacitor electrode to the second electrode of the compensation transistor and / or the second electrode of the first reset transistor; and the second node connection line connects the electrode block to the second electrode of the data write transistor and / or the second electrode of the second reset transistor.

[0009] Optionally, the first node connection line and the second node connection line are located on a side of the fourth capacitor electrode away from the electrode block.

[0010] Optionally, the first node connection line and the second node connection line are located in the same layer as the fourth capacitor electrode.

[0011] Optionally, the array substrate also includes a fourth node portion located in the semiconductor material layer; wherein each pixel driving circuit also includes a compensation transistor and a second light-emitting control transistor; wherein the fourth node portion includes at least a portion of the second electrode of the driving transistor, at least a portion of the first electrode of the compensation transistor, and at least a portion of the first electrode of the second light-emitting control transistor; and the orthographic projection of the fourth node portion on the base substrate at least partially overlaps with the orthographic projection of a corresponding data line among the multiple data lines on the base substrate.

[0012] Optionally, the orthographic projection of the fourth node portion on the base substrate is covered by at least 50% of an orthographic projection of a combination of the fourth capacitor electrode and a corresponding first reset signal line of the plurality of first reset signal lines on the base substrate.

[0013] Optionally, the fourth capacitor electrode includes a first part and a second part; the orthographic projection of the first part on the substrate substantially covers the orthographic projection of the electrode block on the substrate; the orthographic projection of the second part on the substrate does not overlap with the orthographic projection of the electrode block on the substrate; and the orthographic projection of the fourth node part on the substrate partially overlaps with the orthographic projection of the second part on the substrate.

[0014] Optionally, the orthographic projection of the second part on the substrate partially overlaps with the orthographic projection of a corresponding reset control signal line among multiple reset control signal lines on the substrate, and partially overlaps with the orthographic projection of a corresponding second compensation control signal line among multiple second compensation control signal lines on the substrate.

[0015] Optionally, the corresponding first reset signal line includes a main body, a first protrusion extending away from the main body, and a second protrusion extending away from the main body; the first protrusion and the second protrusion extend away from the main body in substantially opposite directions; and the orthographic projection of the fourth node portion on the substrate partially overlaps with the orthographic projection of the first protrusion and the second protrusion on the substrate, and partially overlaps with the orthographic projection of the portion of the main body connecting the first protrusion and the second protrusion on the substrate.

[0016] Optionally, the array substrate also includes: a first data line, which is configured to provide a data signal to the first sub-pixel; a second data line, which is configured to provide a data signal to the second sub-pixel; a third data line, which is configured to provide a data signal to the third sub-pixel; a first anode, which is located in the first sub-pixel; a second anode, which is located in the second sub-pixel; and a third anode, which is located in the third sub-pixel; wherein the orthographic projection of the combination of the first anode, the second anode and the third anode on the substrate substrate partially overlaps with the orthographic projection of the first data line on the substrate substrate, partially overlaps with the orthographic projection of the second data line on the substrate substrate, and does not overlap with the orthographic projection of the third data line on the substrate substrate.

[0017] Optionally, the orthographic projection of the first data line on the base substrate partially overlaps with the orthographic projection of the first anode on the base substrate, and partially overlaps with the orthographic projection of the second anode on the base substrate; and the orthographic projection of the second data line on the base substrate partially overlaps with the orthographic projection of the third anode on the base substrate.

[0018] Optionally, the length of the first overlapping area along the extension direction of the first corresponding data line is smaller than the total length of the first anode along the extension direction of the first corresponding data line, wherein the first overlapping area is the area where the orthographic projection of the first anode on the substrate overlaps with the orthographic projection of the first corresponding data line on the substrate; the length of the second overlapping area along the extension direction of the second corresponding data line is smaller than the total length of the second anode along the extension direction of the second corresponding data line, wherein the second overlapping area is the area where the orthographic projection of the second anode on the substrate overlaps with the orthographic projection of the second corresponding data line on the substrate; the length of the third overlapping area along the extension direction of the third corresponding data line is smaller than the total length of the third anode along the extension direction of the third corresponding data line, and the third overlapping area is the area where the orthographic projection of the third anode on the substrate overlaps with the orthographic projection of the third corresponding data line on the substrate; and the first corresponding data line, the second corresponding data line and the third corresponding data line are selected from the first data line and the second data line.

[0019] Optionally, the array substrate also includes an interconnected first voltage supply network; wherein the interconnected first voltage supply network includes: a plurality of first voltage supply line third branches, which are located in the semiconductor material layer; an overall structure including a plurality of fourth capacitor electrodes in the same row, which are located in the first signal line layer, and the first signal line layer is located on the side of the semiconductor material layer away from the base substrate; and a plurality of first voltage supply line second branches, which are located in the second signal line layer, and the second signal line layer is located on the side of the first signal line layer away from the semiconductor material layer.

[0020] Optionally, a portion of a corresponding first voltage supply line third branch among the plurality of first voltage supply line third branches, the electrode block, and one or more insulating material layers located between the corresponding first voltage supply line third branch and the electrode block form a portion of the second capacitor.

[0021] Optionally, each pixel driving circuit also includes a compensation transistor, a first reset transistor, a first light emission control transistor, a second light emission control transistor, a second reset transistor, a third reset transistor, a fourth reset transistor, a first node, a second node, a third node and a fourth node; wherein the first node is connected to the first capacitor electrode of the first capacitor, the second electrode of the compensation transistor and the gate of the driving transistor; the second node is connected to the second capacitor electrode of the first capacitor, the third capacitor electrode of the second capacitor, the second electrode of the data writing transistor and the second electrode of the second reset transistor; the third node is connected to the second electrode of the first light emission control transistor, the second electrode of the fourth reset transistor and the first electrode of the driving transistor; and the fourth node is connected to the second electrode of the driving transistor, the first electrode of the compensation transistor and the first electrode of the second light emission control transistor.

[0022] On the other hand, the present disclosure provides a display device, which includes an array substrate described herein or manufactured by the method described herein, and one or more integrated circuits connected to the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] According to various disclosed embodiments, the following drawings are examples only for illustration purposes and are not intended to limit the scope of the present invention.

[0024] Figure 1 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0025] Figure 2 is a circuit diagram showing the structure of a pixel driving circuit in some embodiments according to the present disclosure.

[0026] Figure 3A is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure.

[0027] Figure 3B is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure.

[0028] Figure 4A is a schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure.

[0029] Figure 4B It is shown Figure 4A Schematic diagram of the arrangement of multiple pixel driving circuits in an array substrate depicted in FIG.

[0030] Figure 4C It is shown Figure 4ASchematic diagram of the structure of the semiconductor material layer in the array substrate depicted in FIG.

[0031] Figure 4D It is shown Figure 4A A schematic diagram of the structure of the first conductive layer in the array substrate depicted in FIG.

[0032] Figure 4E It is shown Figure 4A A schematic diagram of the structure of the second conductive layer in the array substrate depicted in FIG.

[0033] Figure 4F It is shown Figure 4A Schematic diagram of the structure of the third conductive layer in the array substrate depicted in FIG.

[0034] Figure 4G It is shown Figure 4A Schematic diagram of the structure of the first planarization layer in the array substrate depicted in FIG.

[0035] Figure 4H It is shown Figure 4A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in FIG.

[0036] Fig. 4I It is shown Figure 4A Schematic diagram of the structure of the second planarization layer in the array substrate depicted in FIG.

[0037] Figure 4J It is shown Figure 4A A schematic diagram of the structure of the second signal line layer in the array substrate depicted in FIG.

[0038] Figure 4K It is shown Figure 4A Schematic diagram of the structure of the third planarization layer in the array substrate depicted in FIG.

[0039] Figure 4L It is shown Figure 4A Schematic diagram of the structure of the anode layer in the array substrate depicted in FIG.

[0040] Figure 4M It is shown Figure 4A Schematic diagram of the structure of the pixel defining layer in the array substrate depicted in FIG.

[0041] Figure 5 is along Figure 4A Cross-sectional view along line A-A'.

[0042] Figure 6 The stacking structure of capacitor electrodes in an array substrate in some embodiments of the present disclosure is shown.

[0043] Figure 7is a schematic diagram showing the structure of a fourth capacitor electrode in some embodiments according to the present disclosure.

[0044] Figure 8 is a schematic diagram showing the structures of a semiconductor material layer, a second conductive layer and a third conductive layer according to some embodiments of the present disclosure.

[0045] Fig. 9 is a schematic diagram showing the structure of a second signal line layer and an anode layer according to some embodiments of the present disclosure.

[0046] Fig.10 is a schematic diagram showing the structure of an interconnected first voltage supply network in some embodiments according to the present disclosure.

[0047] Fig.11 is a schematic diagram showing the structure of an interconnected reference signal network according to some embodiments of the present disclosure.

[0048] Fig.12 is a schematic diagram showing the structure of an interconnected second voltage supply network in some embodiments according to the present disclosure.

[0049] Fig.13A is a schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure.

[0050] Fig. 13B It is shown Fig.13A Schematic diagram of the structure of the semiconductor material layer in the array substrate depicted in FIG.

[0051] Fig. 13C It is shown Fig.13A A schematic diagram of the structure of the first conductive layer in the array substrate depicted in FIG.

[0052] Fig.13D It is shown Fig.13A A schematic diagram of the structure of the second conductive layer in the array substrate depicted in FIG.

[0053] Fig.13E It is shown Fig.13A A schematic diagram of the structure of the interlayer dielectric layer in the array substrate depicted in FIG.

[0054] Fig.13F It is shown Fig.13A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in FIG.

[0055] Figure 13G It is shown Fig.13A Schematic diagram of the structure of the first planarization layer in the array substrate depicted in FIG.

[0056] Fig.13H It is shown Fig.13AA schematic diagram of the structure of the second signal line layer in the array substrate depicted in FIG.

[0057] Fig.13I It is shown Fig.13A Schematic diagram of the structure of the second planarization layer in the array substrate depicted in FIG.

[0058] Fig.13J It is shown Fig.13A Schematic diagram of the structure of the anode layer in the array substrate depicted in FIG.

[0059] Figure 13K It is shown Fig.13A Schematic diagram of the structure of the pixel defining layer in the array substrate depicted in FIG.

[0060] Fig.14 is along Fig.13A Cross-sectional view along line BB'.

[0061] Fig.15 is a schematic diagram showing the structure of an interconnected first voltage supply network in some embodiments according to the present disclosure.

[0062] Fig.16A is a schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure.

[0063] Fig. 16B It is shown Fig.16A Schematic diagram of the structure of the semiconductor material layer in the array substrate depicted in FIG.

[0064] Fig. 16C It is shown Fig.16A A schematic diagram of the structure of the first conductive layer in the array substrate depicted in FIG.

[0065] Fig.16D It is shown Fig.16A A schematic diagram of the structure of the second conductive layer in the array substrate depicted in FIG.

[0066] Fig.16E It is shown Fig.16A A schematic diagram of the structure of the interlayer dielectric layer in the array substrate depicted in FIG.

[0067] Fig.16F It is shown Fig.16A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in FIG.

[0068] Figure 16G It is shown Fig.16A Schematic diagram of the structure of the first planarization layer in the array substrate depicted in FIG.

[0069] Fig.16H It is shown Fig.16AA schematic diagram of the structure of the second signal line layer in the array substrate depicted in FIG.

[0070] Fig.17 is along Fig.16A Cross-sectional view along line CC'.

[0071] Fig.18 is a schematic diagram showing the structure of an interconnected first voltage supply network in some embodiments according to the present disclosure.

[0072] Fig.19A is a schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure.

[0073] Fig.19B It is shown Fig.19A Schematic diagram of the arrangement of multiple pixel driving circuits in an array substrate depicted in FIG.

[0074] Fig.19C It is shown Fig.19A Schematic diagram of the structure of the semiconductor material layer in the array substrate depicted in FIG.

[0075] Fig.19D It is shown Fig.19A A schematic diagram of the structure of the first conductive layer in the array substrate depicted in FIG.

[0076] Fig.19E It is shown Fig.19A A schematic diagram of the structure of the second conductive layer in the array substrate depicted in FIG.

[0077] Fig.19F It is shown Fig.19A Schematic diagram of the structure of the third conductive layer in the array substrate depicted in FIG.

[0078] Figure 19G It is shown Fig.19A Schematic diagram of the structure of the first planarization layer in the array substrate depicted in FIG.

[0079] Fig.19H It is shown Fig.19A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in FIG.

[0080] Fig.19I It is shown Fig.19A Schematic diagram of the structure of the second planarization layer in the array substrate depicted in FIG.

[0081] Fig.19J It is shown Fig.19A A schematic diagram of the structure of the second signal line layer in the array substrate depicted in FIG.

[0082] Figure 19K It is shown Fig.19ASchematic diagram of the structure of the third planarization layer in the array substrate depicted in FIG.

[0083] Figure 19L It is shown Fig.19A Schematic diagram of the structure of the anode layer in the array substrate depicted in FIG.

[0084] Fig.19M It is shown Fig.19A Schematic diagram of the structure of the pixel defining layer in the array substrate depicted in FIG.

[0085] Fig. 20 It is shown Fig.19A Schematic diagram of the structure of the semiconductor material layer, the second conductive layer and the third conductive layer in the array substrate depicted in FIG.

[0086] Fig.21A is a schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure.

[0087] Fig. 21B It is shown Fig.21A Schematic diagram of the structure of the semiconductor material layer in the array substrate depicted in FIG.

[0088] Fig. 21C It is shown Fig.21A A schematic diagram of the structure of the first conductive layer in the array substrate depicted in FIG.

[0089] Fig.21D It is shown Fig.21A A schematic diagram of the structure of the second conductive layer in the array substrate depicted in FIG.

[0090] Fig.21E It is shown Fig.21A A schematic diagram of the structure of the interlayer dielectric layer in the array substrate depicted in FIG.

[0091] Fig.21F It is shown Fig.21A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in FIG.

[0092] Figure 21G It is shown Fig.21A Schematic diagram of the structure of the first planarization layer in the array substrate depicted in FIG.

[0093] Fig.21H It is shown Fig.21A A schematic diagram of the structure of the second signal line layer in the array substrate depicted in FIG.

[0094] Fig.21I It is shown Fig.21A Schematic diagram of the structure of the second planarization layer in the array substrate depicted in FIG.

[0095] Fig.21J It is shown Fig.21A Schematic diagram of the structure of the anode layer in the array substrate depicted in FIG.

[0096] Figure 21K It is shown Fig.21A Schematic diagram of the structure of the pixel defining layer in the array substrate depicted in FIG.

[0097] Fig. 22 It is shown Fig.21A A schematic diagram of the structure of the semiconductor material layer, the second conductive layer and the first signal line layer in the array substrate depicted in FIG.

[0098] Fig.23A is a schematic diagram showing the structure of an anode layer in an array substrate according to some embodiments of the present disclosure.

[0099] Fig. 23B is a schematic diagram showing the structure of a second signal line layer and an anode layer in an array substrate according to some embodiments of the present disclosure.

[0100] Fig.24A is a schematic diagram showing the structure of an anode layer in an array substrate according to some embodiments of the present disclosure.

[0101] Fig. 24B is a schematic diagram showing the structure of a second signal line layer and an anode layer in an array substrate according to some embodiments of the present disclosure.

[0102] Fig.25A is a schematic diagram showing the structure of an anode layer in an array substrate according to some embodiments of the present disclosure.

[0103] Fig.25B is a schematic diagram showing the structure of a second signal line layer and an anode layer in an array substrate according to some embodiments of the present disclosure.

[0104] Fig.26A is a schematic diagram showing the structure of a second conductive layer in an array substrate according to some embodiments of the present disclosure.

[0105] Fig.26B is a schematic diagram showing the structure of a semiconductor material layer and a second conductive layer in an array substrate according to some embodiments of the present disclosure.

[0106] Fig.27A is a schematic diagram showing the structure of a second conductive layer in an array substrate according to some embodiments of the present disclosure.

[0107] Fig.27B is a schematic diagram showing the structure of a semiconductor material layer and a second conductive layer in an array substrate according to some embodiments of the present disclosure.

[0108] Fig.28A is a schematic diagram showing the structure of a second conductive layer in an array substrate according to some embodiments of the present disclosure.

[0109] Fig.28B is a schematic diagram showing the structure of a semiconductor material layer and a second conductive layer in an array substrate according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0110] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise form disclosed.

[0111] The present disclosure particularly provides an array substrate and a display device, which substantially overcomes one or more problems caused by the limitations and shortcomings of the prior art. On the one hand, the present disclosure provides an array substrate. In some embodiments, the array substrate includes a plurality of pixel driving circuits. Optionally, each of the plurality of pixel driving circuits includes a driving transistor, a data writing transistor, a first capacitor including a first capacitor electrode and a second capacitor electrode, and a second capacitor including a third capacitor electrode and a fourth capacitor electrode. Optionally, the second capacitor electrode and the third capacitor electrode are coupled to the second electrode of the data writing transistor. Optionally, the array substrate includes a stacked structure of capacitor electrodes. Optionally, the stacked structure includes: a first capacitor electrode; an insulating layer, which is located on the first capacitor electrode; an electrode block including a second capacitor electrode and a third capacitor electrode, which is located on the side of the insulating layer away from the first capacitor electrode; an interlayer dielectric layer, which is located on the side of the electrode block away from the insulating layer; and a fourth capacitor electrode, which is located on the side of the interlayer dielectric layer away from the electrode block.

[0112] Various suitable pixel driving circuits can be used in the array substrate described in the present disclosure. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C and 8T2C. In some embodiments, each of the plurality of pixel driving circuits is a 9T2C driving circuit. Various suitable light-emitting elements can be used in the array substrate described in the present disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes, quantum dot light-emitting diodes and micro light-emitting diodes. Optionally, the light-emitting element is a micro light-emitting diode. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0113] Figure 1 is a plan view of an array substrate in some embodiments of the present disclosure. Figure 1, the array substrate includes an array of sub-pixels Sp. Each sub-pixel includes an electronic component, for example, a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The array substrate includes a plurality of gate lines GL, a plurality of data lines DL, a plurality of first voltage supply lines Vdd, and respective second voltage supply lines (e.g., low voltage supply lines). Each sub-pixel Sp is driven by a corresponding pixel driving circuit PDC to emit light. In one example, a high voltage signal (e.g., a VDD signal) is input to a corresponding pixel driving circuit PDC connected to an anode of a light-emitting element through each of a plurality of first voltage supply lines Vdd; a low voltage signal (e.g., a VSS signal) is input to a cathode of the light-emitting element through a low voltage supply line. The voltage difference between the high voltage signal (e.g., a VDD signal) and the low voltage signal (e.g., a VSS signal) is a driving voltage ΔV, which drives the light-emitting element to emit light.

[0114] In some embodiments, the pixel driving circuit includes a data writing subcircuit configured to receive a data signal, a storage capacitor subcircuit, a reset subcircuit, a threshold compensation subcircuit, a driving subcircuit, and a light emission control subcircuit. Figure 2 is a circuit diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 2 In some embodiments, each pixel driving circuit includes a first transistor T1 (data writing transistor), a second transistor T2 (compensation transistor), a third transistor T3 (driving transistor), a fourth transistor T4 (first reset transistor), a fifth transistor T5 (first light emission control transistor), a sixth transistor T6 (second light emission control transistor), a seventh transistor T7 (second reset transistor), an eighth transistor T8 (third reset transistor), a ninth transistor T9 (fourth reset transistor), a first capacitor C1 and a second capacitor C2. In some embodiments, the data writing subcircuit includes a first transistor T1; the storage capacitor subcircuit includes a first capacitor C1 and a second capacitor C2; the reset subcircuit includes a fourth transistor T4, a seventh transistor T7, an eighth transistor T8 and a ninth transistor T9; the threshold compensation subcircuit includes a second transistor T2, the driving subcircuit includes a third transistor T3, and the light emission control subcircuit includes a fifth transistor T5 and a sixth transistor T6.

[0115] In some embodiments, the pixel driving circuit includes a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node N5. In some embodiments, the first node N1 is connected to the first capacitor electrode Ce1 of the first capacitor C1, the second electrode of the second transistor T2, and the gate of the third transistor T3. In some embodiments, the second node N2 is connected to the second capacitor electrode Ce2 of the first capacitor C1, the third capacitor electrode Ce3 of the second capacitor C2, the second electrode of the first transistor T1, and the second electrode of the seventh transistor T7. In some embodiments, the third node N3 is connected to the second electrode of the fifth transistor T5, the second electrode of the ninth transistor T9, and the first electrode of the third transistor T3. In some embodiments, the fourth node N4 is connected to the second electrode of the third transistor T3, the first electrode of the second transistor T2, and the first electrode of the sixth transistor T6. In some embodiments, the fifth node N5 is connected to the second electrode of the sixth transistor T6, the second electrode of the eighth transistor T8, and the anode of the light emitting element LE.

[0116] In some embodiments, the gate of the first transistor T1 is connected to a corresponding gate line among a plurality of gate lines GL, the first electrode of the first transistor T1 is connected to a corresponding data line among a plurality of data lines DL, and the second electrode of the first transistor T1 is connected to a second capacitor electrode Ce2 of the first capacitor C1, a third capacitor electrode Ce3 of the second capacitor C2, and a second electrode of the seventh transistor T7.

[0117] In some embodiments, the gate of the second transistor T2 is connected to a corresponding compensation control signal line among a plurality of compensation control signal lines AZ, the first electrode of the second transistor T2 is connected to the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6, and the second electrode of the second transistor T2 is connected to the first capacitor electrode Ce1 of the first capacitor C1 and the gate of the third transistor T3.

[0118] In some embodiments, the gate of the third transistor T3 is connected to the first capacitor electrode Ce1 of the first capacitor C1, the second electrode of the second transistor T2, and the second electrode of the fourth transistor T4; the first electrode of the third transistor T3 is connected to the second electrode of the fifth transistor T5 and the second electrode of the ninth transistor T9; the second electrode of the third transistor T3 is connected to the first electrode of the second transistor T2 and the first electrode of the sixth transistor T6.

[0119] In some embodiments, the gate of the fourth transistor T4 is connected to a corresponding reset control signal line among multiple reset control signal lines rst; the first electrode of the fourth transistor T4 is connected to a corresponding first reset signal line among multiple first reset signal lines Vint1; the second electrode of the fourth transistor T4 is connected to the second electrode of the second transistor T2, the first capacitor electrode Ce1 of the first capacitor C1 and the gate of the third transistor T3.

[0120] In some embodiments, the gate of the fifth transistor T5 is connected to a corresponding first light-emitting control signal line among a plurality of first light-emitting control signal lines em1; the first electrode of the fifth transistor T5 is connected to a first voltage supply line among a plurality of first voltage supply lines Vdd; the second electrode of the fifth transistor T5 is connected to the first electrode of the third transistor T3 and the second electrode of the ninth transistor T9.

[0121] In some embodiments, the gate of the sixth transistor T6 is connected to a corresponding second light-emitting control signal line among a plurality of second light-emitting control signal lines em2; the first electrode of the sixth transistor T6 is connected to the first electrode of the second transistor T2 and the second electrode of the third transistor T3; the second electrode of the sixth transistor T6 is connected to the second electrode of the eighth transistor T8 and the anode of the light-emitting element LE.

[0122] In some embodiments, the gate of the seventh transistor T7 is connected to a corresponding compensation control signal line among a plurality of compensation control signal lines AZ; the first electrode of the seventh transistor T7 is connected to a corresponding first reference signal line among a plurality of first reference signal lines Vref1; the second electrode of the seventh transistor T7 is connected to the second capacitor electrode Ce2 of the first capacitor C1, the third capacitor electrode Ce3 of the second capacitor C2, and the second electrode of the first transistor T1.

[0123] In some embodiments, the gate of the eighth transistor T8 is connected to a corresponding scan line among multiple scan lines scan; the first electrode of the eighth transistor T8 is connected to a corresponding second reset signal line among multiple second reset signal lines Vint2; the second electrode of the eighth transistor T8 is connected to the second electrode of the sixth transistor T6 and the anode of the light-emitting element LE.

[0124] In some embodiments, the gate of the ninth transistor T9 is connected to a corresponding scan line among multiple scan lines scan; the first electrode of the ninth transistor T9 is connected to a corresponding second reference signal line among multiple second reference signal lines Vref2; the second electrode of the ninth transistor T9 is connected to the second electrode of the fifth transistor T5 and the first electrode of the third transistor T3.

[0125] In some embodiments, the first capacitor electrode Ce1 of the first capacitor C1 is connected to the gate of the third transistor T3, the second electrode of the second transistor T2, and the second electrode of the fourth transistor T4; the second capacitor electrode Ce2 of the first capacitor C1 is connected to the second electrode of the first transistor T1, the third capacitor electrode Ce3 of the second capacitor C2, and the second electrode of the seventh transistor T7.

[0126] In some embodiments, the third capacitor electrode Ce3 of the second capacitor C2 is connected to the second electrode of the first transistor T1, the second capacitor electrode Ce2 of the first capacitor C1, and the second electrode of the seventh transistor T7; the fourth capacitor electrode Ce4 of the second capacitor C2 is connected to the first voltage supply line among the plurality of first voltage supply lines Vdd.

[0127] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, and the first terminal and the second terminal are connected to the active layer of the transistor. The direction of the current flowing through the transistor can be configured to be from the first electrode to the second electrode, or from the second electrode to the first electrode. Therefore, depending on the direction of the current flowing through the transistor, in one example, the first electrode is configured to receive an input signal, and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal, and the first electrode is configured to output an output signal.

[0128] In some embodiments, one or more transistors in the pixel driving circuit may be a "dual gate" transistor. Optionally, in a "dual gate" transistor, the active layer of the transistor crosses twice over the gate (alternatively, the gate crosses twice over the active layer of the transistor). In one example, at least one of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, or the seventh transistor T7 is a "dual gate" transistor. In another example, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are "dual gate" transistors.

[0129] The present disclosure can be implemented in a pixel driving circuit having various types of transistors, including a pixel driving circuit having a p-type transistor such as a polysilicon transistor, a pixel driving circuit having an n-type transistor such as a metal oxide transistor, and a pixel driving circuit having one or more p-type transistors and one or more n-type transistors. For a p-type transistor, a valid control signal (e.g., a turn-on control signal) is a low voltage signal, while an invalid control signal (e.g., a turn-off control signal) is a high voltage signal. For an n-type transistor, a valid control signal (e.g., a turn-on control signal) is a high voltage signal, while an invalid control signal (e.g., a turn-off control signal) is a low voltage signal. Reference Figure 2 In some embodiments, the transistors in the pixel driving circuit are p-type transistors.

[0130] Figure 3A is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure. Figure 3B is a timing diagram showing the operation of the pixel driving circuit in some embodiments according to the present disclosure. Figure 2 , Figure 3A and Figure 3B During one frame of image, the operation of the pixel driving circuit includes a first stage t1, a second stage t2, a third stage t3, a fourth stage t4, a fifth stage t5, a sixth stage t6 and a seventh stage t7. In the first stage t1, a cut-off reset control signal is provided to the gate of the fourth transistor T4 through a corresponding reset control signal line among a plurality of reset control signal lines rst, so that the fourth transistor T4 is cut off. In the first stage t1, a corresponding gate line among a plurality of gate lines GL is provided with a cut-off signal, so that the first transistor T1 is cut off.

[0131] In the second stage t2, a turn-on reset control signal is provided to the gate of the fourth transistor T4 through a corresponding reset control signal line among the plurality of reset control signal lines rst, so that the fourth transistor T4 is turned on; so that the initialization voltage signal from the corresponding first reset signal line among the plurality of first reset signal lines Vint1 is transmitted from the first electrode of the fourth transistor T4 to the second electrode of the fourth transistor T4, and then to the first capacitor electrode Ce1 and the gate of the third transistor T3. The first node N1 is reset. The gate of the third transistor T3 is initialized.

[0132] In the second stage t2, the on-scan signal is provided to the gate of the eighth transistor T8 through the corresponding scan signal line among the plurality of scan signal lines scan, so that the eighth transistor T8 is turned on; so that the initialization voltage signal from the corresponding second reset signal line among the plurality of second reset signal lines Vint2 is transferred from the first electrode of the eighth transistor T8 to the second electrode of the eighth transistor T8, and then to the second electrode of the sixth transistor T6 and the anode of the light emitting element LE. The fifth node N5 is reset.

[0133] In the second stage t2, a conduction scan signal is provided to the gate of the ninth transistor T9 through a corresponding scan signal line among the plurality of scan signal lines scan, so that the ninth transistor T9 is turned on; so that a second reference voltage signal from a corresponding second reference signal line among the plurality of second reference signal lines Vref2 is transmitted from the first electrode of the ninth transistor T9 to the second electrode of the ninth transistor T9, and then to the second electrode of the fifth transistor T5 and the first electrode of the third transistor T3. The third node N3 is reset.

[0134] In the third stage t3, a turn-on scan signal is provided through a corresponding compensation control signal line among the plurality of compensation control signal lines AZ to turn on the seventh transistor T7, so that a first reference voltage signal from a corresponding first reference signal line among the plurality of first reference signal lines Vref1 is transferred from the first electrode of the seventh transistor T7 to the second electrode of the seventh transistor T7, and then to the second capacitor electrode Ce2 of the first capacitor C1, the third capacitor electrode Ce3 of the second capacitor C2, and the second electrode of the first transistor T1. The second node N2 is reset.

[0135] In the fourth stage t4, a turn-on reset control signal is provided to the gate of the fourth transistor T4 through a corresponding reset control signal line among the plurality of reset control signal lines rst, so that the fourth transistor T4 is turned on; so that the initialization voltage signal from the corresponding first reset signal line among the plurality of first reset signal lines Vint1 is transmitted from the first electrode of the fourth transistor T4 to the second electrode of the fourth transistor T4, and then to the first capacitor electrode Ce1 and the gate of the third transistor T3. The first node N1 is reset. The gate of the third transistor T3 is initialized.

[0136] In the fourth stage t4, a conduction scan signal is provided to the gate of the eighth transistor T8 through a corresponding scan signal line among the plurality of scan signal lines scan, so that the eighth transistor T8 is turned on; so that the initialization voltage signal from the corresponding second reset signal line among the plurality of second reset signal lines Vint2 is transferred from the first electrode of the eighth transistor T8 to the second electrode of the eighth transistor T8, and then to the second electrode of the sixth transistor T6 and the anode of the light emitting element LE. The fifth node N5 is reset.

[0137] In the fourth stage t4, a conduction scan signal is provided to the gate of the ninth transistor T9 through a corresponding scan signal line among the plurality of scan signal lines scan, so that the ninth transistor T9 is turned on; so that the second reference voltage signal from the corresponding second reference signal line among the plurality of second reference signal lines Vref2 is transmitted from the first electrode of the ninth transistor T9 to the second electrode of the ninth transistor T9, and then to the second electrode of the fifth transistor T5 and the first electrode of the third transistor T3. The third node N3 is reset.

[0138] In the fifth stage t5, a turn-on scan signal is provided to the gate of the fifth transistor T5 through a corresponding first light-emitting control signal line among a plurality of first light-emitting control signal lines em1, so that the fifth transistor T5 is turned on; so that the first voltage supply signal from the corresponding first voltage supply signal line among a plurality of first voltage supply signal lines Vdd is transmitted from the first electrode of the fifth transistor T5 to the second electrode of the fifth transistor T5, and then to the first electrode of the third transistor T3. The second electrode of the third transistor T3 is connected to the first electrode of the second transistor T2. The gate of the third transistor T3 is electrically connected to the second electrode of the second transistor T2. Since the second transistor T2 is turned on in the fifth stage t5, the gate of the third transistor T3 is connected to the second electrode and short-circuited, and only the PN junction between the gate of the third transistor T3 and the first electrode is effective, so that the third transistor T3 is in a diode connection mode. The first node N1 is written to (Vdd-Vth), where Vth is the threshold voltage of the third transistor T3.

[0139] In the fifth stage t5, a turn-on scan signal is provided through a corresponding compensation control signal line among the plurality of compensation control signal lines AZ to turn on the seventh transistor T7 and the second transistor T2; so that the first reference voltage signal from the corresponding first reference voltage signal line among the plurality of first reference voltage signal lines Vref1 is transferred from the first electrode of the seventh transistor T7 to the second electrode of the seventh transistor T7, and then to the second node N2. The voltage stored in the first capacitor C1 is Vdd-Vth-Vref2. The second transistor writes the voltage information of the corresponding first voltage supply line and the voltage information of the threshold voltage of the third transistor T3 into one end of the first capacitor C1.

[0140] In the sixth stage t6, the cut-off signal is provided to the corresponding scan line in the plurality of scan lines scan, the corresponding second light-emitting control signal line in the plurality of second light-emitting control signal lines em2, and the corresponding compensation control signal line in the plurality of compensation control signal lines AZ, so that the second transistor T2, the sixth transistor T6, and the ninth transistor T9 are turned off. The voltage of the first node N1 is maintained at (Vdd-Vth) by the first capacitor C1. In the sixth stage t6, the corresponding gate line in the plurality of gate lines GL is provided with a turn-on signal, so that the first transistor T1 is turned on. The data voltage of the data signal is written to the second node N2. Due to the bootstrap effect of the first capacitor C1, the voltage of the first node N1 is bootstrapped to (Vdd-Vth+Vdt), so that the third transistor T3 is turned on.

[0141] In the seventh stage t7, the cut-off signal is provided to the corresponding gate line in the plurality of gate lines GL, the corresponding scan line in the plurality of scan lines scan, the corresponding compensation control signal line in the plurality of compensation control signal lines AZ, and the corresponding reset control signal line in the plurality of reset control signal lines rst, so that the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are cut off. In the seventh stage t7, the turn-on signal is provided to the corresponding first light-emitting control signal line in the plurality of first light-emitting control signal lines em1 and the corresponding second light-emitting control signal line in the plurality of second light-emitting control signal lines em2, so that the fifth transistor T5 and the sixth transistor T6 are turned on. The third transistor T3 is turned on due to (Vdd-Vth+Vdt) and operates in the saturation region. A path is formed through the fifth transistor T5, the third transistor T3, and the sixth transistor T6 to the light-emitting element LE. The driving transistor Td generates a driving current to drive the light-emitting element LE to emit light. The voltage level at the fifth node N5 connected to the second electrode of the sixth transistor T6 is equal to the light-emitting voltage of the light-emitting element LE.

[0142] Each of the plurality of compensation control signal lines AZ may have various appropriate duty cycles. Each of the plurality of compensation control signal lines AZ may have various appropriate effective voltage (on-voltage) durations. Figure 3A In one example depicted in , the duration of the effective voltage of the corresponding compensation control signal line among the plurality of compensation control signal lines AZ is greater than the duration of the effective voltage of the corresponding reset control signal line among the plurality of reset control signal lines rst. Figure 3BIn another example depicted in , the duration of the effective voltage of the corresponding compensation control signal line in the plurality of compensation control signal lines AZ is substantially the same as the duration of the effective voltage of the corresponding reset control signal line in the plurality of reset control signal lines rst. As used herein, the term "substantially the same" means that the difference between the two values ​​does not exceed 10% of the base value (e.g., one of the two values), such as not more than 8%, not more than 6%, not more than 4%, not more than 2%, not more than 1%, not more than 0.5%, not more than 0.1%, not more than 0.05%, and not more than 0.01% of the base value.

[0143] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels include respective first sub-pixels, respective second sub-pixels, and respective third sub-pixels. Optionally, each pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a S1-S2-S3 format repeating array, wherein S1 represents the corresponding first sub-pixel, S2 represents the corresponding second sub-pixel, and S3 represents the corresponding third sub-pixel. In another example, the S1-S2-S3 format is a C1-C2-C3 format, wherein C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, and C3 represents the corresponding third sub-pixel of the third color. In another example, the C1-C2-C3 format is an RGB format, wherein the corresponding first sub-pixel is a red sub-pixel, the corresponding second sub-pixel is a green sub-pixel, and the corresponding third sub-pixel is a blue sub-pixel.

[0144] In another example, the array of multiple sub-pixels includes a repeating array of the S1-S2-S3-S4 format, wherein S1 represents the corresponding first sub-pixel, S2 represents the corresponding second sub-pixel, S3 represents the corresponding third sub-pixel, and S4 represents the corresponding fourth sub-pixel. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, wherein C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, C3 represents the corresponding third sub-pixel of the third color, and C4 represents the corresponding fourth sub-pixel of the fourth color. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C2' format, wherein C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, C3 represents the corresponding third sub-pixel of the third color, and C2' represents the corresponding fourth sub-pixel of the second color. In another example, the C1-C2-C3-C2′ format is an RGBG format, wherein the corresponding first subpixel is a red subpixel, the corresponding second subpixel is a green subpixel, the corresponding third subpixel is a blue subpixel, and the corresponding fourth subpixel is a green subpixel.

[0145] In some embodiments, the minimum repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, and the corresponding third sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a first capacitor C1, and a second capacitor C2.

[0146] In an alternative embodiment, the minimum repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, the corresponding third sub-pixel, and the corresponding fourth sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a first capacitor C1, and a second capacitor C2.

[0147] Figure 4A is a schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure. Figure 4B It is shown Figure 4A A schematic diagram of the arrangement of multiple pixel driving circuits in an array substrate. Figure 4A and Figure 4B A portion of an array substrate having three pixel driving circuits (including PDC1, PDC2 and PDC3) is depicted.

[0148] Figure 4C It is shown Figure 4A Schematic diagram of the structure of the semiconductor material layer in the array substrate. Figure 4D It is shown Figure 4A Schematic diagram of the structure of the first conductive layer in the array substrate. Figure 4E It is shown Figure 4A Schematic diagram of the structure of the second conductive layer in the array substrate. Figure 4F It is shown Figure 4A Schematic diagram of the structure of the third conductive layer in the array substrate depicted in FIG. Figure 4G It is shown Figure 4A Schematic diagram of the structure of the first planarization layer in the array substrate depicted in FIG. Figure 4H It is shown Figure 4A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in FIG. Fig. 4I It is shown Figure 4A Schematic diagram of the structure of the second planarization layer in the array substrate depicted in FIG. Figure 4J It is shown Figure 4AA schematic diagram of the structure of the second signal line layer in the array substrate depicted in FIG. Figure 4K It is shown Figure 4A Schematic diagram of the structure of the third planarization layer in the array substrate depicted in FIG. Figure 4L It is shown Figure 4A Schematic diagram of the structure of the anode layer in the array substrate depicted in FIG. Figure 4M It is shown Figure 4A Schematic diagram of the structure of the pixel defining layer in the array substrate depicted in FIG. Figure 5 is along Figure 4A Cross-sectional view along line A-A'.

[0149] Reference FIG. 4A to FIG. 4M and Figure 5 In some embodiments, the display panel includes: a base substrate BS; a semiconductor material layer SML, which is located on the base substrate BS; a gate insulating layer GI, which is located on a side of the semiconductor material layer SML away from the base substrate BS; a first conductive layer CT1, which is located on a side of the gate insulating layer GI away from the semiconductor material layer SML; an insulating layer IN, which is located on a side of the first conductive layer CT1 away from the gate insulating layer GI; a second conductive layer CT2, which is located on a side of the insulating layer IN away from the first conductive layer CT1; an interlayer dielectric layer ILD, which is located on a side of the second conductive layer CT2 away from the insulating layer IN; a third conductive layer CT3, which is located on a side of the interlayer dielectric layer ILD away from the second conductive layer CT2; a first planarization layer PLN1, It is located on the side of the third conductive layer CT3 away from the interlayer dielectric layer ILD; the first signal line layer SL1 is located on the side of the first planarization layer PLN1 away from the third conductive layer CT3; the second planarization layer PLN2 is located on the side of the first signal line layer SL1 away from the first planarization layer PLN1; the second signal line layer SL2 is located on the side of the second planarization layer PLN2 away from the first signal line layer SL1; the third planarization layer PLN3 is located on the side of the second signal line layer SL2 away from the second planarization layer PLN2; the anode layer ADL is located on the side of the third planarization layer PLN3 away from the second signal line layer SL2; and the pixel defining layer PDL is located on the side of the anode layer ADL away from the substrate BS.

[0150] Reference Figure 2 , Figure 4A and Figure 4C, each pixel driving circuit is marked with a number, and the number indicates the area corresponding to the multiple transistors (including the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9) in each pixel driving circuit. Each pixel driving circuit is also marked with a number, and the number indicates the component of each of the multiple transistors in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1, and a second electrode D1. The second transistor T2 includes an active layer ACT2, a first electrode S2, and a second electrode D2. The third transistor T3 includes an active layer ACT3, a first electrode S3, and a second electrode D3. The fourth transistor T4 includes an active layer ACT4, a first electrode S4, and a second electrode D4. The fifth transistor T5 includes an active layer ACT5, a first electrode S5, and a second electrode D5. The sixth transistor T6 includes an active layer ACT6, a first electrode 6, and a second electrode D6. The seventh transistor T7 includes an active layer ACT7, a first electrode S7, and a second electrode D7. The eighth transistor T8 includes an active layer ACT8, a first electrode S8 and a second electrode D8. The ninth transistor T9 includes an active layer ACT9, a first electrode S9 and a second electrode D9. In one example, the active layers (ACT2, ACT3, ACT4, ACT5, ACT6, ACT8 and ACT9) of the transistors (T2, T3, T4, T5, T6, T8 and T9) in each pixel driving circuit are part of the overall structure. In another example, the active layers (ACT2, ACT3, ACT4, ACT5, ACT6, ACT8 and ACT9) of the transistors (T2, T3, T4, T5, T6, T8 and T9) in each pixel driving circuit, the first electrodes (S2, S3, S4, S5, S6, S8 and S9) and the second electrodes (D2, D3, D4, D5, D6, D8 and D9) are part of the overall structure. In another example, the active layers (ACT1 and ACT7) of the transistors (T1 and T7) in each pixel driving circuit are part of the overall structure. In another example, the active layers (ACT1 and ACT7), the first electrodes (S1 and S7), and the second electrodes (D1 and D7) of the transistors (T1 and T7) in each pixel driving circuit are part of the overall structure. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, ACT7, ACT8, and ACT9) of the transistors (T1, T2, T3, T4, T5, T6, T7, T8, and T9) are located on the same layer.In another example, the active layer (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, ACT7, ACT8 and ACT9) of the transistors (T1, T2, T3, T4, T5, T6, T7, T8 and T9), the first electrodes (S1, S2, S3, S4, S5, S6, S7, S8 and S9) and the second electrodes (D1, D2, D3, D4, D5, D6, D7, D8 and D9) are located on the same layer.

[0151] As used herein, an active layer refers to a component of a transistor including at least a portion of a semiconductor material layer, the orthographic projection of which on the substrate substrate overlaps with the orthographic projection of the gate on the substrate substrate. A first electrode refers to a component of a transistor connected to one side of the active layer, and a second electrode refers to a component of a transistor connected to the other side of the active layer. In the context of a dual-gate transistor (e.g., a third transistor T3), an active layer refers to a component of a transistor including a first portion of a semiconductor material layer, a second portion of a semiconductor material layer, and a third portion between the first portion and the second portion, wherein the orthographic projection of the first portion of the semiconductor material layer on the substrate substrate overlaps with the orthographic projection of the first gate on the substrate substrate, and the orthographic projection of the second portion of the semiconductor material layer on the substrate substrate overlaps with the orthographic projection of the second gate on the substrate substrate. In the context of a dual-gate transistor, a first electrode refers to a component of a transistor connected to a side of the first portion away from the third portion, and a second electrode refers to a component of a transistor connected to a side of the second portion away from the third portion.

[0152] Reference Figure 2 , Figure 4A and Figure 4C , in some embodiments, the semiconductor material layer further includes a plurality of first reference signal line first branches Vref1-1 and a plurality of second reset signal line first branches Vint2-1. In some embodiments, the plurality of first reference signal lines include a plurality of first reference signal line first branches Vref1-1, a plurality of first reference signal line second branches, and a plurality of first reference signal line third branches. Optionally, at least two of the plurality of first reference signal line first branches Vref1-1, the plurality of first reference signal line second branches, and the plurality of first reference signal line third branches are located in different layers. In some embodiments, the plurality of second reset signal lines include a plurality of second reset signal line first branches Vint2-1 and a plurality of second reset signal line second branches. Optionally, the plurality of second reset signal line first branches Vint2-1 and the plurality of second reset signal line second branches are located in different layers.

[0153] In some embodiments, each of the first reference signal line first branches Vref1-1 is connected to the first electrode of the seventh transistor of the pixel driving circuit in the same row. In one example, the active layers (ACT2, ACT3, ACT4, ACT5, ACT6, ACT8 and ACT9), the first electrodes (S2, S3, S4, S5, S6, S8 and S9) and the second electrodes (D2, D3, D4, D5, D6, D8 and D9) of the transistors (T2, T3, T4, T5, T6, T8 and T9) in each pixel driving circuit and the corresponding second reset signal line first branch are part of the integral structure. In some embodiments, each of the second reset signal line first branches Vint2-1 is connected to the first electrode of the eighth transistor of the pixel driving circuit in the same row. In another example, active layers (ACT1 and ACT7), first electrodes (S1 and S7) and second electrodes (D1 and D7) of transistors (T1 and T7) in respective pixel driving circuits and corresponding first reference signal line first branches are part of an integral structure.

[0154] Reference Figure 2 , Figure 4A and Figure 4D In some embodiments, the first conductive layer includes a plurality of scan lines scan, an electrode block including one or more gates G7 of the seventh transistor, an electrode block including one or more gates G1 of the first transistor, an electrode block including one or more gates G2 of the second transistor, an electrode block including one or more gates G4 of the fourth transistor, an electrode block including one or more gates G5 of the fifth transistor, an electrode block including one or more gates G6 of the sixth transistor, and a first capacitor electrode Ce1 of the first capacitor C1. Optionally, at least a portion of the first capacitor electrode Ce1 is the gate of the third transistor T3 (driving transistor of the pixel driving circuit). Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the first conductive layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, and the like. Optionally, multiple scan lines scan, an electrode block including one or more gates G7 of the seventh transistor, an electrode block including one or more gates G1 of the first transistor, an electrode block including one or more gates G2 of the second transistor, an electrode block including one or more gates G4 of the fourth transistor, an electrode block including one or more gates G5 of the fifth transistor, an electrode block including one or more gates G6 of the sixth transistor, and the first capacitor electrode Ce1 of the first capacitor C1 are located on the same layer.

[0155] As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, when multiple scan lines scan and the first capacitor electrode Ce1 are formed due to one or more steps of the same patterning process performed in the same material layer, the multiple scan lines scan and the first capacitor electrode Ce1 are located in the same layer. In another example, by simultaneously performing the steps of forming the multiple scan lines scan and the step of forming the first capacitor electrode Ce1, the multiple scan lines scan and the first capacitor electrode Ce1 can be formed in the same layer. The term "same layer" does not always mean that the thickness of the layer or the height of the layer in the cross-sectional view is the same.

[0156] Reference Figure 2 , Figure 4A and Figure 4E In some embodiments, the second conductive layer includes a plurality of second reference signal lines Vref2, a plurality of first reset signal lines Vint1, a plurality of second light-emitting control signal lines em2, and an electrode block used as a second capacitor electrode Ce2 of the first capacitor C1 and a third capacitor electrode Ce3 of the second capacitor C2. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second conductive layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, a plurality of second reference signal lines Vref2, a plurality of first reset signal lines Vint1, a plurality of second light-emitting control signal lines em2, and an electrode block used as a second capacitor electrode Ce2 of the first capacitor C1 and a third capacitor electrode Ce3 of the second capacitor C2 are located in the same layer.

[0157] Reference Figure 2 , Figure 4A and Figure 4FIn some embodiments, the third conductive layer includes a plurality of first light emitting control signal lines em1 and a fourth capacitor electrode Ce4 of the second capacitor C2. Optionally, the fourth capacitor electrodes of the plurality of pixel driving circuits in the same row are part of the integral structure. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the third conductive layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the third conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the plurality of first light emitting control signal lines em1 and the fourth capacitor electrode Ce4 of the second capacitor C2 are located in the same layer.

[0158] Figure 4G A via extending through the first planarization layer PLN1 is depicted in FIG.

[0159] Reference Figure 2 , Figure 4A and Figure 4H In some embodiments, the first signal line layer includes a first node connection line Cln1, a second node connection line Cln2, a plurality of gate lines GL, a plurality of first compensation control signal lines AZ1, a plurality of second compensation control signal lines AZ2, a plurality of first reference signal lines second branches Vref1-2, a plurality of first voltage supply lines first branches Vdd1, a plurality of reset control signal lines rst, a plurality of second reset signal lines second branches Vint2-2, a voltage signal connection pad VCP, a data signal connection pad DCP and a relay electrode RE.

[0160] The data signal connection pad DCP is configured to connect a corresponding data line among the plurality of data lines to the first electrode of the first transistor T1 .

[0161] The relay electrode RE is connected to the second electrodes of the sixth transistor T6 and the eighth transistor T8. The relay electrode RE is also connected to the anode connection pad in the second signal line layer. The anode connection pad is connected to the anode of the light emitting element in the anode layer.

[0162] The voltage signal connection pad VCP is configured to connect a corresponding first voltage supply line second branch in a plurality of first voltage supply line second branches to a first electrode of the fifth transistor T5. Each first voltage supply line first branch Vdd1 in a plurality of first voltage supply line first branches is connected to a corresponding first voltage supply line second branch in a plurality of first voltage supply line second branches, and is connected to a fourth capacitor electrode of the second capacitor. The plurality of first voltage supply line first branches Vdd1 and the plurality of first voltage supply line second branches form an interconnected first voltage supply network.

[0163] The corresponding first reference signal line second branches in the plurality of first reference signal line second branches Vref1-2 are connected to the first electrodes of the seventh transistors in the pixel driving circuit in the same row, and the first electrodes of these seventh transistors are part of the overall structure having the corresponding first reference signal line first branches in the plurality of first reference signal line first branches. The corresponding first reference signal line second branches in the plurality of first reference signal line second branches Vref1-2 are also connected to one or more first reference signal line third branches in the plurality of first reference signal line third branches in the second signal line layer. The plurality of first reference signal line first branches, the plurality of first reference signal line second branches Vref1-2, and the plurality of first reference signal line third branches form an interconnected reference signal network.

[0164] Each second reset signal line second branch in a plurality of second reset signal line second branches Vint2-2 is connected to a corresponding second reset signal line first branch in a plurality of second reset signal line first branches in the semiconductor material layer. Optionally, the orthographic projection of each second reset signal line second branch on the substrate substrate overlaps at least partially with the orthographic projection of the corresponding second reset signal line first branch on the substrate substrate. Optionally, the orthographic projection of each second reset signal line second branch on the substrate substrate substantially covers (e.g., covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers) the orthographic projection of the corresponding second reset signal line first branch on the substrate substrate.

[0165] In some embodiments, the plurality of compensation control signal lines include a plurality of first compensation control signal lines AZ1 and a plurality of second compensation control signal lines AZ2 .

[0166] In some embodiments, the plurality of first voltage supply lines include a plurality of first voltage supply line first branches Vdd1 and a plurality of first voltage supply line second branches. Optionally, the plurality of first voltage supply line first branches Vdd1 extend in a direction substantially parallel to the first direction DR1. Optionally, the plurality of first voltage supply line second branches extend in a direction substantially parallel to the second direction DR2. As used herein, the term "substantially parallel" refers to an angle in the range of 0 degrees to about 45 degrees, for example, 0 degrees to about 5 degrees, 0 degrees to about 10 degrees, 0 degrees to about 15 degrees, 0 degrees to about 20 degrees, 0 degrees to about 25 degrees, 0 degrees to about 30 degrees. Optionally, the plurality of first voltage supply line first branches Vdd1 and the plurality of first voltage supply line second branches are located at different layers.

[0167] In some embodiments, the plurality of first reference signal lines include a plurality of first reference signal line first branches, a plurality of first reference signal line second branches Vref1-2, and a plurality of first reference signal line third branches. Optionally, the plurality of first reference signal line first branches, the plurality of first reference signal line second branches Vref1-2, and the plurality of first reference signal line third branches are located at different layers. Optionally, the plurality of first reference signal line first branches and the plurality of first reference signal line second branches Vref1-2 extend in a direction substantially parallel to the first direction DR1. Optionally, the plurality of first reference signal line third branches extend in a direction substantially parallel to the second direction DR2.

[0168] In some embodiments, the plurality of second reset signal lines include a plurality of second reset signal line first branches and a plurality of second reset signal line second branches Vint2 - 2. Optionally, the plurality of second reset signal line first branches and the plurality of second reset signal line second branches Vint2 - 2 are located in different layers.

[0169] Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the first signal line layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the first node connection line Cln1, the second node connection line Cln2, a plurality of gate lines GL, a plurality of first compensation control signal lines AZ1, a plurality of second compensation control signal lines AZ2, a plurality of first reference signal lines second branches Vref1-2, a plurality of first voltage supply lines first branches Vdd1, a plurality of reset control signal lines rst, a plurality of second reset signal lines second branches Vint2-2, a voltage signal connection pad VCP, a data signal connection pad DCP and a relay electrode RE are located in the same layer.

[0170] Fig. 4I A via extending through the second planarization layer PLN2 is depicted.

[0171] Reference Figure 2 , Figure 4A and Figure 4J In some embodiments, the second signal line layer includes a plurality of data lines DL, a plurality of first reference signal line third branches Vref1-3, a plurality of first voltage supply line second branches Vdd2, a plurality of second voltage supply lines Vss and an anode connection pad ACP.

[0172] The anode connection pad ACP is connected to the anode of the light emitting element in the anode layer. The anode connection pad ACP is connected to the relay electrode RE in the first signal line layer. The relay electrode RE is also connected to the second electrodes of the sixth transistor T6 and the eighth transistor T8.

[0173] Each first voltage supply line second branch Vdd2 in a plurality of first voltage supply line second branches is connected to a corresponding first voltage supply line first branch in a plurality of first voltage supply line first branches in the first signal line layer. The corresponding first voltage supply line first branch in a plurality of first voltage supply line first branches is also connected to a fourth capacitor electrode of a second capacitor located in a third conductive layer. Each first voltage supply line second branch in a plurality of first voltage supply line second branches Vdd2 is also connected to a voltage signal connection pad VCP in the first signal line layer. The voltage signal connection pad VCP is configured to connect a corresponding first voltage supply line second branch in a plurality of first voltage supply line second branches to a first electrode of a fifth transistor T5. The plurality of first voltage supply line first branches Vdd1 and the plurality of first voltage supply line second branches form an interconnected first voltage supply network.

[0174] Each of the plurality of first reference signal line third branches Vref1-3 is connected to a corresponding first reference signal line second branch in a plurality of first reference signal line second branches in the first signal line layer. A corresponding first reference signal line second branch in a plurality of first reference signal line second branches is also connected to a first electrode of a seventh transistor in a pixel driving circuit in the same row, the seventh transistor being part of an overall structure having a corresponding first reference signal line first branch in a plurality of first reference signal line first branches. The plurality of first reference signal line first branches, the plurality of first reference signal line second branches, and the plurality of first reference signal line third branches Vref1-3 form an interconnected reference signal network.

[0175] In some embodiments, the plurality of first voltage supply lines include a plurality of first voltage supply line first branches and a plurality of first voltage supply line second branches Vdd2. Optionally, the plurality of first voltage supply line first branches extend in a direction substantially parallel to the first direction DR1. Optionally, the plurality of first voltage supply line second branches Vdd2 extend in a direction substantially parallel to the second direction DR2.

[0176] Each second voltage supply line in the plurality of second voltage supply lines Vss is connected to one or more second reset signal line second branches in the plurality of second reset signal line second branches in the first signal line layer. The corresponding second reset signal line second branches in the plurality of second reset signal line second branches are further connected to the corresponding second reset signal line first branches in the plurality of second reset signal line first branches in the semiconductor material layer. The plurality of second voltage supply lines Vss, the plurality of second reset signal line first branches, and the plurality of second reset signal line second branches form an interconnected second voltage supply network.

[0177] In some embodiments, the plurality of first reference signal lines include a plurality of first reference signal line first branches, a plurality of first reference signal line second branches, and a plurality of first reference signal line third branches Vref1-3. Optionally, the plurality of first reference signal line first branches, the plurality of first reference signal line second branches, and the plurality of first reference signal line third branches Vref1-3 are located at different layers. Optionally, the plurality of first reference signal line first branches and the plurality of first reference signal line second branches extend in a direction substantially parallel to the first direction DR1. Optionally, the plurality of first reference signal line third branches Vref1-3 extend in a direction substantially parallel to the second direction DR2.

[0178] Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second signal line layer. For example, the conductive material can be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the second signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, a plurality of data lines DL, a plurality of first reference signal line third branches Vref1-3, a plurality of first voltage supply line second branches Vdd2, a plurality of second voltage supply lines Vss and an anode connection pad ACP are located on the same layer.

[0179] Figure 4K A via extending through the third planarization layer PLN3 is depicted in FIG.

[0180] Reference Figure 2 , Figure 4A and Figure 4L , the array substrate further includes an anode layer ADL. Figure 4L A plurality of sub-pixel openings SA corresponding to the plurality of anodes are indicated in FIG. Figure 4K Vias extending through the third planarization layer PLN3 are depicted. Each anode is connected to a respective anode contact pad through a respective via extending through the third planarization layer PLN3.

[0181] Reference Figure 2 , Figure 4Aand Figure 4M The array substrate further includes a pixel defining layer PDL defining a plurality of sub-pixel openings SA.

[0182] Reference Figure 2 , Figure 4A , Figure 4D , Figure 4E and Figure 5 In some embodiments, the orthographic projection of the electrode block including the second capacitor electrode Ce2 and the third capacitor electrode Ce3 on the substrate substrate BS substantially covers (for example, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers) the orthographic projection of the first capacitor electrode Ce1 on the substrate substrate BS.

[0183] Reference Figure 2 , Figure 4A , Figure 4E , Figure 4F and Figure 5 In some embodiments, except for the hole area H in which a portion of the fourth capacitor electrode Ce4 does not exist, the orthographic projection of the fourth capacitor electrode Ce4 on the base substrate BS completely covers and exceeds the orthographic projection of the electrode block including the second capacitor electrode Ce2 and the third capacitor electrode Ce3 on the base substrate BS. In some embodiments, the first signal line layer includes a second node connection line Cln2 located on a side of the first planarization layer PLN1 away from the electrode block including the second capacitor electrode Ce2 and the third capacitor electrode Ce3. The second node connection line Cln2 is located in the same layer as at least one of the first node connection line Cln1, a plurality of gate lines GL, a plurality of first compensation control signal lines AZ1, a plurality of second compensation control signal lines AZ2, a plurality of first reference signal lines second branches Vref1-2, a plurality of first voltage supply lines first branches Vdd1, a plurality of reset control signal lines rst, a plurality of second reset signal lines second branches Vint2-2, a voltage signal connection pad VCP, a data signal connection pad DCP, or a relay electrode RE.

[0184] In some embodiments, the array substrate further includes a first via hole v1 and a second via hole v2. The first via hole v1 is located in the hole area H and extends through the first planarization layer PLN1 and the interlayer dielectric layer ILD. The second via hole v2 extends through the first planarization layer PLN1, the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, the second node connection line Cln2 is connected to the electrode block including the second capacitor electrode Ce2 and the third capacitor electrode Ce3 through the first via hole v1, and is connected to the semiconductor material layer SML through the second via hole v2. Optionally, as Figure 5As depicted in FIG. 1 , the second node connection line Cln2 is connected to the second electrode D7 of the seventh transistor and / or the second electrode D1 of the first transistor. In one example, the second node connection line Cln2 corresponds to the second node N2.

[0185] In some embodiments, the array substrate further includes a third via hole v3 and a fourth via hole v4. The third via hole v3 extends through the first planarization layer PLN1, the interlayer dielectric layer ILD, and the insulating layer IN. The fourth via hole v4 extends through the first planarization layer PLN1, the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, the first node connection line Cln1 is connected to the first capacitor electrode Ce1 through the third via hole v3, and is connected to the semiconductor material layer SML through the fourth via hole v4. Optionally, as Figure 5 As depicted in FIG. 1 , the first node connection line Cln1 is connected to the second electrode D2 of the second transistor and / or the second electrode D4 of the fourth transistor. In one example, the first node connection line Cln1 corresponds to the first node N1.

[0186] Figure 6 The stacking structure of capacitor electrodes in an array substrate according to some embodiments of the present disclosure is shown. Figure 5 and Figure 6 In some embodiments, the array substrate includes a stacked structure, which includes a first capacitor electrode Ce1, an insulating layer IN, an electrode block including a second capacitor electrode Ce2 and a third capacitor electrode Ce3, an interlayer dielectric layer ILD, and a fourth capacitor electrode Ce4. The first capacitor electrode Ce1, the insulating layer IN, and the electrode block including the second capacitor electrode Ce2 and the third capacitor electrode Ce3 form a first capacitor. The electrode block including the second capacitor electrode Ce2 and the third capacitor electrode Ce3, the interlayer dielectric layer ILD, and the fourth capacitor electrode Ce4 form a second capacitor.

[0187] In some embodiments, the first capacitor electrode Ce1 is located on the first conductive layer CT1; the electrode block including the second capacitor electrode Ce2 and the third capacitor electrode Ce3 is located on the second conductive layer CT2, and the second conductive layer CT2 is located on the side of the insulating layer IN away from the first conductive layer CT1; the fourth capacitor electrode Ce4 is located on the third conductive layer CT3, and the third conductive layer CT3 is located on the side of the interlayer dielectric layer ILD away from the second conductive layer CT2.

[0188] The inventors of the present disclosure have found that by providing a unique stacking structure of capacitor electrodes, the capacitance area can be effectively increased, and crosstalk and flickering caused by leakage can be reduced. By having increased capacitance, noise interference to the gate and drain of the third transistor (driving transistor) during the threshold voltage compensation stage can be reduced, thereby reducing block crosstalk.

[0189] Reference FIG. 4A to FIG. 4J In some embodiments, the semiconductor material layer includes a portion corresponding to the fourth node N4. In some embodiments, the semiconductor material layer includes a fourth node portion N4P, which includes at least a portion of the second electrode of the third transistor T3, at least a portion of the first electrode of the second transistor T2, and at least a portion of the first electrode of the sixth transistor T6. In some embodiments, an orthographic projection of the fourth node portion N4P on the substrate substrate at least partially overlaps with an orthographic projection of a corresponding data line among the plurality of data lines DL on the substrate substrate.

[0190] In some embodiments, the orthographic projection of the fourth node portion N4P on the substrate substrate is substantially covered by the orthographic projection of the combination of the fourth capacitor electrode Ce4 and the corresponding first reset signal line among the plurality of first reset signal lines Vint1 on the substrate substrate (e.g., at least 50% covered, at least 55% covered, at least 60% covered, at least 65% covered, at least 70% covered, at least 75% covered, at least 80% covered, at least 85% covered, at least 90% covered, at least 95% covered, at least 99% covered, or completely covered). The inventors of the present disclosure have found that by making the orthographic projection of the fourth node portion N4P substantially covered by a component having a constant voltage level, the parasitic capacitance between the fourth node portion N4P and the corresponding data line among the plurality of data lines DL can be reduced, thereby preventing the data signal from interfering with the fourth node portion N4P.

[0191] Figure 7 is a schematic diagram showing the structure of a fourth capacitor electrode in some embodiments according to the present disclosure. Figure 8 Schematic diagram showing the structure of the semiconductor material layer, the second conductive layer and the third conductive layer in some embodiments of the present disclosure. FIG. 4A to FIG. 4J , Figure 6 , Figure 7 and Figure 8 In some embodiments, the fourth capacitor electrode Ce4 includes a first portion P1 and a second portion P2. The orthographic projection of the first portion P1 on the substrate substantially covers the orthographic projection of the electrode block including the second capacitor electrode Ce2 and the third capacitor electrode Ce3 on the substrate. The orthographic projection of the second portion P2 on the substrate does not overlap with the orthographic projection of the electrode block including the second capacitor electrode Ce2 and the third capacitor electrode Ce3 on the substrate. The orthographic projection of the fourth node portion N4P on the substrate partially overlaps with the orthographic projection of the second portion P2 on the substrate.

[0192] Optionally, the orthographic projection of the second part P2 on the substrate partially overlaps with the orthographic projection of a corresponding reset control signal line among the multiple reset control signal lines rst on the substrate, and partially overlaps with the orthographic projection of a corresponding second compensation control signal line among the multiple second compensation control signal lines AZ2 on the substrate.

[0193] Reference Figure 4E In some embodiments, a corresponding first reset signal line of the plurality of first reset signal lines Vint1 includes a main body MB, a first protrusion PR1 extending away from the main body MB, and a second protrusion PR2 extending away from the main body MB. The first protrusion PR1 and the second protrusion PR2 extend away from the main body MB in substantially opposite directions. FIG. 4A to FIG. 4J , Figure 6 , Figure 7 and Figure 8 , the orthographic projection of the fourth node portion N4P on the base substrate partially overlaps with the orthographic projection of the first protrusion PR1 and the second protrusion PR2 on the base substrate. Optionally, the orthographic projection of the fourth node portion N4P on the base substrate partially overlaps with the orthographic projection of the portion connecting the first protrusion PR1 and the second protrusion PR2 in the body MB on the base substrate.

[0194] Optionally, the orthographic projection of the fourth node portion N4P on the substrate partially overlaps with the orthographic projection of a first light emitting control signal line among multiple first light emitting control signal lines em1 on the substrate substrate, and partially overlaps with the orthographic projection of a second light emitting control signal line among multiple second light emitting control signal lines em2 on the substrate substrate.

[0195] Fig. 9 Schematic diagram showing the structure of the second signal line layer and the anode layer according to some embodiments of the present disclosure. Fig. 9 In some embodiments, the plurality of data lines include three adjacent data lines (including a first data line DL1, a second data line DL2, and a third data line DL3). In some embodiments, the first data line DL1 is configured to provide a data signal to a first sub-pixel (e.g., a red sub-pixel), the second data line DL2 is configured to provide a data signal to a second sub-pixel (e.g., a green sub-pixel), and the third data line DL3 is configured to provide a data signal to a third sub-pixel (e.g., a blue sub-pixel).

[0196] In some embodiments, the anode layer includes a first anode AD1, a second anode AD2, and a third anode AD3. In some embodiments, the first anode AD1 is an anode in a first sub-pixel (e.g., a red sub-pixel), the second anode AD2 is an anode in a second sub-pixel (e.g., a green sub-pixel), and the third anode AD3 is an anode in a third sub-pixel (e.g., a blue sub-pixel).

[0197] In some embodiments, the orthographic projection of the combination of the anode layers on the base substrate partially overlaps with the orthographic projection of the first data line DL1 on the base substrate, partially overlaps with the orthographic projection of the second data line DL2 on the base substrate, and does not overlap with the orthographic projection of the third data line DL3 on the base substrate. The inventors of the present disclosure have found that by making the orthographic projection of the third data line DL3 not overlap with the orthographic projection of the anode layer, the load of the third data line DL3 can be reduced.

[0198] In some embodiments, the orthographic projection of the first data line DL1 on the substrate partially overlaps with the orthographic projection of the first anode AD1 on the substrate, and partially overlaps with the orthographic projection of the second anode AD2 on the substrate. In some embodiments, the orthographic projection of the second data line DL2 on the substrate partially overlaps with the orthographic projection of the third anode AD3 on the substrate.

[0199] Optionally, the orthographic projection of the first anode AD1 on the base substrate does not overlap with the orthographic projection of the second data line DL2 on the base substrate, and does not overlap with the orthographic projection of the third data line DL3 on the base substrate.

[0200] Optionally, the orthographic projection of the second anode AD2 on the base substrate does not overlap with the orthographic projection of the second data line DL2 on the base substrate, and does not overlap with the orthographic projection of the third data line DL3 on the base substrate.

[0201] Optionally, the orthographic projection of the third anode AD3 on the base substrate does not overlap with the orthographic projection of the first data line DL1 on the base substrate, and does not overlap with the orthographic projection of the third data line DL3 on the base substrate.

[0202] Fig.10 is a schematic diagram showing the structure of an interconnected first voltage supply network in some embodiments according to the present disclosure. Fig.10 In some embodiments, the interconnected first voltage supply network includes a plurality of first voltage supply line first branches Vdd1 and a plurality of first voltage supply line second branches Vdd2. Optionally, the interconnected first voltage supply network further includes an integral structure including a plurality of fourth capacitor electrodes in the same row. Optionally, the plurality of first voltage supply line first branches Vdd1 extend in a direction substantially parallel to the first direction DR1. Optionally, the plurality of first voltage supply line second branches Vdd2 extend in a direction substantially parallel to the second direction DR2. Optionally, the integral structure including the plurality of fourth capacitor electrodes in the same row extends in a direction substantially parallel to the first direction DR1.

[0203] Reference Fig.10, a first voltage supply line second branch among the plurality of first voltage supply line second branches Vdd2 is connected to a corresponding first voltage supply line first branch among the plurality of first voltage supply line first branches Vdd1 through a fifth via v5. A corresponding first voltage supply line first branch among the plurality of first voltage supply line first branches Vdd1 is connected to the fourth capacitor electrode Ce4 through a sixth via v6.

[0204] Fig.11 is a schematic diagram showing the structure of an interconnected reference signal network in some embodiments of the present disclosure. Fig.11 In some embodiments, the interconnection reference signal network includes a plurality of first reference signal line first branches Vref1-1, a plurality of first reference signal line second branches Vref1-2, and a plurality of first reference signal line third branches Vref1-3. Optionally, the plurality of first reference signal line first branches Vref1-1 extend in a direction substantially parallel to the first direction DR1. Optionally, the plurality of first reference signal line second branches Vref1-2 extend in a direction substantially parallel to the first direction DR1. Optionally, the plurality of first reference signal line third branches Vref1-3 extend in a direction substantially parallel to the second direction DR2.

[0205] Reference Fig.11 , the third branch of the first reference signal line in the plurality of first reference signal line third branches Vref1-3 is connected to the second branch of the first reference signal line in the plurality of first reference signal line second branches Vref1-2 through the seventh via v7. The second branch of the first reference signal line in the plurality of first reference signal line second branches Vref1-2 is connected to the first electrode of the seventh transistor through the eighth via v8. The second branch of the first reference signal line in the plurality of first reference signal line second branches Vref1-2 is connected to the first electrode of the seventh transistor in the pixel driving circuit in the same row, and the first electrode of the seventh transistor is part of the overall structure having the first branch of the first reference signal line in the plurality of first reference signal line first branches Vref1-1.

[0206] Fig.12 is a schematic diagram showing the structure of an interconnected second voltage supply network in some embodiments according to the present disclosure. Fig.12In some embodiments, the interconnected second voltage supply network includes a plurality of second voltage supply lines Vss, a plurality of second reset signal line first branches Vint2-1, and a plurality of second reset signal line second branches Vint2-2, and optionally, the plurality of second reset signal line first branches Vint2-1 extend in a direction substantially parallel to the first direction DR1. Optionally, the plurality of second reset signal line second branches Vint2-2 extend in a direction substantially parallel to the first direction DR1. Optionally, the plurality of second voltage supply lines Vss extend in a direction substantially parallel to the second direction DR2.

[0207] Reference Fig.12 The second voltage supply line in the plurality of second voltage supply lines Vss is connected to the second reset signal line second branch in the plurality of second reset signal line second branches Vint2-2 through the ninth via v9. The second reset signal line second branch in the plurality of second reset signal line second branches Vint2-2 is connected to the second reset signal line first branch in the plurality of second reset signal line first branches Vint2-1 through the tenth via v10.

[0208] Optionally, the orthographic projection of each second reset signal line second branch Vint2-2 of the multiple second reset signal line second branches Vint2-2 on the substrate substrate substantially covers (for example, covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers) the orthographic projection of the corresponding second reset signal line first branch Vint2-1 of the multiple second reset signal line first branches Vint2-1 on the substrate substrate.

[0209] Fig.13A is a schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure. Fig. 13B It is shown Fig.13A Schematic diagram of the structure of the semiconductor material layer in the array substrate depicted in FIG. Fig. 13C It is shown Fig.13A A schematic diagram of the structure of the first conductive layer in the array substrate depicted in FIG. Fig.13D It is shown Fig.13A A schematic diagram of the structure of the second conductive layer in the array substrate depicted in FIG. Fig.13E It is shown Fig.13A A schematic diagram of the structure of the interlayer dielectric layer in the array substrate depicted in FIG. Fig.13F It is shown Fig.13A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in FIG. Figure 13G It is shown Fig.13A Schematic diagram of the structure of the first planarization layer in the array substrate depicted in FIG. Fig.13H It is shown Fig.13A A schematic diagram of the structure of the second signal line layer in the array substrate depicted in FIG. Fig.13I It is shown Fig.13A Schematic diagram of the structure of the second planarization layer in the array substrate depicted in FIG. Fig.13J It is shown Fig.13A Schematic diagram of the structure of the anode layer in the array substrate depicted in FIG. Figure 13K It is shown Fig.13A Schematic diagram of the structure of the pixel defining layer in the array substrate depicted in FIG. Fig.14 is along Fig.13A Cross-sectional view along line BB'.

[0210] Reference FIG. 13A to FIG. 13K and Fig.14 In some embodiments, the array substrate includes: a base substrate BS; a semiconductor material layer SML, which is located on the base substrate BS; a gate insulating layer GI, which is located on a side of the semiconductor material layer SML away from the base substrate BS; a first conductive layer CT1, which is located on a side of the gate insulating layer GI away from the semiconductor material layer SML; an insulating layer IN, which is located on a side of the first conductive layer CT1 away from the gate insulating layer GI; a second conductive layer CT2, which is located on a side of the insulating layer IN away from the first conductive layer CT1; an interlayer dielectric layer ILD, which is located on a side of the second conductive layer CT2 away from the insulating layer IN; a first signal line layer SL 1, which is located on the side of the interlayer dielectric layer ILD away from the second conductive layer CT2; the first planarization layer PLN1, which is located on the side of the first signal line layer SL1 away from the interlayer dielectric layer ILD; the second signal line layer SL2, which is located on the side of the first planarization layer PLN1 away from the first signal line layer SL1; the second planarization layer PLN2, which is located on the side of the second signal line layer SL2 away from the first planarization layer PLN1; the anode layer ADL, which is located on the side of the second planarization layer PLN2 away from the second signal line layer SL2; and the pixel defining layer PDL, which is located on the side of the anode layer ADL away from the substrate BS. FIG. 4A to FIG. 4M and Figure 5 Compared with the array substrate depicted in FIG. 13A to FIG. 13K and Fig.14 The array substrate depicted in FIG. 1 does not have the third conductive layer CT3 . FIG. 13A to FIG. 13K and Fig.14 The first signal line layer in the array substrate depicted in FIG. 4 further includes a fourth capacitor electrode Ce4. FIG. 13A to FIG. 13K and Fig.14 The array substrate depicted in FIG. 1 does not include a plurality of first voltage supply line first branches ( FIG. 4A to FIG. 4M and Figure 5 Vdd1 in the array substrate depicted in FIG.

[0211] In some embodiments, the array substrate further includes an eleventh via hole v11 and a twelfth via hole v12. The eleventh via hole v11 extends through the interlayer dielectric layer ILD. The twelfth via hole v12 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, the second node connection line Cln2 is connected to the electrode block including the second capacitor electrode Ce2 and the third capacitor electrode Ce3 through the eleventh via hole v11, and is connected to the semiconductor material layer SML through the twelfth via hole v12. Optionally, as Fig.14 As shown, the second node connection line Cln2 is connected to the second electrode D7 of the seventh transistor and / or the second electrode D1 of the first transistor. In one example, the second node connection line Cln2 corresponds to the second node N2.

[0212] In some embodiments, the array substrate further includes a thirteenth via hole v13 and a fourteenth via hole v14. The thirteenth via hole v13 extends through the interlayer dielectric layer ILD and the insulating layer IN. The fourteenth via hole v14 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, the first node connection line Cln1 is connected to the first capacitor electrode Ce1 through the thirteenth via hole v13, and is connected to the semiconductor material layer SML through the fourteenth via hole v14. Optionally, as Fig.14 As shown, the first node connection line Cln1 is connected to the second electrode D2 of the second transistor and / or the second electrode D4 of the fourth transistor. In one example, the first node connection line Cln1 corresponds to the first node N1.

[0213] In some embodiments, the array substrate includes a stacked structure of capacitor electrodes. In some embodiments, the stacked structure includes a first capacitor electrode Ce1, an insulating layer IN, an electrode block including a second capacitor electrode Ce2 and a third capacitor electrode Ce3, an interlayer dielectric layer ILD, and a fourth capacitor electrode Ce4. The first capacitor electrode Ce1, the insulating layer IN, and the electrode block including the second capacitor electrode Ce2 and the third capacitor electrode Ce3 form a first capacitor. The electrode block including the second capacitor electrode Ce2 and the third capacitor electrode Ce3, the interlayer dielectric layer ILD, and the fourth capacitor electrode Ce4 form a second capacitor.

[0214] In some embodiments, the first capacitor electrode Ce1 is located on the first conductive layer CT1; the electrode block including the second capacitor electrode Ce2 and the third capacitor electrode Ce3 is located on the second conductive layer CT2, and the second conductive layer CT2 is located on the side of the insulating layer IN away from the first conductive layer CT1; the fourth capacitor electrode Ce4 is located on the first signal line layer SL1, and the first signal line layer SL1 is located on the side of the interlayer dielectric layer ILD away from the second conductive layer CT2.

[0215] Fig.15is a schematic diagram showing the structure of an interconnected first voltage supply network in some embodiments according to the present disclosure. Fig.15 In some embodiments, the interconnected first voltage supply network includes a plurality of first voltage supply line second branches Vdd2 and an overall structure including a plurality of fourth capacitor electrodes in the same row. Optionally, the plurality of first voltage supply line second branches Vdd2 extend in a direction substantially parallel to the second direction DR2. Optionally, the overall structure including a plurality of fourth capacitor electrodes in the same row extends in a direction substantially parallel to the first direction DR1. Fig.15 , the first voltage supply line second branch among the plurality of first voltage supply line second branches Vdd2 is connected to the fourth capacitor electrode Ce4 through the fifteenth via hole v15.

[0216] Fig.16A is a schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure. Fig. 16B It is shown Fig.16A Schematic diagram of the structure of the semiconductor material layer in the array substrate depicted in FIG. Fig. 16C It is shown Fig.16A A schematic diagram of the structure of the first conductive layer in the array substrate depicted in FIG. Fig.16D It is shown Fig.16A A schematic diagram of the structure of the second conductive layer in the array substrate depicted in FIG. Fig.16E It is shown Fig.16A A schematic diagram of the structure of the interlayer dielectric layer in the array substrate depicted in FIG. Fig.16F It is shown Fig.16A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in FIG. Figure 16G It is shown Fig.16A Schematic diagram of the structure of the first planarization layer in the array substrate depicted in FIG. Fig.16H It is shown Fig.16A A schematic diagram of the structure of the second signal line layer in the array substrate depicted in FIG. Fig.17 is along Fig.16A Cross-sectional view along line C-C'.

[0217] Reference FIG. 16A to FIG. 1 6K and Fig.17In some embodiments, the array substrate includes: a base substrate BS; a semiconductor material layer SML, which is located on the base substrate BS; a gate insulating layer GI, which is located on a side of the semiconductor material layer SML away from the base substrate BS; a first conductive layer CT1, which is located on a side of the gate insulating layer GI away from the semiconductor material layer SML; an insulating layer IN, which is located on a side of the first conductive layer CT1 away from the gate insulating layer GI; a second conductive layer CT2, which is located on a side of the insulating layer IN away from the first conductive layer CT1; an interlayer dielectric layer ILD, which is located on a side of the second conductive layer CT2 away from the insulating layer IN; a first signal line layer SL 1, which is located on the side of the interlayer dielectric layer ILD away from the second conductive layer CT2; the first planarization layer PLN1, which is located on the side of the first signal line layer SL1 away from the interlayer dielectric layer ILD; the second signal line layer SL2, which is located on the side of the first planarization layer PLN1 away from the first signal line layer SL1; the second planarization layer PLN2, which is located on the side of the second signal line layer SL2 away from the first planarization layer PLN1; the anode layer ADL, which is located on the side of the second planarization layer PLN2 away from the second signal line layer SL2; and the pixel defining layer PDL, which is located on the side of the anode layer ADL away from the substrate BS.

[0218] and FIG. 4A to FIG. 4M and Figure 5 Compared with the array substrate depicted in FIG. 16A to FIG. 1 6K and Fig.17 The array substrate depicted in FIG. 1 does not have the third conductive layer CT3 . FIG. 16A to FIG. 1 6K and Fig.17 The first signal line layer in the array substrate depicted in FIG. 4 further includes a fourth capacitor electrode Ce4. FIG. 16A to FIG. 1 6K and Fig.17 The array substrate depicted in FIG. 1 does not include a plurality of first voltage supply line first branches ( FIG. 4A to FIG. 4M and Figure 5 Vdd1 in the array substrate depicted in FIG.

[0219] and FIG. 13A to FIG. 13K and Fig.14 Compared with the array substrate depicted in FIG. 16A to FIG. 1 6K and Fig.17 The array substrate depicted in FIG further includes a plurality of first voltage supply line third branches Vdd3. Optionally, the plurality of first voltage supply line third branches Vdd3 are located in the semiconductor material layer SML. Optionally, the plurality of first voltage supply line third branches Vdd3 extend in a direction substantially parallel to the first direction DR1. Fig. 16B In an example depicted in , each of the plurality of first voltage supply line third branches Vdd3 is located between a corresponding first reference signal line first branch Vref1-1 and an active layer of a third transistor of a pixel driving circuit in the same row.

[0220] In some embodiments, the array substrate further includes a sixteenth via hole v16 and a seventeenth via hole v17. The sixteenth via hole v16 extends through the interlayer dielectric layer ILD. The seventeenth via hole v17 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, the second node connection line Cln2 is connected to the electrode block including the second capacitor electrode Ce2 and the third capacitor electrode Ce3 through the sixteenth via hole v16, and is connected to the semiconductor material layer SML through the seventeenth via hole v17. Optionally, as Fig.17 As shown, the second node connection line Cln2 is connected to the second electrode D7 of the seventh transistor and / or the second electrode D1 of the first transistor. In one example, the second node connection line Cln2 corresponds to the second node N2.

[0221] In some embodiments, the array substrate further includes an eighteenth via hole v18 and a nineteenth via hole v19. The eighteenth via hole v18 extends through the interlayer dielectric layer ILD and the insulating layer IN. The nineteenth via hole v19 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, the first node connection line Cln1 is connected to the first capacitor electrode Ce1 through the eighteenth via hole v18, and is connected to the semiconductor material layer SML through the nineteenth via hole v19. Optionally, as Fig.17 As shown, the first node connection line Cln1 is connected to the second electrode D2 of the second transistor and / or the second electrode D4 of the fourth transistor. In one example, the first node connection line Cln1 corresponds to the first node N1.

[0222] In some embodiments, the array substrate includes a stacked structure of capacitor electrodes. In some embodiments, the stacked structure includes a corresponding first voltage supply line third branch Vdd3 among a plurality of first voltage supply line third branches Vdd3, a gate insulating layer GI, a first capacitor electrode Ce1, an insulating layer IN, an electrode block including a second capacitor electrode Ce2 and a third capacitor electrode Ce3, an interlayer dielectric layer ILD, and a fourth capacitor electrode Ce4. The first capacitor electrode Ce1, the insulating layer IN, and the electrode block including the second capacitor electrode Ce2 and the third capacitor electrode Ce3 form a first capacitor. The electrode block including the second capacitor electrode Ce2 and the third capacitor electrode Ce3, the interlayer dielectric layer ILD, and the fourth capacitor electrode Ce4 form a first portion of the second capacitor (at Fig.17 The electrode block including the second capacitor electrode Ce2 and the third capacitor electrode Ce3, the insulating layer IN, the gate insulating layer GI, and a portion of a corresponding first voltage supply line third branch Vdd3 in a plurality of first voltage supply line third branches form a second portion of the second capacitor (in Fig.17 Indicated as C2-2).

[0223] In some embodiments, a corresponding first voltage supply line third branch Vdd3 among a plurality of first voltage supply line third branches Vdd3 is located at the semiconductor material layer SML; the first capacitor electrode Ce1 is located at the first conductive layer CT1, and the first conductive layer CT1 is located at a side of the gate insulating layer GI away from the semiconductor material layer SML; the electrode block including the second capacitor electrode Ce2 and the third capacitor electrode Ce3 is located at the second conductive layer CT2, and the second conductive layer CT2 is located at a side of the insulating layer IN away from the first conductive layer CT1; the fourth capacitor electrode Ce4 is located at the first signal line layer SL1, and the first signal line layer SL1 is located at a side of the interlayer dielectric layer ILD away from the second conductive layer CT2.

[0224] Fig.18 is a schematic diagram showing the structure of an interconnected first voltage supply network in some embodiments according to the present disclosure. Fig.18 In some embodiments, the interconnected first voltage supply network includes a plurality of first voltage supply line third branches Vdd3, a plurality of first voltage supply line second branches Vdd2, and an overall structure including a plurality of fourth capacitor electrodes in the same row. Optionally, the plurality of first voltage supply line third branches Vdd3 extend in a direction substantially parallel to the first direction DR1. Optionally, the plurality of first voltage supply line second branches Vdd2 extend in a direction substantially parallel to the second direction DR2. Optionally, the overall structure including a plurality of fourth capacitor electrodes in the same row extends in a direction substantially parallel to the first direction DR1.

[0225] Reference Fig.18 The first voltage supply line second branch Vdd2 is connected to the fourth capacitor electrode Ce4 through the twentieth via v20. The fourth capacitor electrode Ce4 is connected to the corresponding first voltage supply line third branch Vdd3 through the twenty-first via v21.

[0226] Fig.19A is a schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure. Fig.19B It is shown Fig.19A Schematic diagram of the arrangement of multiple pixel driving circuits in an array substrate depicted in FIG.

[0227] Fig.19C It is shown Fig.19A Schematic diagram of the structure of the semiconductor material layer in the array substrate depicted in FIG. Fig.19D It is shown Fig.19A A schematic diagram of the structure of the first conductive layer in the array substrate depicted in FIG. Fig.19E It is shown Fig.19A A schematic diagram of the structure of the second conductive layer in the array substrate depicted in FIG. Fig.19F It is shown Fig.19A Schematic diagram of the structure of the third conductive layer in the array substrate depicted in FIG. Figure 19G It is shown Fig.19A Schematic diagram of the structure of the first planarization layer in the array substrate depicted in FIG. Fig.19H It is shown Fig.19A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in FIG. Fig.19I It is shown Fig.19A Schematic diagram of the structure of the second planarization layer in the array substrate depicted in FIG. Fig.19J It is shown Fig.19A A schematic diagram of the structure of the second signal line layer in the array substrate depicted in FIG. Figure 19K It is shown Fig.19A Schematic diagram of the structure of the third planarization layer in the array substrate depicted in FIG. Figure 19L It is shown Fig.19A Schematic diagram of the structure of the anode layer in the array substrate depicted in FIG. Fig.19M It is shown Fig.19A Schematic diagram of the structure of the pixel defining layer in the array substrate depicted in FIG. Fig. 20 It is shown Fig.19A Schematic diagram of the structure of the semiconductor material layer, the second conductive layer and the third conductive layer in the array substrate depicted in FIG.

[0228] FIG. 19A to FIG. 19M and Fig. 20 The array substrate depicted in Figure 3A The difference from the array substrate depicted in FIG. 3M is that: FIG. 19A to FIG. 19M and Fig. 20 In the array substrate depicted in , the positive projection of the fourth capacitor electrode Ce4 on the base substrate overlaps with the positive projection of the combination of the second electrode D3 of the third transistor T3 and the first electrode S2 of the second transistor T2 on the base substrate by no more than 50% (e.g., no more than 45%, no more than 40%, no more than 35%, no more than 30%, no more than 25%, no more than 20%, no more than 15%, no more than 10%, or no more than 5%); and Figure 3A In the array substrate depicted in Figure 3M, the orthographic projection of the fourth capacitor electrode Ce4 on the substrate overlaps with at least 50% (for example, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90% or at least 95%) of the orthographic projection of the second electrode D3 of the third transistor T3 on the substrate.

[0229] FIG. 19A to FIG. 19M and Fig. 20 The array substrate depicted in Figure 3A The difference between the array substrate depicted in FIG. 3M is that: FIG. 19A to FIG. 19M and Fig. 20 In the array substrate depicted in FIG. 1 , each of the plurality of first reset signal lines Vint1 does not include the first protrusion PR1 and the second protrusion PR2 ; and Figure 3A In the array substrate depicted in FIG. 3M , each of the plurality of first reset signal lines Vint1 includes a main body MB, a first protrusion PR1 extending away from the main body MB, and a second protrusion PR2 extending away from the main body MB. Optionally, FIG. 19A to FIG. 19M and Fig. 20 The first reset signal lines in the array substrate depicted in FIG. 1 have substantially uniform line widths.

[0230] The inventors of the present disclosure have discovered that by setting FIG. 19A to FIG. 19M and Fig. 20 The structure described in the above can reduce the parasitic capacitance between the node N4 and the fourth capacitor electrode Ce4 and between the node N4 and the corresponding first reset signal line. The reduced parasitic capacitance at the node N4 helps to achieve enhanced display uniformity, especially at relatively high refresh rates.

[0231] Fig.21A is a schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure. Fig. 21B It is shown Fig.21A Schematic diagram of the structure of the semiconductor material layer in the array substrate depicted in FIG. Fig. 21C It is shown Fig.21A A schematic diagram of the structure of the first conductive layer in the array substrate depicted in FIG. Fig.21D It is shown Fig.21A A schematic diagram of the structure of the second conductive layer in the array substrate depicted in FIG. Fig.21E It is shown Fig.21A A schematic diagram of the structure of the interlayer dielectric layer in the array substrate depicted in FIG. Fig.21F It is shown Fig.21A A schematic diagram of the structure of the first signal line layer in the array substrate depicted in FIG. Figure 21G It is shown Fig.21A Schematic diagram of the structure of the first planarization layer in the array substrate depicted in FIG. Fig.21H It is shown Fig.21A A schematic diagram of the structure of the second signal line layer in the array substrate depicted in FIG. Fig.21I It is shown Fig.21A Schematic diagram of the structure of the second planarization layer in the array substrate depicted in FIG. Fig.21J It is shown Fig.21A Schematic diagram of the structure of the anode layer in the array substrate depicted in FIG. Figure 21K It is shown Fig.21A Schematic diagram of the structure of the pixel defining layer in the array substrate depicted in FIG. Fig. 22It is shown Fig.21A A schematic diagram of the structure of the semiconductor material layer, the second conductive layer and the first signal line layer in the array substrate depicted in FIG.

[0232] FIG. 21A to FIG. 21K and Fig. 22 The array substrate depicted in FIG. 13A to FIG. 13K The difference between the array substrate described in FIG. 21A to FIG. 21K and Fig. 22 In the array substrate depicted in , the positive projection of the fourth capacitor electrode Ce4 on the base substrate overlaps with the positive projection of the combination of the second electrode D3 of the third transistor T3 and the first electrode S2 of the second transistor T2 on the base substrate by no more than 50% (e.g., no more than 45%, no more than 40%, no more than 35%, no more than 30%, no more than 25%, no more than 20%, no more than 15%, no more than 10%, or no more than 5%); and FIG. 13A to FIG. 13K In the array substrate depicted in , the positive projection of the fourth capacitor electrode Ce4 on the substrate overlaps with at least 50% (for example, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90% or at least 95%) of the positive projection of the second electrode D3 of the third transistor T3 on the substrate.

[0233] FIG. 21A to FIG. 21K and Fig. 22 The array substrate depicted in FIG. 13A to FIG. 13K The difference between the array substrate described in the embodiment is that: FIG. 21A to FIG. 21K and Fig. 22 In the array substrate depicted in FIG. 1 , each of the plurality of first reset signal lines Vint1 does not include the first protrusion PR1 and the second protrusion PR2 ; and FIG. 13A to FIG. 13K In the array substrate depicted in , each of the plurality of first reset signal lines Vint1 includes a main body MB, a first protrusion PR1 extending away from the main body MB, and a second protrusion PR2 extending away from the main body MB. Optionally, FIG. 21A to FIG. 21K and Fig. 22 The first reset signal lines in the array substrate depicted in FIG. 1 have substantially uniform line widths.

[0234] The inventors of the present disclosure have discovered that by setting FIG. 21A to FIG. 21K and Fig. 22 The structure depicted in FIG. 1 can reduce the parasitic capacitance between the node N4 and the fourth capacitor electrode Ce4 and between the node N4 and the corresponding first reset signal line. The reduced parasitic capacitance at the node N4 helps to achieve enhanced display uniformity, especially at relatively high refresh rates.

[0235] Fig.23Ais a schematic diagram showing the structure of an anode layer in an array substrate according to some embodiments of the present disclosure. Fig. 23B Schematic diagram showing the structure of the second signal line layer and the anode layer in the array substrate according to some embodiments of the present disclosure. Figures 4A to 4K , Fig.23A and Fig. 23B , the array substrate includes corresponding gaps extending through corresponding anodes AD. For example, the array substrate includes a first gap GP1 extending through the first anode AD1, a second gap GP2 extending through the second anode AD2, a third gap GP3-1 and a fourth gap GP3-2 extending through the third anode AD3, respectively.

[0236] In some embodiments, the orthographic projection of the insulating material in each gap on the substrate overlaps with the orthographic projection of the corresponding data line on the substrate. For example, the orthographic projection of the insulating material in the first gap GP1 on the substrate overlaps with the orthographic projection of the first data line DL1 on the substrate. The orthographic projection of the insulating material in the second gap GP2 on the substrate overlaps with the orthographic projection of the first data line DL1 on the substrate. The orthographic projection of the insulating material in the third gap GAP3-1 on the substrate overlaps with the orthographic projection of the second data line DL2 on the substrate. The orthographic projection of the insulating material in the fourth gap GAP3-2 on the substrate overlaps with the orthographic projection of the second data line DL2 on the substrate.

[0237] In some embodiments, the length of the first overlapping region along the extension direction of the first corresponding data line is less than the total length of the first anode AD1 along the extension direction of the first corresponding data line, wherein the first overlapping region is the region where the orthographic projection of the first anode AD1 on the substrate overlaps with the orthographic projection of the first corresponding data line on the substrate. Optionally, the length of the second overlapping region along the extension direction of the second corresponding data line is less than the total length of the second anode AD2 along the extension direction of the second corresponding data line, wherein the second overlapping region is the region where the orthographic projection of the second anode AD2 on the substrate overlaps with the orthographic projection of the second corresponding data line on the substrate. Optionally, the length of the third overlapping region along the extension direction of the third corresponding data line is less than the total length of the third anode AD3 along the extension direction of the third corresponding data line, wherein the third overlapping region is the region where the orthographic projection of the third anode AD3 on the substrate overlaps with the orthographic projection of the third corresponding data line on the substrate. Optionally, the first corresponding data line, the second corresponding data line, and the third corresponding data line are selected from the first data line DL1 and the second data line DL2.

[0238] In one example, the length of the first overlapping region along the extension direction of the first data line DL1 is less than the total length of the first anode AD1 along the extension direction of the first data line DL1, wherein the first overlapping region is a region where the orthographic projection of the first anode AD1 on the substrate overlaps with the orthographic projection of the first data line DL1 on the substrate. The length of the second overlapping region along the extension direction of the first data line DL1 is less than the total length of the second anode AD2 along the extension direction of the first data line DL1, wherein the second overlapping region is a region where the orthographic projection of the second anode AD2 on the substrate overlaps with the orthographic projection of the first data line DL1 on the substrate. The length of the third overlapping region along the extension direction of the second data line DL2 is less than the total length of the third anode AD3 along the extension direction of the second data line DL2, wherein the third overlapping region is a region where the orthographic projection of the third anode AD3 on the substrate overlaps with the orthographic projection of the second data line DL2 on the substrate.

[0239] Fig.24A is a schematic diagram showing the structure of an anode layer in an array substrate according to some embodiments of the present disclosure. Fig. 24B is a schematic diagram showing the structure of a second signal line layer and an anode layer in an array substrate according to some embodiments of the present disclosure. Fig.24A and Fig. 24B The individual anodes depicted in Fig.23A and Fig. 23B The first anode AD1 has an increased area compared to the corresponding anode depicted in FIG. 1 to compensate for the reduced light emitting area due to the presence of the corresponding gap. Fig.23A and Fig. 23B Compared with the first anode AD1 in FIG. 1 , the second anode AD2 has an additional portion located on the right side. Fig.23A and Fig. 23B Compared with the second anode AD2 in FIG. 1 , the third anode AD3 has an additional portion located on the right side, and the third anode AD3 has an additional portion located on the right side. Fig.23A and Fig. 23B Compared with the third anode AD2 in FIG. 1 , FIG.

[0240] Fig.25A is a schematic diagram showing the structure of an anode layer in an array substrate according to some embodiments of the present disclosure. Fig.25B Schematic diagram showing the structure of the second signal line layer and the anode layer in the array substrate according to some embodiments of the present disclosure. Figures 4A to 4K , Fig.24A and Fig. 24BCompared to the array substrate depicted in FIG, the orthographic projection of the third anode AD3 on the substrate substrate does not substantially overlap (e.g., at least 80% non-overlapping, at least 85% non-overlapping, at least 90% non-overlapping, at least 95% non-overlapping, at least 97% non-overlapping, at least 98% non-overlapping, at least 99% non-overlapping, or no overlap) with the orthographic projection of the plurality of first voltage supply line second branches Vdd2 on the substrate substrate. On the contrary, in Figures 4A to 4K , Fig.24A and Fig. 24B In the array substrate depicted in , the orthographic projection of the third anode AD3 on the substrate substrate overlaps at least partially (e.g., at least 1%, at least 2%, at least 5%, at least 10%, at least 15% or at least 20%) with the orthographic projection of the second branches Vdd2 of the plurality of first voltage supply lines on the substrate substrate.

[0241] and Figures 4A to 4K , Fig.24A and Fig. 24B Compared to the array substrate depicted in FIG, the overlapping area between the orthographic projection of the second anode AD2 on the base substrate and the orthographic projection of the plurality of first voltage supply line second branches Vdd2 on the base substrate increases.

[0242] In some embodiments, the second anode AD2 is an anode in a green sub-pixel, and the third anode AD3 is an anode in a blue sub-pixel. The overlapping area between the orthographic projection of the second anode AD2 on the substrate substrate and the orthographic projection of the second branches Vdd2 of the plurality of first voltage supply lines on the substrate substrate increases, resulting in an increase in parasitic capacitance between the second anode AD2 and the second branches Vdd2 of the plurality of first voltage supply lines. The overlapping area between the orthographic projection of the third anode AD3 on the substrate substrate and the orthographic projection of the second branches Vdd2 of the plurality of first voltage supply lines on the substrate substrate decreases, resulting in a decrease in parasitic capacitance between the third anode AD3 and the second branches Vdd2 of the plurality of first voltage supply lines.

[0243] The inventors of the present disclosure have found that the green sub-pixel has a relatively higher luminous efficiency than the blue sub-pixel. By increasing the parasitic capacitance between the second anode AD2 and the second branches Vdd2 of the plurality of first voltage supply lines, and reducing the parasitic capacitance between the third anode AD3 and the second branches Vdd2 of the plurality of first voltage supply lines, the luminous efficiency of the green sub-pixel and the blue sub-pixel can be finely tuned to achieve higher display uniformity.

[0244] In some embodiments, the second anode AD2 includes a main body MB and a connection line CL connecting the main body MB to the corresponding anode connection pad. In some embodiments, the orthographic projection of the connection line CL on the substrate substrate overlaps at least partially with the orthographic projection of the second branches Vdd2 of the plurality of first voltage supply lines on the substrate substrate. Optionally, the orthographic projection of the main body MB on the substrate substrate does not overlap with the orthographic projection of the second branches Vdd2 of the plurality of first voltage supply lines on the substrate substrate.

[0245] Fig.26A is a schematic diagram showing the structure of a second conductive layer in an array substrate according to some embodiments of the present disclosure. Fig.26B Schematic diagram showing the structure of a semiconductor material layer and a second conductive layer in an array substrate according to some embodiments of the present disclosure. FIG. 4A to FIG. 4M Compared with the array substrate depicted in Figures 4A to 4K , Fig.26A and Fig.26B Each of the plurality of first reset signal lines Vint1 in the array substrate depicted in FIG. 1 further includes a third protrusion PR3 protruding away from the body MB.

[0246] In some embodiments, the orthographic projection of the third protrusion PR3 on the substrate substrate overlaps at least partially with the orthographic projection of the portion between the two active layer portions (such as two channel portions) of the second transistor T2 in the first adjacent pixel driving circuit of two adjacent pixel driving circuits in the same row of the semiconductor material layer on the substrate substrate, and overlaps at least partially with the orthographic projection of the portion between the two active layer portions (such as two channel portions) of the fourth transistor T4 in the second adjacent pixel driving circuit of two adjacent pixel driving circuits in the same row of the semiconductor material layer on the substrate substrate. The inventors of the present disclosure have found that this unique structure enhances the stability of the second transistor T2 and the fourth transistor T4.

[0247] Fig.27A is a schematic diagram showing the structure of a second conductive layer in an array substrate according to some embodiments of the present disclosure. Fig.27B Schematic diagram showing the structure of a semiconductor material layer and a second conductive layer in an array substrate according to some embodiments of the present disclosure. Figures 4A to 4K , Fig.26A and Fig.26B Compared with the array substrate depicted in Figures 4A to 4K , Fig.27A and Fig.27B The third protrusion PR3 in the array substrate depicted in FIG. 1 is directly connected to the first protrusion PR1. Alternatively, the first protrusion PR1 connects the third protrusion PR3 with the body MB.

[0248] In some embodiments, the orthographic projection of the third protrusion PR3 on the substrate substrate overlaps at least partially with the orthographic projection of the portion between the two active layer portions (such as two channel portions) of the second transistor T2 in the first adjacent pixel driving circuit of two adjacent pixel driving circuits in the same row of the semiconductor material layer on the substrate substrate, and overlaps at least partially with the orthographic projection of the portion between the two active layer portions (such as two channel portions) of the fourth transistor T4 in the second adjacent pixel driving circuit of two adjacent pixel driving circuits in the same row of the semiconductor material layer on the substrate substrate. The inventors of the present disclosure have found that this unique structure enhances the stability of the second transistor T2 and the fourth transistor T4.

[0249] Fig.28A is a schematic diagram showing the structure of a second conductive layer in an array substrate according to some embodiments of the present disclosure. Fig.28B Schematic diagram showing the structure of a semiconductor material layer and a second conductive layer in an array substrate according to some embodiments of the present disclosure. FIG. 4A to FIG. 4M Compared with the array substrate depicted in Figures 4A to 4K , Fig.28A and Fig.28B Each of the plurality of first reset signal lines Vint1 in the array substrate depicted in FIG. 1 further includes a third protrusion PR3 and a fourth protrusion PR4 .

[0250] In some embodiments, Figures 4A to 4K , Fig.28A and Fig.28B The third protrusion PR3 in the array substrate depicted in FIG. 1 is directly connected to the first protrusion PR1. Optionally, the first protrusion PR1 connects the third protrusion PR3 to the body MB. In some embodiments, Figures 4A to 4K , Fig.28A and Fig.28B The fourth protrusion PR4 in the array substrate depicted in FIG. 1 is directly connected to the body MB.

[0251] In some embodiments, the orthographic projection of the third protrusion PR3 on the substrate substrate overlaps at least partially with the orthographic projection of the portion between the two active layer portions (e.g., two channel portions) of the second transistor T2 in the first adjacent pixel drive circuit in two adjacent pixel drive circuits in the same row of the semiconductor material layer on the substrate substrate. In some embodiments, the orthographic projection of the fourth protrusion PR4 on the substrate substrate overlaps at least partially with the orthographic projection of the portion between the two active layer portions (e.g., two channel portions) of the fourth transistor T4 in the second adjacent pixel drive circuit in two adjacent pixel drive circuits in the same row of the semiconductor material layer on the substrate substrate. The inventors of the present disclosure have found that this unique structure enhances the stability of the second transistor T2 and the fourth transistor T4.

[0252] In some embodiments, the orthographic projection of the third protrusion PR3 on the substrate substrate does not substantially overlap with the orthographic projection of any data line on the substrate substrate (e.g., at least 80% non-overlapping, at least 85% non-overlapping, at least 90% non-overlapping, at least 95% non-overlapping, at least 97% non-overlapping, at least 98% non-overlapping, at least 99% non-overlapping, or no overlap). In some embodiments, the orthographic projection of the fourth protrusion PR4 on the substrate substrate does not substantially overlap with the orthographic projection of any data line on the substrate substrate (e.g., at least 80% non-overlapping, at least 85% non-overlapping, at least 90% non-overlapping, at least 95% non-overlapping, at least 97% non-overlapping, at least 98% non-overlapping, at least 99% non-overlapping, or no overlap). The inventors of the present disclosure have found that this unique structure contributes to image display with a relatively high refresh rate.

[0253] In another aspect, the present invention provides a display device, comprising an array substrate as described herein or manufactured by the method described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light emitting diode display device. Optionally, the display device is a micro light emitting diode display device. Optionally, the display device is a mini light emitting diode display device.

[0254] On the other hand, the present disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes: forming a plurality of pixel drive circuits. Optionally, forming each of the plurality of pixel drive circuits includes: forming a drive transistor, forming a data write transistor, forming a first capacitor including a first capacitor electrode and a second capacitor electrode, and forming a second capacitor including a third capacitor electrode and a fourth capacitor electrode. Optionally, the second capacitor electrode and the third capacitor electrode are coupled to the second electrode of the data write transistor. Optionally, the method includes: forming a stacked structure of capacitor electrodes. Optionally, forming a stacked structure includes: forming a first capacitor electrode; forming an insulating layer on the first capacitor electrode; forming an electrode block including a second capacitor electrode and a third capacitor electrode on a side of the insulating layer away from the first capacitor electrode; forming an interlayer dielectric layer on a side of the electrode block away from the insulating layer; and forming a fourth capacitor electrode on a side of the interlayer dielectric layer away from the electrode block.

[0255] For the purpose of illustration and description, the above description of the embodiments of the present invention has been given. It is not exhaustive, nor is it intended to limit the present invention to the precise form or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments are selected and described to explain the principles of the present invention and its best mode practical application, so that those skilled in the art can understand the various embodiments of the present invention and the various modifications suitable for the specific use or implementation under consideration. The scope of the present invention is intended to be defined by the appended claims and their equivalents, wherein all terms are meant to have the broadest reasonable meaning unless otherwise stated. Therefore, the term "the present invention" and the like do not necessarily limit the scope of the claims to a specific embodiment, and the reference to the exemplary embodiments of the present invention does not mean a limitation of the present invention, and such limitation should not be inferred. The present invention is limited only by the spirit and scope of the appended claims. In addition, these claims may involve the use of "first", "second", etc., followed by a noun or element. These terms should be understood as nomenclature, and should not be interpreted as limiting the number of elements modified by these nomenclatures, unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, the elements and assemblies in this disclosure are not intended to be contributed to the public, regardless of whether the element or assembly is clearly described in the appended claims.

Claims

1. An array substrate comprising a plurality of pixel driving circuits; in, Each of the plurality of pixel driving circuits includes a driving transistor, a data writing transistor, a first capacitor including a first capacitor electrode and a second capacitor electrode, and a second capacitor including a third capacitor electrode and a fourth capacitor electrode; wherein the second capacitor electrode and the third capacitor electrode are coupled to the second electrode of the data writing transistor; Wherein, the array substrate comprises a stacked structure of capacitor electrodes; Wherein, the stacking structure comprises: the first capacitor electrode; an insulating layer located on the first capacitor electrode; an electrode block including the second capacitor electrode and the third capacitor electrode, which is located on a side of the insulating layer away from the first capacitor electrode; an interlayer dielectric layer, which is located on a side of the electrode block away from the insulating layer; and The fourth capacitor electrode is located on a side of the interlayer dielectric layer away from the electrode block.

2. The array substrate according to claim 1, wherein: The fourth capacitor electrode is connected to the first voltage supply line.

3. The array substrate according to claim 1, wherein: The first capacitor electrode, the insulating layer and the electrode block form the first capacitor; as well as The electrode block, the interlayer dielectric layer, and the fourth capacitor electrode form at least a portion of the second capacitor.

4. The array substrate according to claim 1, further comprising a plurality of third branches of the first voltage supply lines located in the semiconductor material layer; in, The stacking structure further comprises: a gate insulating layer located on a side of the first capacitor electrode away from the insulating layer; and A corresponding first voltage supply line third branch among the plurality of first voltage supply line third branches is located at a side of the gate insulating layer away from the first capacitor electrode.

5. The array substrate according to claim 4, wherein: The first capacitor electrode, the insulating layer and the electrode block form the first capacitor; The electrode block, the interlayer dielectric layer and the fourth capacitor electrode form a first part of the second capacitor; as well as The electrode block, the insulating layer, the gate insulating layer, and a portion of the third branch of the corresponding first voltage supply line form a second portion of the second capacitor.

6. The array substrate according to any one of claims 1 to 5, further comprising a first node connection line and a second node connection line located in the first signal line layer; in, Each pixel driving circuit further includes a compensation transistor, a first reset transistor and a second reset transistor; The first node connection line connects the first capacitor electrode to the second electrode of the compensation transistor and / or the second electrode of the first reset transistor; as well as The second node connection line connects the electrode block to the second electrode of the data write transistor and / or the second electrode of the second reset transistor.

7. The array substrate according to claim 6, wherein: The first node connection line and the second node connection line are located at a side of the fourth capacitor electrode away from the electrode block.

8. The array substrate according to claim 6, wherein: The first node connection line and the second node connection line are located in the same layer as the fourth capacitor electrode.

9. The array substrate according to any one of claims 1 to 8, further comprising a fourth node portion located in the semiconductor material layer; in, Each pixel driving circuit further includes a compensation transistor and a second light emission control transistor; wherein the fourth node portion includes at least a portion of the second electrode of the driving transistor, at least a portion of the first electrode of the compensation transistor, and at least a portion of the first electrode of the second light emission control transistor; and An orthographic projection of the fourth node portion on the base substrate at least partially overlaps with an orthographic projection of a corresponding data line among the plurality of data lines on the base substrate.

10. The array substrate according to claim 9, wherein: The orthographic projection of the fourth node portion on the base substrate is covered by at least 50% of an orthographic projection of a combination of the fourth capacitor electrode and a corresponding first reset signal line of the plurality of first reset signal lines on the base substrate.

11. The array substrate according to claim 9, wherein: The fourth capacitor electrode includes a first portion and a second portion; The orthographic projection of the first portion on the substrate substantially covers the orthographic projection of the electrode block on the substrate; The orthographic projection of the second portion on the base substrate does not overlap with the orthographic projection of the electrode block on the base substrate; as well as The orthographic projection of the fourth node portion on the base substrate partially overlaps with the orthographic projection of the second portion on the base substrate.

12. The array substrate according to claim 11, wherein: The orthographic projection of the second part on the substrate partially overlaps with the orthographic projection of a corresponding reset control signal line among multiple reset control signal lines on the substrate, and partially overlaps with the orthographic projection of a corresponding second compensation control signal line among multiple second compensation control signal lines on the substrate.

13. The array substrate according to claim 10, wherein: The corresponding first reset signal line includes a main body, a first protrusion extending away from the main body, and a second protrusion extending away from the main body; the first protrusion and the second protrusion extending away from the body in substantially opposite directions; as well as The orthographic projection of the fourth node portion on the base substrate partially overlaps with the orthographic projections of the first protrusion and the second protrusion on the base substrate, and partially overlaps with the orthographic projection of a portion of the body connecting the first protrusion and the second protrusion on the base substrate.

14. The array substrate according to any one of claims 1 to 13, further comprising: a first data line configured to provide a data signal to the first sub-pixel; a second data line configured to provide a data signal to a second sub-pixel; a third data line configured to provide a data signal to a third sub-pixel; a first anode, which is located in the first sub-pixel; a second anode, located in the second sub-pixel; as well as a third anode, located in the third sub-pixel; Among them, the orthographic projection of the combination of the first anode, the second anode and the third anode on the base substrate partially overlaps with the orthographic projection of the first data line on the base substrate, partially overlaps with the orthographic projection of the second data line on the base substrate, and does not overlap with the orthographic projection of the third data line on the base substrate.

15. The array substrate according to claim 14, wherein: The orthographic projection of the first data line on the base substrate partially overlaps with the orthographic projection of the first anode on the base substrate, and partially overlaps with the orthographic projection of the second anode on the base substrate; as well as The orthographic projection of the second data line on the base substrate partially overlaps with the orthographic projection of the third anode on the base substrate.

16. The array substrate according to claim 14, wherein: The length of the first overlapping area along the extension direction of the first corresponding data line is less than the total length of the first anode along the extension direction of the first corresponding data line, wherein the first overlapping area is an area where the orthographic projection of the first anode on the substrate overlaps with the orthographic projection of the first corresponding data line on the substrate; The length of the second overlapping area along the extension direction of the second corresponding data line is less than the total length of the second anode along the extension direction of the second corresponding data line, wherein the second overlapping area is an area where the orthographic projection of the second anode on the base substrate overlaps with the orthographic projection of the second corresponding data line on the base substrate; A length of a third overlapping region along an extension direction of a third corresponding data line is less than a total length of the third anode along the extension direction of the third corresponding data line, and the third overlapping region is a region where an orthographic projection of the third anode on the substrate overlaps with an orthographic projection of the third corresponding data line on the substrate; and The first corresponding data line, the second corresponding data line, and the third corresponding data line are selected from the first data line and the second data line.

17. The array substrate according to any one of claims 1 to 16, further comprising an interconnected first voltage supply network; in, The interconnected first voltage supply network comprises: a plurality of third branches of the first voltage supply lines, which are located in the semiconductor material layer; an overall structure including a plurality of fourth capacitor electrodes in a same row, which are located in a first signal line layer, the first signal line layer being located on a side of the semiconductor material layer away from the substrate; and A plurality of second branches of the first voltage supply lines are located in a second signal line layer, and the second signal line layer is located on a side of the first signal line layer away from the semiconductor material layer.

18. The array substrate according to claim 17, wherein: A portion of a corresponding first voltage supply line third branch of the plurality of first voltage supply line third branches, the electrode block, and one or more insulating material layers between the corresponding first voltage supply line third branch and the electrode block form a portion of the second capacitor.

19. The array substrate according to any one of claims 1 to 5 and claims 14 to 18, wherein: Each pixel driving circuit further includes a compensation transistor, a first reset transistor, a first light emission control transistor, a second light emission control transistor, a second reset transistor, a third reset transistor, a fourth reset transistor, a first node, a second node, a third node and a fourth node; wherein the first node is connected to the first capacitor electrode of the first capacitor, the second electrode of the compensation transistor and the gate of the driving transistor; the second node is connected to the second capacitor electrode of the first capacitor, the third capacitor electrode of the second capacitor, the second electrode of the data write transistor, and the second electrode of the second reset transistor; the third node is connected to the second electrode of the first light emission control transistor, the second electrode of the fourth reset transistor, and the first electrode of the driving transistor; and The fourth node is connected to the second electrode of the driving transistor, the first electrode of the compensation transistor, and the first electrode of the second light emission control transistor. 20 . A display device comprising the array substrate according to claim 1 and one or more integrated circuits connected to the array substrate.

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