Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a substrate (90), a plurality of first signal lines (L1), a plurality of first signal connecting lines (Ls1), a plurality of second signal lines (L2) and a plurality of first bridging parts (41). Orthographic projections of the plurality of first signal lines (L1) on the substrate (90) extend along a first direction (X) and are distributed at intervals along a second direction (Y), and the first direction (X) and the second direction (Y) intersect; orthographic projections of the first signal connecting lines (Ls1) on the substrate (90) extend along a second direction (Y), and the first signal connecting lines (Ls1) are connected between two adjacent first signal lines (L1) in the second direction (Y) so as to form a grid structure with the first signal lines (L1); the second signal lines (L2) and the first signal lines (L1) are located on different conducting layers, and orthographic projections of the multiple second signal lines (L2) on the substrate (90) extend in the second direction (Y) and are distributed at intervals in the first direction (X); each first bridging part (41) is connected between two adjacent second signal lines (L2) in the first direction (X) so as to form a grid structure with the second signal lines (L2); wherein the orthographic projection of the first bridging part (41) on the substrate (90) is located between the orthographic projections of the two adjacent first signal connecting lines (Ls1) on the substrate (90) in the first direction (X), and the orthographic projection of the first bridging part (41) on the substrate (90) is located between the orthographic projections of the two adjacent first signal connecting lines (L1) on the substrate (90). According to the display panel, the first signal lines (L1) and the second signal lines (L2) can form a grid structure, so that the voltage drop of signals on the first signal lines (L1) and the second signal lines (L2) can be reduced.

Description

Display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In the related art, there is a voltage drop in the signal on the signal line of the display panel, which causes uneven display of the display panel.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0004] Summary of the Invention

[0005] According to one aspect of the present disclosure, a display panel is provided, wherein the display panel includes: a substrate, a plurality of first signal lines, a plurality of first signal connection lines, a plurality of second signal lines, and a plurality of first bridge portions. The orthographic projections of the plurality of first signal lines on the substrate extend along a first direction and are spaced apart along a second direction, the first direction and the second direction intersecting; the orthographic projections of the first signal connection lines on the substrate extend along the second direction, and the first signal connection lines are connected between two adjacent first signal lines in the second direction to form a grid structure with the first signal lines; the second signal lines and the first signal lines are located on different conductive layers, and the orthographic projections of the plurality of second signal lines on the substrate extend along the second direction and are spaced apart along the first direction; the first bridge portion is connected between two adjacent second signal lines in the first direction to form a grid structure with the second signal lines; wherein the orthographic projection of the first bridge portion on the substrate is located between the orthographic projections of two adjacent first signal connection lines in the first direction, and the orthographic projection of the first bridge portion on the substrate is located between the orthographic projections of two adjacent first signal lines on the substrate.

[0006] In an exemplary embodiment of the present disclosure, two adjacent first signal connection lines and two adjacent first signal lines connected thereto form a ring structure, wherein the plurality of ring structures include a first ring structure, a second ring structure, and a third ring structure; the first ring structure and the second ring structure are distributed in the first direction, the first ring structure and the third ring structure are distributed in the second direction, and the first ring structure and the third ring structure are staggered in the first direction; the second ring structure and the third ring structure are distributed in the second direction, and the second ring structure and the third ring structure are staggered in the first direction; the first bridging portion whose orthographic projection on the substrate is located within one of the ring structures forms a bridging portion group; the multiple bridge portion groups include a first bridge portion group, a second bridge portion group, and a third bridge portion group, the orthographic projection of the first bridge portion group on the substrate substrate is located within the orthographic projection of the first annular structure on the substrate substrate, the orthographic projection of the second bridge portion group on the substrate substrate is located within the orthographic projection of the second annular structure on the substrate substrate, and the orthographic projection of the third bridge portion group on the substrate substrate is located within the orthographic projection of the third annular structure on the substrate substrate; the first bridge portion group and the second bridge portion group are respectively connected to different second signal lines, the first bridge portion group and the third bridge portion group are connected to at least one identical second signal line, and the second bridge portion group and the third bridge portion group are connected to at least one identical second signal line.

[0007] In an exemplary embodiment of the present disclosure, the first ring structure and the second ring structure share the same first signal connection line, the first ring structure and the third ring structure share a partial structure of the same first signal line, and the second ring structure and the third ring structure share a partial structure of the same first signal line.

[0008] In an exemplary embodiment of the present disclosure, the first bridging portions located between two adjacent first signal lines in the same group are spaced apart in the first direction; the distance between the orthographic projections of the two first signal connection lines on the substrate in each of the annular structures in the first direction is the same or approximately the same, and each of the bridging portion groups includes the same number of the first bridging portions.

[0009] In an exemplary embodiment of the present disclosure, the first bridge portion in the first bridge portion group includes a first sub-bridge portion, the first bridge portion in the second bridge portion group includes a second sub-bridge portion, and the first bridge portion in the third bridge portion group includes a third sub-bridge portion; in the first direction, the orthographic projection of the third sub-bridge portion on the substrate substrate is located between the orthographic projection of the first sub-bridge portion on the substrate substrate and the orthographic projection of the second sub-bridge portion on the substrate substrate; the orthographic projection of the first sub-bridge portion on the substrate substrate and the orthographic projection of the second sub-bridge portion on the substrate substrate are adjacent to each other in the first direction, and the orthographic projection of the first signal connection line on the substrate substrate is located between the orthographic projection of the first sub-bridge portion on the substrate substrate and the orthographic projection of the second sub-bridge portion on the substrate substrate.

[0010] In an exemplary embodiment of the present disclosure, the bridging portion group includes a first bridging portion, the first signal connection lines connected between adjacent first signal lines in the same group form a first signal connection line row, and the first bridging portions located between adjacent first signal lines in the same group form a first bridging portion row; in the first signal connection line rows adjacent in the second direction, the orthographic projections of the first signal connection lines located in different first signal connection line rows on the substrate are alternately distributed in sequence in the first direction; in the first bridging portion rows adjacent in the second direction, the orthographic projections of the first bridging portions located in different first bridging portion rows on the substrate are alternately distributed in sequence in the first direction.

[0011] In an exemplary embodiment of the present disclosure, the orthographic projections of the first signal connection lines in the same row of the first signal connection lines on the substrate are distributed at equal intervals or approximately at equal intervals in the first direction; the orthographic projections of the first bridging portions in the same row of the first bridging portions on the substrate are distributed at equal intervals or approximately at equal intervals in the first direction.

[0012] In an exemplary embodiment of the present disclosure, the display panel includes a light-emitting unit, a power line, and a pixel driving circuit arrayed in the first direction and the second direction. The pixel driving circuit is connected to the first electrode of the light-emitting unit, and the power line is used to provide a high-level power signal to the pixel driving circuit. The second direction is the column direction, and a power line is provided for each column of pixel driving circuits. The display panel also includes: an electrode layer and a pixel definition layer. The electrode layer is located on one side of the substrate. The electrode layer includes a plurality of electrode portions. The electrode portion is used to form the first electrode of the light-emitting unit. The pixel definition layer is located on the side of the electrode layer away from the substrate. A plurality of pixel openings are formed on the pixel definition layer. The pixel openings and the electrode portions are provided correspondingly. The orthographic projection of the pixel opening on the substrate coincides with the orthographic projection of the corresponding electrode portion on the substrate. The plurality of electrode portions include a first electrode portion, a second electrode portion, a third electrode portion, and a fourth electrode portion. Among the plurality of electrode portions connected to the pixel driving circuit in the same row, the first electrode portion, the second electrode portion, the third electrode portion, and the fourth electrode portion are arranged in the row direction in accordance with the first electrode portion. The power lines are alternately distributed one after another; the positive projection of the power lines on the substrate extends along the second direction, and among the adjacent power lines, the power line corresponding to the pixel driving circuit connected to the first electrode portion and the power line corresponding to the pixel driving circuit connected to the fourth electrode portion are connected to form the second signal line, and the power line corresponding to the pixel driving circuit connected to the second electrode portion and the power line corresponding to the pixel driving circuit connected to the third electrode portion are connected to form the second signal line; the pixel driving circuit connected to the first electrode portion is correspondingly provided with the first signal connection line, and the pixel driving circuit connected to the third electrode portion and the fourth electrode portion is correspondingly provided with the first bridge portion, and the first bridge portion is connected between the two power lines in the pixel driving circuit corresponding thereto.

[0013] In an exemplary embodiment of the present disclosure, the first electrode portion is used to form a first electrode of a red light-emitting unit, the second electrode portion and the fourth electrode portion are used to form a first electrode of a green light-emitting unit, and the third electrode portion is used to form a first electrode of a blue light-emitting unit.

[0014] In an exemplary embodiment of the present disclosure, the display panel further includes: a data line, the orthographic projection of the data line on the base substrate extending along the second direction, the data line being used to provide a data signal to the pixel driving circuit; in the correspondingly arranged pixel driving circuit and the first signal connecting line, the orthographic projection of the first signal connecting line on the base substrate is located on a side where the orthographic projection of the data line on the base substrate faces the orthographic projection of the power line on the base substrate.

[0015] In an exemplary embodiment of the present disclosure, the display panel also includes: a first adapter portion, the first adapter portion and the first bridging portion are located in the same conductive layer, the orthographic projection of the first adapter portion on the base substrate is located between the orthographic projections of two adjacent first signal connection lines on the base substrate in the first direction, and the orthographic projection of the first adapter portion on the base substrate is located between the orthographic projections of two adjacent first signal lines on the base substrate; the pixel driving circuits connected to the first electrode portion and the second electrode portion are correspondingly provided with the first adapter portion, the first adapter portion is connected to the corresponding pixel driving circuit, and the first adapter portion is connected to the power line in the pixel driving circuit connected to the corresponding second electrode portion.

[0016] In an exemplary embodiment of the present disclosure, the first bridge portion is also connected to the corresponding pixel driving circuit, and the first bridge portion includes: a first connecting portion, the orthographic projection of the first connecting portion on the substrate extends along the second direction, and the first connecting portion is connected to the pixel driving circuit; the first adapter portion includes: a second connecting portion, the orthographic projection of the second connecting portion on the substrate extends along the second direction, and the second connecting portion is connected to the pixel driving circuit. The display panel also includes: a data line, the orthographic projection of the data line on the substrate extends along the second direction, and the data line is used to provide a data signal to the pixel driving circuit; the orthographic projection of the first connecting portion on the substrate is located between the orthographic projections of two adjacent data lines on the substrate; and / or the orthographic projection of the second connecting portion on the substrate is located between the orthographic projections of two adjacent data lines on the substrate.

[0017] In an exemplary embodiment of the present disclosure, an orthographic projection of the first signal connection line on the base substrate and an orthographic projection of the electrode portion on the base substrate do not overlap.

[0018] In an exemplary embodiment of the present disclosure, the first electrode portion includes a first side, the orthographic projection of the first side on the substrate intersecting the second direction. The first signal connection line includes a first sub-segment and a second sub-segment, the orthographic projection of the first sub-segment on the substrate being parallel to the orthographic projection of the first side on the substrate; and the second sub-segment connected to the first sub-segment, the orthographic projection of the second sub-segment on the substrate being parallel to the second direction.

[0019] In an exemplary embodiment of the present disclosure, the display panel further includes a pixel driving circuit, the pixel driving circuit including a driving transistor and a fifth transistor, wherein a first electrode of the fifth transistor is connected to a power line, and a second electrode is connected to the first electrode of the driving transistor. The display panel further includes: a first active layer, the first active layer being located on one side of the base substrate, the first active layer including a third active portion and a fifth active portion, the third active portion being used to form a channel region of the driving transistor, and the fifth active portion being used to form a channel region of the fifth transistor; an orthographic projection of the first signal connection line on the base substrate being located on a side of the orthographic projection of the third active portion on the base substrate that is close to the orthographic projection of the fifth active portion on the base substrate.

[0020] In an exemplary embodiment of the present disclosure, the display panel also includes a light-emitting unit, a pixel driving circuit, a power line, and a second initial signal line. The pixel driving circuit is connected to the first electrode of the light-emitting unit, the power line is used to provide a high-level power signal to the pixel driving circuit, and the second initial signal line is used to provide an initial signal line to the first electrode of the light-emitting unit; the first signal line is used to form the second initial signal line, and / or the second signal line is used to form the power line.

[0021] In an exemplary embodiment of the present disclosure, the first signal line, the first signal connection line, and the first bridge portion are located in the same conductive layer, and the first signal line and the first signal connection line are connected in the same layer; multiple second signal lines are located in the same conductive layer.

[0022] In an exemplary embodiment of the present disclosure, the display panel includes a pixel driving circuit and a light-emitting unit, and the pixel driving circuit includes a driving transistor, a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a capacitor; the first electrode of the first transistor is connected to the first initial signal line, and the second electrode is connected to the gate of the driving transistor; the first electrode of the second transistor is connected to the gate of the driving transistor, and the second electrode is connected to the second electrode of the driving transistor; the first electrode of the fourth transistor is connected to the data line, and the second electrode is connected to the first electrode of the driving transistor; the first electrode of the fifth transistor is connected to the power line, and the second electrode is connected to the first electrode of the driving transistor; the first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light-emitting unit; the first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode is connected to the first electrode of the light-emitting unit; the first electrode of the capacitor is connected to the gate of the driving transistor, and the second electrode is connected to the power line.

[0023] In an exemplary embodiment of the present disclosure, the display panel further includes: a first active layer, a first conductive layer, a second active layer, and a third conductive layer, wherein the first active layer is located on one side of the substrate base, and the first active layer includes a third active portion, a fourth active portion, a fifth active portion, a sixth active portion, and a seventh active portion, wherein the third active portion is used to form a channel region of the driving transistor, the fourth active portion is used to form a channel region of the fourth transistor, the fifth active portion is used to form a channel region of the fifth transistor, the sixth active portion is used to form a channel region of the sixth transistor, and the seventh active portion is used to form a channel region of the seventh transistor. The first conductive layer is located on a side of the first active layer facing away from the base substrate, the first conductive layer includes a first gate line, an enable signal line, a second reset signal line, and a first conductive portion, the orthographic projection of the first gate line on the base substrate extends along the first direction and covers the orthographic projection of the fourth active portion on the base substrate, the orthographic projection of the enable signal line on the base substrate extends along the first direction and covers the orthographic projection of the fifth active portion on the base substrate and the orthographic projection of the sixth active portion on the base substrate, the orthographic projection of the second reset signal line on the base substrate extends along the first direction and covers the orthographic projection of the fifth active portion on the base substrate and the orthographic projection of the sixth active portion on the base substrate, The orthographic projection of the seventh active portion on the substrate substrate, the orthographic projection of the first conductive portion on the substrate substrate covers the orthographic projection of the third active portion on the substrate substrate; the second active layer is located on the side of the first conductive layer away from the substrate substrate, the second active layer includes a first active portion and a second active portion, the first active portion is used to form a channel region of the first transistor, and the second active portion is used to form a channel region of the second transistor; the third conductive layer is located on the side of the second active layer away from the substrate substrate, the third conductive layer includes a second gate line and a first reset signal line, the orthographic projection of the second gate line on the substrate substrate extends along the first direction and covers the orthographic projection of the second active portion on the substrate substrate, the orthographic projection of the first reset signal line on the substrate substrate extends along the first direction and covers the orthographic projection of the first active portion on the substrate substrate; wherein the orthographic projection of the second reset signal line on the substrate substrate, the orthographic projection of the enable signal line on the substrate substrate, the orthographic projection of the first conductive portion on the substrate substrate, the orthographic projection of the second gate line on the substrate substrate, the orthographic projection of the first gate line on the substrate substrate, and the orthographic projection of the first reset signal line on the substrate substrate are distributed in sequence along the second direction.

[0024] In an exemplary embodiment of the present disclosure, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are P-type transistors, and the first transistor and the second transistor are N-type transistors.

[0025] According to one aspect of the present disclosure, a display panel is provided, comprising: a base substrate, a plurality of first signal lines, a plurality of first signal connection lines, a plurality of second signal lines, and a plurality of first bridging portions, wherein the orthographic projections of the plurality of first signal lines on the base substrate extend along a first direction and are spaced apart along a second direction, the first direction and the second direction intersecting; the orthographic projections of the first signal connection lines on the base substrate extend along the second direction, the first signal connection lines are connected between two adjacent first signal lines in the second direction to form a grid structure with the first signal lines; the second signal lines and the first signal lines are located on different conductive layers, the orthographic projections of the plurality of second signal lines on the base substrate extend along the second direction and are spaced apart along the first direction; the first bridging portions are configured to electrically connect to the second signal lines to form a grid structure with the second signal lines; wherein the orthographic projection of the first bridging portion on the base substrate is located between the orthographic projections of two adjacent first signal connection lines on the base substrate in the first direction, and the orthographic projection of the first bridging portion on the base substrate is located between the orthographic projections of two adjacent first signal lines on the base substrate.

[0026] According to one aspect of the present disclosure, a display device is provided, comprising the above-mentioned display panel.

[0027] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0029] FIG1 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0030] FIG2 is a structural diagram of the fourth conductive layer in FIG1 ;

[0031] FIG3 is a structural diagram of the fifth conductive layer in FIG1 ;

[0032] FIG4 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0033] FIG5 is a structural diagram of the fourth conductive layer in FIG1 ;

[0034] FIG6 is a structural diagram of the fifth conductive layer in FIG1 ;

[0035] FIG7 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0036] FIG8 is a structural diagram of the fourth conductive layer in FIG1 ;

[0037] FIG9 is a structural diagram of the fifth conductive layer in FIG1 ;

[0038] FIG10 is a schematic diagram of the circuit structure of a pixel driving circuit in a display panel disclosed herein;

[0039] FIG11 is a timing diagram of each node in a driving method of the pixel driving circuit in FIG10 ;

[0040] FIG12 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0041] FIG13 is a structural diagram of the shielding layer in FIG12 ;

[0042] FIG14 is a structural diagram of the first active layer in FIG12;

[0043] FIG15 is a structural diagram of the first conductive layer in FIG12;

[0044] FIG16 is a structural diagram of the second conductive layer in FIG12;

[0045] FIG17 is a structural diagram of the second active layer in FIG12;

[0046] FIG18 is a structural diagram of the third conductive layer in FIG12;

[0047] FIG19 is a structural layout diagram of the fourth conductive layer in FIG12;

[0048] FIG20 is a structural layout diagram of the fifth conductive layer in FIG12;

[0049] FIG21 is a structural layout diagram of the electrode layer and pixel definition layer in FIG12;

[0050] FIG22 is a structural diagram of the shielding layer and the first active layer in FIG12;

[0051] FIG23 is a structural layout diagram of the shielding layer, the first active layer, and the first conductive layer in FIG12;

[0052] FIG24 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, and the second conductive layer in FIG12 ;

[0053] FIG25 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in FIG12 ;

[0054] FIG26 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in FIG12 ;

[0055] FIG27 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in FIG12 ;

[0056] FIG28 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer, and the pixel definition layer in FIG12 ;

[0057] FIG29 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0058] FIG30 is a structural layout diagram of the fourth conductive layer in FIG29;

[0059] FIG31 is a structural layout diagram of the fifth conductive layer in FIG29;

[0060] FIG32 is a partial cross-sectional view of the display panel shown in FIG12 taken along dotted line AA. DETAILED DESCRIPTION

[0061] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent like or similar structures, and thus their detailed description will be omitted.

[0062] The terms "a", "an", and "said" are used to indicate that there are one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.

[0063] This exemplary embodiment first provides a display panel, which may include a base substrate, a fourth conductive layer, and a fifth conductive layer stacked in sequence, as shown in Figures 1-3. Figure 1 is a structural layout of an exemplary embodiment of the display panel disclosed in the present invention, Figure 2 is a structural layout of the fourth conductive layer in Figure 1, and Figure 3 is a structural layout of the fifth conductive layer in Figure 1.

[0064] The fourth conductive layer may include a plurality of first signal lines L1, a plurality of first signal connection lines Ls1, and a plurality of first bridges 41. The orthographic projections of the plurality of first signal lines L1 on the base substrate extend along a first direction X and are spaced apart along a second direction Y, with the first direction X and the second direction Y intersecting. For example, the first direction X may be a row direction, and the second direction Y may be a column direction. The orthographic projections of the first signal connection lines L1 on the base substrate extend along the second direction Y, and the first signal connection lines Ls1 are connected between two adjacent first signal lines L1 in the second direction Y, forming a grid structure with the first signal lines L1. The fifth conductive layer may include a plurality of second signal lines L2, which are located on a different conductive layer from the first signal lines L1. The orthographic projections of the plurality of second signal lines L2 on the base substrate extend along the second direction Y and are spaced apart along the first direction X. The first bridges 41 are connected between two adjacent second signal lines L2 in the first direction X, forming a grid structure with the second signal lines L2. The second signal lines L2 may be connected to the first bridges 41 via vias H. The orthographic projection of the first bridge portion 41 on the base substrate is located between the orthographic projections of two adjacent first signal connection lines Ls1 on the base substrate in the first direction X, and the orthographic projection of the first bridge portion 41 on the base substrate is located between the orthographic projections of two adjacent first signal lines L1 on the base substrate.

[0065] In this exemplary embodiment, the first signal lines L1 and the second signal lines L2 can provide different signals. The first signal lines L1 and the second signal lines L2 can form a grid structure. The first signal lines L1 and the second signal lines L2 in the grid structure have low resistance, thereby minimizing voltage drops between the first signal lines L1 at different locations on the display panel and minimizing voltage drops between the second signal lines L2 at different locations on the display panel. This arrangement can improve display uniformity and reduce power consumption of the display panel.

[0066] As shown in Figures 1-3, the first signal line L1, the first signal connection line Ls1, and the first bridge portion 41 are located in the same conductive layer. It should be understood that in other exemplary embodiments, the first signal line L1, the first signal connection line Ls1, and the first bridge portion 41 may also be located in any other conductive layer. For example, the first signal line L1, the first signal connection line Ls1, and the first bridge portion 41 may be located in different conductive layers; for another example, the first signal connection line Ls1 and the first bridge portion 41 are located in the same conductive layer, and the first signal connection line Ls1 and the first signal line L1 are located in different conductive layers.

[0067] In this exemplary embodiment, as shown in Figures 1-3, two adjacent first signal connection lines Ls1 and two adjacent first signal lines L1 connected thereto form a ring structure K, and the multiple ring structures K include a first ring structure K1, a second ring structure K2, and a third ring structure K3; the first ring structure K1 and the second ring structure K2 are distributed in the first direction X, the first ring structure K1 and the third ring structure K3 are distributed in the second direction Y, and the first ring structure K1 and the third ring structure K3 are staggered in the first direction X; the second ring structure K2 and the third ring structure K3 are distributed in the second direction Y, and the second ring structure K2 and the third ring structure K3 are staggered in the first direction X; the first bridge portion 41 whose orthographic projection on the substrate is located in the same ring structure K forms a bridge portion group N41; multiple bridges The connection portion group N41 includes a first bridging portion group N411, a second bridging portion group N412, and a third bridging portion group N413. The orthographic projection of the first bridging portion group N411 on the substrate substrate is located within the orthographic projection of the first annular structure K1 on the substrate substrate. The orthographic projection of the second bridging portion group N412 on the substrate substrate is located within the orthographic projection of the second annular structure K2 on the substrate substrate. The orthographic projection of the third bridging portion group N413 on the substrate substrate is located within the orthographic projection of the third annular structure K3 on the substrate substrate. The first bridging portion group N411 and the second bridging portion group N412 are respectively connected to different second signal lines L2, the first bridging portion group N411 and the third bridging portion group N413 are connected to at least one identical second signal line L2, and the second bridging portion group N412 and the third bridging portion group N413 are connected to at least one identical second signal line L2.

[0068] In this exemplary embodiment, no first bridge is provided between the second signal lines L2 connected to the first bridge group N411 and the second signal lines L2 connected to the second bridge group N412. The first signal connection line Ls1 can be provided in the position where the first bridge is not provided. Furthermore, in this exemplary embodiment, the third bridge group N413 connects the second signal lines L2 correspondingly connected to the first bridge group N411 and the second bridge group N412, thereby enabling each second signal line L2 to be connected via the bridge group N41.

[0069] As shown in Figures 1-3, in this exemplary embodiment, the multiple second signal lines L2 connected to any bridge portion group N41 can be divided into two parts, and the two parts of the second signal lines L2 can be respectively connected to two bridge portion groups N41 distributed in the second direction of the bridge portion group N41.

[0070] As shown in Figures 1-3, in this exemplary embodiment, the first ring structure K1 and the second ring structure K2 can share the same first signal connection line Ls1, the first ring structure K1 and the third ring structure K3 can share the same partial structure of the first signal line L1, and the second ring structure K2 and the third ring structure K3 can share the same partial structure of the first signal line L1.

[0071] It should be understood that in other exemplary embodiments, the first annular structure K1 and the second annular structure K2 may also be spaced apart in the first direction X, the first annular structure K1 and the third annular structure K3 may also be spaced apart in the second direction Y, and the second annular structure K2 and the third annular structure K3 may also be spaced apart in the second direction Y. As shown in Figures 4-6, Figure 4 is a structural layout diagram of an exemplary embodiment of the display panel of the present disclosure, Figure 5 is a structural layout diagram of the fourth conductive layer in Figure 1, and Figure 6 is a structural layout diagram of the fifth conductive layer in Figure 1. Among them, the first annular structure K1 and the third annular structure K3 may also be spaced apart in the second direction Y, and the second annular structure K2 and the third annular structure K3 may also be spaced apart in the second direction Y.

[0072] As shown in Figures 1-3, the bridging portion group N41 includes a first bridging portion 41, and the first signal connection lines Ls1 connected between the same group of adjacent first signal lines L1 form a first signal connection line row, and the first bridging portions 41 located between the same group of adjacent first signal lines L1 form a first bridging portion row; in the first signal connection line rows adjacent in the second direction Y, the orthographic projections of the first signal connection lines Ls1 located in different first signal connection line rows on the substrate are alternately distributed in sequence in the first direction; in the first bridging portion rows adjacent in the second direction Y, the orthographic projections of the first bridging portions 41 located in different first bridging portion rows on the substrate are alternately distributed in sequence in the first direction X.

[0073] In this exemplary embodiment, the orthographic projections of the first signal connection lines Ls1 in the same first signal connection line row on the substrate are equally spaced or approximately equally spaced in the first direction; and the orthographic projections of the first bridge portions 41 in the same first bridge portion row on the substrate are equally spaced or approximately equally spaced in the first direction. The structures A being approximately equally spaced in one direction can be understood as meaning that the maximum distance between adjacent structures A in the first direction is L1, the minimum distance between adjacent structures A in the first direction is L2, and (L1-L2) / L1 is less than or equal to 0.2. For example, (L1-L2) / L1 can be 0.2, 0.1, 0.05, etc.

[0074] It should be understood that in other exemplary embodiments, the bridge portion group N41 may include multiple first bridge portions 41. As shown in Figures 7-9, Figure 7 is a structural layout diagram of an exemplary embodiment of a display panel of the present disclosure, Figure 8 is a structural layout diagram of the fourth conductive layer in Figure 1, and Figure 9 is a structural layout diagram of the fifth conductive layer in Figure 1. Specifically, the bridge portion group N41 may include multiple first bridge portions 41.

[0075] As shown in Figures 1-3, the first bridging portions 41 located between two adjacent first signal lines L1 in the same group are spaced apart in the first direction X. The distance between the orthographic projections of the two first signal connection lines Ls1 on the substrate in each of the ring structures K in the first direction X can be the same or approximately the same, and each of the bridging portion groups N41 can include the same number of first bridging portions. It should be noted that the approximately same distance between the orthographic projections of the two first signal connection lines Ls1 on the substrate in each of the ring structures K in the first direction X can be understood as follows: the maximum value of the distance between the orthographic projections of the two first signal connection lines Ls1 on the substrate in each of the ring structures K in the first direction X is S1, the minimum value of the distance between the orthographic projections of the two first signal connection lines Ls1 on the substrate in each of the ring structures K in the first direction X is S2, and (S1-S2) / S1 is less than or equal to 0.2. For example, (S1-S2) / S1 can be equal to 0.2, 0.1, 0.05, etc.

[0076] It should be understood that, in other exemplary embodiments, different bridging portion groups N41 also include different numbers of the first bridging portions.

[0077] As shown in FIG1-9 , the first bridge portion in the first bridge portion group N411 includes a first sub-bridge portion 411, the first bridge portion in the second bridge portion group N412 includes a second sub-bridge portion 412, and the first bridge portion in the third bridge portion group N413 includes a third sub-bridge portion 413. In the first direction, the orthographic projection of the third sub-bridge portion 413 on the substrate is located between the orthographic projection of the first sub-bridge portion 411 on the substrate and the orthographic projection of the second sub-bridge portion 412 on the substrate. The orthographic projection of the first sub-bridge portion 411 on the substrate and the orthographic projection of the second sub-bridge portion 412 on the substrate are adjacent to each other in the first direction X, that is, no other first bridge portion is provided between the first sub-bridge portion 411 and the second sub-bridge portion 412. The empty space between the first sub-bridge portion 411 and the second sub-bridge portion 412 can be used to set the first signal connection line Ls1, and the orthographic projection of the first signal connection line Ls1 on the base substrate is located between the orthographic projection of the first sub-bridge portion 411 on the base substrate and the orthographic projection of the second sub-bridge portion 412 on the base substrate.

[0078] In this exemplary embodiment, the first signal line and the second signal line can respectively provide any signal to the display panel. For example, the first signal line and the second signal line can be used to provide a high-level power signal, a low-level power signal, an initial signal, etc.

[0079] As shown in FIG10 , a circuit structure diagram of a pixel driving circuit in a display panel of the present disclosure is shown. The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. The first electrode of the fourth transistor T4 is connected to the data signal terminal Da, and the fourth transistor T4 is connected to the data signal terminal Da. The second electrode of the fourth transistor T4 is connected to the first electrode of the driving transistor T3, and the gate of the fourth transistor T4 is connected to the first gate driving signal terminal Gate1; the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor T3, and the gate of the fifth transistor T5 is connected to the enable signal terminal EM; the gate of the driving transistor T3 is connected to the node N; the first electrode of the second transistor T2 is connected to the node N, the second electrode of the second transistor T2 is connected to the second electrode of the driving transistor T3, and the gate of the second transistor T2 is connected to the second gate driving signal terminal Gate2; the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7, the gate of the sixth transistor T6 is connected to the enable signal terminal EM, the first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate of the seventh transistor T7 is connected to the second reset signal terminal Re2; the second electrode of the first transistor T1 is connected to the node N, the first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit1, and the gate of the first transistor T1 is connected to the first reset signal terminal Re1; the first electrode of the capacitor C is connected to the node N, and the second electrode of the capacitor C is connected to the first power supply terminal VDD. The pixel driving circuit can be connected to a light-emitting unit (OLED) and configured to drive the light-emitting unit (OLED) to emit light. The first electrode of the light-emitting unit (OLED) can be connected to the second electrode of the sixth transistor T6, and the second electrode of the light-emitting unit can be connected to the second power supply terminal VSS. The first electrode of the light-emitting unit can be the anode of the light-emitting unit, and the second electrode of the light-emitting unit can be the cathode of the light-emitting unit. The first transistor T1 and the second transistor T2 can be N-type transistors, for example, N-type metal oxide transistors. N-type transistors have low leakage current, thereby preventing leakage of node N through the first transistor T1 and the second transistor T2 during the light-emitting phase. Meanwhile, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type transistors, for example, P-type low-temperature polysilicon transistors. P-type transistors have high carrier mobility, thereby facilitating the realization of a display panel with high resolution, high response speed, high pixel density, and high aperture ratio. The first initial signal terminal and the second initial signal terminal can output the same or different voltage signals, depending on actual conditions.

[0080] FIG11 is a timing diagram of each node in a driving method for the pixel driving circuit in FIG10 . Gate1 represents the timing of the first gate driving signal terminal Gate1, Gate2 represents the timing of the second gate driving signal terminal Gate2, Re1 represents the timing of the first reset signal terminal Re1, Re2 represents the timing of the second reset signal terminal Re2, EM represents the timing of the enable signal terminal EM, and Da represents the timing of the data signal terminal Da. The driving method for the pixel driving circuit may include a reset phase t1, a data writing phase t2, and a light-emitting phase t3. During the reset phase t1, the first reset signal terminal Re1 outputs a high-level signal, the second reset signal terminal Re2 outputs a low-level signal, the first transistor T1 and the seventh transistor T7 are turned on, the first initial signal terminal Vinit1 inputs a first initial signal to the node N, and the second initial signal terminal Vinit2 inputs a second initial signal to the first electrode of the light-emitting unit OLED. In the data writing phase t2: the second gate drive signal terminal Gate2 outputs a high-level signal, the first gate drive signal terminal Gate1 outputs a low-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and at the same time, the data signal terminal Da outputs a data signal to write the compensation voltage Vdata+Vth to the node N, where Vdata is the voltage of the data signal and Vth is the threshold voltage of the driving transistor T3. In the light-emitting phase t3: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the compensation voltage Vdata+Vth stored in the capacitor C. The output current I of the driving transistor in the pixel driving circuit of the present disclosure is (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 . Wherein, I is the output current of the driving transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor. This pixel driving circuit can avoid the influence of the threshold of the driving transistor on its output current. It should be understood that in other exemplary embodiments, the pixel driving circuit can also have other driving methods. For example, the seventh transistor T7 can reset the first electrode of the light-emitting unit in the period between the data writing stage t2 and the light-emitting stage t3.

[0081] In this exemplary embodiment, the display panel may include a base substrate, a blocking layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, an electrode layer, and a pixel definition layer stacked in sequence, wherein an insulating layer may be arranged between the above adjacent layers. As shown in Figures 12-28, Figure 12 is a structural layout diagram of an exemplary embodiment of the display panel disclosed herein, Figure 13 is a structural layout diagram of the blocking layer in Figure 12, Figure 14 is a structural layout diagram of the first active layer in Figure 12, Figure 15 is a structural layout diagram of the first conductive layer in Figure 12, Figure 16 is a structural layout diagram of the second conductive layer in Figure 12, Figure 17 is a structural layout diagram of the second active layer in Figure 12, Figure 18 is a structural layout diagram of the third conductive layer in Figure 12, Figure 19 is a structural layout diagram of the fourth conductive layer in Figure 12, Figure 20 is a structural layout diagram of the fifth conductive layer in Figure 12, Figure 21 is a structural layout diagram of the electrode layer and the pixel definition layer in Figure 12, Figure 22 is a structural layout diagram of the blocking layer and the first active layer in Figure 12, and Figure 23 is a structural layout diagram of the blocking layer, the first active layer, and the first conductive layer in Figure 12. Figure 24 is a structural layout diagram of the shielding layer, first active layer, first conductive layer, and second conductive layer in Figure 12. Figure 25 is a structural layout diagram of the shielding layer, first active layer, first conductive layer, second conductive layer, and second active layer in Figure 12. Figure 26 is a structural layout diagram of the shielding layer, first active layer, first conductive layer, second conductive layer, second active layer, and third conductive layer in Figure 12. Figure 27 is a structural layout diagram of the shielding layer, first active layer, first conductive layer, second conductive layer, second active layer, third conductive layer, and fourth conductive layer in Figure 12. Figure 28 is a structural layout diagram of the shielding layer, first active layer, first conductive layer, second conductive layer, second active layer, third conductive layer, fourth conductive layer, fifth conductive layer, and pixel definition layer in Figure 12. The display panel may include multiple pixel driving circuits shown in Figure 10. As shown in FIG28 , the plurality of pixel driving circuits may include a first pixel driving circuit Pix1 and a second pixel driving circuit Pix2 adjacently distributed in a first direction X. At least portions of the structures of the first pixel driving circuit Pix1 and the second pixel driving circuit Pix2 may be arranged in mirror symmetry about a mirror symmetry plane DD. The mirror symmetry plane DD may be perpendicular to the substrate. Furthermore, the orthographic projection of the first pixel driving circuit Pix1 on the substrate and the orthographic projection of the second pixel driving circuit Pix2 on the substrate may be arranged symmetrically about the intersection of the mirror symmetry plane DD and the substrate as an axis of symmetry. The first pixel driving circuit Pix1 and the second pixel driving circuit Pix2 may form a repeating unit, and the display panel may include a plurality of repeating units arranged in an array in the first direction X and the second direction Y.

[0082] As shown in Figures 12, 13, and 22, the shielding layer may include a plurality of shielding portions 61, and adjacent shielding portions 61 may be interconnected. It should be understood that in other exemplary embodiments, the display panel may not include a shielding layer.

[0083] As shown in Figures 12, 14, and 22, the first active layer may include a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, and a seventh active portion 77. The third active portion 73 may be used to form the channel region of the driving transistor T3; the fourth active portion 74 may be used to form the channel region of the fourth transistor T4; the fifth active portion 75 may be used to form the channel region of the fifth transistor T5; the sixth active portion 76 may be used to form the channel region of the sixth transistor T6; and the seventh active portion 77 may be used to form the channel region of the seventh transistor T7. The first active layer also includes an eighth active portion 78, a ninth active portion 79, a tenth active portion 710, an eleventh active portion 711, a twelfth active portion 712, and a thirteenth active portion 713. The ninth active portion 79 is connected to a side of the fifth active portion 75 away from the third active portion 73, and is connected between two adjacent fifth active portions 75 in the first direction X. The tenth active portion 710 is connected between the sixth active portion 76 and the seventh active portion 77, the eleventh active portion 711 is connected between the sixth active portion 76 and the third active portion 73, the twelfth active portion 712 is connected to an end of the fourth active portion 74 away from the third active portion 73, and the thirteenth active portion 713 is connected to an end of the seventh active portion 77 away from the sixth active portion 76. The orthographic projection of the shielding portion 61 on the base substrate can cover the orthographic projection of the third active portion 73 on the base substrate, and the shielding portion 61 can reduce the impact of light on the driving characteristics of the driving transistor T3. The first active layer may be formed of polysilicon material. Accordingly, the driving transistor T3 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , and the seventh transistor T7 may be P-type low-temperature polysilicon thin film transistors.

[0084] As shown in Figures 12, 15, and 23, the first conductive layer may include: a first conductive portion 11, a first gate line Gate1, an enable signal line EM, and a second reset signal line Re2. The first gate line Gate1 can be used to provide the first gate drive signal terminal shown in Figure 10; the enable signal line EM can be used to provide the enable signal terminal shown in Figure 10; and the second reset signal line Re2 can be used to provide the second reset signal terminal shown in Figure 10. The orthographic projections of the first gate line Gate1, the enable signal line EM, and the second reset signal line Re2 on the substrate can all extend along a first direction X. The orthographic projection of the first gate line Gate1 on the substrate overlaps the orthographic projection of the fourth active portion 74 on the substrate, and a portion of the first gate line Gate1 is used to form the gate of the fourth transistor. The orthographic projection of the enable signal line EM on the substrate overlaps the orthographic projections of the fifth active portion 75 and the orthographic projections of the sixth active portion 76 on the substrate, and a portion of the enable signal line EM is used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the second reset signal line Re2 on the substrate can cover the orthographic projection of the seventh active portion 77 on the substrate, and a portion of the structure of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7. The orthographic projection of the first conductive portion 11 on the substrate covers the orthographic projection of the third active portion 73 on the substrate, and the first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C. As shown in Figure 23, the first gate line Gate1 in the pixel driving circuit of this row can be reused as the second reset signal line Re2 in the pixel driving circuit of the next row. The display panel can be driven row by row from top to bottom or from bottom to top. This setting can improve the integration of the pixel driving circuit and reduce the layout area of ​​the pixel driving circuit. The shielding layer can also be connected to a stable power supply terminal. For example, the shielding layer can be connected to the first power supply terminal, the first initial signal terminal, the second initial signal terminal, etc. in Figure 10. The shielding portion 61 can shield the noise influence of other signals on the driving transistor T3. The display panel can use the first conductive layer as a mask to conduct conductor processing on the first active layer, that is, the area of ​​the first active layer covered by the first conductive layer can form the channel region of the transistor, and the area of ​​the first active layer not covered by the first conductive layer forms a conductor structure.

[0085] As shown in Figures 12, 16, and 24, the second conductive layer may include: a first initial signal line Vinit1, a third reset signal line 2Re1, a third gate line 2G2, and a plurality of second conductive portions 22. Among them, the first initial signal line Vinit1 is used to provide the first initial signal terminal in Figure 10, the third reset signal line 2Re1 can be used to provide the first reset signal terminal in Figure 10, and the third gate line 2G2 can be used to provide the second gate drive signal terminal in Figure 10. The orthographic projection of the first initial signal line Vinit1 on the base substrate, the orthographic projection of the third reset signal line 2Re1 on the base substrate, and the orthographic projection of the third gate line 2G2 on the base substrate can all extend along the first direction X. As shown in Figure 16, the second conductive layer may further include a plurality of third connecting portions 23, and the third connecting portion 23 is connected between two adjacent second conductive portions 22 in the same repeating unit.

[0086] As shown in Figures 12, 17, and 25, the second active layer may include an active portion 8, which may include a first active portion 81, a second active portion 82, a fourteenth active portion 814, a fifteenth active portion 815, and a sixteenth active portion 816. The first active portion 81 is used to form the channel region of the first transistor T1, and the second active portion 82 is used to form the channel region of the second transistor T2. The fifteenth active portion 815 is connected between the first active portion 81 and the second active portion 82. The fourteenth active portion 814 is connected to an end of the first active portion 81 away from the second active portion 82, and the sixteenth active portion 816 is connected to an end of the second active portion 82 away from the first active portion 81. The second active layer may be formed of indium gallium zinc oxide, and accordingly, the first transistor T1 and the second transistor T2 may be N-type metal oxide thin film transistors. The orthographic projection of the third gate line 2G2 on the substrate can overlap the orthographic projection of the second active portion 82 on the substrate, and a portion of the third gate line 2G2 can be used to form the bottom gate of the second transistor T2. The orthographic projection of the third reset signal line 2Re1 on the substrate can overlap the orthographic projection of the first active portion 81 on the substrate, and a portion of the third reset signal line 2Re1 can be used to form the bottom gate of the first transistor T1.

[0087] As shown in Figures 12, 18, and 26, the third conductive layer may include a first reset signal line 3Re1 and a second gate line 3G2. The orthographic projection of the first reset signal line 3Re1 on the substrate and the orthographic projection of the second gate line 3G2 on the substrate may both extend along the first direction X. The first reset signal line 3Re1 may be used to provide the first reset signal terminal shown in Figure 10. The orthographic projection of the first reset signal line 3Re1 on the substrate may cover the orthographic projection of the first active portion 81 on the substrate. A portion of the structure of the first reset signal line 3Re1 may be used to form the top gate of the first transistor T1. At the same time, the first reset signal line 3Re1 may be connected to the third reset signal line 2Re1 through a via located in the border area of ​​the display panel. The second gate line 3G2 may be used to provide the second gate drive signal terminal shown in Figure 32. The orthographic projection of the second gate line 3G2 on the substrate may cover the orthographic projection of the second active portion 82 on the substrate. A portion of the structure of the second gate line 3G2 may be used to form the top gate of the second transistor T2. At the same time, the second gate line 3G2 may be connected to the third gate line 2G2 through a via located in the border area of ​​the display panel. In addition, the display panel can use the third conductive layer as a mask to conduct the second active layer, that is, the area of ​​the second active layer covered by the third conductive layer can form the channel region of the transistor, and the area of ​​the second active layer not covered by the third conductive layer forms a conductor structure.

[0088] As shown in Figures 12, 19, and 27, the fourth conductive layer may include the above-mentioned first signal line L1, the first signal connection line Ls1, and the first bridge portion 41. The first signal line L1 can be used to provide the second initial signal end in Figure 10. The fourth conductive layer may also include: a first transition portion D41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, and a sixth bridge portion 46. Among them, some repeating units are correspondingly provided with the first bridge portion 41, and some repeating units are correspondingly provided with the first transition portion D41. The orthographic projection of the first transition portion D41 on the base substrate is located between the orthographic projections of two adjacent first signal connection lines Ls1 on the base substrate in the first direction X, and the orthographic projection of the first transition portion D41 on the base substrate is located between the orthographic projections of two adjacent first signal lines L1 on the base substrate. The structures of the first bridge portion 41 and the first adapter portion D41 are slightly different. The first bridge portion 41 includes a first connecting portion 41x and two protruding portions 41t connected to the first connecting portion 41x. The orthographic projection of the first connecting portion 41x on the substrate extends along the second direction Y and is located between the orthographic projections of the two protruding portions 41t on the substrate. The first adapter portion D41 includes a second connecting portion 41y and a protruding portion 41t connected to the second connecting portion 41y. The orthographic projection of the second connecting portion 41y on the substrate extends along the second direction Y. The first connecting portion 41x in the first bridge portion 41 and the second connecting portion 41y in the first adapter portion D41 are respectively connected to the third connecting portion 23 and the ninth active portion 79 in their corresponding pixel driving circuits through vias, thereby connecting the first electrode of the fifth transistor and the second electrode of the capacitor C. The second bridge portion 42 can be connected to the tenth active portion 710 through a via, thereby connecting the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. The third bridge portion 43 can be connected to the eleventh active portion 711 and the sixteenth active portion 816 through vias, respectively, to connect the second electrode of the second transistor T2, the first electrode of the sixth transistor T6, and the second electrode of the driving transistor T3. The fourth bridge portion 44 can be connected to the fifteenth active portion 815 and the first conductive portion 11 through vias, respectively, to connect the first electrode of the second transistor T2 and the gate of the driving transistor. An opening 221 is formed on the second conductive portion 22. The orthographic projection of the via connecting between the first conductive portion 11 and the fourth bridge portion 44 on the substrate is located within the orthographic projection of the opening 221 on the substrate, so that the via is insulated from the second conductive portion 22. The fifth bridge portion 45 can be connected to the twelfth active portion 712 through a via, to connect the first electrode of the fourth transistor. The sixth bridge portion 46 can be connected to the fourteenth active portion 814 and the first initial signal line Vinit1 through vias, respectively, to connect the first electrode of the first transistor and the first initial signal terminal. In adjacent repeating units in the first direction X, two adjacent pixel driving circuits may share the same sixth bridge portion 46 .The first signal line L1 may be connected to the thirteenth active portion 713 through a via hole to connect the first electrode and the second initial signal terminal of the seventh transistor.

[0089] As shown in Figures 12, 19, and 27, the orthographic projection of the first signal connection line Ls1 on the substrate at least partially overlaps with the orthographic projection of the eighth active portion 78 on the substrate. This arrangement prevents the first signal connection line Ls1 from overlapping with the equipotential structure of the second electrode of the driving transistor T3 in the first active layer, thereby improving the problem of image retention in the display panel.

[0090] As shown in Figures 12, 20, and 28, the fifth conductive layer may include: the aforementioned second signal line L2, multiple data lines Da, and a seventh bridge portion 57. The second signal line L2 includes two power lines VDD extending parallel to and interconnected in the second direction Y. The orthographic projections of the data lines Da on the substrate may each extend along the second direction Y. The power line VDD may be used to provide the first power terminal shown in Figure 10, and the data lines Da may be used to provide the data signal terminal shown in Figure 10. A power line VDD may be provided for each column of pixel driving circuits. The power line VDD may be connected to the first bridge portion 41 via a via to connect the first electrode of the fifth transistor to the first power terminal. The data line Da may be connected to the fifth bridge portion 45 via a via to connect the first electrode of the fourth transistor to the data signal terminal. The seventh bridge portion 57 may be connected to the second bridge portion 42 via a via to connect the second electrode of the seventh transistor. In adjacent repeating units in the first direction, adjacent power lines VDD are interconnected. The power lines VDD may form a grid structure via the first bridge portion 41. This grid structure of power lines can reduce the voltage drop of the power signal across them.

[0091] As shown in Figures 12, 20, and 28, the power line VDD may include a first power line segment VDD1, a second power line segment VDD2, and a third power line segment VDD3. The second power line segment VDD2 is connected between the first power line segment VDD1 and the third power line segment VDD3. The orthographic projection of the second power line segment VDD2 on the substrate in the first direction X may be larger than the orthographic projection of the first power line segment VDD1 on the substrate in the first direction X, and the orthographic projection of the second power line segment VDD2 on the substrate in the first direction X may be larger than the orthographic projection of the third power line segment VDD3 on the substrate in the first direction X. Furthermore, the orthographic projection of the second power line segment VDD2 on the substrate may also cover the orthographic projections of the first active portion 81 and the second active portion 82 on the substrate. The second power line segment VDD2 can reduce the effects of light on the characteristics of the first transistor T1 and the second transistor T2. The orthographic projection of the power line VDD on the substrate may also at least partially overlap with the orthographic projection of the fourth bridge portion 44 on the substrate. The power line VDD may be used to shield the fourth bridge portion 44 from noise interference from other signals, thereby improving the stability of the gate voltage of the driving transistor T3.

[0092] As shown in Figures 12, 19, 20, 27, and 28, the orthographic projection of the first connecting portion 41x on the substrate is located between the orthographic projections of two adjacent data lines Da on the substrate; the orthographic projection of the second connecting portion 41y on the substrate is located between the orthographic projections of two adjacent data lines Da on the substrate. This arrangement prevents the orthographic projection of the data line Da on the substrate from overlapping with the orthographic projections of the first connecting portion 41x and the second connecting portion 41y on the substrate, thereby reducing the parasitic capacitance of the data line Da. A data line Da with a smaller parasitic capacitance can increase the charging speed of the data signal on the data line Da, thereby ensuring that the data signal is fully written to the data signal terminal of each pixel driving circuit within a shorter scanning period, thereby improving the accuracy of the output current of the driving transistor.

[0093] As shown in Figures 12 and 21, the electrode layer may include multiple electrode portions: the multiple electrode portions include a first electrode portion R, a second electrode portion G1, a third electrode portion B, and a fourth electrode portion G2. The electrode portions may be connected to the seventh bridge portion 57 via vias. As shown in Figures 12 and 21, the electrode layer includes multiple electrode blocks, with partial structures of the electrode blocks forming electrode portions, and other structures of the electrode blocks forming extensions of the electrode portions and connecting portions connecting the electrode portions and the seventh bridge portion 57. Among the multiple electrode portions connected to the same row of pixel driving circuits, the first electrode portion R, the second electrode portion G1, the third electrode portion B, and the fourth electrode portion G2 are alternately distributed in the row direction; in two adjacent columns of pixel driving circuits, the first electrode portion R and the third electrode portion B are connected to the same column of pixel driving circuits, and the first electrode portion R and the third electrode portion B connected to the same column of pixel driving circuits are alternately distributed in the column direction, and the second electrode portion G1 and the fourth electrode portion G2 are connected to the other column of pixel driving circuits, and the second electrode portion G1 and the fourth electrode portion G2 connected to the same column of pixel driving circuits are alternately distributed in the column direction. The pixel definition layer includes a plurality of pixel openings PH, each of which is used to form a light-emitting unit. The plurality of pixel openings PH are provided in a one-to-one correspondence with the plurality of electrode portions, and the orthographic projections of the electrode portions on the substrate coincide with the orthographic projections of the corresponding pixel openings on the substrate. In this exemplary embodiment, the first electrode portion R forms the first electrode of the red light-emitting unit, the second electrode portion G1 and the fourth electrode portion G2 form the first electrode of the green light-emitting unit, and the third electrode portion B forms the first electrode of the blue light-emitting unit.

[0094] As shown in Figures 12 and 21, among adjacent power lines VDD, the power line VDD corresponding to the pixel driving circuit connected to the first electrode portion R and the power line VDD corresponding to the pixel driving circuit connected to the fourth electrode portion G2 are connected to form the second signal line L2. The power line VDD corresponding to the pixel driving circuit connected to the second electrode portion G1 and the power line VDD corresponding to the pixel driving circuit connected to the third electrode portion B are connected to form the second signal line L2. The pixel driving circuit connected to the first electrode portion R is provided with a first signal connection line Ls1. In the corresponding pixel driving circuit and the first signal connection line Ls1, the orthographic projection of the first signal connection line Ls1 on the substrate is located on the side of the orthographic projection of the data line Da on the substrate facing the orthographic projection of the power line VDD on the substrate. The pixel driving circuits connected to the third electrode portion B and the fourth electrode portion G2 are provided with a first bridge portion 41, which is connected between the two power lines in the corresponding pixel driving circuit.

[0095] As shown in Figures 12, 19, 20, 21, 27 and 28, the pixel driving circuits connected to the first electrode portion R and the second electrode portion G1 are correspondingly provided with the first adapter portion D41, the first adapter portion D41 is connected to the corresponding pixel driving circuit, and the first adapter portion D41 is connected to the power line VDD in the pixel driving circuit connected to the corresponding second electrode portion G1 through the protrusion 41t.

[0096] As shown in Figures 12, 19, 20, 21, 27 and 28, the orthographic projection of the first signal connection line Ls1 on the base substrate does not overlap with the orthographic projection of any electrode portion on the base substrate. This arrangement can improve color deviation caused by local protrusion of the electrode portion.

[0097] As shown in Figures 12, 19, 20, 21, 27, and 28, the first electrode portion R includes a first side R1, the orthographic projection of the first side R1 on the base substrate extending in a direction intersecting the second direction Y. The first signal connection line Ls1 may include a first sub-segment Ls11 and a second sub-segment Ls12, the orthographic projection of the first sub-segment Ls11 on the base substrate being parallel to the orthographic projection of the first side R1 on the base substrate; and the second sub-segment Ls12 connected to the first sub-segment Ls11, the orthographic projection of the second sub-segment Ls12 on the base substrate extending in a direction parallel to the second direction Y. That is, the first signal connection line Ls1 avoids the first electrode portion R by bending the first sub-segment Ls11 to prevent the first signal connection line Ls1 and the first electrode portion R from overlapping.

[0098] As shown in Figures 29-31, Figure 29 is a structural layout diagram of an exemplary embodiment of the display panel of the present disclosure, Figure 30 is a structural layout diagram of the fourth conductive layer in Figure 29, and Figure 31 is a structural layout diagram of the fifth conductive layer in Figure 29. The partial layout structure of the display panel shown in Figure 29 (not all structural film layers are shown) includes the partial layout structure of the display panel shown in Figure 12, arranged in a two-by-two array. As can be clearly seen in Figures 29-31, the first signal lines L1 form a grid structure through the first signal connection lines Ls1, and the second signal lines L2 form a grid structure through the first bridge portion 41.

[0099] It should be noted that, as shown in Figures 12, 27, 28, and 29, the black squares drawn on the side of the fourth conductive layer facing away from the substrate represent vias connecting the fourth conductive layer to other layers facing the substrate; the black squares drawn on the side of the fifth conductive layer facing away from the substrate represent vias connecting the fifth conductive layer to other layers facing the substrate; and the black squares drawn on the side of the electrode layer facing away from the substrate represent vias connecting the electrode layer to other layers facing the substrate. The black squares merely indicate the locations of the vias; different vias represented by black squares in different locations can penetrate different insulating layers.

[0100] FIG32 is a partial cross-sectional view of the display panel shown in FIG12 taken along dotted line AA. The display panel may further include a first insulating layer 91, a second insulating layer 92, a third insulating layer 93, a fourth insulating layer 94, a fifth insulating layer 95, a first dielectric layer 96, a passivation layer 97, a first planarization layer 98, and a second planarization layer 99. The base substrate 90, the shielding layer, the first insulating layer 91, the first active layer, the second insulating layer 92, the first conductive layer, the third insulating layer 93, the second conductive layer, the fourth insulating layer 94, the second active layer, the fifth insulating layer 95, the third conductive layer, the first dielectric layer 96, the fourth conductive layer, the passivation layer 97, the first planarization layer 98, the fifth conductive layer, the second planarization layer 99, and the electrode layer are stacked in sequence. The first insulating layer 91, the second insulating layer 92, the third insulating layer 93, the fourth insulating layer 94, and the fifth insulating layer 95 can be single-layer or multi-layer structures, and the material of the first insulating layer 91, the second insulating layer 92, the third insulating layer 93, the fourth insulating layer 94, and the fifth insulating layer 95 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride. The first dielectric layer 96 can be a silicon nitride layer. The materials of the first planarizing layer 98 and the second planarizing layer 99 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG), etc. The passivation layer 97 can be a silicon oxide layer. The base substrate 90 can include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence. The barrier layer can be an inorganic material. The materials of the first conductive layer, the second conductive layer, and the third conductive layer can be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stacked conductive layer. The fourth and fifth conductive layers may be made of metal materials, such as molybdenum, aluminum, copper, titanium, or niobium, or an alloy thereof, or a molybdenum / titanium alloy or laminate, or a titanium / aluminum / titanium laminate. The square resistance of any of the fourth and fifth conductive layers may be less than the square resistance of any of the first, second, and third conductive layers.

[0101] In this exemplary embodiment, there is a process error in the manufacturing process of capacitor C, which causes the output current of the pixel driving circuit to fluctuate with the standard value. Through simulation, it can be seen that when different capacitor design values ​​fluctuate between -5fF and +5fF, the current output by the pixel driving circuit fluctuates differently. For example, in an 8-grayscale driving environment, when the capacitor design value is (C1-10)fF: when the actual value of the capacitor fluctuates to -5fF, the output current of the red pixel driving circuit fluctuates by 41.91%, the output current of the blue pixel driving circuit fluctuates by 47.62%, and the output current of the green pixel driving circuit fluctuates by 54.41%; when the actual value of the capacitor fluctuates to 5fF, the output current of the red pixel driving circuit fluctuates by -35.55%, the output current of the blue pixel driving circuit fluctuates by -40.61%, and the output current of the green pixel driving circuit fluctuates by -44.04%. In the 8-grayscale driving environment, when the capacitor design value is C1fF: when the actual value of the capacitor fluctuates by -5fF, the output current fluctuation of the red pixel driving circuit is 41.58%, the output current fluctuation of the blue pixel driving circuit is 45.83%, and the output current fluctuation of the green pixel driving circuit is 50.45%; when the actual value of the capacitor fluctuates by 5fF, the output current fluctuation of the red pixel driving circuit is -35.51%, the output current fluctuation of the blue pixel driving circuit is -39.38%, and the output current fluctuation of the green pixel driving circuit is -42.04%. In an 8-grayscale driving environment, when the capacitance design value is (C1+10)fF: when the actual capacitance value fluctuates by -5fF, the output current fluctuation of the red pixel driving circuit is 39.73%, the output current fluctuation of the blue pixel driving circuit is 42.58%, and the output current fluctuation of the green pixel driving circuit is 50.66%; when the actual capacitance value fluctuates by 5fF, the output current fluctuation of the red pixel driving circuit is -34.31%, the output current fluctuation of the blue pixel driving circuit is -37.01%, and the output current fluctuation of the green pixel driving circuit is -42.52%. Based on the above data, it can be seen that the larger the capacitance of capacitor C, the smaller the fluctuation of the pixel driving circuit output current. The reason is that the larger the capacitance of capacitor C, the stronger the voltage stabilizing effect of capacitor C on the gate of the driving transistor, and the smaller the fluctuation of the driving transistor output current. In this exemplary embodiment, the capacitance of capacitor C can be designed to be as large as possible to reduce the fluctuation of the pixel driving circuit output current. For example, the capacitance of capacitor C can be increased by 2%-10% based on the original design value of capacitor C.

[0102] It should be noted that the proportions of the drawings in this disclosure can be used as a reference in actual processes, but are not limited to this. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematics. In addition, qualifiers such as first and second are only used to limit different structural names, and they do not have a specific order of meaning. The same structural layer can be formed by the same composition process. In this exemplary embodiment, the orthographic projection of a certain structure on the base substrate extends in a certain direction, which can be understood as the orthographic projection of the structure on the base substrate extending in a straight line or bending along that direction.

[0103] This exemplary embodiment also provides a display device, which includes the above-mentioned display panel. The display device can be a mobile phone, a tablet computer, a television, or other display device.

[0104] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0105] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0106] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A display panel, wherein: The display panel comprises: substrate substrate; A plurality of first signal lines, wherein the orthographic projections of the plurality of first signal lines on the substrate extend along a first direction and are spaced apart along a second direction, and the first direction and the second direction intersect; a plurality of first signal connection lines, wherein the orthographic projections of the first signal connection lines on the substrate extend along the second direction, and the first signal connection lines are connected between two adjacent first signal lines in the second direction to form a grid structure with the first signal lines; a plurality of second signal lines, wherein the second signal lines and the first signal lines are located in a different conductive layer, and the orthographic projections of the plurality of second signal lines on the base substrate extend along the second direction and are spaced apart along the first direction; a plurality of first bridge portions, wherein the first bridge portions are connected between two adjacent second signal lines in the first direction to form a grid structure with the second signal lines; The orthographic projection of the first bridging portion on the base substrate is located between the orthographic projections of two adjacent first signal connection lines on the base substrate in the first direction, and the orthographic projection of the first bridging portion on the base substrate is located between the orthographic projections of two adjacent first signal lines on the base substrate.

2. The display panel according to claim 1, wherein: Two adjacent first signal connection lines and two adjacent first signal lines connected thereto form a ring structure, wherein the plurality of ring structures include a first ring structure, a second ring structure, and a third ring structure; The first annular structure and the second annular structure are distributed in the first direction, the first annular structure and the third annular structure are distributed in the second direction, and the first annular structure and the third annular structure are staggered in the first direction; The second annular structure and the third annular structure are distributed in the second direction, and the second annular structure and the third annular structure are staggered in the first direction; The first bridging portions whose orthographic projections on the substrate are located within one of the annular structures form a bridging portion group; The plurality of bridge portions groups include a first bridge portion group, a second bridge portion group, and a third bridge portion group. The orthographic projection of the first bridge portion group on the substrate is located within the orthographic projection of the first annular structure on the substrate. The projection is located within the orthographic projection of the second annular structure on the substrate, and the orthographic projection of the third bridging portion group on the substrate is located within the orthographic projection of the third annular structure on the substrate; The first bridge portion group and the second bridge portion group are respectively connected to different second signal lines, the first bridge portion group and the third bridge portion group are connected to at least one same second signal line, and the second bridge portion group and the third bridge portion group are connected to at least one same second signal line.

3. The display panel according to claim 2, wherein: The first annular structure and the second annular structure share the same first signal connection line, the first annular structure and the third annular structure share a partial structure of the same first signal line, and the second annular structure and the third annular structure share a partial structure of the same first signal line.

4. The display panel according to claim 2, wherein: The distances between the orthographic projections of two first signal connection lines on the substrate in each of the annular structures in the first direction are the same or substantially the same, and each of the bridge portion groups includes the same number of the first bridge portions.

5. The display panel according to claim 2, wherein: The first bridge portion in the first bridge portion group includes a first sub-bridge portion, the first bridge portion in the second bridge portion group includes a second sub-bridge portion, and the first bridge portion in the third bridge portion group includes a third sub-bridge portion; In the first direction, the orthographic projection of the third sub-bridge portion on the base substrate is located between the orthographic projection of the first sub-bridge portion on the base substrate and the orthographic projection of the second sub-bridge portion on the base substrate; The orthographic projection of the first sub-bridge portion on the base substrate and the orthographic projection of the second sub-bridge portion on the base substrate are arranged adjacent to each other in a first direction, and the orthographic projection of the first signal connection line on the base substrate is located between the orthographic projection of the first sub-bridge portion on the base substrate and the orthographic projection of the second sub-bridge portion on the base substrate.

6. The display panel according to claim 2, wherein: The bridge portion group includes one first bridge portion, the first signal connection lines connected between adjacent first signal lines in the same group form a first signal connection line row, and the first bridge portions located between adjacent first signal lines in the same group form a first bridge portion row; In the adjacent rows of the first signal connection lines in the second direction, the orthographic projections of the first signal connection lines in different rows of the first signal connection lines on the substrate are alternately distributed in sequence in the first direction; In the adjacent rows of the first bridging portions in the second direction, the orthographic projections of the first bridging portions in different rows of the first bridging portions on the substrate are alternately distributed in sequence in the first direction.

7. The display panel according to claim 6, wherein: The orthographic projections of the first signal connection lines in the same first signal connection line row on the substrate are distributed at equal intervals or approximately at equal intervals in the first direction; The orthographic projections of the first bridging portions in the same first bridging portion row on the substrate are distributed at equal intervals or approximately at equal intervals in the first direction.

8. The display panel according to claim 1, wherein: The display panel comprises a light-emitting unit, a power line, and a pixel driving circuit arrayed in the first direction and the second direction, wherein the pixel driving circuit is connected to a first electrode of the light-emitting unit, and the power line is used to provide a high-level power signal to the pixel driving circuit. The second direction is a column direction, and each column of pixel driving circuits is correspondingly provided with a power line. The display panel further includes: An electrode layer, located on one side of the base substrate, the electrode layer comprising a plurality of electrode portions, the electrode portions being used to form a first electrode of the light emitting unit; a pixel definition layer, located on a side of the electrode layer away from the base substrate, wherein a plurality of pixel openings are formed on the pixel definition layer, wherein the pixel openings and the electrode portions are arranged correspondingly, and the orthographic projections of the pixel openings on the base substrate coincide with the orthographic projections of the corresponding electrode portions on the base substrate; The plurality of electrode portions include a first electrode portion, a second electrode portion, a third electrode portion, and a fourth electrode portion. Among the plurality of electrode portions connected to the pixel driving circuit in the same row, the first electrode portion, the second electrode portion, the third electrode portion, and the fourth electrode portion are alternately distributed in the row direction. The orthographic projection of the power line on the base substrate extends along the second direction, and among the adjacent power lines, the power line corresponding to the pixel driving circuit connected to the first electrode portion and the power line corresponding to the pixel driving circuit connected to the fourth electrode portion are connected to form the second A signal line, wherein a power line corresponding to the pixel driving circuit connected to the second electrode portion and a power line corresponding to the pixel driving circuit connected to the third electrode portion are connected to form the second signal line; The pixel driving circuit connected to the first electrode portion is correspondingly provided with the first signal connection line, and the pixel driving circuit connected to the third electrode portion and the fourth electrode portion is correspondingly provided with the first bridge portion, and the first bridge portion is connected between two power lines in the corresponding pixel driving circuit.

9. The display panel according to claim 8, wherein: The first electrode portion is used to form a first electrode of a red light emitting unit, the second electrode portion and the fourth electrode portion are used to form a first electrode of a green light emitting unit, and the third electrode portion is used to form a first electrode of a blue light emitting unit.

10. The display panel according to claim 8, wherein: The display panel further includes: a data line, the orthographic projection of which on the substrate extends along the second direction, the data line being used to provide a data signal to the pixel driving circuit; In the correspondingly arranged pixel driving circuit and the first signal connecting line, the orthographic projection of the first signal connecting line on the base substrate is located on the side where the orthographic projection of the data line on the base substrate faces the orthographic projection of the power line on the base substrate.

11. The display panel according to claim 8, wherein: The display panel further includes: A first transfer portion is located in the same conductive layer as the first bridge portion, an orthographic projection of the first transfer portion on the base substrate is located between orthographic projections of two adjacent first signal connection lines on the base substrate in the first direction, and an orthographic projection of the first transfer portion on the base substrate is located between orthographic projections of two adjacent first signal lines on the base substrate; The first adapter is correspondingly provided to the pixel driving circuits connected to the first electrode portion and the second electrode portion, the first adapter is connected to the corresponding pixel driving circuit, and the first adapter is connected to a power line in the pixel driving circuit connected to the corresponding second electrode portion.

12. The display panel according to claim 11, wherein: The first bridge portion is also connected to a corresponding pixel driving circuit, and the first bridge portion includes: a first connecting portion, wherein an orthographic projection of the first connecting portion on the base substrate extends along the second direction, and the first connecting portion is connected to the pixel driving circuit; The first transfer portion comprises: a second connection portion, wherein an orthographic projection of the second connection portion on the base substrate extends along the second direction, and the second connection portion is connected to the pixel driving circuit; The display panel further includes: a data line, the orthographic projection of which on the substrate extends along the second direction, the data line being used to provide a data signal to the pixel driving circuit; The orthographic projection of the first connecting portion on the base substrate is located between the orthographic projections of two adjacent data lines on the base substrate; And / or, the orthographic projection of the second connecting portion on the base substrate is located between the orthographic projections of two adjacent data lines on the base substrate.

13. The display panel according to claim 8, wherein: An orthographic projection of the first signal connection line on the base substrate and an orthographic projection of the electrode portion on the base substrate do not overlap.

14. The display panel according to claim 13, wherein: The first electrode portion includes a first side edge, and an extension direction of an orthographic projection of the first side edge on the base substrate intersects with the second direction; The first signal connection line comprises: a first sub-line segment, wherein an orthographic projection of the first sub-line segment on the substrate is parallel to an orthographic projection of the first side on the substrate; The second sub-line segment is connected to the first sub-line segment, and an extension direction of an orthographic projection of the second sub-line segment on the base substrate is parallel to the second direction.

15. The display panel according to claim 1, wherein: The display panel further includes a pixel driving circuit, the pixel driving circuit includes a driving transistor and a fifth transistor, a first electrode of the fifth transistor is connected to a power line, and a second electrode is connected to the first electrode of the driving transistor; The display panel further includes: a first active layer, located on one side of the base substrate, the first active layer comprising a third active portion and a fifth active portion, the third active portion is used to form a channel region of the driving transistor, and the fifth active portion is used to form a channel region of the fifth transistor; The orthographic projection of the first signal connection line on the base substrate is located on a side where the orthographic projection of the third active portion on the base substrate is close to the orthographic projection of the fifth active portion on the base substrate.

16. The display panel according to claim 1, wherein: The display panel further comprises a light emitting unit, a pixel driving circuit, a power line, and a second initial signal line, wherein the pixel driving circuit is connected to the first electrode of the light emitting unit, the power line is used to provide a high-level power signal to the pixel driving circuit, and the second initial signal line is used to provide an initial signal line to the first electrode of the light emitting unit; The first signal line is used to form the second initial signal line, and / or the second signal line is used to form the power line.

17. The display panel according to claim 1, wherein: The first signal line, the first signal connection line, and the first bridge portion are located in the same conductive layer, and the first signal line and the first signal connection line are connected in the same layer; A plurality of the second signal lines are located in the same conductive layer.

18. The display panel according to claim 1, wherein: The display panel includes a pixel driving circuit and a light emitting unit, wherein the pixel driving circuit includes a driving transistor, a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a capacitor; A first electrode of the first transistor is connected to a first initial signal line, and a second electrode is connected to a gate of the driving transistor; A first electrode of the second transistor is connected to the gate of the driving transistor, and a second electrode of the second transistor is connected to the second electrode of the driving transistor; A first electrode of the fourth transistor is connected to the data line, and a second electrode is connected to the first electrode of the driving transistor; A first electrode of the fifth transistor is connected to a power line, and a second electrode is connected to a first electrode of the driving transistor; The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light emitting unit; A first electrode of the seventh transistor is connected to the second initial signal line, and a second electrode is connected to the first electrode of the light emitting unit; A first electrode of the capacitor is connected to the gate of the driving transistor, and a second electrode of the capacitor is connected to the power line.

19. A display panel, wherein: The display panel comprises: substrate substrate; A plurality of first signal lines, wherein the orthographic projections of the plurality of first signal lines on the substrate extend along a first direction and are spaced apart along a second direction, and the first direction and the second direction intersect; a plurality of first signal connection lines, wherein the orthographic projections of the first signal connection lines on the substrate extend along the second direction, and the first signal connection lines are connected between two adjacent first signal lines in the second direction to form a grid structure with the first signal lines; a plurality of second signal lines, wherein the second signal lines and the first signal lines are located in a different conductive layer, and the orthographic projections of the plurality of second signal lines on the base substrate extend along the second direction and are spaced apart along the first direction; a plurality of first bridge portions, wherein the first bridge portions are used to be electrically connected to the second signal lines to form a grid structure with the second signal lines; The orthographic projection of the first bridging portion on the base substrate is located between the orthographic projections of two adjacent first signal connection lines on the base substrate in the first direction, and the orthographic projection of the first bridging portion on the base substrate is located between the orthographic projections of two adjacent first signal lines on the base substrate.

20. A display device, wherein: The display device comprises the display panel according to any one of claims 1-19.

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