Array substrate and display panel

Abstract

The present application provides an array substrate and a display panel. The array substrate includes a driving line and an electrostatic protection line; the driving line includes a first sub-driving line and a second sub-driving line, the first sub-driving line has a first connecting portion, the second sub-driving line and the first sub-driving line are arranged in different layers, the second sub-driving line includes a first driving segment, a second driving segment and a first electrostatic release portion, one end of the first driving segment has a second connecting portion, the second connecting portion is electrically connected to the first connecting portion, the second driving segment is bent and connected to the other end of the first driving segment away from the second connecting portion, and the first electrostatic release portion is located at the connection between the first driving segment and the other end of the second driving segment; the electrostatic protection line and the second sub-driving line are arranged in the same layer, the electrostatic protection line includes a connected line body and a second electrostatic release portion, and the second electrostatic release portion is arranged opposite to and spaced from the first electrostatic release portion. The array substrate of the present application has good electrostatic protection capability and a high product yield.

Description

Technical Field

[0001] The present application relates to the field of display, and in particular to an array substrate and a display panel. Background Art

[0002] With the development of technology, electronic devices including liquid crystal display panels are increasingly widely used. Liquid crystal display panels include array substrates. The array substrates are more susceptible to static electricity, which may cause the circuits on the array substrates to burn, thereby causing product defects. Summary of the invention

[0003] In a first aspect, an embodiment of the present application provides an array substrate, wherein the array substrate comprises:

[0004] A driving line, wherein the driving line comprises a first sub-driving line and a second sub-driving line, the first sub-driving line has a first connecting portion, the second sub-driving line and the first sub-driving line are arranged in different layers, the second sub-driving line comprises a first driving segment, a second driving segment and a first electrostatic release portion, one end of the first driving segment has a second connecting portion, the second connecting portion is electrically connected to the first connecting portion, the second driving segment is bent and connected to the other end of the first driving segment away from the second connecting portion, and the first electrostatic release portion is located at the connection between the first driving segment and the other end of the second driving segment; and

[0005] The electrostatic protection line is arranged in the same layer as the second sub-driving line, and the electrostatic protection line includes a connected line body and a second electrostatic release portion, and the second electrostatic release portion is arranged opposite to the first electrostatic release portion and spaced apart.

[0006] In a second aspect, an embodiment of the present application provides a display panel, wherein the display panel includes the array substrate as described in the first aspect.

[0007] In summary, the array substrate provided in the embodiment of the present application includes a driving line and an electrostatic protection line, the driving line includes a first electrostatic release portion, the electrostatic protection line includes a second electrostatic release portion, and the second electrostatic release portion is arranged opposite to and spaced from the first electrostatic release portion. When static electricity exists in the array substrate during the preparation process or in the use process, the static electricity can be released to the second electrostatic release portion via the first electrostatic release portion, thereby reducing or even preventing the risk of static electricity accumulation in the array substrate and burning or breaking down the driving line or other devices in the array substrate. It can be seen that the array substrate provided in the embodiment of the present application has a high yield rate, and when the array substrate is used in a display panel, the display image quality of the display panel is high. In addition, in the array substrate provided in the embodiment of the present application, the first electrostatic release portion is located at the connection between the first driving segment and the other end of the second driving segment. Therefore, the first electrostatic release portion is far away from the connection between the first connection portion and the second connection portion, and the first electrostatic release portion is also far away from the thin film transistor. Therefore, when the first electrostatic release portion and the second electrostatic release portion release static electricity, it is not easy to damage the thin film transistor of the array substrate, nor is it easy to damage the connection between the second connection portion and the first connection portion, thereby further improving the display quality of the display panel used by the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the implementation will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0009] Figure 1 A schematic diagram of a display panel provided in one embodiment of the present application;

[0010] Figure 2 for Figure 1 A schematic cross-sectional view of the display panel along line II;

[0011] Figure 3 A partial top view of the array substrate provided in the first embodiment of the present application;

[0012] Figure 4 for Figure 3 A schematic cross-sectional view of the array substrate along II-II provided in;

[0013] Figure 5 A partial schematic diagram of an array substrate provided in the first embodiment of the present application;

[0014] Figure 6 for Figure 5 Detailed dimensions of various parts of the array substrate shown in FIG.

[0015] Figure 7 A diagram showing the dimensions of multiple different parts of the array substrate provided in the first embodiment of the present application;

[0016] Figure 8 A partial top view of an array substrate provided in the second embodiment of the present application;

[0017] Fig. 9 for Figure 8 A schematic diagram of the detailed dimensions of various parts of the array substrate shown;

[0018] Fig.10 A diagram showing the dimensions of multiple different parts of an array substrate provided in the second embodiment of the present application;

[0019] Fig.11 A partial top view of an array substrate provided in the third embodiment of the present application;

[0020] Fig.12 for Fig.11 A schematic diagram of the detailed dimensions of various parts of the array substrate shown;

[0021] Fig.13 A dimension chart of multiple different parts of the array substrate provided in the third embodiment of the present application;

[0022] Fig.14 A flow chart of a method for preparing an array substrate provided in one embodiment of the present application;

[0023] Fig.15 A schematic diagram of a display panel provided in accordance with an embodiment of the present application.

[0024] Description of main component numbers:

[0025] Display panel 10, display area 10a, non-display area 10b;

[0026] Array substrate 100, color filter substrate 300, liquid crystal layer 500, housing 600;

[0027] Carrying substrate 101, driving wire 110, first driving wire 110a, second driving wire 110b, third driving wire 110c, first sub-driving wire 111, connecting member 111a, second sub-driving wire 112, first wire body 1111, first connecting portion 1112, first driving segment 1121, second driving segment 1122, first electrostatic release portion 1123, first end surface 112a, second connecting portion 11211;

[0028] Insulating layer 120, through hole 121;

[0029] The electrostatic protection line 130 , the line body 131 , the second electrostatic release portion 132 , and the second end surface 130 a . DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0031] The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0032] Reference to "embodiment" or "implementation" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiment or implementation may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0033] See also Figure 1 and Figure 2 , Figure 1 A schematic diagram of a display panel provided in one embodiment of the present application; Figure 2 for Figure 1 The cross-sectional diagram of the display panel along line II in FIG. The display panel 10 is also referred to as a display device. In the present embodiment, the display panel 10 is illustrated as a liquid crystal display panel (LCD) as an example, which is understandable and should not be construed as a limitation on the display panel 10 provided in the embodiment of the present application. In other embodiments, the display panel 10 may also be an organic electroluminescent (OLED) display panel, or a mini light-emitting diode (Mini-LED) display panel, etc.

[0034] When the display panel 10 is a liquid crystal display panel, the display panel 10 includes an array substrate 100, a color filter substrate 300 and a liquid crystal layer 500. The array substrate 100 and the color filter substrate 300 are arranged opposite to each other and spaced apart to form a containing space. The liquid crystal layer 500 is arranged in the containing space. It can be understood that the display panel 10 in the embodiment of the present application is a liquid crystal display panel, which is only an introduction to an application of the array substrate 100, and should not be understood as a limitation on the array substrate 100 provided in the embodiment of the present application.

[0035] The display panel 10 includes an array substrate 100. The display panel 10 includes a display area 10a and a non-display area 10b. The array substrate 100 has a plurality of pixel areas at positions corresponding to the display area 10a, and the array substrate 100 includes thin film transistors (TFTs) corresponding to the pixel areas. In the related art, the thin film transistor is an amorphous silicon semiconductor thin film transistor (a-Si TFT) or a low-temperature polycrystalline silicon semiconductor thin film transistor. With the development of technology, high-mobility metal oxide semiconductor materials are widely used in various display panels 10 to replace amorphous silicon semiconductor thin film transistors or low-temperature polycrystalline silicon semiconductor thin film transistors. Compared with amorphous silicon semiconductor thin film transistors (a-Si TFTs), oxide semiconductor thin film transistors (Oxide TFTs) have more advantages in various performances, can meet the technical requirements of high-level LCD and OLED display products such as high resolution, high refresh rate, high transmittance and ultra-low power consumption, and have high comprehensive competitiveness.

[0036] However, the metal oxide semiconductor thin film transistors in the related art are more susceptible to static damage due to process manufacturing tolerances. On the one hand, this is because metal oxide semiconductor thin film transistors are mostly used in high-generation production lines during preparation, and the amount of static electricity generated by the process equipment is large and difficult to control; on the other hand, it is because the metal oxide semiconductor thin film transistor has a high carrier concentration and is more likely to accumulate static electricity on the surface of the substrate. The electrostatic protection design in the related art has low voltage breakdown resistance and concentrated electrostatic release, which can easily cause burns in the drive line 110 and other lines in the array substrate 100, resulting in defective products. In the related art, the product yield loss (also called yield loss) caused by static electricity is as high as 20%.

[0037] The embodiment of the present application provides an array substrate 100 , and the array substrate 100 has good electrostatic protection capability. Next, the array substrate 100 provided in the embodiment of the present application is introduced in detail.

[0038] Please also read Figure 3 and Figure 4 , Figure 3A partial top view of the array substrate provided in the first embodiment of the present application; Figure 4 for Figure 3 The cross-sectional schematic diagram of the array substrate along II-II provided in the embodiment. The array substrate 100 includes a driving line 110 and an electrostatic protection line 130. The driving line 110 includes a first sub-driving line 111 and a second sub-driving line 112. The first sub-driving line 111 has a first connecting portion 1112. The second sub-driving line 112 is arranged in a different layer from the first sub-driving line 111. The second sub-driving line 112 includes a first driving segment 1121, a second driving segment 1122 and a first electrostatic release portion 1123. One end of the first driving segment 1121 has a second connecting portion 11211. The second connecting portion 11211 is electrically connected to the first connecting portion 1112. The second driving segment 1122 is bent and connected to the other end of the first driving segment 1121 away from the second connecting portion 11211. The first electrostatic release portion 1123 is located at the connection between the first driving segment 1121 and the other end of the second driving segment 1122. The electrostatic protection line 130 is disposed in the same layer as the second sub-driving line 112. The electrostatic protection line 130 includes a connected line body 131 and a second electrostatic release portion 132. The second electrostatic release portion 132 is disposed opposite to the first electrostatic release portion 1123 and spaced apart.

[0039] In this embodiment, the array substrate 100 further includes a carrier substrate 101 , and the carrier substrate 101 is used to carry the driving lines 110 and the electrostatic protection lines 130 .

[0040] The material of the driving line 110 in the array substrate 100 provided in the embodiment of the present application may be, but is not limited to, a conductive metal or alloy. The driving line 110 may be a single layer, or multiple layers (such as double layers or more layers). The material of the driving line 110 may be, but is not limited to, one or more of Cu, Mo, Al, Ti, Nb, and Mg.

[0041] In this embodiment, the array substrate 100 includes a thin film transistor (TFT). The driving line 110 is electrically connected to the thin film transistor, so the driving line 110 is also called a TFT driving line 110 .

[0042] In this embodiment, the second sub-driving line 112 is closer to the carrier substrate 101 than the first sub-driving line 111. It can be understood that in other embodiments, the second sub-driving line 112 is away from the carrier substrate 101 compared to the first sub-driving line 111. It is sufficient that the second sub-driving line 112 and the first sub-driving line 111 are arranged in different layers.

[0043] The first sub-driving line 111 has a first line body 1111 and a first connecting portion 1112. The first connecting portion 1112 is connected to the first line body 1111. The first line body 1111 is at least partially located in the non-display area 10b of the display panel 10 applied to the array substrate 100. The line width of the first connecting portion 1112 is greater than the line width of the first line body 1111.

[0044] The second sub-driving line 112 is disposed in a different layer from the first sub-driving line 111. For example, an insulating layer 120 is disposed between the second sub-driving line 112 and the first sub-driving line 111. The insulating layer 120 has a through hole 121 corresponding to the first connecting portion 1112 and the second connecting portion 11211. The through hole 121 has a connecting member 111a, and the connecting member 111a connects the first connecting portion 1112 and the second connecting portion 11211. In one embodiment, the connecting member 111a and the first connecting portion 1112 are an integral structure.

[0045] The insulating layer 120 may be, but is not limited to, one or more of silicon oxide, silicon nitride, or silicon oxynitride. The number of layers of the insulating layer 120 may be, but is not limited to, one layer, or greater than or equal to two layers. In one embodiment, when the insulating layer 120 is multiple layers, and when the second sub-driving line 112 is closer to the carrier substrate 101 than the first sub-driving line 111, the insulating layer 120 near the second sub-driving line 112 is one of two film layers of silicon nitride and silicon oxynitride, and the film layer away from the second sub-driving line 112 is a silicon oxide film layer.

[0046] The second sub-driving line 112 is at least partially located in the display area 10a of the display panel 10 used in the array substrate 100. The second driving line 110b is used to electrically connect the thin film transistor located in the display area 10a. Specifically, the second driving line 110b includes a first driving segment 1121, a second driving segment 1122 and a first electrostatic release portion 1123. One end of the first driving segment 1121 has a second connecting portion 11211. Accordingly, the line width of the second connecting portion 11211 is greater than the line width of the remaining portion of the first driving segment 1121.

[0047] The line width of the first connecting portion 1112 is greater than the line width of the first line body 1111, and the line width of the second connecting portion 11211 is greater than the line width of the remaining portion of the first driving segment 1121. Therefore, when the first connecting portion 1112 is electrically connected to the second connecting portion 11211, the electrical connection performance between the first sub-driving line 111 and the second sub-driving line 112 can be better.

[0048] The end of the second driving segment 1122 away from the second connecting portion 11211 is used to be electrically connected to the thin film transistor. The first electrostatic release portion 1123 is located at the connection between the first driving segment 1121 and the other end of the second driving segment 1122. Therefore, the first electrostatic release portion 1123 is far away from the connection between the first connecting portion 1112 and the second connecting portion 11211, and the first electrostatic release portion 1123 is also far away from the thin film transistor. Therefore, when the first electrostatic release portion 1123 and the second electrostatic release portion 132 release static electricity, it is not easy to damage the thin film transistor of the array substrate 100, nor is it easy to damage the connection between the second connecting portion 11211 and the first connecting portion 1112.

[0049] The electrostatic protection layer may be, but is not limited to, a conductive metal or alloy. The driving line 110 may be a single layer or multiple layers (such as double layers or more layers). The material of the electrostatic protection layer may be, but is not limited to, one or more of Cu, Mo, Al, Ti, Nb, and Mg.

[0050] In one embodiment, the electrostatic protection line 130 is located in the non-display area 10b of the display panel 10 applied to the array substrate 100. The electrostatic protection line 130 is arranged in the same layer as the second sub-driving line 112, and there is a gap between the electrostatic protection line 130 and the second sub-driving element. The electrostatic protection line 130 includes a circuit body 131 and a second electrostatic release portion 132, and the circuit body 131 and the second sub-driving line 112 are arranged at intervals. The second electrostatic release portion 132 is located on a side of the circuit body 131 adjacent to the first electrostatic release portion 1123. The second electrostatic release portion 132 is at least partially facing the first electrostatic release portion 1123. In this embodiment, the second electrostatic release portion 132 is directly facing the first electrostatic release portion 1123 as an example for illustration, which can be understood that it should not be understood as a limitation on the embodiment of the present application.

[0051] In this embodiment, the orthographic projection of the first electrostatic discharging portion 1123 on the carrier substrate 101 is a rectangle, and the orthographic projection of the second electrostatic discharging portion 132 on the carrier substrate 101 is a trapezoid.

[0052] When static electricity exists (for example, static electricity generated during the preparation of the array substrate 100 or during use), the static electricity on the driving line 110 is released to the second static electricity releasing portion 132 via the first static electricity releasing portion 1123 , thereby preventing the static electricity on the driving line 110 from damaging the driving line 110 .

[0053] In summary, the array substrate 100 provided in the embodiment of the present application includes a driving line 110 and an electrostatic protection line 130, wherein the driving line 110 includes a first electrostatic release portion 1123, and the electrostatic protection line 130 includes a second electrostatic release portion 132, and the second electrostatic release portion 132 is arranged opposite to and spaced from the first electrostatic release portion 1123. When static electricity exists in the array substrate 100 during the preparation process or in the use process, the static electricity can be released to the second electrostatic release portion 132 via the first electrostatic release portion 1123, thereby reducing or even preventing the risk of static electricity accumulation in the array substrate 100 and burning or breaking down the driving line 110 or other devices in the array substrate 100. It can be seen that the array substrate 100 provided in the embodiment of the present application has a high yield rate, and when the array substrate 100 is applied to the display panel 10, the display image quality of the display panel 10 is high. In addition, in the array substrate 100 provided in the embodiment of the present application, the first electrostatic release portion 1123 is located at the connection between the first driving segment 1121 and the other end of the second driving segment 1122. Therefore, the first electrostatic release portion 1123 is far away from the connection between the first connection portion 1112 and the second connection portion 11211, and the first electrostatic release portion 1123 is also far away from the thin film transistor. Therefore, when the first electrostatic release portion 1123 and the second electrostatic release portion 132 release static electricity, it is not easy to damage the thin film transistor of the array substrate 100, nor is it easy to damage the connection between the second connection portion 11211 and the first connection portion 1112, thereby further improving the display quality of the display panel 10 used by the array substrate 100.

[0054] Please also read Figure 3 , Figure 5 and Figure 6 , Figure 5 A partial schematic diagram of an array substrate provided in the first embodiment of the present application; Figure 6 for Figure 5 Schematic diagram of detailed dimensions of various parts of the array substrate shown in FIG. Figure 5 and Figure 3 The difference is Figure 5 More driving lines 110 are shown in the array substrate.

[0055] In order to facilitate the description of the parameters of each component in the array substrate 100 provided in each embodiment, the parameters of each component in the array substrate 100 in each embodiment are expressed as x. n, where x is a parameter of each component, such as x=a, or b, or c, or d, etc.; n=1, or 2, or 3, the first embodiment is marked with 1, the second embodiment is marked with 2, and the third embodiment is marked with 3. In one implementation, the line width a of the circuit body 131 satisfies: satisfies: 12μm≤a≤18μm. For example, in the array substrate 100 provided in the first embodiment, the line width a1 of the circuit body 131 satisfies: 12μm≤a1≤18μm.

[0056] In this embodiment, the line width a1 of the line body 131 may be, but is not limited to, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, or 18 μm.

[0057] When the line width a1 of the line body 131 is too small, the static electricity is easily damaged when it is transmitted to the line body 131 via the second static electricity release part 132; when the line width a1 of the line body 131 is too large, the non-display area 10b of the display panel 10 used by the array substrate 100 is wider. In the array substrate 100 provided in the embodiment of the present application, the line width a1 of the line body 131 of the static electricity protection line 130 satisfies: 12μm≤a1≤18μm, which can make it difficult for the static electricity transmitted to the line body 131 via the second static electricity release part 132 to damage the line body 131; on the other hand, the non-display area 10b of the display panel 10 used by the array substrate 100 is narrower.

[0058] Please continue reading Figure 3 , Figures 5 and 6 The first electrostatic release portion 1123 is rectangular, and the second electrostatic release portion 132 is trapezoidal. The width of the top side of the second electrostatic release portion 132 is d1, and the width of the bottom side of the second electrostatic release portion 132 is c1, c1-d1≥2μm, 5μm≤c1≤9μm, 3μm≤d1≤7μm.

[0059] In this embodiment, the second electrostatic release portion 132 is a trapezoid, and the width of the top edge of the second electrostatic release portion 132 is smaller than the width of the bottom edge of the second electrostatic release portion 132. Therefore, the second electrostatic release portion 132 and the first electrostatic release portion 1123 can form a better tip discharge, thereby allowing the static electricity of the first electrostatic release portion 1123 to be better released to the second electrostatic release portion 132.

[0060] In addition, the width of the top edge of the second electrostatic release portion 132 is d1, and the width of the bottom edge of the second electrostatic release portion 132 is c1, c1-d1≥2μm. For example, c1-d1 can be but is not limited to 2.0μm, or 2.5μm, or 3.0μm, or 3.5μm, or 4.0μm, or 4.5μm, or 5.0μm, or 5.5μm, or 6.0μm.

[0061] The bottom side c1 of the second electrostatic dissipation portion 132 may be, but is not limited to, 5.0 μm, 5.5 μm, 6.0 μm, 6.5 μm, 7.0 μm, 7.5 μm, 8.0 μm, 8.5 μm, or 9.0 μm.

[0062] The width d1 of the top edge of the second electrostatic release portion 132 may be, but is not limited to, 3.0 μm, 3.5 μm, 4.0 μm, 4.5 μm, 5.0 μm, 5.5 μm, 6.0 μm, 6.5 μm, or 7.0 μm.

[0063] The second electrostatic release portion 132 is a trapezoid. The width of the top side of the second electrostatic release portion 132 is d1, and the width of the bottom side of the second electrostatic release portion 132 is c1, c1-d1≥2μm, and 5μm≤c1≤9μm, 3μm≤d1≤7μm, so that a tip can be formed between the side and the top side of the second electrostatic release portion 132, so that the second electrostatic release portion 132 and the first electrostatic release portion 1123 can form a good tip discharge, so that the static electricity of the first electrostatic release portion 1123 can be better released to the second electrostatic release portion 132.

[0064] Please read further Figure 3 , Figure 5 and Figure 6 The first electrostatic release portion 1123 has a first end surface 112a away from the second driving section 1122. The second electrostatic release portion 132 has a second end surface 130a away from the circuit body 131. The second end surface 130a is at least partially opposite to the first end surface 112a, and the distance e1 between the first end surface 112a and the second end surface 130a satisfies: 12μm≤e1≤18μm.

[0065] For example, the interval e1 between the second end surfaces 130a may be, but is not limited to, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, or 18 μm.

[0066] When the distance between the first end face 112a and the second end face 130a is too small, the static electricity of the first electrostatic release part 1123 can release the static electricity to the second electrostatic release part 132. However, the distance between the first electrostatic release part 1123 and the second electrostatic release part 132 is too small, and when the static electricity is released, the first electrostatic release part 1123 may be damaged. When the distance between the first end face 112a and the second end face 130a is too large, the static electricity of the first electrostatic release part 1123 is not easily conducted to the second electrostatic release part 132, thereby increasing the risk of the driving line 110 and other components of the array substrate 100 (such as TFT, etc.) being damaged by static electricity.

[0067] In the array substrate 100 provided in the embodiment of the present application, the spacing e1 between the first end face 112a and the second end face 130a satisfies: 12μm≤e1≤18μm, and the distance between the first end face 112a and the second end face 130a is moderate. On the one hand, static electricity can be easily released to the second static electricity release portion 132 via the first static electricity release portion 1123, thereby reducing the risk of the driving line 110 and other components of the array substrate 100 being damaged by static electricity; on the other hand, the first static electricity release portion 1123 is not easily damaged.

[0068] In one embodiment, the center line of the first end surface 112a coincides with the center line of the second end surface 130a. When the center line of the first end surface 112a coincides with the center line of the second end surface 130a, when static electricity is transmitted to the second static electricity releasing portion 132 via the first static electricity releasing portion 1123, static electricity can be transmitted to the sharp corner formed by the two side edges and the top edge of the second static electricity releasing portion 132 in a relatively balanced manner, so that the second static electricity releasing portion 132 is not easily damaged by the explosion.

[0069] Furthermore, in one embodiment, the width d1 of the top edge of the second electrostatic release portion 132 is the width of the second end face 130a, and therefore, the width of the second end face 130a is also indicated as d1, and d1 and the width f1 of the first end face 112a satisfy: d1<f1; 3μm≤d1≤7μm, and 7μm≤f1≤11μm.

[0070] The width d1 of the second end surface 130a may be, but is not limited to, 3 μm, 4 μm, 5 μm, 6 μm, or 7 μm. The width f1 of the first end surface 112a may be, but is not limited to, 7 μm, 8 μm, 9 μm, 10 μm, or 11 μm.

[0071] In the array substrate 100 provided in the embodiment of the present application, d1<f1, 3μm≤d1≤7μm, and 7μm≤f1≤11μm. On the one hand, it can make it easier to form tip discharge between the second electrostatic release part 132 and the first electrostatic release part 1123, and it is easier to guide the static electricity of the first electrostatic release part 1123 to the second electrostatic release part 132, thereby reducing or even preventing the risk of static electricity accumulation in the array substrate 100 and burning or breaking down the drive line 110 or other devices in the array substrate 100; on the other hand, the size of the first electrostatic release part 1123 and the second electrostatic release part 132 can be made smaller, which is convenient for setting in the array substrate 100.

[0072] Please refer again Figure 3 , Figures 5 and 6 , a distance k1 between the second connecting portion 11211 and the second driving segment 1122 satisfies: 20 μm≤k1≤26 μm.

[0073] For example, the distance k1 between the second connecting portion 11211 and the second driving segment 1122 may be, but is not limited to, 20 μm, 21 μm, 22 μm, 23 μm, 24 μm, 25 μm, or 26 μm.

[0074] When the distance k1 between the second connecting portion 11211 and the second driving segment 1122 is small, the static electricity of the first electrostatic release portion 1123 may cause damage to the connection between the second connecting portion 11211 and the first connecting portion 1112; when the distance k1 between the second connecting portion 11211 and the second driving segment 1122 is large, the number of driving lines 110 arranged on the array substrate 100 is small, so that the resolution of the display panel 10 used by the array substrate 100 is low.

[0075] In the array substrate 100 provided in the embodiment of the present application, since the first electrostatic release portion 1123 is located at the connection between the first driving segment 1121 and the other end of the second driving segment 1122, when the distance k1 between the second connecting portion 11211 and the second driving segment 1122 satisfies: 20μm≤k1≤26μm, on the one hand, the distance between the first electrostatic release portion 1123 and the connection between the second connecting portion 11211 and the first connecting portion 1112 is relatively far, which can reduce the probability that the static electricity of the first electrostatic release portion 1123 causes damage to the connection between the second connecting portion 11211 and the first connecting portion 1112; on the other hand, the resolution of the display panel 10 used by the array substrate 100 can be higher.

[0076] For further information, see Figure 5 and Figure 6 The array substrate 100 provided in the embodiment of the present application further includes a plurality of driving lines 110. In the present embodiment, the array substrate 100 including three driving lines 110 is used as an example for illustration, which is understandable and should not be construed as limiting the array substrate 100 provided in the embodiment of the present application.

[0077] In this embodiment, the three driving lines 110 are respectively identified as a first driving line 110a, a second driving line 110b and a third driving line 110c. The first sub-driving line 111 of the second driving line 110b is arranged on the side of the second sub-driving line 112 of the first driving line 110a away from the first sub-driving line 111 of the first driving line 110a, and the first sub-driving line 111 of the second driving line 110b is opposite to and spaced from the first sub-driving line 111 of the first driving line 110a. The second sub-driving line 112 of the second driving line 110b is arranged adjacent to the second sub-driving line 112 of the first driving line 110a compared to the first sub-driving line 111 of the second driving line 110b.

[0078] In this embodiment, a distance g1 between the second sub-driving line 112 of the first driving line 110 a and the second sub-driving line 112 of the first driving line 110 a satisfies: 18 μm≤g1≤24 μm.

[0079] For example, the g1 may be, but is not limited to, 18 μm, 19 μm, 20 μm, 21 μm, 22 μm, 23 μm, or 24 μm.

[0080] When the distance g1 between the second sub-driving line 112 of the first driving line 110a and the second sub-driving line 112 of the first driving line 110a satisfies: 18μm≤g1≤24μm, on the one hand, the distance between the adjacent first driving line 110a and the second driving line 110b can be more moderate, which can take into account the resolution requirements of the display panel 10 used by the array substrate 100, and meet the electrostatic release requirements of the adjacent first driving line 110a and the second driving line 110b passing through the same electrostatic protection line 130.

[0081] Further, the first sub-driving line 111 of the third driving line 110c is arranged at an interval with the first sub-driving line of the second driving line 110b, and the first sub-driving line 111 of the third driving line 110c is arranged on a side of the first sub-driving line 111 of the second driving line 110b away from the second sub-driving line 112 of the second driving line 110b. The second sub-driving line 112 of the third driving line 110c is arranged on a side of the first sub-driving line 111 of the third driving line 110c away from the first sub-driving line 111 of the second driving line 110b.

[0082] In this embodiment, a distance l1 between the second connection portion 11211 in the second driving line 110 b and the second connection portion 11211 in the third driving line 110 c satisfies: 12 μm≤l1≤18 μm.

[0083] For example, the g1 may be, but is not limited to, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, or 18 μm.

[0084] When the distance l1 between the second connection portion 11211 in the second driving line 110b and the second connection portion 11211 in the third driving line 110c satisfies: 12μm≤l1≤18μm, on the one hand, the distance between the adjacent second driving lines 110b and the third driving lines 110c can be more moderate, which can take into account the resolution requirements of the display panel 10 used by the array substrate 100, and meet the electrostatic release requirements of the adjacent second driving lines 110b and the third driving lines 110c passing through the same electrostatic protection line 130.

[0085] See also Figure 7 , Figure 7 This is a dimension chart of multiple different parts of the array substrate provided in the first embodiment of the present application. The various parameters of the array substrate 100 provided in this embodiment are based on the application of the array substrate 100 in the display panel 10 of 27UD DRD, and the thin film transistor in the array substrate 100 is a metal oxide thin film transistor as an example, and the yield loss of the array substrate 100 caused by static electricity is reduced to 0%.

[0086] See also Figure 8 and Fig. 9 , Figure 8 A partial top view of an array substrate provided in the second embodiment of the present application; Fig. 9 for Figure 8Detailed dimensions of various parts of the array substrate shown in FIG. The array substrate 100 includes a driving line 110 and an electrostatic protection line 130. The driving line 110 includes a first sub-driving line 111 and a second sub-driving line 112. The first sub-driving line 111 has a first connecting portion 1112. The second sub-driving line 112 is arranged in a different layer from the first sub-driving line 111. The second sub-driving line 112 includes a first driving segment 1121, a second driving segment 1122 and a first electrostatic release portion 1123. One end of the first driving segment 1121 has a second connecting portion 11211. The second connecting portion 11211 is electrically connected to the first connecting portion 1112. The second driving segment 1122 is bent and connected to the other end of the first driving segment 1121 away from the second connecting portion 11211. The first electrostatic release portion 1123 is located at the connection between the first driving segment 1121 and the other end of the second driving segment 1122. The electrostatic protection line 130 is disposed in the same layer as the second sub-driving line 112. The electrostatic protection line 130 includes a connected line body 131 and a second electrostatic release portion 132. The second electrostatic release portion 132 is disposed opposite to the first electrostatic release portion 1123 and spaced apart.

[0087] Please refer to the previous description for the driving line 110 and the electrostatic protection line 130 , which will not be described in detail here.

[0088] In this embodiment, the line width a2 of the line body 131 satisfies: 12 μm≤a2≤18 μm.

[0089] In this embodiment, the line width a2 of the line body 131 may be, but is not limited to, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, or 18 μm.

[0090] When the line width a2 of the line body 131 is too small, the static electricity is easily damaged when it is transmitted to the line body 131 via the second static electricity release part 132; when the line width a2 of the line body 131 is too large, the non-display area 10b of the display panel 10 used by the array substrate 100 is wider. In the array substrate 100 provided in the embodiment of the present application, the line width a2 of the line body 131 of the static electricity protection line 130 satisfies: 12μm≤a2≤18μm, which can make it difficult for the static electricity transmitted to the line body 131 via the second static electricity release part 132 to damage the line body 131; on the other hand, the non-display area 10b of the display panel 10 used by the array substrate 100 is narrower.

[0091] In addition, the difference from the array substrate 100 provided in the first embodiment is that in the array substrate 100 provided in the second embodiment of the present application, the first electrostatic release portion 1123 is arc-shaped, and the second electrostatic release portion 132 is trapezoidal. The width of the top side of the second electrostatic release portion 132 is d2, and the width of the bottom side of the second electrostatic release portion 132 is c2, c2-d2≥2μm, and 5μm≤c2≤9μm, 3μm≤d2≤7μm; the width f2 of the first electrostatic release portion 1123 connected to the connection satisfies: c2<f2.

[0092] In this embodiment, the surface of the first electrostatic release portion 1123 facing the second electrostatic release portion 132 is an arc surface. Therefore, the first electrostatic release portion 1123 can better disperse the static electricity accumulation on the driving line 110, and can better transfer the static electricity from the first electrostatic release portion 1123 to the second electrostatic release portion 132, thereby reducing or even preventing the risk of static electricity accumulation in the array substrate 100 and burning or breaking down the driving line 110 or other devices in the array substrate 100. It can be seen that the array substrate 100 provided in the embodiment of the present application has a high yield rate, and when the array substrate 100 is applied to the display panel 10, the display image quality of the display panel 10 is high.

[0093] Furthermore, in this embodiment, the second electrostatic release portion 132 is a trapezoid, and the width of the top edge of the second electrostatic release portion 132 is smaller than the width of the bottom edge of the second electrostatic release portion 132. Therefore, the second electrostatic release portion 132 and the first electrostatic release portion 1123 can form a better tip discharge, thereby allowing the static electricity of the first electrostatic release portion 1123 to be better released to the second electrostatic release portion 132.

[0094] In addition, the width of the top edge of the second electrostatic release portion 132 is d2, and the width of the bottom edge of the second electrostatic release portion 132 is c2, c2-d2≥2μm. For example, c2-d2 can be but is not limited to 2.0μm, or 2.5μm, or 3.0μm, or 3.5μm, or 4.0μm, or 4.5μm, or 5.0μm, or 5.5μm, or 6.0μm.

[0095] The bottom side c2 of the second electrostatic release portion 132 may be, but is not limited to, 5.0 μm, 5.5 μm, 6.0 μm, 6.5 μm, 7.0 μm, 7.5 μm, 8.0 μm, 8.5 μm, or 9.0 μm.

[0096] The top edge d2 of the second electrostatic release portion 132 may be, but is not limited to, 3.0 μm, 3.5 μm, 4.0 μm, 4.5 μm, 5.0 μm, 5.5 μm, 6.0 μm, 6.5 μm, or 7.0 μm.

[0097] The second electrostatic release portion 132 is a trapezoid. The width of the top side of the second electrostatic release portion 132 is d2, and the width of the bottom side of the second electrostatic release portion 132 is c2, c2-d2≥2μm, and 5μm≤c2≤9μm, 3μm≤d2≤7μm, so that a tip can be formed between the side and the top side of the second electrostatic release portion 132, so that the second electrostatic release portion 132 and the first electrostatic release portion 1123 can form a good tip discharge, so that the static electricity of the first electrostatic release portion 1123 can be better released to the second electrostatic release portion 132.

[0098] In addition, the width f2 of the first electrostatic release portion 1123 at the connection portion satisfies: c2<f2, so that when the first electrostatic release portion 1123 transmits static electricity to the second electrostatic release portion 132, the risk of the first electrostatic release portion 1123 being damaged by static electricity is reduced, thereby reducing the risk of the driving line 110 being burned by static electricity and causing product defects (array substrate 100 and display panel 10 used by array substrate 100).

[0099] Please read further Figure 8 and Fig. 9 The first electrostatic release portion 1123 has a first end surface 112a away from the second driving section 1122. The second electrostatic release portion 132 has a second end surface 130a away from the circuit body 131. The second end surface 130a is at least partially opposite to the first end surface 112a, and the distance e2 between the first end surface 112a and the second end surface 130a satisfies: 12μm≤e2≤18μm.

[0100] For example, the interval e2 between the second end surfaces 130a and the second end surfaces 130a may be, but is not limited to, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, or 18 μm.

[0101] When the distance between the first end face 112a and the second end face 130a is too small, the static electricity of the first electrostatic release part 1123 can release the static electricity to the second electrostatic release part 132. However, the distance between the first electrostatic release part 1123 and the second electrostatic release part 132 is too small, and when the static electricity is released, the first electrostatic release part 1123 may be damaged. When the distance between the first end face 112a and the second end face 130a is too large, the static electricity of the first electrostatic release part 1123 is not easily conducted to the second electrostatic release part 132, thereby increasing the risk of the driving line 110 and other components of the array substrate 100 (such as TFT, etc.) being damaged by static electricity.

[0102] In the array substrate 100 provided in the embodiment of the present application, the spacing e2 between the first end face 112a and the second end face 130a satisfies: 12μm≤e2≤18μm. The distance between the first end face 112a and the second end face 130a is moderate. On the one hand, static electricity can be easily released to the second static electricity release portion 132 via the first static electricity release portion 1123, thereby reducing the risk of the driving line 110 and other components of the array substrate 100 being damaged by static electricity. On the other hand, the first static electricity release portion 1123 is not easily damaged.

[0103] In one embodiment, the center line of the first end surface 112a coincides with the center line of the second end surface 130a. When the center line of the first end surface 112a coincides with the center line of the second end surface 130a, when static electricity is transmitted to the second static electricity releasing portion 132 via the first static electricity releasing portion 1123, static electricity can be transmitted to the sharp corner formed by the two side edges and the top edge of the second static electricity releasing portion 132 in a relatively balanced manner, so that the second static electricity releasing portion 132 is not easily damaged by the explosion.

[0104] Further, when the first electrostatic release portion 1123 is arc-shaped: in the direction from the first electrostatic release portion 1123 to the second electrostatic release portion 132, the size h2 of the first electrostatic release portion 1123 satisfies: 4μm≤h2≤8μm; and 10μm≤f2≤14μm.

[0105] For example, in the direction from the first electrostatic release portion 1123 to the second electrostatic release portion 132, the size h2 of the first electrostatic release portion 1123 may be, but not limited to, 4 μm, 5 μm, 6 μm, 7 μm, or 8 μm. The width f2 of the first electrostatic release portion 1123 at the connection may be, but not limited to, 10 μm, 11 μm, 12 μm, 13 μm, or 14 μm.

[0106] When the first electrostatic release portion 1123 is arc-shaped: in the direction from the first electrostatic release portion 1123 to the second electrostatic release portion 132, the size h2 of the first electrostatic release portion 1123 satisfies: 4μm≤h2≤8μm; and 10μm≤f2≤14μm, the first electrostatic release portion 1123 can better disperse the static electricity accumulation on the driving line 110, and can better transfer the static electricity from the first electrostatic release portion 1123 to the second electrostatic release portion 132, thereby reducing or even preventing the risk of static electricity accumulation in the array substrate 100 and burning or breaking down the driving line 110 or other devices in the array substrate 100. It can be seen that the array substrate 100 provided in the embodiment of the present application has a high yield rate, and when the array substrate 100 is applied to the display panel 10, the display image quality of the display panel 10 is high.

[0107] It can be understood that if the components not introduced in the array substrate provided in the second embodiment are the same as the corresponding components of the array substrate provided in the first embodiment, please refer to the description of the array substrate provided in the first embodiment and no further details will be given here.

[0108] See also Fig.10 , Fig.10 This is a size chart of multiple different parts of the array substrate provided in the second embodiment of the present application. The various parameters of the array substrate 100 provided in this embodiment are based on the application of the array substrate 100 in the display panel 10 of 27UD DRD, and the thin film transistor in the array substrate 100 is a metal oxide thin film transistor as an example, and the yield loss of the array substrate 100 caused by static electricity is reduced to 0%.

[0109] Please also read Fig.11 and Fig.12 , Fig.11 A partial top view of an array substrate provided in the third embodiment of the present application; Fig.12 for Fig.11Detailed dimensions of various parts of the array substrate shown in FIG. The array substrate 100 includes a driving line 110 and an electrostatic protection line 130. The driving line 110 includes a first sub-driving line 111 and a second sub-driving line 112. The first sub-driving line 111 has a first connecting portion 1112. The second sub-driving line 112 is arranged in a different layer from the first sub-driving line 111. The second sub-driving line 112 includes a first driving segment 1121, a second driving segment 1122 and a first electrostatic release portion 1123. One end of the first driving segment 1121 has a second connecting portion 11211. The second connecting portion 11211 is electrically connected to the first connecting portion 1112. The second driving segment 1122 is bent and connected to the other end of the first driving segment 1121 away from the second connecting portion 11211. The first electrostatic release portion 1123 is located at the connection between the first driving segment 1121 and the other end of the second driving segment 1122. The electrostatic protection line 130 is disposed in the same layer as the second sub-driving line 112. The electrostatic protection line 130 includes a connected line body 131 and a second electrostatic release portion 132. The second electrostatic release portion 132 is disposed opposite to the first electrostatic release portion 1123 and spaced apart.

[0110] The driving line 110 and the electrostatic protection line 130 are described above and will not be described again. The first electrostatic release portion 1123 is a trapezoid, and the second electrostatic release portion 132 is a trapezoid.

[0111] In this embodiment, the line width a3 of the line body 131 satisfies: 12 μm≤a3≤18 μm.

[0112] In this embodiment, the line width a3 of the line body 131 may be, but is not limited to, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, or 18 μm.

[0113] When the line width a3 of the line body 131 is too small, the static electricity is easily damaged when it is transmitted to the line body 131 via the second static electricity release part 132; when the line width a3 of the line body 131 is too large, the non-display area 10b of the display panel 10 used by the array substrate 100 is wider. In the array substrate 100 provided in the embodiment of the present application, the line width a3 of the line body 131 of the static electricity protection line 130 satisfies: 12μm≤a3≤18μm, which can make it difficult for the static electricity transmitted to the line body 131 via the second static electricity release part 132 to damage the line body 131; on the other hand, the non-display area 10b of the display panel 10 used by the array substrate 100 is narrower.

[0114] Furthermore, the width of the top side of the second electrostatic release portion 132 is d3, the width of the bottom side of the second electrostatic release portion 132 is c3, c3-d3≥2μm, 5μm≤c3≤9μm, 3μm≤d3≤7μm.

[0115] In this embodiment, the second electrostatic release portion 132 is a trapezoid, and the width of the top edge of the second electrostatic release portion 132 is smaller than the width of the bottom edge of the second electrostatic release portion 132. Therefore, the second electrostatic release portion 132 and the first electrostatic release portion 1123 can form a better tip discharge, thereby allowing the static electricity of the first electrostatic release portion 1123 to be better released to the second electrostatic release portion 132.

[0116] In addition, the width of the top edge of the second electrostatic release portion 132 is d3, and the width of the bottom edge of the second electrostatic release portion 132 is c3, c3-d3≥2μm. For example, c3-d3 can be but is not limited to 2.0μm, or 2.5μm, or 3.0μm, or 3.5μm, or 4.0μm, or 4.5μm, or 5.0μm, or 5.5μm, or 6.0μm.

[0117] The width c3 of the bottom side of the second electrostatic release portion 132 may be, but is not limited to, 5.0 μm, 5.5 μm, 6.0 μm, 6.5 μm, 7.0 μm, 7.5 μm, 8.0 μm, 8.5 μm, or 9.0 μm.

[0118] The width d3 of the top edge of the second electrostatic release portion 132 may be, but is not limited to, 3.0 μm, 3.5 μm, 4.0 μm, 4.5 μm, 5.0 μm, 5.5 μm, 6.0 μm, 6.5 μm, or 7.0 μm.

[0119] The second electrostatic release portion 132 is a trapezoid. The width of the top side of the second electrostatic release portion 132 is d3, the width of the bottom side of the second electrostatic release portion 132 is c3, c3-d3≥2μm, 5μm≤c3≤9μm, 3μm≤d3≤7μm, so that a tip can be formed between the side and the top side of the second electrostatic release portion 132, so that the second electrostatic release portion 132 and the first electrostatic release portion 1123 can form a good tip discharge, so that the static electricity of the first electrostatic release portion 1123 can be better released to the second electrostatic release portion 132.

[0120] The first electrostatic release portion 1123 has a first end surface 112a away from the second driving section 1122. The second electrostatic release portion 132 has a second end surface 130a away from the circuit body 131. The second end surface 130a is at least partially opposite to the first end surface 112a, and a distance e3 between the first end surface 112a and the second end surface 130a satisfies: 12μm≤e3≤18μm.

[0121] For example, the interval e3 between the second end surfaces 130a may be, but is not limited to, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, or 18 μm.

[0122] When the distance between the first end face 112a and the second end face 130a is too small, the static electricity of the first electrostatic release part 1123 can release the static electricity to the second electrostatic release part 132. However, the distance between the first electrostatic release part 1123 and the second electrostatic release part 132 is too small, and when the static electricity is released, the first electrostatic release part 1123 may be damaged. When the distance between the first end face 112a and the second end face 130a is too large, the static electricity of the first electrostatic release part 1123 is not easily conducted to the second electrostatic release part 132, thereby increasing the risk of the driving line 110 and other components of the array substrate 100 (such as TFT, etc.) being damaged by static electricity.

[0123] In the array substrate 100 provided in the embodiment of the present application, the spacing e3 between the first end face 112a and the second end face 130a satisfies: 12μm≤e3≤18μm. The distance between the first end face 112a and the second end face 130a is moderate. On the one hand, static electricity can be easily released to the second static electricity release portion 132 via the first static electricity release portion 1123, thereby reducing the risk of the driving line 110 and other components of the array substrate 100 being damaged by static electricity. On the other hand, the first static electricity release portion 1123 is not easily damaged.

[0124] In one embodiment, the center line of the first end surface 112a coincides with the center line of the second end surface 130a. When the center line of the first end surface 112a coincides with the center line of the second end surface 130a, when static electricity is transmitted to the second static electricity releasing portion 132 via the first static electricity releasing portion 1123, static electricity can be transmitted to the sharp corner formed by the two side edges and the top edge of the second static electricity releasing portion 132 in a relatively balanced manner, so that the second static electricity releasing portion 132 is not easily damaged by the explosion.

[0125] In the array substrate 100 provided in the third embodiment, the first electrostatic release portion 1123 is a trapezoid, and the second electrostatic release portion 132 is a trapezoid. The width of the top side of the second electrostatic release portion 132 is d3, and the width of the bottom side of the second electrostatic release portion 132 is c3, c3-d3≥2μm, and 5μm≤c3≤9μm, 3μm≤d3≤7μm; the width f3 of the first electrostatic release portion 1123 connected to the connection portion satisfies: c3<f3.

[0126] In this embodiment, the first electrostatic release portion 1123 is a trapezoid, and the second electrostatic release portion 132 is a trapezoid, and the side and top of the trapezoid are pointed. Therefore, both the first electrostatic release portion 1123 and the second electrostatic release portion 132 have pointed ends, and the first electrostatic release portion 1123 and the second electrostatic release portion 132 can discharge through the pointed ends, and the static electricity can be better transferred from the first electrostatic release portion 1123 to the second electrostatic release portion 132, thereby reducing or even preventing the risk of static electricity accumulation in the array substrate 100 and burning or breaking down the drive line 110 or other devices in the array substrate 100. It can be seen that the array substrate 100 provided in the embodiment of the present application has a high yield rate, and when the array substrate 100 is applied to the display panel 10, the display image quality of the display panel 10 is high.

[0127] Furthermore, in this embodiment, the second electrostatic release portion 132 is a trapezoid, and the width of the top edge of the second electrostatic release portion 132 is smaller than the width of the bottom edge of the second electrostatic release portion 132. Therefore, the second electrostatic release portion 132 and the first electrostatic release portion 1123 can form a better tip discharge, thereby allowing the static electricity of the first electrostatic release portion 1123 to be better released to the second electrostatic release portion 132.

[0128] In addition, the width of the top edge of the second electrostatic release portion 132 is d3, and the width of the bottom edge of the second electrostatic release portion 132 is c3, c3-d3≥2μm. For example, c3-d3 can be but is not limited to 2.0μm, or 2.5μm, or 3.0μm, or 3.5μm, or 4.0μm, or 4.5μm, or 5.0μm, or 5.5μm, or 6.0μm.

[0129] The bottom side c3 of the second electrostatic release portion 132 may be, but is not limited to, 5.0 μm, 5.5 μm, 6.0 μm, 6.5 μm, 7.0 μm, 7.5 μm, 8.0 μm, 8.5 μm, or 9.0 μm.

[0130] The top edge d3 of the second electrostatic release portion 132 may be, but is not limited to, 3.0 μm, 3.5 μm, 4.0 μm, 4.5 μm, 5.0 μm, 5.5 μm, 6.0 μm, 6.5 μm, or 7.0 μm.

[0131] The second electrostatic release portion 132 is a trapezoid. The width of the top side of the second electrostatic release portion 132 is d3, the width of the bottom side of the second electrostatic release portion 132 is c3, c3-d3≥2μm, 5μm≤c3≤9μm, 3μm≤d3≤7μm, so that a tip can be formed between the side and the top side of the second electrostatic release portion 132, so that the second electrostatic release portion 132 and the first electrostatic release portion 1123 can form a good tip discharge, so that the static electricity of the first electrostatic release portion 1123 can be better released to the second electrostatic release portion 132.

[0132] In addition, the width f3 of the first electrostatic release portion 1123 at the connection portion satisfies: c3<f3, so that when the first electrostatic release portion 1123 transmits static electricity to the second electrostatic release portion 132, the risk of the first electrostatic release portion 1123 being damaged by static electricity is reduced, thereby reducing the risk of the driving line 110 being burned by static electricity and causing product defects (array substrate 100 and display panel 10 used by array substrate 100).

[0133] Further, in this embodiment, the first electrostatic release portion 1123 is a trapezoid, the size m3 of the top side of the trapezoid satisfies: 8μm≤m3≤12μm, and the width f3 of the first electrostatic release portion 1123 connected to the connection satisfies: 10μm≤m3≤14μm. The connection of the first electrostatic release portion 1123 to the connection is the bottom side of the trapezoid.

[0134] For example, m3 may be, but is not limited to, 8 μm, 9 μm, 10 μm, 11 μm, or 12 μm. f3 may be, but is not limited to, 10 μm, 11 μm, 12 μm, 13 μm, or 14 μm.

[0135] The first electrostatic release portion 1123 is a trapezoid, and the size m3 of the top side of the trapezoid satisfies: 8μm≤m3≤12μm, and the width f3 of the first electrostatic release portion 1123 at the connection (that is, the size of the bottom side of the trapezoid) satisfies: 10μm≤m3≤14μm, so that static electricity can be better transmitted to the second electrostatic release portion 132 via the first electrostatic release portion 1123, and static electricity accumulation on the driving line 110 can be more effectively dispersed, and product defects caused by burns of the driving line 110 can be effectively reduced.

[0136] It can be understood that if the components not introduced in the array substrate provided in the third embodiment are the same as the corresponding components of the array substrate provided in the first embodiment or the second embodiment, please refer to the description of the array substrate provided in the first embodiment or the second embodiment and no further details will be given here.

[0137] See also Fig.13 , Fig.13 This is a dimension chart of multiple different parts of the array substrate provided in the third embodiment of the present application. The various parameters of the array substrate 100 provided in this embodiment are based on the application of the array substrate 100 in the display panel 10 of 27UD DRD, and the thin film transistor in the array substrate 100 is a metal oxide thin film transistor as an example, and the yield loss of the array substrate 100 caused by static electricity is reduced to 0%.

[0138] Further, in combination with the array substrate 100 provided in the first embodiment, the second embodiment and the third embodiment, the line width i of the first driving segment 1121 is n is greater than the line width j of the second driving segment 1122 n , where n=1, or 2, or 3.

[0139] The line width of the first driving segment 1121 is greater than the line width of the second driving line 110b, so that static electricity on the array substrate 100 is not easily transmitted to the connection between the second connecting portion 11211 and the first connecting portion 1112 through the first driving segment 1121, and the first driving segment 1121 is not easily damaged.

[0140] In summary, the embodiment of the present application provides an array substrate 100. In summary, the array substrate 100 provided in the embodiment of the present application includes a driving line 110 and an electrostatic protection line 130. The driving line 110 includes a first electrostatic release portion 1123, and the electrostatic protection line 130 includes a second electrostatic release portion 132. The second electrostatic release portion 132 is arranged opposite to and spaced from the first electrostatic release portion 1123. When static electricity exists in the array substrate 100 during the preparation process or in the use process, the static electricity can be released to the second electrostatic release portion 132 via the first electrostatic release portion 1123, thereby reducing or even preventing the risk of static electricity accumulation in the array substrate 100 and burning or breaking down the driving line 110 or other devices in the array substrate 100. It can be seen that the array substrate 100 provided in the embodiment of the present application has a high yield rate. When the array substrate 100 is applied to the display panel 10, the display image quality of the display panel 10 is high. For example, the yield loss of the array substrate 100 including the metal oxide semiconductor TFT in the related art is about 20%, while the yield loss of the array substrate 100 provided in the embodiment of the present application can be greatly reduced, even to 0%.

[0141] The following is a brief introduction to the preparation method of the array substrate 100 provided in one embodiment of the present application. The preparation method of the array substrate 100 provided in the embodiment of the present application can be used to prepare the array substrate 100 introduced in the previous embodiment. Accordingly, the array substrate 100 introduced in the previous embodiment can be prepared by the preparation method of the array substrate 100 provided in the embodiment of the present application.

[0142] See also Fig.14 , Fig.14 The flowchart of the method for preparing an array substrate provided in one embodiment of the present application is as follows: The method for preparing the array substrate 100 includes but is not limited to S100, S200, and S300, which are described in detail as follows.

[0143] S100 , forming a first metal layer on one side of the carrier substrate 101 , and patterning the first metal layer to form a second sub-driving line 112 and an electrostatic protection line 130 , wherein the second sub-driving line 112 includes a first driving segment 1121 , a second driving segment 1122 and a first electrostatic release portion 1123 .

[0144] The carrier substrate 101 may be, but is not limited to, a glass substrate. The first metal layer may be, but is not limited to, a single metal or an alloy. The material of the first metal layer may be, but is not limited to, one or more of Cu, Mo, Al, Ti, Nb, and Mg. The first metal layer may be a single layer or multiple layers (such as double layers or more layers).

[0145] The first metal layer may be formed by, but not limited to, magnetron sputtering. Patterning the first metal layer may include, but not limited to, exposure, development, wet etching and stripping.

[0146] S200 , forming an insulating layer 120 covering the second sub-driving line 112 and the electrostatic protection line 130 , and forming a new through hole 121 corresponding to the second connecting portion 11211 on the insulating layer 120 .

[0147] Specifically, the insulating layer 120 is also referred to as an insulating medium layer or an insulating dielectric layer. The insulating layer 120 may be formed by, but is not limited to, chemical vapor deposition.

[0148] The insulating layer 120 may be, but is not limited to, one or more of silicon oxide, silicon nitride, or silicon oxynitride. The number of layers of the insulating layer 120 may be, but is not limited to, one layer, or greater than or equal to two layers. In one embodiment, when the insulating layer 120 is multiple layers, the insulating layer 120 near the second sub-driving line 112 in the insulating layer 120 is one of two film layers of silicon nitride and silicon oxynitride, and the film layer away from the second sub-driving line 112 is a silicon oxide film layer.

[0149] When forming the through hole 121 on the insulating layer 120 , it can be formed by coating, exposing, developing, dry etching, etc.

[0150] S300 , forming a second metal layer on the insulating layer 120 , and patterning the second metal layer to form a first sub-driving line 111 , wherein the first sub-driving line 111 includes a first connecting portion 1112 , and the first connecting portion 1112 is electrically connected to the second connecting portion 11211 through the through hole 121 .

[0151] The first metal layer may be, but is not limited to, a single metal or an alloy. The material of the first metal layer may be, but is not limited to, one or more of Cu, Mo, Al, Ti, Nb, and Mg. The first metal layer may be a single layer or multiple layers (such as a double layer or more layers).

[0152] The second metal layer may be formed by, but not limited to, magnetron sputtering. Patterning the second metal layer may include, but not limited to, exposure, development, wet etching and stripping.

[0153] It can be seen that, compared with the method for preparing the array substrate 100 provided in the related art, the method for preparing the array substrate 100 provided in the embodiment of the present application does not change the materials and process conditions, and there is no additional cost increase.

[0154] The present application also provides a display panel 10. Fig.15 , Fig.15 This is a schematic diagram of a display panel provided in one embodiment of the present application. The display panel 10 includes an array substrate 100 as described in any of the above embodiments. Please refer to the above description of the array substrate 100, which will not be described again here.

[0155] The display panel 10 may be, but is not limited to, an LCD display panel, or an organic electroluminescent (OLED) display panel, or a mini light emitting diode (Mini-LED) display panel, etc.

[0156] In the schematic diagram of this embodiment, the display panel 10 further includes a housing 600. The housing 600 is used to carry the array substrate 100. It is understandable that this should not be construed as a limitation on the display panel 10 and the array substrate 100 provided in the embodiment of the present application.

[0157] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in the field can change, modify, replace and modify the above embodiments within the scope of the present application, and these improvements and modifications are also regarded as the scope of protection of the present application.

Claims

1. An array substrate, characterized in that: The array substrate comprises: A driving line, wherein the driving line comprises a first sub-driving line and a second sub-driving line, the first sub-driving line has a first connecting portion, the second sub-driving line and the first sub-driving line are arranged in different layers, the second sub-driving line comprises a first driving segment, a second driving segment and a first electrostatic release portion, one end of the first driving segment has a second connecting portion, the second connecting portion is electrically connected to the first connecting portion, the second driving segment is bent and connected to the other end of the first driving segment away from the second connecting portion, and the first electrostatic release portion is located at the connection between the first driving segment and the other end of the second driving segment; and an electrostatic protection line, arranged in the same layer as the second sub-driving line, the electrostatic protection line comprising a connected line body and a second electrostatic release portion, the second electrostatic release portion being opposite to and spaced from the first electrostatic release portion, the second electrostatic release portion and the first electrostatic release portion forming a tip discharge, thereby causing the static electricity of the first electrostatic release portion to be released to the second electrostatic release portion; The first electrostatic release portion has a first end surface facing away from the second driving section, the second electrostatic release portion has a second end surface facing away from the circuit body, and the center line of the first end surface coincides with the center line of the second end surface.

2. The array substrate according to claim 1, characterized in that: The line width a of the circuit body satisfies: 12 μm≤a≤18 μm.

3. The array substrate according to claim 2, characterized in that: The first electrostatic release portion is rectangular, and the second electrostatic release portion is trapezoidal; The width of the top side of the second electrostatic release portion is d1, the width of the bottom side of the second electrostatic release portion is c1, c1-d1≥2μm, 5μm≤c1≤9μm, 3μm≤d1≤7μm.

4. The array substrate according to claim 2, characterized in that: The second end surface is at least partially opposite to the first end surface, and a distance e1 between the first end surface and the second end surface satisfies: 12 μm≤e1≤18 μm.

5. The array substrate according to claim 4, characterized in that: The width d1 of the second end surface and the width f1 of the first end surface satisfy: d1<f1; 3μm≤d1≤7μm, and 7μm≤f1≤11μm.

6. The array substrate according to claim 1, characterized in that: A distance k1 between the second connecting portion and the second driving segment satisfies: 20 μm≤k1≤26 μm.

7. The array substrate according to claim 2, characterized in that: The first electrostatic release portion is arc-shaped or trapezoidal, and the second electrostatic release portion is trapezoidal; the width of the top edge of the second electrostatic release portion is d2, and the width of the bottom edge of the second electrostatic release portion is c2, c2-d2≥2μm, and 5μm≤c2≤9μm, 3μm≤d2≤7μm; the width f2 of the first electrostatic release portion connected to the connection satisfies: c2<f2.

8. The array substrate according to claim 7, characterized in that: When the first electrostatic releasing portion is arc-shaped: in the direction from the first electrostatic releasing portion to the second electrostatic releasing portion, a size h2 of the first electrostatic releasing portion satisfies: 4μm≤h2≤8μm; and 10μm≤f2≤14μm.

9. The array substrate according to any one of claims 1 to 8, characterized in that: The line width of the first driving segment is greater than the line width of the second driving segment.

10. A display panel, characterized in that: The display panel comprises the array substrate as claimed in any one of claims 1 to 9.

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