A current mirror circuit

Abstract

The present application proposes a current mirror circuit, comprising: a first branch, one end of which is configured to receive a fixed level, and a second end of which is configured to receive an input current; a second branch, which is electrically connected to the first branch at a first node and a second node, one end of which is configured to receive a fixed level, and a second end of which is configured to provide an output current, wherein the output current is generated based on the input current; a third branch, which at least includes: a first resistor, one end of which is configured to receive a fixed level; a first transistor, a drain of which is electrically connected to the other end of the first resistor, a gate of which is electrically connected to the first node, a source of which and a substrate of which are electrically connected to the second node and configured to receive a bias current. The current mirror circuit of the present application has high replication accuracy, a wide range of replicable reference current, less occupied voltage margin, a simple circuit, no need to introduce a clamping loop, and eliminates potential loop stability problems.

Description

Technical Field

[0001] The present application relates to the field of circuits, and in particular to a current mirror circuit. Background Art

[0002] In integrated circuit chips, there are many voltage bias and current bias circuits, which are used to enable the chip circuits to operate normally. Most of them use current mirror technology for current bias.

[0003] A current mirror is a basic unit in analog circuits. Its function is to receive a reference current and replicate it as an equal or multiple current output. It can also be used to load a differential pair.

[0004] In addition, the current of some chips is controlled by external resistors to adjust some parameters of the chip, such as chip operating frequency, output current, etc. In this case, the resistance range of the external resistor is relatively large, and the corresponding bias current variation range is also relatively large, so a current mirror circuit that can accurately mirror and copy the reference current is very important.

[0005] The design requirements for the current mirror circuit are not only to be able to accurately replicate the reference current, but also to occupy as little voltage margin as possible while maintaining the replication accuracy, and to be able to mirror the replicated current in a range as wide as possible to provide as much margin as possible for the design of other circuits. At the same time, it is hoped that the reference current will not be affected by changes in the power supply voltage.

[0006] Conventional current mirrors occupy relatively small voltage margins, but have limited replication accuracy.

[0007] The cascode current mirror can accurately replicate the reference current and resist a certain degree of power supply voltage variation, but it will occupy a large voltage margin and the mirror-copied current range is relatively narrow.

[0008] The current mirror with operational amplifier clamp can improve the replication accuracy of the current mirror and the range of the mirror-replicated current. Figure 1 The figure shows a schematic circuit diagram of an existing current mirror. This circuit not only introduces an operational amplifier, but also has a clamping loop. The circuit structure is complex and the layout area is large. Figure 2 FIG. 2 is another schematic circuit diagram of an existing current mirror. The clamping loop in the circuit may cause stability problems to the current mirror circuit. Figure 1 and Figure 2 As shown in the example, this type of current mirror requires the introduction of an additional operational amplifier, which increases the complexity of the circuit and the area of ​​the chip, resulting in a significant increase in the complexity and cost of chip design.

[0009] Therefore, a current mirror circuit is needed that has a wide replicable reference current range, high replica accuracy, small occupied voltage margin, and will not significantly increase the layout area. Summary of the invention

[0010] In view of the technical problems existing in the prior art, the present application proposes a current mirror circuit, comprising: a first branch, one end of which is configured to receive a fixed level, and a second end of which is configured to receive an input current; a second branch, which is electrically connected to the first branch at a first node and a second node, one end of which is configured to receive the fixed level, and a second end of which is configured to provide an output current, wherein the output current is generated based on the input current; a third branch, which at least comprises: a first resistor, one end of which is configured to receive the fixed level; a first transistor, a drain of which is electrically connected to the other end of the first resistor, a gate of which is electrically connected to the first node, a source and a substrate of which are electrically connected to the second node and configured to receive a bias current; wherein the first branch comprises at least one first sub-branch, and the first sub-branch comprises at least: a second transistor , whose source and substrate are configured to receive the fixed level, and whose gate is electrically connected to the first node; at least one third transistor, whose source is electrically connected to the drain of the second transistor, whose drain is electrically connected to the gate of the second transistor and configured to receive the input current, whose gate is electrically connected to the second node, and whose substrate is electrically connected to the substrate of the second transistor; wherein the second branch includes at least one second sub-branch, and the second sub-branch includes at least: a fourth transistor, whose gate is electrically connected to the gate of the second transistor, whose source and substrate are configured to receive the fixed level; at least one fifth transistor, whose source is electrically connected to the drain of the fourth transistor, whose gate is electrically connected to the second node, whose drain is configured to output the output current, and whose substrate is electrically connected to the substrate of the fourth transistor.

[0011] In particular, the second transistor and the fourth transistor have the same size; and the third transistor and the fifth transistor have the same size.

[0012] In particular, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are of the same type; and the first transistor is of a complementary type to the other transistors.

[0013] In particular, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are PMOS transistors; and the first transistor is an NMOS transistor.

[0014] In particular, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are NMOS transistors; and the first transistor is a PMOS transistor.

[0015] In particular, the fixed level is a power supply voltage.

[0016] In particular, the fixed level is a ground level.

[0017] In particular, the first branch includes one first sub-branch, and the second branch includes one second sub-branch.

[0018] In particular, the first branch includes one first sub-branch, and the second branch includes M second sub-branches, where M is an integer greater than 1; wherein the drains of all the fifth transistors in the M second sub-branches are electrically connected together.

[0019] In particular, the first branch includes N first sub-branches, and the second branch includes one second sub-branch, N is an integer greater than 1; wherein the drains of all the third transistors in the N first sub-branches are electrically connected together.

[0020] In particular, the input current has an order of magnitude range of 10 -6 Ampere to 10 -2 ampere.

[0021] The current mirror circuit proposed in the present application has high replication accuracy, a wide range of replicable reference current, small occupied voltage margin, a simple circuit, no need to introduce a clamping loop, and eliminates potential loop stability problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Below, the preferred embodiments of the present application will be further described in detail with reference to the accompanying drawings, wherein:

[0023] Figure 1 is a schematic circuit diagram of an existing current mirror;

[0024] Figure 2 is another schematic circuit diagram of an existing current mirror;

[0025] Figure 3 is a schematic diagram of a current mirror circuit according to an embodiment of the present application;

[0026] Figure 4 is a schematic diagram of another current mirror circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0028] In the following detailed description, reference may be made to the various specification drawings that are part of the present application and are used to illustrate specific embodiments of the present application. In the accompanying drawings, similar reference numerals describe substantially similar components in different figures. The various specific embodiments of the present application are described below in sufficient detail so that a person of ordinary skill in the art with relevant knowledge and skills in the art can implement the technical solutions of the present application. It should be understood that other embodiments may also be used or structural, logical or electrical changes may be made to the embodiments of the present application.

[0029] The technologies, methods and devices known to those skilled in the art may not be discussed in detail, but where appropriate, the technologies, methods and devices shall be considered as part of the specification. The lines between the units in the drawings are only for the convenience of explanation, indicating that at least the units at both ends of the lines are communicating with each other, and are not intended to limit the unconnected units from being unable to communicate. In addition, the number of lines between two units is intended to indicate at least the number of signals involved in the communication between the two units or at least the output terminals, and is not intended to limit the two units to only be able to communicate with each other through the signals shown in the figure.

[0030] A transistor may refer to a transistor of any structure, such as a field effect transistor (FET) or a bipolar junction transistor (BJT). When the transistor is a field effect transistor, it may be hydrogenated amorphous silicon, metal oxide, low temperature polysilicon, organic transistor, etc., depending on the channel material. Depending on whether the carrier is an electron or a hole, it can be divided into an N-type transistor and a P-type transistor, wherein the control electrode refers to the gate of the field effect transistor, the first electrode may be the drain or source of the field effect transistor, and the corresponding second electrode may be the source or drain of the field effect transistor; when the transistor is a bipolar transistor, the control electrode refers to the base of the bipolar transistor, the first electrode may be the collector or emitter of the bipolar transistor, and the corresponding second electrode may be the emitter or collector of the bipolar transistor. The transistor may be manufactured using amorphous silicon, polycrystalline silicon, oxide semiconductor, organic semiconductor, NMOS / PMOS process or CMOS process.

[0031] The present application proposes a current mirror circuit, which, compared with a traditional current mirror circuit, not only has high replication accuracy, but also has a wide range of replicable reference current and occupies less voltage margin; compared with a current mirror with an operational amplifier and a clamping loop, the circuit is simplified, the layout area is saved, and there is no clamping loop in the circuit, eliminating potential loop stability problems.

[0032] Figure 3 is a schematic diagram of a current mirror circuit according to an embodiment of the present application.

[0033] According to one embodiment, Figure 3 The current mirror 100 shown may include a first branch 110 configured to receive an analog power supply voltage AVDD and a reference current I source1 .

[0034] According to one embodiment, Figure 3 The current mirror 100 shown may include a second branch 120, which is configured to receive an analog power supply voltage AVDD and output a current I mirror1 .

[0035] According to one embodiment, the first branch 110 and the second branch 120 are electrically connected at a first node A1 and a second node B1.

[0036] According to one embodiment, the first branch 110 may include at least one first sub-branch 111 .

[0037] According to one embodiment, the first sub-branch 111 may include a second transistor M11 .

[0038] According to one embodiment, the second transistor M11 may be a PMOS transistor, a source and a substrate of which are electrically connected to the analog power supply voltage AVDD, and a gate of which is electrically connected to the first node A1.

[0039] According to one embodiment, the first sub-branch 111 may include at least one third transistor M12 .

[0040] According to one embodiment, the third transistor M12 may be a PMOS transistor having a substrate electrically connected to the substrate of the second transistor M11, a source electrically connected to the drain of the second transistor M11, a drain electrically connected to the first node A1, and a gate electrically connected to the second node B1.

[0041] According to one embodiment, the drain of the third transistor M12 is configured to receive the reference current I source1 .

[0042] According to one embodiment, the reference current I source1It can be the current set by the external resistor of the chip, or the sampling current of the current sampling circuit.

[0043] According to one embodiment, the second branch 120 may include at least one second sub-branch 121 .

[0044] According to one embodiment, the second sub-branch 121 may include a fourth transistor M14 .

[0045] According to one embodiment, the fourth transistor M14 may be a PMOS transistor, a source and a substrate of which are electrically connected to the analog power supply voltage AVDD, and a gate of which is electrically connected to the first node A1.

[0046] According to one embodiment, the second sub-branch 121 may include at least one fifth transistor M15 .

[0047] According to one embodiment, the fifth transistor M15 may be a PMOS transistor having a substrate electrically connected to the substrate of the fourth transistor M14, a source electrically connected to the drain of the fourth transistor M14, and a gate electrically connected to the second node B1.

[0048] According to one embodiment, the drain of the fifth transistor M15 is configured to output the current I mirrored by the current mirror 100. mirror1 .

[0049] According to one embodiment, Figure 3 The current mirror 100 shown may include a third branch 130 configured to receive an analog power supply voltage AVDD and a bias current I required by the current mirror 100. bias1 .

[0050] According to one embodiment, the third branch 130 may include a first resistor R1 , a first end of which is electrically connected to the analog power supply voltage AVDD.

[0051] According to one embodiment, the third branch 130 may include a first transistor M13 .

[0052] According to one embodiment, the first transistor M13 may be an NMOS transistor, whose gate is electrically connected to the gate of the second transistor M11 and the drain of the third transistor M12, whose source and substrate are electrically connected to the second node B1, and whose drain is electrically connected to the second end of the first resistor R1.

[0053] According to one embodiment, the source and substrate of the first transistor M13 are configured to receive the bias current I required by the current mirror 100. bias1 .

[0054] According to one embodiment, the bias current I bias1 It can be a current of the order of microamperes, which can be selected according to actual needs.

[0055] According to one embodiment, Figure 3 The second transistor M11, the third transistor M12, the fourth transistor M14 and the fifth transistor M15 in the current mirror 100 are of the same type, for example, they may all be PMOS transistors; the type of the first transistor M13 is complementary to the aforementioned four transistor types, for example, it may be an NMOS transistor.

[0056] According to one embodiment, the size of the second transistor M11 in the first branch 110 is the same as the size of the fourth transistor M14 in the second branch 120 .

[0057] According to one embodiment, the size of the third transistor M12 in the first branch 110 is the same as the size of the fifth transistor M15 in the second branch 120 .

[0058] When the current mirror 100 works normally, the gate-source voltage (ie, the voltage difference between the gate and the source) of the second transistor M11 and the fourth transistor M14 is equal, that is:

[0059] V gs11 = V gs14 (1)

[0060] When the current mirror 100 operates normally, the drain-source voltage (ie, the voltage difference between the drain and the source) of the second transistor M11 is V ds11 for:

[0061] V ds11 = AVDD - V gs11 - V gs13 + V gs12 (2)

[0062] Where V gs13 and V gs12 are the gate-source voltages of the first transistor M13 and the third transistor M12 respectively.

[0063] When the current mirror 100 operates normally, the drain-source voltage V ds14 for:

[0064] V ds14 = AVDD - V gs14 - V gs13 + V gs15 (3)

[0065] Where V gs15 is the gate-source voltage of the fifth transistor M15.

[0066] By setting the width-to-length ratio W / L of the third transistor M12, the first transistor M13 and the fifth transistor M15, and the number of the third transistor M12 and the fifth transistor M15 during circuit design, the gate-source voltage of the third transistor M12 and the gate-source voltage of the fifth transistor M15 are equal, that is:

[0067] V gs12 = V gs15 (4)

[0068] Substituting equation (1) and equation (4) into equation (2) or equation (3), we can obtain: When the current mirror 100 works normally, the drain-source voltage V of the second transistor M11 is ds11 and the drain-source voltage V ds14 Equal, that is:

[0069] V ds11 = V ds14 (5)

[0070] Meanwhile, when the current mirror 100 operates normally, the second transistor M11 and the fourth transistor M14 should operate in the saturation region, that is:

[0071] V ds11 ≥ V gs11 -V th11 (6)

[0072] And V ds14 ≥ V gs14 -V th14 (7)

[0073] Among them, V th11 and V th14 are the threshold voltages of the second transistor M11 and the fourth transistor M14 respectively.

[0074] When the second transistor M11 and the fourth transistor M14 operate in the saturation region, the reference current I source1 The working principle is:

[0075]

[0076] in, is the electron mobility of the second transistor M11, is the gate oxide capacitance per unit area of ​​the second transistor M11, is the width-to-length ratio of the second transistor M11, is the channel length modulation coefficient of the second transistor M11.

[0077] When the second transistor M11 and the fourth transistor M14 operate in the saturation region, the reference current I mirror1 The working principle is:

[0078]

[0079] in, is the electron mobility of the fourth transistor M14, is the gate oxide capacitance per unit area of ​​the fourth transistor M14, is the width-to-length ratio of the fourth transistor M14, is the channel length modulation coefficient of the fourth transistor M14.

[0080] Since the parameters of the second transistor M11 and the fourth transistor M14 , , , , are the same, and by substituting formula (5) into formula (8) or formula (9), we can get:

[0081] I mirror1 = k×I source1 (10)

[0082] According to one embodiment, the value of k may be 1, in which case the current mirror 100 is configured to convert the reference current I source1 One-to-one mirror copy and output, that is: I mirror1 = I source1 , the structure of the current mirror circuit is as follows Figure 3 shown.

[0083] According to one embodiment, the value of k may be an integer greater than 1. In this case, the current mirror 100 is configured to convert the reference current I source1 Expand k times and output.

[0084] In this case, according to one embodiment, the second branch 120 may include k sub-branches, each of which has the same structure and connection relationship as the second sub-branch 121 (not shown), and the drains of all fifth transistors M15 in the k sub-branches are electrically connected together, configured to output the current I replicated by the current mirror circuit. mirror1 .

[0085] According to one embodiment, the value of k may be 1 / n, where n is an integer greater than 1. In this case, the current mirror 100 is configured to convert the reference current I source1 Reduce to one-n and output.

[0086] In this case, according to one embodiment, the first branch 110 may include n sub-branches, each of which has the same structure and connection relationship as the first sub-branch 111 (not shown), and the drains of all third transistors M12 in the n sub-branches are electrically connected together and configured to receive the reference current Isource1 .

[0087] When the reference current I source1 When the gate-source voltage V gs11 and the gate-source voltage V gs14 It will also follow the reference current I source1 Increase or decrease, the corresponding drain-source voltage V ds11 and the drain-source voltage V ds14 It is difficult for traditional current mirror circuits and common-source and common-gate current mirrors to keep V constant when the reference current changes. ds11 and V ds14 equal, so the accuracy of the current mirror replicating the reference current cannot be guaranteed.

[0088] Although the accuracy of the cascode current mirror is improved to a certain extent, if it is based on the cascode current mirror structure, the bias voltage of the second transistor M11 and the third transistor M12 needs to be set by a resistor R, which needs to satisfy: V gs11 -V th11 ≤Reference current×R<V th12 (21) can make the second transistor M11 and the third transistor M12 work in the saturation region and ensure the accuracy of the current mirror. When the reference current changes greatly, the voltage of the reference current × R changes greatly, and the above formula (21) cannot be satisfied. The second transistor M11 and the third transistor M12 cannot work in the saturation region, and the accuracy of the current mirror cannot be guaranteed; at the same time, due to the large voltage change of the reference current × R, it may also cause the second transistor M11 and the third transistor M12 to enter the linear region, and then cause the current mirror to fail to work normally.

[0089] And as Figure 1 and Figure 2 To solve this problem, the conventional current mirror circuit shown not only greatly increases the circuit layout, but also introduces a clamping loop to bring about new stability problems.

[0090] The current mirror proposed in this application, for example: Figure 3 The current mirror 100 shown in the figure introduces the third branch 130. It is precisely because the first transistor M13 in the third branch 130 can dynamically bias the third transistor M12 and the fifth transistor M15 that the gate-source voltage V gs12 and the gate-source voltage V gs15 equal, so when the reference current I source1 When the drain-source voltage V ds11 and the drain-source voltage V ds14Still maintain dynamic equality and achieve dynamic tracking V ds11 and V ds14 The purpose is to achieve the mirror copy effect shown in formula (10). Therefore, the reference current I source1 Under different current conditions, the current mirror 100 can mirror the reference current I with high precision. source1 , output current I mirror1 , thereby achieving the purpose of high-precision mirror copying of the reference current under the conditions of a wide reference current range and a simple circuit structure.

[0091] According to one embodiment, the reference current I source1 The range can be between one microampere and more than ten milliamperes, covering three orders of magnitude.

[0092] Since the gate of the second transistor M11 is electrically connected to the drain of the third transistor M12, as long as the analog power supply voltage AVDD is greater than the reference current I source1 The corresponding gate-source voltage V gs11 When , the current mirror 100 can work normally, thereby achieving the purpose of low occupied voltage margin.

[0093] It should be pointed out that only some embodiments are listed in this article, and other embodiments that can be changed on the three branches by those skilled in the art without creative work belong to the protection scope of this application.

[0094] Figure 4 is a schematic diagram of another current mirror circuit according to an embodiment of the present application.

[0095] According to one embodiment, Figure 4 The current mirror 200 shown may include a first branch 210 configured to receive an analog ground level AGND and a reference current I to be mirrored by the current mirror 200. source2 .

[0096] According to one embodiment, Figure 4 The current mirror 100 shown may include a second branch 220, which is configured to receive an analog ground level AGND and output a current I mirror2 .

[0097] According to one embodiment, the first branch 210 and the second branch 220 are electrically connected to a first node A2 and a second node B2.

[0098] According to one embodiment, the first branch 210 may include at least one first sub-branch 211 .

[0099] According to one embodiment, the first sub-branch 211 may include a second transistor M22 .

[0100] According to one embodiment, the second transistor M22 may be an NMOS transistor, a source and a substrate of which are electrically connected to the analog ground level AGND, and a gate of which is electrically connected to the first node A2.

[0101] According to one embodiment, the first sub-branch 211 may include at least one third transistor M21 .

[0102] According to one embodiment, the third transistor M21 may be an NMOS transistor having a substrate electrically connected to a substrate of the second transistor M22, a source electrically connected to a drain of the second transistor M22, a drain electrically connected to the first node A2, and a gate electrically connected to the second node B2.

[0103] According to one embodiment, the drain of the third transistor M21 is configured to receive the reference current I source2 .

[0104] According to one embodiment, the reference current I source2 It can be the current set by the external resistor of the chip, or the sampling current of the current sampling circuit.

[0105] According to one embodiment, the second branch 220 may include at least one second sub-branch 221 .

[0106] According to one embodiment, the second sub-branch 221 may include a fourth transistor M25 .

[0107] According to one embodiment, the fourth transistor M25 may be an NMOS transistor, a source and a substrate of which are electrically connected to the analog ground level AGND, and a gate of which is electrically connected to the first node A2.

[0108] According to one embodiment, the second sub-branch 221 may include at least one fifth transistor M24 .

[0109] According to one embodiment, the fifth transistor M24 may be an NMOS transistor having a substrate electrically connected to a substrate of the fourth transistor M25 , a source electrically connected to a drain of the fourth transistor M25 , and a gate electrically connected to the second node B2 .

[0110] According to one embodiment, the drain of the fifth transistor M24 is configured to output the current I mirror2 .

[0111] According to one embodiment, Figure 4 The current mirror 200 shown may include a third branch 230 configured to receive the analog ground level AGND and receive the bias current I required by the current mirror 200. bias2 .

[0112] According to one embodiment, the third branch 230 may include a first resistor R2 , a first end of which is electrically connected to the analog ground level AGND.

[0113] According to one embodiment, the third branch 230 may include a first transistor M23 .

[0114] According to one embodiment, the first transistor M23 may be a PMOS transistor, whose gate is electrically connected to the gate of the second transistor M22 and the drain of the third transistor M21, whose source and substrate are electrically connected to the second node B2, and whose drain is electrically connected to the second end of the first resistor R2.

[0115] According to one embodiment, the source and substrate of the first transistor M23 are configured to receive the bias current I bias2 .

[0116] According to one embodiment, the bias current I bias2 It can be a current of the order of microamperes, which can be selected according to actual needs.

[0117] According to one embodiment, Figure 4 The third transistor M21, the second transistor M22, the fifth transistor M24 and the fourth transistor M25 in the current mirror 200 are of the same type, for example, they may all be NMOS transistors; the type of the first transistor M23 is complementary to the aforementioned four transistor types, for example, it may be a PMOS transistor.

[0118] According to one embodiment, the size of the second transistor M22 in the first branch 210 is the same as the size of the fourth transistor M25 in the second branch 220 .

[0119] According to one embodiment, the size of the third transistor M21 in the second branch 210 is the same as the size of the fifth transistor M24 in the second branch 220 .

[0120] When the current mirror 200 works normally, the gate-source voltage (ie, the voltage difference between the gate and the source) of the second transistor M22 and the fourth transistor M25 is equal, that is:

[0121] V gs22 = V gs25 (11)

[0122] When the current mirror 200 operates normally, the drain-source voltage (ie, the voltage difference between the drain and the source) of the second transistor M22 is V ds22 for:

[0123] V ds11 = AGND + V gs22 + V gs23 - Vgs21 (12)

[0124] Where V gs23 and V gs21 are the gate-source voltages of the first transistor M23 and the third transistor M21 respectively.

[0125] When the current mirror 200 operates normally, the drain-source voltage V ds25 for:

[0126] V ds25 = AGND + V gs25 + V gs23 - V gs24 (13)

[0127] Where V gs24 is the gate-source voltage of the fifth transistor M24.

[0128] By setting the width-to-length ratio W / L of the third transistor M21, the first transistor M23 and the fifth transistor M24, and the number of the third transistor M21 and the fifth transistor M24 during circuit design, the gate-source voltages of the third transistor M21 and the fifth transistor M24 are equal, that is:

[0129] V gs21 = V gs24 (14)

[0130] Substituting equation (11) and equation (14) into equation (12) or equation (13), it can be obtained that when the current mirror 200 works normally, the drain-source voltage V of the second transistor M22 is ds22 and the drain-source voltage V ds25 Equal, that is:

[0131] V ds22 = V ds25 (15)

[0132] Meanwhile, when the current mirror 200 operates normally, the second transistor M22 and the fourth transistor M25 should operate in the saturation region, that is:

[0133] V ds22 ≥ V gs22 - V th22 (16)

[0134] And V ds25 ≥ V gs25 - V th25 (17)

[0135] Among them, V th22 and V th25 are the threshold voltages of the second transistor M22 and the fourth transistor M25 respectively.

[0136] When the second transistor M22 and the fourth transistor M25 operate in the saturation region, the reference current I source2 The working principle is:

[0137]

[0138] in, is the electron mobility of the second transistor M22, is the gate oxide capacitance per unit area of ​​the second transistor M22, is the width-to-length ratio of the second transistor M22, is the channel length modulation coefficient of the second transistor M22.

[0139] When the second transistor M22 and the fourth transistor M25 operate in the saturation region, the reference current I mirror2 The working principle is:

[0140]

[0141] in, is the electron mobility of the fourth transistor M25, is the gate oxide capacitance per unit area of ​​the fourth transistor M25, is the width-to-length ratio of the fourth transistor M25, is the channel length modulation coefficient of the fourth transistor M25.

[0142] Since the parameters of the second transistor M22 and the fourth transistor M25 , , , , are the same, and by substituting formula (15) into formula (18) or formula (19), we can get:

[0143] I mirror2 = k×I source2 (20)

[0144] According to one embodiment, the value of k can be 1, in which case the current mirror 200 is configured to convert the reference current I source2 One-to-one mirror copy and output, that is: I mirror2 = I source2 , the structure of the current mirror circuit is as follows Figure 4 shown.

[0145] According to one embodiment, the value of k may be an integer greater than 1. In this case, the current mirror 200 is configured to convert the reference current I source2 Expand k times and output.

[0146] In this case, according to one embodiment, the second branch 220 may include k sub-branches, each of which has the same structure and connection relationship as the second sub-branch 221 (not shown), and the drains of all fifth transistors M24 in the k sub-branches are electrically connected together, configured to output the current I copied by the current mirror circuit. mirror2 .

[0147] According to one embodiment, the value of k may be 1 / n, where n is an integer greater than 1. In this case, the current mirror 200 is configured to convert the reference current I source2 Reduce to one-n and output.

[0148] In this case, according to one embodiment, the first branch 210 may include n sub-branches, each of which has the same structure and connection relationship as the first sub-branch 211 (not shown), and the drains of all third transistors M21 in the n sub-branches are electrically connected together and configured to receive the reference current I source2 .

[0149] When the reference current I source2 When the gate-source voltage V gs22 and the gate-source voltage V gs25 It will also follow the reference current I source2 Increase or decrease, the corresponding drain-source voltage V ds22 and the drain-source voltage V ds25 It is difficult for traditional current mirror circuits and common-source and common-gate current mirrors to keep V constant when the reference current changes. ds22 and V ds25 equal, so the accuracy of the current mirror replicating the reference current cannot be guaranteed.

[0150] Although the accuracy of the cascode current mirror is improved to a certain extent, if it is based on the cascode current mirror structure, the bias voltage of the second transistor M22 and the third transistor M21 needs to be set by a resistor R, which needs to satisfy: V gs22 -V th22 ≤Reference current×R<V th21 (22) can make the second transistor M22 and the third transistor M21 work in the saturation region and ensure the accuracy of the current mirror. When the reference current changes greatly, the voltage of the reference current × R changes greatly, and the above formula (22) cannot be satisfied. The second transistor M22 and the third transistor M21 cannot work in the saturation region, and the accuracy of the current mirror cannot be guaranteed; at the same time, due to the large voltage change of the reference current × R, it may also cause the second transistor M22 and the third transistor M21 to enter the linear region, and then cause the current mirror to fail to work normally.

[0151] And as Figure 1 and Figure 2 To solve this problem, the conventional current mirror circuit shown not only greatly increases the circuit layout, but also introduces a clamping loop to bring about new stability problems.

[0152] The current mirror proposed in this application, for example: Figure 4 The current mirror 200 shown in the figure introduces the third branch 230. It is precisely because the first transistor M23 in the third branch 230 can dynamically bias the third transistor M21 and the fifth transistor M24 that the gate-source voltage V gs21 and the gate-source voltage V gs24 equal, so when the reference current I source2 When the drain-source voltage V ds22 and the drain-source voltage V ds25 Still maintain dynamic equality and achieve dynamic tracking V ds22 and V ds25 The purpose is to achieve the mirror copy effect shown in formula (20). Therefore, the reference current I source2 Under different current conditions, the current mirror 200 can mirror the reference current I with high precision. source2 , output current I mirror2 , thereby achieving the purpose of high-precision mirror copying of the reference current under the conditions of a wide reference current range and a simple circuit structure.

[0153] According to one embodiment, the reference current I source2 The range can be between one microampere and more than ten milliamperes, covering three orders of magnitude.

[0154] Since the gate of the first transistor M23 is electrically connected to the gate of the second transistor M22, as long as the power supply voltage is greater than the gate-source voltage V gs22 The gate-source voltage V gs23 When the current mirror 200 is able to work normally, the purpose of low occupied voltage margin can also be achieved.

[0155] It should be pointed out that only some embodiments are listed in this article, and other embodiments that can be changed on the three branches by those skilled in the art without creative work belong to the protection scope of this application.

[0156] The above embodiments are only used to illustrate the present application, and are not intended to limit the present application. Ordinary technicians in the relevant technical field may make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should also fall within the scope disclosed in the present application.

Claims

1. A current mirror circuit, comprising: A first branch, one end of which is configured to receive a fixed voltage level and a second end of which is configured to receive an input current; A second branch, which is electrically connected to the first branch at a first node and a second node, one end of which is configured to receive the fixed voltage level, and a second end of which is configured to provide an output current, wherein the output current is generated based on the input current; as well as The third branch includes at least: a first transistor having a drain configured to receive the fixed voltage level, a gate electrically connected to the first node, a source and a substrate electrically connected to the second node and configured to receive a bias current; The first branch includes at least one first sub-branch, and the first sub-branch includes at least: a second transistor having a source and a substrate configured to receive the fixed voltage level and a gate electrically connected to the first node; and at least one third transistor, whose source is electrically connected to the drain of the second transistor, whose drain is electrically connected to the gate of the second transistor and configured to receive the input current, whose gate is electrically connected to the second node, and whose substrate is electrically connected to the substrate of the second transistor; The second branch includes at least one second sub-branch, and the second sub-branch includes at least: a fourth transistor having a gate electrically connected to the gate of the second transistor and a source and a substrate configured to receive the fixed level; and at least one fifth transistor, whose source is electrically connected to the drain of the fourth transistor, whose gate is electrically connected to the second node, whose drain is configured to output the output current, and whose substrate is electrically connected to the substrate of the fourth transistor; The second transistor, the third transistor, the fourth transistor, and the fifth transistor are of the same type; and the first transistor is complementary to the other transistors in type.

2. The current mirror circuit according to claim 1, wherein: The second transistor and the fourth transistor have the same size; wherein the third transistor and the fifth transistor have the same size.

3. The current mirror circuit according to claim 2, wherein: The third branch further includes a first resistor, one end of which is configured to receive the fixed voltage level, and the other end of which is electrically connected to the drain of the first transistor.

4. The current mirror circuit according to claim 2, wherein: The second transistor, the third transistor, the fourth transistor, and the fifth transistor are PMOS transistors; and the first transistor is an NMOS transistor.

5. The current mirror circuit according to claim 2, wherein: The second transistor, the third transistor, the fourth transistor, and the fifth transistor are NMOS transistors; and the first transistor is a PMOS transistor.

6. The current mirror circuit according to claim 4, wherein: The fixed level is the power supply voltage.

7. The current mirror circuit according to claim 5, wherein: The fixed level is a ground level.

8. The current mirror circuit according to claim 6 or 7, wherein: The first branch includes one first sub-branch, and the second branch includes one second sub-branch.

9. The current mirror circuit according to claim 6 or 7, wherein: The first branch includes one first sub-branch, and the second branch includes M second sub-branches, where M is an integer greater than 1; wherein the drains of all the fifth transistors in the M second sub-branches are electrically connected together.

10. The current mirror circuit according to claim 6 or 7, wherein: The first branch includes N first sub-branches, and the second branch includes one second sub-branch, where N is an integer greater than 1; wherein the drains of all the third transistors in the N first sub-branches are electrically connected together.

11. The current mirror circuit according to claim 6 or 7, wherein: The input current has an order of magnitude range of 10 -6 Ampere to 10 -2 ampere.

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