Five-tube half adder circuit, digital in-memory computing array and static random access memory

Abstract

The present application relates to a five-tube half adder circuit, a digital in-memory computing array and a static random access memory, wherein the five-tube half adder circuit comprises: a first NMOS tube N1, a second NMOS tube N2, a first PMOS tube P1, a second PMOS tube P2, and a third PMOS tube P3; the source of the first NMOS tube N1 is connected to the drain of the first PMOS tube P1 and the drain of the second PMOS tube P2 to form a first node SUM, the gate of the first NMOS tube N1 is connected to a voltage source, and the drain of the first NMOS tube N1 is grounded; the gate of the second NMOS tube N2 is connected to the gate of the third PMOS tube P3 to form a second node D, the source of the first PMOS tube P1 and the gate of the second PMOS tube P2 are connected to the second node D; the drain of the third PMOS tube P3 is connected to the drain of the second NMOS tube N2 to form a third node CO, and the source of the third PMOS tube P3 is grounded; the source of the second NMOS tube N2 is connected to the gate of the first PMOS tube P1 and the source of the second PMOS tube P2 to form a fourth node C. The problem that the current half adder circuit structure is relatively complex is solved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a five-tube half adder circuit, a digital in-memory computing array, and a static random access memory. Background Art

[0002] With the rise and development of emerging big data applications such as artificial intelligence, machine learning, and autonomous driving, there are higher requirements for the storage and processing of massive data. However, most of the current computing systems are based on the von Neumann architecture, which has the characteristics of physically separating the storage unit and the computing unit, requiring data to be transmitted between the two. Under modern CMOS technology, the power consumption and delay generated by the transmission of data between the computing unit and the storage unit are already much greater than the power consumption and delay of data processing. Therefore, new solutions are urgently needed to reduce the power consumption and delay of data transmission. In-memory computing, as a new computing method, integrates computing and storage, effectively overcoming the drawbacks of the von Neumann architecture. The in-memory computing architecture significantly reduces power consumption and improves computing efficiency, becoming a favorable candidate for building efficient systems.

[0003] According to the mechanism of in-memory computing, it can be divided into analog domain computing and digital domain computing. Among them, digital domain computing has the characteristics of high precision, which can embed logic units into arrays for more complex computing to realize the application of different networks. However, for in-memory computing, digital domain computing will bring great challenges to the circuit area overhead, operation complexity and computing speed. One of the reasons for the large area overhead of the current digital in-memory computing structure is that the half adder circuit structure used is relatively complex.

[0004] With regard to the problem that the current half adder circuit structure is relatively complex, no effective solution has been proposed yet. Summary of the invention

[0005] The present invention provides a five-tube half adder circuit, a digital in-memory computing array and a static random access memory to solve the problem that the current half adder circuit structure is relatively complex.

[0006] In a first aspect, the present invention provides a five-tube half adder circuit, comprising: a first NMOS tube, a second NMOS tube, a first PMOS tube, a second PMOS tube, and a third PMOS tube;

[0007] The source of the first NMOS tube is connected to the drain of the first PMOS tube and the drain of the second PMOS tube to form a first node, the gate of the first NMOS tube is connected to a voltage source, and the drain of the first NMOS tube is grounded;

[0008] The gate of the second NMOS tube is connected to the gate of the third PMOS tube and forms a second node, and the source of the first PMOS tube and the gate of the second PMOS tube are connected to the second node;

[0009] The drain of the third PMOS tube is connected to the drain of the second NMOS tube to form a third node, and the source of the third PMOS tube is grounded;

[0010] The source of the second NMOS tube is connected to the gate of the first PMOS tube and the source of the second PMOS tube to form a fourth node C;

[0011] The second node and the fourth node are input nodes of the five-tube half adder, and the first node and the third node are output nodes of the five-tube half adder.

[0012] In a second aspect, the present invention provides a digital in-memory computing array, comprising a weight storage part and a computing part;

[0013] The weight storage part is a SRAM cell array;

[0014] The calculation part realizes calculation through the five-tube half adder circuit described in the first aspect.

[0015] In a third aspect, the present invention provides a static random access memory, which integrates a data storage computing module and an auxiliary module;

[0016] The data in-memory computing module includes a plurality of array-distributed digital in-memory computing arrays as described in the second aspect;

[0017] The auxiliary module is used to control the data storage computing module in response to the clock signal and transmit the input data and output data of the data storage computing module.

[0018] In a fourth aspect, the present invention provides an electronic device having a built-in static random access memory as described in the third aspect.

[0019] Compared with the related art, the five-tube half adder circuit provided by the present invention can realize basic addition operation. Furthermore, the above-mentioned tube half adder circuit is realized by only five MOS tubes, which has the advantages of simple structure and small area occupation. The problem that the current half adder circuit structure is relatively complex is solved. When the above-mentioned half adder circuit is used for digital in-memory calculation, the area overhead of the circuit can be greatly reduced.

[0020] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a schematic structural diagram of a five-tube half adder circuit provided in an embodiment of the present invention;

[0022] Figure 2 is a working waveform diagram of a five-tube half adder circuit provided in an embodiment of the present invention;

[0023] Figure 3 is a schematic diagram of the structure of a digital in-memory computing array provided in an embodiment of the present invention;

[0024] Figure 4 is a schematic diagram of the structure of the computing part in the digital in-memory computing array provided in an embodiment of the present invention;

[0025] Figure 5 is a schematic diagram of the structure of the storage part in the digital in-memory computing array provided in an embodiment of the present invention;

[0026] Figure 6 is a schematic diagram of the structure of an AND gate circuit provided in some embodiments of the present invention;

[0027] Figure 7 is a working waveform diagram of an AND gate circuit provided in some embodiments of the present invention;

[0028] Figure 8 is a schematic diagram of a digital in-memory computing solution provided in some embodiments of the present invention;

[0029] Fig. 9 A schematic diagram of the operation of the calculation part in the calculation mode in some embodiments of the present invention;

[0030] Fig.10 A schematic diagram of the configuration of a static random access memory in some embodiments of the present invention;

[0031] Fig.11 A schematic diagram of implementing 8-bit weights in a static random access memory in some embodiments of the present invention;

[0032] Fig.12 Schematic diagram of the implementation of 8-bit input in static random access memory in some embodiments of the present invention. DETAILED DESCRIPTION

[0033] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0034] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the general meaning understood by people with general skills in the technical field to which this application belongs. The words "one", "a", "the", "these" and the like in this application do not indicate a quantitative limitation, and they may be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusions; for example, a process, method and system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, "A and / or B" may mean: A exists alone, A and B exist at the same time, and B exists alone. Generally, the character " / " indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", "third", etc. in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0035] In an embodiment of the present invention, a five-tube half adder circuit is provided. Figure 1 Schematic diagram of the structure of a five-tube half adder circuit provided in an embodiment of the present invention. Figure 1 The five-tube half adder circuit includes: a first NMOS tube N1, a second NMOS tube N2, a first PMOS tube P1, a second PMOS tube P2, and a third PMOS tube P3.

[0036] The source of the first NMOS tube N1 is connected to the drain of the first PMOS tube P1 and the drain of the second PMOS tube P2 to form a first node SUM, the gate of the first NMOS tube N1 is connected to a voltage source, and the drain of the first NMOS tube N1 is grounded; the gate of the second NMOS tube N2 is connected to the gate of the third PMOS tube P3 to form a second node D, the source of the first PMOS tube P1 and the gate of the second PMOS tube P2 are connected to the second node D; the drain of the third PMOS tube P3 is connected to the drain of the second NMOS tube N2 to form a third node CO, and the source of the third PMOS tube P3 is grounded; the source of the second NMOS tube N2 is connected to the gate of the first PMOS tube P1 and the source of the second PMOS tube P2 to form a fourth node C; the second node D and the fourth node C are input nodes of the five-tube half adder, and the first node SUM and the third node CO are output nodes of the five-tube half adder.

[0037] The above is a five-tube half adder circuit provided by the present invention. The operation function realized by the five-tube half adder circuit is: SUM= , CO=C·D.

[0038] Figure 2 1 is a working waveform diagram of a five-tube half adder circuit provided in an embodiment of the present invention. Figure 2 , when the input node C=0 and D=0, the half adder output node SUM=0 and CO=0; when the input node C=0 and D=1, the half adder output node SUM=1 and CO=0; when the input node C=1 and D=0, the half adder output node SUM=1 and CO=0; when the input node C=1 and D=1, the half adder output node SUM=0 and CO=1. Among them, the third node CO is used to output the carry signal, and the fourth node SUM is used to output the addition sum. The truth table of the half adder circuit is shown in Table 1.

[0039] Table 1 Half adder circuit truth table

[0040]

[0041] It can be seen from the above description that the five-tube half adder circuit provided by the present invention can realize basic addition operations. Furthermore, the above-mentioned tube half adder circuit is realized by only five MOS tubes, which has the advantages of simple structure and small area occupation. The problem that the current half adder circuit structure is relatively complex is solved. When the above-mentioned half adder circuit is used for digital in-memory calculation, the area overhead of the circuit can be greatly reduced.

[0042] A digital in-memory computing array is also provided in an embodiment of the present invention. Figure 3 Schematic diagram of the structure of the digital in-memory computing array provided in an embodiment of the present invention. Figure 3 The digital memory computing array includes a weight storage part and a computing part; the weight storage part is an SRAM cell array; the computing part realizes the calculation through the five-tube half adder circuit provided by the present invention.

[0043] Figure 4 Schematic diagram of the structure of the computing part of the digital in-memory computing array provided in an embodiment of the present invention. Figure 4 The calculation part includes four AND gate circuits, a first half adder circuit HA0 and a second half adder circuit HA1. The four AND gate circuits are a first AND gate circuit AND0, a second AND gate circuit AND1, a third AND gate circuit AND2, and a fourth AND gate circuit AND3. The first half adder circuit HA0 and the second half adder circuit HA1 are both five-tube half adder circuits provided by the present invention.

[0044] The two input nodes of the first AND gate circuit AND0 are connected to the first local bit line LBL and the first global bit line GBL respectively; the two input nodes of the second AND gate circuit AND1 are connected to the first global bit line GBL and the second local bit line LBLB respectively; the two input nodes of the third AND gate circuit AND2 are connected to the first local bit line LBL and the second global bit line GBLB respectively; the two input nodes of the fourth AND gate circuit AND3 are connected to the second global bit line GBLB and the second local bit line LBLB respectively; the first node and the second node of the first half adder circuit HA0 are connected to the output nodes A[1] and A[2] of the second AND gate circuit AND1 and the third AND gate circuit AND2 respectively, and the first node and the second node of the second half adder circuit HA1 are connected to the third node of the first half adder circuit HA0 and the output node A[3] of the fourth AND gate circuit AND3 respectively.

[0045] The output node A[1] of the first AND gate circuit AND0, the fourth node of the first half adder circuit HA0, and the third and fourth nodes of the second half adder circuit HA1 constitute four output nodes S[0] and S[1], S[2] and S[3] of the calculation part.

[0046] Figure 5 Schematic diagram of the structure of the storage part of the digital in-memory computing array provided in an embodiment of the present invention. Figure 5 In some embodiments, the SRAM cell array includes a third NMOS tube N3, a fourth NMOS tube N4, and a plurality of 6T-SRAM cells distributed in the column direction. Exemplarily, the number of 6T-SRAM cells in each SRAM cell array is 16. The first storage node Q and the second storage node QB of each 6T-SRAM cell are respectively connected to the first local bit line LBL and the second local bit line LBLB; the source and the drain of the third NMOS tube N3 are respectively connected to the first local bit line LBL and the first global bit line GBL, the source and the drain of the fourth NMOS tube N4 are respectively connected to the second local bit line LBLB and the second global bit line GBLB, and the gates of the third NMOS tube N3 and the fourth NMOS tube N4 are both connected to the control word line HWL.

[0047] The 6T-SRAM unit includes a fifth NMOS tube N5, a sixth NMOS tube N6, a first inverter INV1 and a second inverter INV2; the output end of the second inverter INV2 is connected to the input end of the first inverter INV1 and forms a first storage node Q, the output end of the first inverter INV1 is connected to the input end of the second inverter INV2 and forms a second storage node QB; the source, drain and gate of the fifth NMOS tube N5 are respectively connected to the first storage node Q, the first local bit line LBL and the left word line WLL, and the source, drain and gate of the sixth NMOS tube N6 are respectively connected to the second storage node QB, the second local bit line LBLB and the right word line WLR.

[0048] For the SRAM cell array, two adjacent 6T-SRAM cells in a column are used to store a 2-bit weight in a calculation process. Exemplarily, the storage operation is as follows: the upper 6T-SRAM cell Cell[0], its first storage node Q stores the weight W[0] and the second storage node QB stores the weight WB[0]; the lower 6T-SRAM cell Cell[1], its first storage node Q stores the weight WB[1] and the second storage node QB stores the weight W[1]. Among them, W[0] and WB[0], W[1] and WB[1] are opposite signals.

[0049] Figure 6 Schematic diagram of the structure of an AND gate circuit provided in some embodiments of the present invention. Figure 6 In some embodiments, the AND gate circuit includes a fourth PMOS transistor P4 and a seventh NMOS transistor N7; the gate of the fourth PMOS transistor P4 and the gate of the seventh NMOS transistor N7 are connected to form a fifth node The source of the fourth PMOS tube P4 constitutes the sixth node A, and the drain of the seventh NMOS tube N7 is usually grounded to VSS, and the fifth node The drain of the fourth PMOS transistor P4 and the source of the seventh NMOS transistor N7 are connected to form the output node AND of the AND gate circuit (i.e. Figure 4 A[n] in .

[0050] Figure 7 is a working waveform diagram of an AND gate circuit provided in some embodiments of the present invention, wherein It is the opposite signal of B. Figure 7 , when input node A=1 and =0, that is, B=1, the output node AND=1 of the AND gate circuit; when the input node A=0 and =0, that is, B=1, the output node AND of the AND gate circuit is 0; when the input node A=1 and =1, that is, B=0, the output node AND of the AND gate circuit is 0; when the input node A=0 and =1, that is, when B=0, the output node AND of the AND gate circuit is 0. The truth table of the AND gate circuit is shown in Table 2. Among them, the output node of the AND gate circuit is used to output the AND operation result.

[0051] Table 2 AND gate circuit truth table

[0052]

[0053] The above is a digital in-memory computing array provided in an embodiment of the present invention. For the weight storage part, the first storage node Q of each 6T-SRAM unit transmits the weight to the computing part through the same first local bit line LBL, and the second storage node QB of each 6T-SRAM unit transmits the weight to the computing part through the same second local bit line LBLB. The first storage node Q and the second storage node QB are turned on or off by the left word line WLL and the right word line WLR, respectively. When turned on, the weight in the storage node can be transmitted to the computing part through the corresponding local bit line. In summary, the 2-bit weights W[0] and W[1] stored in the weight storage part enter the computing part through the left word line WLL and the right word line WLR, respectively. Correspondingly, the 2-bit inputs IN[1] and IN[0] enter the computing part through the first global bit line GBL and the second global bit line GBLB, respectively. The multiplication operation of the 2-bit weight by the 2-bit input in the computing part is completed.

[0054] Figure 8 Schematic diagram of a digital in-memory computing solution provided in some embodiments of the present invention. Figure 8 ,The above digital in-memory computing array has two working modes, namely storage mode and computing mode.

[0055] When the control word line HWL is 1, the digital memory computing array is in storage mode.

[0056] The first local bit line LBL and the second local bit line LBLB are connected to the first global bit line GBL and the second global bit line GBLB respectively, and the digital memory calculation array is in storage mode. The control logic of its write operation, read operation and data retention operation is the same as that of the traditional 6T-SRAM cell array, including the following process:

[0057] Before the write operation, the voltage of the first global bit line GBL and the second global bit line GBLB is precharged to VDD. When the external address signal is valid, the 6T-SRAM cell to be written is determined by the address decoding circuit, and the written data is sent to the bit line by the write drive circuit. When the access NMOS tubes (the third NMOS tube and the fourth NMOS tube) on both sides of the 6T-SRAM cell are turned on, the data is written into the corresponding 6T-SRAM cell, and the write operation is completed.

[0058] Before the read operation, the voltage of the first global bit line GBL and the second global bit line GBLB is precharged to VDD. When the external address signal is valid, the 6T-SRAM cell of the data to be read is determined by the address decoding circuit. When the left word line WLL and the right word line WLR are at a high level, the first global bit line GBL and the second global bit line GBLB form a path with the SRAM cell so that the two bits have a certain voltage difference. The voltage difference between the first global bit line GBL and the second global bit line GBLB is amplified by the sensitive amplifier and the driving circuit, so that the data of the 6T-SRAM cell is read out, and the read operation is completed.

[0059] Hold operation: When the left word line WLL and the right word line WLR of the 6T-SRAM cell are at a low level, the local bit line of the 6T-SRAM cell is isolated from the storage node. The core of the 6T-SRAM cell is a latch structure formed by a pair of inverters, which keeps the storage node of the 6T-SRAM cell in a bistable state at all times, completing the hold operation.

[0060] When the control word line HWL is 0, the digital memory computing array is in computing mode. Fig. 9 Schematic diagram of the operation of the computing part in computing mode in some embodiments of the present invention.

[0061] Reference Fig. 9 The calculation part circuit accepts four input signals, namely 2-bit weights W[1], W[0], 2-bit inputs IN[1], IN[0], and completes the multiplication operation between them, and outputs the signals OUT[3], OUT[2], OUT[1], OUT[0] from high to low (provided by the four output nodes of the calculation part respectively) as the calculation results. The specific operations are as follows:

[0062] When performing a calculation operation, the first local bit line LBL transmits a signal W[0], the second local bit line LBLB transmits a signal W[1], the first global bit line GBL transmits a signal IN[0], and the second global bit line GBLB transmits a signal IN[1]. Fig. 9 , we can get:

[0063] The signals W[0] and IN[0] are multiplied by each other through the first AND gate circuit AND0 to output a signal W[0]×IN[0] which is a result of the multiplication between them.

[0064] The signals W[1] and IN[0] are multiplied by each other through the second AND gate circuit AND1 to output a result signal W[1]×IN[0].

[0065] The signals W[0] and IN[1] are multiplied by each other through the third AND gate circuit AND0 to output a result signal W[0]×IN[1].

[0066] The signals W[1] and IN[1] are multiplied by each other through the fourth AND gate circuit AND0 to output a signal W[1]×IN[1] which is a result of the multiplication between them.

[0067] The signal W[1]×IN[0] and the signal W[0]×IN[1] output the addition results CO0 and SUM0 therebetween through the first half adder circuit HA0, where CO0 is the carry signal and SUM0 is the low-order signal after the input signals are added.

[0068] The signal CO0 and the signal W[0]×IN[1] output the addition results CO1 and SUM1 therebetween through the second half adder circuit HA1, wherein CO1 is a carry signal and SUM1 is a low-order signal after the input signals are added.

[0069] At this point, the multiplication operation of the 2-bit weight and the 2-bit input in the calculation part is completed, where the signals CO1, SUM1, SUM0, and W[0]×IN[0] are the final operation results, and the four outputs of the calculation part are OUT[3], OUT[2], OUT[1], and OUT[0]. Table 3 is the calculation mode truth table of the digital memory calculation array.

[0070] Table 3 Truth table of the calculation mode of the digital memory calculation array

[0071]

[0072] Fig.10 FIG. 1 is a schematic diagram of the configuration of a static random access memory in some embodiments of the present invention. Fig.10 In an embodiment of the present invention, a static random access memory is also provided, which integrates a data memory computing module and an auxiliary module; the data memory computing module includes a plurality of array-distributed digital memory computing arrays provided in the present invention; the auxiliary module is used to respond to a clock signal to control the data memory computing module and transmit the input data and output data of the data memory computing module.

[0073] The auxiliary module specifically includes a row decoder, a word line driver, an adder circuit, a timing control module, a sensitive amplifier, a column selector, a precharge circuit / read-write selection circuit, an input-output unit, a word line group, and a bit line group.

[0074] Exemplarily, the in-memory computing module includes 4 64 digital in-memory computing arrays provided by the present invention. The word line group is composed of 128 word lines. 63 left word lines WLL[0]~WLL

[63] and 63 right word lines WLR[0]~WLR

[63] , and 4 fixed voltage word lines. Each word line is used to turn on the sixth NMOS tube and the seventh NMOS tube in the 6TSRAM unit of the corresponding row. Each fixed voltage word line is used to provide a fixed 300mV voltage required by the half adder in the computing part of the 4 sub-arrays in a column. The bit line group includes 64 first global bit lines GBL and 64 second global bit lines GBLB respectively connected to each column of the storage array; that is, a column of 4 digital in-memory computing arrays share the same set of first global bit lines GBL and second global bit lines GBLB.

[0075] The adding circuit includes a series of adder tree circuits applied in the calculation mode, which can directly integrate the multiplication results of 2-bit weights and 2-bit inputs realized by 4 digital in-memory calculation arrays in a column into the multiplication results of 8-bit weights and 2-bit inputs, which are the outputs of a column of digital in-memory calculation arrays based on the digital in-memory calculation scheme, and accumulate the outputs between corresponding columns to realize the accumulation process in the convolution operation. The final output of this adder tree circuit is the final output of the entire static random access memory in a digital calculation.

[0076] The row decoder is used to control the word line driving of each word line.

[0077] The timing control module is used to generate the various clock signals required during the read / write operation and to generate the control signals for four cycles of calculation input to IN[0:1], IN[2:3], IN[4:5] and IN[6:7] respectively.

[0078] The word line driver is used to control the opening or closing of each word line according to the decoding result of the row decoder.

[0079] The precharge circuit is used to charge each bit line capacitor in the bit line group.

[0080] The column selector is used to select each bit line group, and then combined with the row decoder and word line driver to select any 6T-SRAM cell in the array and perform read / write operations on the corresponding 6T-SRAM cell in read / write mode.

[0081] The sense amplifier is used to determine the sampling time of the bit line voltage difference VIN according to the received control signal SAEN in the read mode, and to generate and output the storage data of the corresponding 6T-SRAM unit according to the sampling result of VIN.

[0082] The input-output unit is used to obtain input data to be written in a write mode, and to output the read storage data in a read mode.

[0083] It should be noted that each part in the auxiliary module is a standard configuration for in-memory computing, and the present invention does not involve changes to this part, and thus the present invention does not make a specific introduction to the auxiliary module.

[0084] As follows, the calculation process of static random access memory is explained through a specific example.

[0085] The timing control module can generate the various clock signals required in the read / write operation process and the control signals of IN[0:1], IN[2:3], IN[4:5] and IN[6:7] respectively for four cycle calculations; the adder circuit can accumulate the outputs between the corresponding columns to realize the accumulation process in the convolution operation, and its final output is the final output of the entire static random access memory in one digital calculation.

[0086] Fig.11 Schematic diagram of the implementation of 8-bit weight in static random access memory in some embodiments of the present invention. Fig.11 Regarding the 8-bit weight, the static random access memory is stored through 4 digital in-memory computing arrays, that is, a column of digital in-memory computing arrays of the digital in-memory computing module. Taking the storage of 8-bit weight W[0:7] as an example, W[0:1] is stored in the first group of two adjacent 6T-SRAM cells in the storage part of the first array in a column, W[2:3] is stored in the second group of two adjacent 6T-SRAM cells in the storage part of the second array in a column, W[4:5] is stored in the third group of two adjacent 6T-SRAM cells in the storage part of the third array in a column, and W[6:7] is stored in the fourth group of two adjacent 6T-SRAM cells in the storage part of the fourth array in a column.

[0087] Fig.12 Schematic diagram of the implementation of 8-bit input in static random access memory in some embodiments of the present invention. Fig.12 , for 8-bit input, the static random access memory can be input to the first global bit line GBL and the second global bit line GBLB through a 4-cycle cycle. Take the input of 8-bit input IN[0:7] as an example:

[0088] In cycle 1, 2-bit data IN[1] and IN[0] are input to the first global bit line GBL and the second global bit line GBLB respectively, and IN[0:1]×W[0:7] is calculated by the calculation part.

[0089] In cycle two, 2-bit data IN[3] and IN[2] are input to the first global bit line GBL and the second global bit line GBLB respectively, and IN[2:3]×W[0:7] is calculated by the calculation part.

[0090] In cycle three, 2-bit data IN[5] and IN[4] are input to the first global bit line GBL and the second global bit line GBLB respectively, and IN[4:5]×W[0:7] is calculated by the calculation part.

[0091] In cycle four, 2-bit data IN[7] and IN[6] are input to the first global bit line GBL and the second global bit line GBLB respectively, and IN[6:7]×W[0:7] is calculated by the calculation part.

[0092] The calculation result of each cycle is sent to the adder circuit for shift accumulation. The output result of cycle 4 is shifted left by 6 bits, the output result of cycle 3 is shifted left by 4 bits, and the output result of cycle 2 is shifted left by 2 bits. They are added to the output result of cycle 1 respectively. Finally, the adder circuit outputs the calculation result of 8-bit input × 8-bit weight, that is, IN[0:7]×W[0:7]. Therefore, the static random access memory can realize the "multiplication + accumulation" operation of 8-bit input and 8-bit weight, which can be better applied to CNN network reasoning.

[0093] In an embodiment of the present invention, an electronic device is provided, which is equipped with the static random access memory provided by the present invention. The working principle of the static random access memory is as described above.

[0094] It should be understood that the specific embodiments described herein are only used to explain the application, rather than to limit it. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of this application.

[0095] Obviously, the drawings are only some examples or embodiments of the present application. For ordinary technicians in the field, the present application can also be applied to other similar situations based on these drawings without creative work. In addition, it is understandable that although the work done in this development process may be complicated and lengthy, for ordinary technicians in the field, certain changes in design, manufacturing or production based on the technical content disclosed in this application are only conventional technical means and should not be regarded as insufficient content disclosed in this application.

Claims

1. A five-tube half adder circuit, characterized in that: include: A first NMOS tube, a second NMOS tube, a first PMOS tube, a second PMOS tube, and a third PMOS tube; The source of the first NMOS tube is connected to the drain of the first PMOS tube and the drain of the second PMOS tube to form a first node, the gate of the first NMOS tube is connected to a voltage source, and the drain of the first NMOS tube is grounded; The gate of the second NMOS tube is connected to the gate of the third PMOS tube and forms a second node, and the source of the first PMOS tube and the gate of the second PMOS tube are connected to the second node; The drain of the third PMOS tube is connected to the drain of the second NMOS tube to form a third node, and the source of the third PMOS tube is grounded; The source of the second NMOS tube is connected to the gate of the first PMOS tube and the source of the second PMOS tube to form a fourth node; The second node and the fourth node are input nodes of the five-tube half adder, the first node and the third node are output nodes of the five-tube half adder, the third node is used to output a carry signal, and the fourth node is used to output an addition sum; The operation function realized by the five-tube half adder circuit is: SUM= , CO=C·D; where SUM is the first node, D is the second node, CO is the third node, and C is the fourth node.

2. The five-tube half adder circuit according to claim 1, characterized in that: The supply voltage of the voltage source is 450mv.

3. A digital in-memory computing array, characterized in that: Including weight storage part and calculation part; The weight storage part is a SRAM cell array; The calculation part realizes calculation through the five-tube half adder circuit described in claim 1 or 2.

4. The digital in-memory computing array according to claim 3, characterized in that: The calculation part includes four AND gate circuits, a first half adder circuit and a second half adder circuit, the four AND gate circuits are respectively a first AND gate circuit, a second AND gate circuit, a third AND gate circuit and a fourth AND gate circuit, the first half adder circuit and the second half adder circuit are both the five-tube half adder circuits described in claim 1; Two input nodes of the first AND gate circuit are respectively connected to a first local bit line and a first global bit line; Two input nodes of the second AND gate circuit are connected to the first global bit line and the second local bit line respectively; Two input nodes of the third AND gate circuit are connected to the first local bit line and the second global bit line respectively; Two input nodes of the fourth AND gate circuit are connected to the second global bit line and the second local bit line respectively; The first node and the second node of the first half adder circuit are connected to the output nodes of the second AND gate circuit and the third AND gate circuit respectively, and the first node and the second node of the second half adder circuit are connected to the third node of the first half adder circuit and the output node of the fourth AND gate circuit respectively; The output node of the first AND gate circuit, the fourth node of the first half adder circuit, and the third node and the fourth node of the second half adder circuit constitute four output nodes of the calculation part.

5. The digital in-memory computing array according to claim 4, characterized in that: The SRAM cell array includes a third NMOS tube, a fourth NMOS tube and a plurality of 6T-SRAM cells distributed in a column direction; The first storage node and the second storage node of each of the 6T-SRAM cells are connected to the first local bit line and the second local bit line respectively; The source and drain of the third NMOS tube are connected to the first local bit line and the first global bit line respectively, the source and drain of the fourth NMOS tube are connected to the second local bit line and the second global bit line respectively, and the gates of the third NMOS tube and the fourth NMOS tube are connected to the control word line.

6. The digital in-memory computing array according to claim 5, characterized in that: The 6T-SRAM unit includes a fifth NMOS tube, a sixth NMOS tube, a first inverter and a second inverter; The output end of the second inverter is connected to the input end of the first inverter and forms the first storage node, and the output end of the first inverter is connected to the input end of the second inverter and forms the second storage node; The source, drain and gate of the fifth NMOS tube are respectively connected to the first storage node, the first local bit line and the left word line, and the source, drain and gate of the sixth NMOS tube are respectively connected to the second storage node, the second local bit line and the right word line.

7. The digital in-memory computing array according to claim 5, characterized in that: The AND gate circuit includes a fourth PMOS tube and a seventh NMOS tube; The gate of the fourth PMOS tube and the gate of the seventh NMOS tube are connected to form a fifth node, the source of the fourth PMOS tube forms a sixth node, and the drain of the seventh NMOS tube is often grounded to VSS, the fifth node and the sixth node are both input nodes of the AND gate circuit, and the drain of the fourth PMOS tube and the source of the seventh NMOS tube are connected to form an output node of the AND gate circuit.

8. The digital in-memory computing array according to claim 5, characterized in that: The number of the 6T-SRAM cells in each of the SRAM cell arrays is 16.

9. A static random access memory, characterized in that: It includes a data storage computing module and an auxiliary module; The data in-memory computing module comprises a plurality of array-distributed digital in-memory computing arrays as claimed in any one of claims 3 to 8; The auxiliary module is used to control the data storage computing module in response to the clock signal and transmit the input data and output data of the data storage computing module.

10. An electronic device, characterized in that: The static random access memory according to claim 9 is built in.

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