Back pressure verification method, computer equipment and medium for chip design

Abstract

The present application relates to the field of computer technology and provides a back pressure verification method, computer equipment and medium for chip design, which are used to deal with the problem of high difficulty in developing back pressure verification. The back pressure verification method includes: initializing the chip simulation verification platform, and then instantiating the top layer, the design to be tested and the interface module; through the back pressure test module, based on at least one back pressure type associated with the design to be tested, determining the corresponding back pressure signal, and then, according to the pre-configured response method, performing back pressure overshoot check and continuity check after back pressure release by monitoring the back pressure signal. In this way, not only can various situations that may cause back pressure be simulated efficiently, but also it has good reusability of back pressure testing, which is convenient for transplantation to various verification environments, which is conducive to shortening the chip verification cycle and improving chip development efficiency.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a back pressure verification method, computer equipment and medium for chip design. Background Art

[0002] In the verification of network chips, back pressure related testing and verification are required to meet the needs of data transmission between upstream and downstream modules in complex application environments. In the prior art, chip simulation and verification personnel generate test cases by writing code, and then test the back pressure performance of the chip design through the back pressure verification component. Depending on the back pressure source, back pressure type, etc., various test cases need to be generated to simulate various situations that may cause back pressure in actual applications. These make the development of back pressure verification difficult and the code redundancy high, which is not conducive to shortening the chip verification cycle and improving chip development efficiency.

[0003] To this end, the present application provides a back pressure verification method, computer equipment and medium for chip design, which can not only efficiently simulate various situations that may cause back pressure, but also have good reusability of back pressure testing, and is easy to port to various verification environments, which is conducive to shortening the chip verification cycle and improving chip development efficiency. Summary of the invention

[0004] In the first aspect, the present application provides a back pressure verification method for chip design. The back pressure verification method includes: initializing a chip simulation verification platform, and then instantiating a top layer, a design to be tested, and an interface module, wherein the chip simulation verification platform includes a sequence generator, a test case library, a reference model, a detection module, and a back pressure test module, wherein the sequence generator is used to generate a stimulus input to the design to be tested, the test case library is used to provide a test case, and the test case is input to the input end of the design to be tested and the reference model, the detection module is used to compare the output of the reference model with the output of the output end of the design to be tested through the interface module to generate a detection result, and the back pressure test module is connected between the input end of the design to be tested and the output end of the design to be tested; through the back pressure test module, based on at least one back pressure type associated with the design to be tested, at least one back pressure signal corresponding to the at least one back pressure type is determined, and then, according to a pre-configured response mode, the back pressure overshoot check and the continuity check after the back pressure release of the design to be tested are performed by monitoring the at least one back pressure signal.

[0005] Through the first aspect of the present application, not only can various situations that may cause back pressure be simulated efficiently, but also the back pressure test has good reusability, which is convenient for porting to various verification environments, which is conducive to shortening the chip verification cycle and improving chip development efficiency.

[0006] In a possible implementation of the first aspect of the present application, the at least one back pressure type includes a first-in-first-out back pressure type and a handshake back pressure type, the back pressure signal corresponding to the first-in-first-out back pressure type is a full threshold signal, and the back pressure signal corresponding to the handshake back pressure type is a handshake signal.

[0007] In a possible implementation manner of the first aspect of the present application, monitoring the full threshold signal is achieved by monitoring a single-bit read / write control signal, and monitoring the handshake signal is achieved by monitoring a handshake request signal.

[0008] In a possible implementation of the first aspect of the present application, the pre-configured response method is determined based on the back pressure overshoot check and the continuity check after the back pressure release of the design to be tested, and the response methods corresponding to the back pressure overshoot check of the design to be tested are beat response, whole package response and whole package plus beat response, and the response methods corresponding to the continuity check of the back pressure after the release of the design to be tested are beat response and whole package response.

[0009] In a possible implementation of the first aspect of the present application, the beat-by-beat response indicates the beat number of monitored overshoots, the whole-packet response indicates the number of monitored whole packs, and the whole-packet plus beat response indicates the beat number before monitoring overshoots the whole pack.

[0010] In a possible implementation of the first aspect of the present application, performing a back-pressure overshoot check on the design to be tested includes determining a maximum back-pressure overshoot value of the design to be tested, and determining whether the maximum back-pressure overshoot value is within a design range of the design to be tested.

[0011] In a possible implementation of the first aspect of the present application, performing a continuity check after the back pressure of the design to be tested is released includes determining the minimum number of clocks required to maintain a continuous value after the back pressure of the design to be tested is released, and determining whether the minimum number of clocks is within the design range of the design to be tested.

[0012] In a possible implementation of the first aspect of the present application, the at least one back pressure signal includes a first back pressure signal, wherein the back pressure verification method further includes: when the design to be tested outputs the first back pressure signal, performing a back pressure overshoot check and a continuity check after back pressure release of the design to be tested by monitoring the first back pressure signal, and performing a simulated back pressure overshoot test to determine whether the design to be tested operates normally when the first back pressure signal is at a maximum back pressure overshoot value.

[0013] In a possible implementation of the first aspect of the present application, the at least one back pressure signal includes a second back pressure signal, wherein the back pressure verification method further includes: when the verification environment of the design to be tested simulates the output of the second back pressure signal to the design to be tested, performing a back pressure overshoot check and a continuity check after back pressure release of the design to be tested by monitoring the second back pressure signal, and randomly simulating the second back pressure signal to determine whether the design to be tested responds normally to the second back pressure signal.

[0014] In a possible implementation of the first aspect of the present application, the at least one back pressure signal includes a third back pressure signal, and the third back pressure signal is instantiated inside the design to be tested. The back pressure verification method also includes: performing a back pressure overshoot check and a continuity check after back pressure release of the design to be tested by monitoring the third back pressure signal.

[0015] In a possible implementation of the first aspect of the present application, the back pressure verification method also includes: by monitoring the at least one back pressure signal, when the at least one back pressure signal reaches a pre-configured back pressure clock cycle, performing a back pressure overshoot check and a continuity check after the back pressure release of the design to be tested.

[0016] In a possible implementation manner of the first aspect of the present application, the verification environment of the design to be tested calls the back pressure testing module in the main stage.

[0017] In a second aspect, an embodiment of the present application further provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements a method according to any one of the implementation modes of any of the above aspects when executing the computer program.

[0018] In a third aspect, an embodiment of the present application further provides a computer-readable storage medium, which stores computer instructions. When the computer instructions are executed on a computer device, the computer device executes a method according to any one of the implementation methods of any of the above aspects.

[0019] In a fourth aspect, an embodiment of the present application further provides a computer program product, which includes instructions stored on a computer-readable storage medium, and when the instructions are executed on a computer device, the computer device executes a method according to any one of the implementation methods of any of the above aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 A schematic diagram of a flow chart of a back pressure verification method for chip design provided in an embodiment of the present application;

[0022] Figure 2 A schematic diagram of a chip simulation verification platform provided in an embodiment of the present application;

[0023] Figure 3 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0025] It should be understood that, in the description of this application, "at least one" means one or more, and "a plurality of" means two or more. In addition, unless otherwise specified, the words "first", "second", etc. are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order.

[0026] Figure 1 A flow chart of a back pressure verification method for chip design provided in an embodiment of the present application. Figure 1 As shown, the back pressure verification method includes the following steps.

[0027] Step S101: Initialize the chip simulation verification platform, and then instantiate the top layer, the design to be tested, and the interface module, wherein the chip simulation verification platform includes a sequence generator, a test case library, a reference model, a detection module, and a back pressure test module, the sequence generator is used to generate a stimulus input to the design to be tested, the test case library is used to provide test cases, the test cases are input to the input end of the design to be tested and the reference model, the detection module is used to compare the output of the reference model with the output end of the design to be tested through the interface module to generate a detection result, and the back pressure test module is connected between the input end of the design to be tested and the output end of the design to be tested.

[0028] Step S103: Based on at least one back pressure type associated with the design to be tested, the back pressure test module determines at least one back pressure signal corresponding to the at least one back pressure type, and then, in accordance with a preconfigured response method, performs a back pressure overshoot check and a continuity check after back pressure release of the design to be tested by monitoring the at least one back pressure signal.

[0029] Figure 1 The back pressure verification method for chip design shown can be used for back pressure verification of network chips, for example. By performing back pressure overshoot check and continuity check after back pressure release, it can be determined whether the design under test (DUT) covers the maximum back pressure overshoot value and whether the overshoot value is within the design range. In this way, it can be combined with verification methodologies such as Universal Verification Methodology (UVM) for integrated circuit design, thereby providing a basis for possible problems and areas for improvement in chip design. Considering that chips may face various actual application environments in actual applications, the relationship between upstream and downstream components is complex and changeable. Therefore, it is necessary to simulate various situations that may cause back pressure in the back pressure verification of chip design, such as the chip itself may cause back pressure, the chip application environment may cause back pressure, etc., and the back pressure type and back pressure signal response mode may also change, all of which need to be considered in constructing the back pressure verification scheme for chip design. Figure 1 The back pressure verification method for chip design shown in the figure uses a highly reusable back pressure test module and is based on an optimized back pressure verification scheme. It can not only efficiently simulate various situations that may cause back pressure, but also has good back pressure test reusability, is easy to transplant to various verification environments, and is conducive to shortening the chip verification cycle and improving chip development efficiency. The following is a detailed description.

[0030] refer to Figure 1In step S101, the chip simulation verification platform is initialized, and then the top layer, the design to be tested, and the interface module are instantiated, wherein the chip simulation verification platform includes a sequence generator, a test case library, a reference model, a detection module, and a back pressure test module, wherein the sequence generator is used to generate a stimulus input to the design to be tested, the test case library is used to provide a test case, the test case is input to the input end of the design to be tested and the reference model, the detection module is used to compare the output of the reference model with the output of the output end of the design to be tested through the interface module to generate a detection result, and the back pressure test module is connected between the input end of the design to be tested and the output end of the design to be tested. In this way, a globally consistent back pressure verification component is provided by using a reusable back pressure test module, and by setting the back pressure test module between the input end of the design to be tested and the output end of the design to be tested, the necessary signals in various situations that may cause back pressure can be collected through the back pressure test module, thereby providing a basis for performing back pressure overshoot inspection and continuity inspection after back pressure release. In addition, the back pressure test module can be configured to cooperate with the generation of test cases, so as to simulate the back pressure scenarios that the chip may face in actual applications, such as the signal transmission relationship between upstream and downstream components, the back pressure that may be caused by the chip itself, and the back pressure that may be caused by the environment in which the chip is located. For example, various back pressure types and back pressure signal response methods can be simulated. By reusing the back pressure test module and changing the configuration of the back pressure test module, as well as writing the code of the test case library, it is possible to avoid developing test cases for back pressure overshoot check and continuity check after back pressure release separately for each back pressure verification test, thereby avoiding redundant code and realizing the use of highly reusable back pressure test modules to construct a back pressure verification scheme based on optimized design. It can not only efficiently simulate various situations that may cause back pressure, but also has good reusability of back pressure testing, which is easy to transplant to various verification environments, which is conducive to shortening the chip verification cycle and improving chip development efficiency.

[0031] Continue to refer Figure 1, in step S103, at least one back pressure signal corresponding to at least one back pressure type is determined through the back pressure test module based on at least one back pressure type associated with the design to be tested, and then, according to the pre-configured response mode, the back pressure overshoot check and the continuity check after the back pressure release of the design to be tested are performed by monitoring the at least one back pressure signal. The back pressure test module is located between the output end of the design to be tested and the input end of the test case, so that the necessary signals in various situations that may cause back pressure can be collected through the back pressure test module, thereby providing a basis for performing the back pressure overshoot check and the continuity check after the back pressure release. First, the chip simulation verification platform is initialized, and then the top layer, the design to be tested and the interface module are instantiated. In this way, the back pressure test module is connected to the back pressure signal, write enable signal or request signal corresponding to the interface module, depending on the back pressure type and the back pressure signal corresponding to the back pressure type. By configuring the back pressure overshoot maximum value of the back pressure test module and setting the value of how many consecutive clock cycles are required after the back pressure is released, the relevant conditions of the back pressure overshoot check and the continuity check after the back pressure release are set. In this way, by multiplexing the back pressure test module and changing the configuration of the back pressure test module, and combining the code writing of the test case library with the test case library, the back pressure signal corresponding to the back pressure type can be determined based on one or more back pressure types associated with the design to be tested, and then the back pressure signal is monitored according to the back pressure signal response mode to perform the back pressure overshoot check and the continuity check after the back pressure release of the design to be tested. For example, the back pressure type can be a first in first out (FIFO) back pressure type, and the back pressure signal corresponding to the first in first out back pressure type is a full threshold (afull) signal. For another example, the back pressure type can be a handshake back pressure type, and the back pressure signal corresponding to the handshake back pressure type is a handshake (ready) signal. It should be understood that more and richer back pressure types and back pressure signals corresponding to the back pressure types can be supported, so that by monitoring necessary signals, such as read enable control signals, write enable control signals, data request signals, etc., more and richer situations that may cause back pressure can be covered. In addition, the design to be tested may have various inherent circuit designs, components, elements, subsystems, etc., and may also face various complex application environments. These factors can be reflected in the back pressure verification scheme as simulations of various situations that may cause back pressure. Therefore, the design to be tested can be associated with multiple back pressure types, such as first-in-first-out back pressure type and handshake back pressure type and other possible back pressure types, and the back pressure signals corresponding to these back pressure types can be used as monitoring objects. In addition, the pre-configured response method can be adjusted in combination with the back pressure overshoot check and the continuity check after the back pressure release. For example, the back pressure overshoot check is a combination of response methods, and the continuity check after the back pressure release is another combination of response methods.In this way, through the back pressure test module, based on at least one back pressure type associated with the design to be tested, at least one back pressure signal corresponding to the at least one back pressure type is determined. In this way, the back pressure test module is connected between the input end of the design to be tested and the output end of the design to be tested. Necessary signals such as control signals and data request signals can be monitored, and the corresponding back pressure verification environment can be simulated in accordance with the pre-configured response mode to cooperate with the test case, so as to perform the back pressure overshoot check and the continuity check after the back pressure release of the design to be tested. A richer back pressure verification scheme can also be constructed and executed. For example, when the design to be tested outputs a back pressure signal itself, a back pressure overshoot test can be simulated to verify whether the design to be tested can work normally under the maximum back pressure overshoot value. For another example, when the environment of the design to be tested simulates back pressure to the design to be tested, the back pressure signal can be randomly simulated and applied to the design to be tested, so as to verify whether the design to be tested can respond normally to the back pressure signal from the environment. For another example, when the back pressure signal is instantiated inside the design to be tested, it is only necessary to perform a back pressure overshoot check and a continuity check after the back pressure release of the design to be tested. The maximum back pressure overshoot value of the design to be tested can be determined, and it can be judged whether the maximum back pressure overshoot value is within the design range of the design to be tested. The minimum number of clocks required to maintain a continuous value after the back pressure of the design to be tested is released can also be determined, and it can be judged whether the minimum number of clocks is within the design range of the design to be tested.

[0032] Continue to refer Figure 1In some embodiments, a systematic programming language or similar tools, such as SystemVerilog (SV), can be used to construct some underlying general back pressure overshoot models and continuity models after back pressure release. Then, by calling the corresponding tasks, the simulation model can be simplified, which is conducive to the transplantation of reference models and verification environments, and improves the overall verification efficiency of the system. By using a highly reusable back pressure test module and configuring the back pressure test module, it is fully considered that the factors that generate back pressure signals are diverse. Therefore, the corresponding back pressure overshoot check and back pressure continuity check conditions are set according to the causes of different back pressure signals, so that the customized requirements of the back pressure verification scheme can be flexibly adapted. In addition, for the three situations of the back pressure generated by the design to be tested itself, the environment simulating back pressure to the design to be tested, and the instantiation inside the design to be tested, a back pressure verification scheme can be provided in a targeted manner, and the back pressure test module is reused to perform the back pressure overshoot check and the continuity check after the back pressure release, which improves the module reusability and simplifies the scheme complexity, which is conducive to improving the chip verification efficiency. In addition, in combination with the complex and changeable application environment of the chip, a configurable back pressure signal response method is provided, as well as support for multiple back pressure types and corresponding back pressure signal monitoring. In this way, the back pressure test module is connected between the input end of the design to be tested and the output end of the design to be tested. It can monitor necessary signals such as control signals and data request signals, and can cooperate with test cases in accordance with the pre-configured response method to simulate the corresponding back pressure verification environment. It can more realistically simulate link anomalies, link failures and other scenarios, and improve the overall chip simulation verification effect. In short, Figure 1 The back pressure verification method for chip design shown in the figure utilizes a highly reusable back pressure test module and is based on an optimized back pressure verification scheme. It can not only efficiently simulate various situations that may cause back pressure, but also has good reusability of back pressure testing, and is easy to port to various verification environments, which is beneficial to shortening the chip verification cycle and improving chip development efficiency.

[0033] Figure 2 A schematic diagram of a chip simulation verification platform provided in an embodiment of the present application. Figure 2 As shown, the chip simulation verification platform includes a sequence generator 201 , a test case library 203 , a reference model 205 , a detection module 207 , and a back pressure test module 280 . Figure 2 Also shown is a design under test 290 and an interface module 292. Figure 1 The back pressure verification method for chip design shown in the figure is Figure 2The chip simulation verification platform shown can apply the following back pressure verification method: initialize the chip simulation verification platform, and then instantiate the top layer, the design to be tested 290 and the interface module 292, wherein the chip simulation verification platform includes a sequence generator 201, a test case library 203, a reference model 205, a detection module 207, and a back pressure test module 280, the sequence generator 201 is used to generate a stimulus input to the design to be tested 290, the test case library 203 is used to provide test cases, the test cases are input to the input end of the design to be tested 290 and the reference model 205, and the detection module 207 is used to generate a stimulus input to the design to be tested 290. In order to compare the output of the reference model 205 with the output of the output end of the design to be tested 290 through the interface module 292 to generate a detection result, the back pressure test module 280 is connected between the input end of the design to be tested 290 and the output end of the design to be tested 290; through the back pressure test module 280, based on at least one back pressure type associated with the design to be tested, at least one back pressure signal corresponding to the at least one back pressure type is determined, and then, according to a pre-configured response method, the back pressure overshoot check and the continuity check after the back pressure release of the design to be tested 290 are performed by monitoring the at least one back pressure signal.

[0034] Figure 2 The chip simulation verification platform shown utilizes a highly reusable back pressure test module 280, and configures the back pressure test module 280, taking into full account the fact that the factors that generate the back pressure signal are diverse. Therefore, the corresponding back pressure overshoot check and continuity check after the back pressure release are set in combination with the causes of the generation of different back pressure signals, so that the customized requirements of the back pressure verification scheme can be flexibly adapted. In addition, for the three situations in which the design to be tested 290 generates back pressure itself, the environment simulates back pressure to the design to be tested 290, and the back pressure is instantiated inside the design to be tested 290, a targeted back pressure verification scheme can be provided, and the back pressure test module 280 is reused to perform the back pressure overshoot check and the continuity check after the back pressure release, which improves the module reusability and simplifies the complexity of the scheme, which is conducive to improving the chip verification efficiency. In addition, in combination with the complex and changeable application environment of the chip, a configurable back pressure signal response method is provided, as well as support for multiple back pressure types and monitoring of corresponding back pressure signals. In this way, the back pressure test module 280 is connected between the input end of the design under test 290 and the output end of the design under test 290, and necessary signals such as control signals and data request signals can be monitored. In addition, the corresponding back pressure verification environment can be simulated in accordance with the pre-configured response method in conjunction with the test case, which can more realistically simulate link anomalies, link failures and other scenarios, and improve the overall chip simulation verification effect. In short, Figure 2The chip simulation and verification platform shown utilizes a highly reusable back pressure test module 280 and is based on an optimized back pressure verification scheme. It can not only efficiently simulate various situations that may cause back pressure, but also has good reusability of back pressure testing, and is easy to port to various verification environments, which is beneficial to shortening the chip verification cycle and improving chip development efficiency.

[0035] refer to Figure 1 and Figure 2 In a possible implementation, the at least one back pressure type includes a first-in-first-out back pressure type and a handshake back pressure type, the back pressure signal corresponding to the first-in-first-out back pressure type is a full threshold signal, and the back pressure signal corresponding to the handshake back pressure type is a handshake signal. In this way, a highly reusable back pressure test module is used, and the back pressure test module is configured, which fully takes into account that the factors that generate the back pressure signal are diverse. Therefore, the corresponding back pressure overshoot check and the continuity check after the back pressure release are set according to the causes of the generation of different back pressure signals, so that the customized requirements of the back pressure verification scheme can be flexibly adapted. In combination with the complex and changeable application environment of the chip, a configurable back pressure signal response mode is provided, and multiple back pressure types and corresponding back pressure signal monitoring are supported. In this way, the deployment of the back pressure test module connected between the input end of the design to be tested and the output end of the design to be tested is utilized, and necessary signals such as control signals and data request signals can be monitored, and the corresponding back pressure verification environment can be simulated in accordance with the pre-configured response mode in conjunction with the test case, so that the link anomaly, link failure and other scenes can be simulated more realistically, and the overall chip simulation verification effect can be improved.

[0036] In some embodiments, monitoring the full threshold signal is achieved by monitoring a single-bit read / write control signal, and monitoring the handshake signal is achieved by monitoring a handshake request signal. In this way, by using the highly reusable back pressure test module 280, based on the back pressure verification scheme after optimized design, not only can various situations that may cause back pressure be simulated efficiently, but also the back pressure test has good reusability, which is convenient for transplantation to various verification environments, and is conducive to shortening the chip verification cycle and improving chip development efficiency.

[0037] In some embodiments, the pre-configured response mode is determined based on the back pressure overshoot check and the continuity check after the back pressure release of the design to be tested. The response modes corresponding to the back pressure overshoot check of the design to be tested are beat response, whole package response and whole package plus beat response. The response modes corresponding to the continuity check of the design to be tested after the back pressure release are beat response and whole package response. The design to be tested can be associated with a variety of back pressure types, such as first-in-first-out back pressure type and handshake back pressure type and other possible back pressure types, and the back pressure signals corresponding to these back pressure types can be used as monitoring objects. In addition, the pre-configured response mode can be adjusted in combination with the back pressure overshoot check and the continuity check after the back pressure release. For example, there is a combination of response modes for the back pressure overshoot check and another combination of response modes for the continuity check after the back pressure release. In this way, through the back pressure testing module, based on at least one back pressure type associated with the design to be tested, at least one back pressure signal corresponding to the at least one back pressure type is determined. In this way, the back pressure testing module is connected between the input end of the design to be tested and the output end of the design to be tested. It is possible to monitor necessary signals such as control signals and data request signals, and to cooperate with test cases in a pre-configured response manner to simulate a corresponding back pressure verification environment, thereby executing a back pressure overshoot check and a continuity check after back pressure release for the design to be tested, and can also construct and execute richer back pressure verification schemes.

[0038] In some embodiments, the beat-by-beat response indicates the number of beats to monitor overshoot, the whole-packet response indicates the number of whole-packets to monitor, and the whole-packet plus-beat response indicates the number of beats before monitoring overshoot of the whole pack. In this way, in combination with the complex and changeable application environment of the chip, a configurable back pressure signal response method is provided, as well as support for multiple back pressure types and corresponding back pressure signal monitoring. In this way, the back pressure test module is connected between the input end of the design to be tested and the output end of the design to be tested. Necessary signals such as control signals and data request signals can be monitored, and the test case can be coordinated according to the pre-configured response method to simulate the corresponding back pressure verification environment, which can more realistically simulate link anomalies, link failures and other scenarios, and improve the overall chip simulation verification effect.

[0039] In one possible implementation, performing the back pressure overshoot check of the design to be tested includes determining the maximum back pressure overshoot value of the design to be tested, and judging whether the maximum back pressure overshoot value is within the design range of the design to be tested. In this way, by using a highly reusable back pressure test module and based on the back pressure verification scheme after optimized design, not only can various situations that may cause back pressure be simulated efficiently, but also the back pressure test has good reusability, which is convenient for porting to various verification environments, and is conducive to shortening the chip verification cycle and improving chip development efficiency.

[0040] In one possible implementation, performing a continuity check after the back pressure release of the design to be tested includes determining the minimum number of clocks required to maintain a continuous value after the back pressure of the design to be tested is released, and determining whether the minimum number of clocks is within the design range of the design to be tested. In this way, by using a highly reusable back pressure test module and based on an optimized back pressure verification scheme, not only can various situations that may cause back pressure be simulated efficiently, but also the back pressure test has good reusability, which is convenient for porting to various verification environments, and is conducive to shortening the chip verification cycle and improving chip development efficiency.

[0041] In a possible implementation, the at least one back pressure signal includes a first back pressure signal, wherein the back pressure verification method further includes: when the design to be tested outputs the first back pressure signal, by monitoring the first back pressure signal, performing a back pressure overshoot check and a continuity check after the back pressure release of the design to be tested, and performing a simulated back pressure overshoot test to determine whether the design to be tested operates normally when the first back pressure signal is at the maximum back pressure overshoot value. In this way, by utilizing the deployment of the back pressure test module connected between the input end of the design to be tested and the output end of the design to be tested, necessary signals such as control signals and data request signals can be monitored, and the corresponding back pressure verification environment can be simulated in accordance with the pre-configured response mode to cooperate with the test case, so as to perform the back pressure overshoot check and the continuity check after the back pressure release of the design to be tested, and a richer back pressure verification scheme can also be constructed and executed. For example, when the design to be tested outputs a back pressure signal itself, a back pressure overshoot test can be simulated to verify whether the design to be tested can operate normally at the maximum back pressure overshoot value.

[0042] In a possible implementation, the at least one back pressure signal includes a second back pressure signal, wherein the back pressure verification method further includes: when the verification environment of the design to be tested simulates the output of the second back pressure signal to the design to be tested, by monitoring the second back pressure signal, to perform the back pressure overshoot check and the continuity check after the back pressure release of the design to be tested, and by randomly simulating the second back pressure signal to determine whether the design to be tested responds normally to the second back pressure signal. In this way, by utilizing the deployment of the back pressure test module connected between the input end of the design to be tested and the output end of the design to be tested, necessary signals such as control signals and data request signals can be monitored, and the corresponding back pressure verification environment can be simulated in accordance with the pre-configured response mode to cooperate with the test case, so as to perform the back pressure overshoot check and the continuity check after the back pressure release of the design to be tested, and a richer back pressure verification scheme can also be constructed and executed. For example, when the environment of the design to be tested simulates back pressure to the design to be tested, the back pressure signal can be randomly simulated and applied to the design to be tested, so as to verify whether the design to be tested can respond normally to the back pressure signal from the environment.

[0043] In a possible implementation, the at least one back pressure signal includes a third back pressure signal, and the third back pressure signal is instantiated inside the design to be tested, and the back pressure verification method further includes: performing a back pressure overshoot check and a continuity check after back pressure release of the design to be tested by monitoring the third back pressure signal. In this way, by utilizing the deployment of the back pressure test module connected between the input end of the design to be tested and the output end of the design to be tested, necessary signals such as control signals and data request signals can be monitored, and the test case can be coordinated according to a pre-configured response method to simulate a corresponding back pressure verification environment, thereby performing a back pressure overshoot check and a continuity check after back pressure release of the design to be tested, and more abundant back pressure verification schemes can also be constructed and executed. For example, when the back pressure signal is instantiated inside the design to be tested, it is only necessary to perform a back pressure overshoot check and a continuity check after the back pressure release of the design to be tested. The maximum back pressure overshoot value of the design to be tested can be determined, and it can be judged whether the maximum back pressure overshoot value is within the design range of the design to be tested. The minimum number of clocks required to maintain a continuous value after the back pressure of the design to be tested is released can also be determined, and it can be judged whether the minimum number of clocks is within the design range of the design to be tested.

[0044] In a possible implementation, the back pressure verification method further includes: by monitoring the at least one back pressure signal, when the at least one back pressure signal reaches a pre-configured back pressure clock cycle, performing a back pressure overshoot check and a continuity check after the back pressure release of the design to be tested. In a fault or link abnormality scenario, abnormal short-time back pressure is easily generated. By making the back pressure overshoot check and the continuity check after the back pressure release of the design to be tested be performed when the at least one back pressure signal reaches a pre-configured back pressure clock cycle, a more flexible check can be provided, and the back pressure overshoot check and the back pressure release continuity check are only performed when the back pressure has a longer clock cycle (the clock cycle value is configurable).

[0045] In a possible implementation, the verification environment of the design to be tested calls the back pressure test module in the main stage, which is conducive to the transplantation of the reference model and the verification environment and improves the overall verification efficiency of the system.

[0046] Figure 33 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application, and the computing device 300 includes: one or more processors 310, a communication interface 320 and a memory 330. The processor 310, the communication interface 320 and the memory 330 are interconnected via a bus 340. Optionally, the computing device 300 may also include an input / output interface 350, and the input / output interface 350 is connected to an input / output device for receiving parameters set by a user, etc. The computing device 300 can be used to implement some or all of the functions of the device embodiment or system embodiment in the above-mentioned embodiment of the present application; the processor 310 can also be used to implement some or all of the operating steps of the method embodiment in the above-mentioned embodiment of the present application. For example, the specific implementation of the various operations performed by the computing device 300 can refer to the specific details in the above-mentioned embodiments, such as the processor 310 is used to perform some or all of the steps in the above-mentioned method embodiment or some or all of the operations in the above-mentioned method embodiment. For another example, in an embodiment of the present application, the computing device 300 may be used to implement part or all of the functions of one or more components in the above-mentioned apparatus embodiment. In addition, the communication interface 320 may be specifically used to perform the communication functions necessary to implement the functions of these apparatuses and components, and the processor 310 may be specifically used to perform the processing functions necessary to implement the functions of these apparatuses and components.

[0047] It should be understood that Figure 3 The computing device 300 may include one or more processors 310, and the multiple processors 310 may provide processing capabilities in a parallel connection mode, a serial connection mode, a serial-parallel connection mode, or any connection mode, or the multiple processors 310 may form a processor sequence or a processor array, or the multiple processors 310 may be divided into a main processor and an auxiliary processor, or the multiple processors 310 may have different architectures such as a heterogeneous computing architecture. In addition, Figure 3 The computing device 300 shown in the figure, and the related structural description and functional description are exemplary and non-limiting. In some exemplary embodiments, the computing device 300 may include Figure 3 More or fewer components may be shown, or some components may be combined or separated, or may have a different arrangement of components.

[0048] The processor 310 may have a variety of specific implementation forms. For example, the processor 310 may include a central processing unit (CPU), a graphic processing unit (GPU), a neural-network processing unit (NPU), a tensor processing unit (TPU) or a data processing unit (DPU), etc., and the embodiment of the present application does not specifically limit it. The processor 310 may also be a single-core processor or a multi-core processor. The processor 310 may be a combination of a CPU and a hardware chip. The above-mentioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof. The processor 310 may also be implemented using a logic device with built-in processing logic alone, such as an FPGA or a digital signal processor (DSP). The communication interface 320 may be a wired interface or a wireless interface for communicating with other modules or devices. The wired interface may be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface may be a cellular network interface or a wireless local area network interface, etc.

[0049] The memory 330 may be a non-volatile memory, such as a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The memory 330 may also be a volatile memory, which may be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM). The memory 330 may also be used to store program codes and data, so that the processor 310 calls the program codes stored in the memory 330 to execute some or all of the operation steps in the above method embodiment, or to execute the corresponding functions in the above device embodiment. Figure 3 Show more or fewer components, or have different component configurations.

[0050] The bus 340 may be a peripheral component interconnect express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 340 may be divided into an address bus, a data bus, a control bus, etc. In addition to the data bus, the bus 340 may also include a power bus, a control bus, and a status signal bus, etc. However, for the sake of clarity, Figure 3 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0051] The method and device provided in the embodiments of the present application are based on the same inventive concept. Since the principles of solving the problems in the methods and devices are similar, the embodiments, implementation methods, examples or implementation methods of the methods and devices can refer to each other, and the repeated parts will not be repeated. The embodiments of the present application also provide a system, which includes multiple computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, which will not be repeated here.

[0052] The present application also provides a computer-readable storage medium, in which computer instructions are stored. When the computer instructions are executed on a computer device (such as one or more processors), the method steps in the above method embodiment can be implemented. The specific implementation of the processor of the computer-readable storage medium in executing the above method steps can refer to the specific operations described in the above method embodiment and / or the specific functions described in the above device embodiment, which will not be repeated here.

[0053] It should be understood by those skilled in the art that the embodiments of the present application may be provided as methods, systems, or computer program products. The present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. The embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented using software, the above embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program codes. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiments of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer-readable storage media can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media. Available media can be magnetic media (such as floppy disks, hard disks, tapes), optical media, or semiconductor media. Semiconductor media can be solid-state hard disks, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other form of suitable storage media.

[0054] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. Each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0055] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the present application can be adjusted in order, merged or deleted according to actual needs; the modules in the system of the embodiment of the present application can be divided, merged or deleted according to actual needs. If these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A back pressure verification method for chip design, characterized in that: The back pressure verification method comprises: Initialize the chip simulation verification platform, and then instantiate the top layer, the design to be tested, and the interface module, wherein the chip simulation verification platform includes a sequence generator, a test case library, a reference model, a detection module, and a back pressure test module, wherein the sequence generator is used to generate a stimulus input to the design to be tested, the test case library is used to provide test cases, and the test cases are input to the input end of the design to be tested and the reference model, the detection module is used to compare the output of the reference model with the output of the output end of the design to be tested through the interface module to generate a detection result, and the back pressure test module is connected between the input end of the design to be tested and the output end of the design to be tested; Determining, by means of the back pressure test module, at least one back pressure signal corresponding to at least one back pressure type associated with the design to be tested, and then, in accordance with a pre-configured response mode, performing a back pressure overshoot check and a continuity check after back pressure release of the design to be tested by monitoring the at least one back pressure signal, The at least one back pressure signal includes a first back pressure signal, wherein the back pressure verification method further includes: When the design under test outputs the first back pressure signal, a back pressure overshoot check and a continuity check after back pressure release of the design under test are performed by monitoring the first back pressure signal, and a simulated back pressure overshoot test is performed to determine whether the design under test operates normally when the first back pressure signal is at a back pressure overshoot maximum value. The at least one back pressure signal includes a second back pressure signal, wherein the back pressure verification method further includes: When the verification environment of the design under test simulates outputting the second back pressure signal to the design under test, a back pressure overshoot check and a continuity check after back pressure release of the design under test are performed by monitoring the second back pressure signal, and the second back pressure signal is randomly simulated to determine whether the design under test responds normally to the second back pressure signal. The at least one back pressure signal includes a third back pressure signal, and the third back pressure signal is instantiated inside the design under test. The back pressure verification method further includes: By monitoring the third back pressure signal, a back pressure overshoot check and a continuity check after back pressure release of the design under test are performed.

2. The back pressure verification method according to claim 1, characterized in that: The at least one back pressure type includes a first-in-first-out back pressure type and a handshake back pressure type. The back pressure signal corresponding to the first-in-first-out back pressure type is a full threshold signal, and the back pressure signal corresponding to the handshake back pressure type is a handshake signal.

3. The back pressure verification method according to claim 2, characterized in that: Monitoring the full threshold signal is achieved by monitoring a single-bit read / write control signal, and monitoring the handshake signal is achieved by monitoring a handshake request signal.

4. The back pressure verification method according to claim 2, characterized in that: The pre-configured response mode is determined based on the back pressure overshoot check and the continuity check after the back pressure release of the design to be tested. The response modes corresponding to the back pressure overshoot check of the design to be tested are beat response, whole package response and whole package plus beat response. The response modes corresponding to the continuity check of the design to be tested after the back pressure release are beat response and whole package response.

5. The back pressure verification method according to claim 4, characterized in that: The beat-by-beat response indicates the number of beats for monitoring overshoot, the whole-packet-by-packet response indicates the number of whole-packets for monitoring, and the whole-packet-plus-beat response indicates the number of beats before monitoring overshoot of the whole packet.

6. The back pressure verification method according to claim 1, characterized in that: Performing the back-voltage overshoot check of the design to be tested includes determining a maximum back-voltage overshoot value of the design to be tested, and judging whether the maximum back-voltage overshoot value is within a design range of the design to be tested.

7. The back pressure verification method according to claim 1, characterized in that: Performing the continuity check after the back pressure release of the design under test includes determining the minimum number of clocks required to maintain a continuous value after the back pressure of the design under test is released, and judging whether the minimum number of clocks is within the design range of the design under test.

8. The back pressure verification method according to claim 1, characterized in that: The back pressure verification method further includes: By monitoring the at least one back pressure signal, when the at least one back pressure signal reaches a pre-configured back pressure clock cycle, a back pressure overshoot check and a continuity check after back pressure release of the design to be tested are performed.

9. The back pressure verification method according to claim 1, characterized in that: The verification environment of the design to be tested calls the back pressure test module in the main stage.

10. A computer device, characterized in that: The computer device comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1 to 9 when executing the computer program.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, which, when executed on a computer device, cause the computer device to perform the method according to any one of claims 1 to 9.

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