Data reading methods, selectable memory and memory system

Abstract

Embodiments of the present application disclose a data reading method, a selector-only memory and a memory system. The data reading method comprises: raising a voltage of a selected word line to a word line reading voltage, and detecting a bit line reading voltage of a selected bit line; in response to the bit line reading voltage of the selected bit line being less than a reference voltage, reading target data as 0; and raising the voltage of the selected bit line to a first compensation voltage.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, specifically to a data reading method, a selective memory, and a memory system. Background Technology

[0002] In 3D XPoint memory (3D magnetic memory), the storage cell consists of a selector (a switch used as a cell selection element) and a storage element (phase change memory PCM); that is, 3D XPoint memory has a 1S1R configuration.

[0003] In a Selector Only Memory (SOM), the memory cell only includes the selector. Compared to 3D XPoint memory, SOM can adapt to smaller processing sizes; even at a processing size of 15nm, the high and low threshold voltage states in the SOM can be maintained. In addition, the write time of SOM devices is shorter, and the write time can be kept almost consistent between the reset and set states. Furthermore, the write cycle lifetime of SOM is also longer than that of 1S1R configured memory.

[0004] However, read disturbance still exists during the reading process of SOM devices, which can lead to a decrease in Ea (activation energy), causing changes in the device's threshold voltage and adversely affecting the device's performance. Summary of the Invention

[0005] In view of this, the embodiments of this application provide a data reading method that selects only the memory and memory system, which can reduce read interference problems and ensure the accuracy of the stored data.

[0006] The technical solution of this application embodiment is implemented as follows:

[0007] This application provides a data reading method applied to a selector-only memory, comprising: increasing the voltage of a selected word line to a word line read voltage and detecting the bit line read voltage of the selected word line; in response to the bit line read voltage of the selected word line being less than a reference voltage, reading target data as 0; and increasing the voltage of the selected word line to a first compensation voltage.

[0008] In some embodiments of this application, the first compensation voltage is greater than the voltage at the ground terminal.

[0009] In some embodiments of this application, after detecting the bit line reading voltage of the selected positioning line, the data reading method further includes: in response to the bit line reading voltage of the selected positioning line being greater than a reference voltage, reading the target data as 1.

[0010] In some embodiments of this application, the data reading method further includes: in response to the voltage of the selected word line rising to the word line reading voltage, raising the voltage of the unselected word line to a second compensation voltage.

[0011] In some embodiments of this application, the second compensation voltage is less than the word line read voltage and greater than the voltage at the ground terminal.

[0012] In some embodiments of this application, before raising the voltage of the selected word line to the word line read voltage, the data reading method further includes: discharging the selected word line to the starting bit line voltage; the starting bit line voltage is less than the reference voltage.

[0013] In some embodiments of this application, after reading the target data, the data reading method further includes: grounding the selected word line and the selected positioning line.

[0014] This application embodiment also provides a selectable memory, including: a memory cell array and peripheral circuitry; wherein, the memory cell array includes: multiple row word lines and multiple column bit lines, and memory cells coupled between the word lines and the bit lines; the peripheral circuitry is coupled to the multiple row word lines and the multiple column bit lines; the peripheral circuitry is configured to increase the voltage of the selected word line to a word line read voltage, and detect the bit line read voltage of the selected word line; and, in response to the bit line read voltage of the selected word line being less than a reference voltage, read target data as 0; and increase the voltage of the selected word line to a first compensation voltage.

[0015] In some embodiments of this application, the peripheral circuit is further configured to raise the voltage of the unselected word line to a second compensation voltage in response to the voltage of the selected word line rising to the word line read voltage; wherein the second compensation voltage is less than the word line read voltage and greater than the voltage of the ground terminal.

[0016] This application also provides a memory system, characterized in that it includes: one or more selectable memories as described in the above scheme, and a memory controller; the memory controller is coupled to the selectable memories; the memory controller controls the selectable memories.

[0017] Understandably, when the voltage of the selected positioning line is lower than the reference voltage, that is, when the data "0" is stored in the SOM device, the voltage of the selected positioning line is increased to the first compensation voltage after the target data is read. In this way, compensation for the SOM device in the "0" state can specifically reduce the read interference problem, that is, solve the problem that the SOM device in the "0" state is prone to read interference. Attached Figure Description

[0018] Figure 1A This is a schematic diagram of the read interference problem in SOM devices;

[0019] Figure 1B This is a schematic diagram of the read interference problem in SOM devices. Figure 2 ;

[0020] Figure 1C This is a schematic diagram of the read interference problem in SOM devices;

[0021] Figure 2 This is a schematic diagram of the selector-only memory provided in an embodiment of this application;

[0022] Figure 3A This is a schematic diagram of the electrical parameter waveforms of the write process of the selector memory provided in this application embodiment;

[0023] Figure 3B This is a schematic diagram of the electrical parameter waveforms of the write process of the selector memory provided in the embodiments of this application. Figure 2 ;

[0024] Figure 4 This is a schematic diagram of the read process of the selector memory provided in an embodiment of this application;

[0025] Figure 5 This is a schematic diagram illustrating the implementation flow of the data reading method provided in this application embodiment;

[0026] Figure 6 This is a schematic diagram of the electrical parameter waveform of the data reading method provided in this application embodiment;

[0027] Figure 7 This is a schematic diagram of the implementation flow of the data reading method provided in the embodiments of this application. Figure 2 ;

[0028] Figure 8 This is a schematic diagram of the electrical parameter waveforms of the data reading method provided in the embodiments of this application. Figure 2 ;

[0029] Figure 9 This is a schematic diagram of the implementation process of the data reading method provided in this application embodiment;

[0030] Figure 10 This is a schematic diagram of the electrical parameter waveforms of the data reading method provided in this application embodiment;

[0031] Figure 11 This is a schematic diagram of the implementation flow of the data reading method provided in the embodiments of this application. Figure 4 ;

[0032] Figure 12 This is a schematic diagram of the implementation flow of the data reading method provided in the embodiments of this application. Figure 5 ;

[0033] Figure 13 This is a schematic diagram of the selector-only memory structure provided in the embodiments of this application. Figure 2 ;

[0034] Figure 14 This is a schematic diagram of the memory system provided in an embodiment of this application. Detailed Implementation

[0035] Exemplary embodiments of this application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.

[0036] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0037] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0038] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0039] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items. For the unit “root,” “strip,” or “piece” of a transmission line, all have the same meaning.

[0041] In order to gain a more detailed understanding of the features and technical content of the embodiments of this application, the implementation of the embodiments of this application will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this application.

[0042] In related technologies, increasing the number of read pulse cycles in a SOM (Self-Operating Machine) can lead to read interference problems. Read interference refers to the performance degradation caused by repeatedly applying large voltage differences across the device due to the increased number of read cycles (e.g., decreased Ea, changes in threshold voltage), and in severe cases, alteration of the data stored in the device. For SOM devices, read interference manifests as abnormal current during the read process.

[0043] refer to Figure 1A When the SOM device stores the data "1", as the number of read cycles increases, the current of the SOM device remains stable during the read process, meaning that read interference is essentially not an issue. (Reference...) Figure 1BWhen the SOM device stores data "0", as the number of read cycles increases, the current of the SOM device during the read process shows obvious abnormalities, that is, a read interference problem occurs.

[0044] refer to Figure 1C In scenario 1, where the SOM device stores data "1", the Ea of the SOM device remains stable as the number of read cycles increases. However, in scenario 2, where the SOM device stores data "0", the Ea of the SOM device decreases significantly as the number of read cycles increases. This causes a significant change in the threshold voltage of the SOM device, adversely affecting its performance.

[0045] In summary, for SOM devices, when the data "1" is stored in the SOM device, there is basically no read interference problem; however, when the data "0" is stored in the SOM device, read interference problems are likely to occur.

[0046] Figure 2 This is a schematic diagram of an optional structure of the selector-only memory provided in an embodiment of this application. (Reference) Figure 2 In SOM, each OTS constitutes a memory cell, and the two ends of each OTS are connected to the corresponding word line and bit line, respectively.

[0047] Combination Figure 2 and Figure 3A During the set process, the voltage of the selected word line WL is increased from the ground terminal voltage VSS to a positive voltage Vp, and the voltage of the selected positioning line BL is decreased from the ground terminal voltage VSS to a negative voltage Vn. In this way, the phase change material in the target OTS can be transformed from an amorphous state to a crystalline state, thereby writing the data "1" into the target OTS.

[0048] Combination Figure 2 and Figure 3B During the reset process, the voltage of the selected word line WL is reduced from the ground terminal voltage VSS to a negative voltage Vn, and the voltage of the selected position line BL is increased from the ground terminal voltage VSS to a positive voltage Vp. In this way, the phase change material in the target OTS can be transformed from a crystalline state to an amorphous state, thereby writing the data "0" to the target OTS.

[0049] Figure 4 The reading process of the SOM device is illustrated. For example... Figure 4 As shown, during the reading process, the voltage of the selected word line WL will rise to a positive voltage. Simultaneously, the voltage of the selected position line BL will be detected, and the SOM device (i.e., Figure 2The target data is stored in the target OTS. The voltage drop between the selected position line BL and the selected word line WL is determined by the resistance value of the SOM device. In other words, the stored target data is determined by the resistance value of the SOM device, which is determined by the state of the phase change material. The current direction during the reading process (i.e., the read direction) is from the selected word line WL to the selected position line BL.

[0050] It should be noted that the reference Figure 4 Since the read direction is from the selected word line WL to the selected position line BL, the higher the voltage of the selected word line WL during the read process, the higher the current on the SOM device. Consequently, the higher the current on the SOM device during the read process, the more likely read interference will occur.

[0051] Figure 5 This is an optional flowchart illustrating a data reading method provided in an embodiment of this application, which is applied to a selector-only memory. For example... Figure 5 As shown, the data reading method includes steps S101 to S103, which will be explained in conjunction with each step.

[0052] S101. Increase the voltage of the selected word line to the word line read voltage and detect the bit line read voltage of the selected word line.

[0053] In this embodiment of the application, reference is made to Figure 6 During the reading process of the SOM device, the voltage of the selected word line WL can be increased to the word line read voltage VBN, that is, the "WL ramping" stage is performed; and the voltage of the selected bit line BL during the "WL ramping" stage (the bit line read voltage of the selected bit line BL) is detected.

[0054] S102. In response to the bit line reading voltage of the selected positioning line being less than the reference voltage, the target data is read as 0.

[0055] In the embodiments of this application, such as Figure 6 As shown in the example, the voltage (bit line read voltage) of the selected bit line BL during the "WL rise" phase remains at the initial bit line voltage VNR1, which is less than the reference voltage Vref. Therefore, it can be determined that... Figure 2 The target OTS in the process is in a state with a large resistance value, which means that the target data to be read can be determined to be 0. Then, the "Datalatch" stage can be executed to latch the determined target data.

[0056] S103. Increase the voltage of the selected positioning line to the first compensation voltage.

[0057] In this embodiment of the application, reference is made to Figure 6With the voltage of the selected bit line BL (bit line read voltage) maintained at the initial bit line voltage VNR1, that is, after reading the target data as 0, the voltage of the selected bit line BL can be increased to the first compensation voltage VDD. This allows for... Figure 2 The voltage difference across the target OTS is compensated to a certain extent, thereby offsetting the effect on the target OTS caused by the increased voltage of the selected word line WL.

[0058] Understandably, when the voltage of the selected positioning line BL is less than the reference voltage Vref, that is, when the data "0" is stored in the SOM device (target OTS), after the target data is read, the voltage of the selected positioning line BL is increased to the first compensation voltage VDD. This compensation for the SOM device in the "0" state can specifically reduce read interference, thus solving the problem of read interference easily occurring in the "0" state SOM device and ensuring the accuracy of the stored data.

[0059] In this embodiment of the application, the first compensation voltage VDD is greater than the voltage VSS at the ground terminal.

[0060] refer to Figure 3A During the writing of data "1", the voltage of the selected word line WL rises to a positive voltage Vp (greater than the ground voltage VSS). Therefore, during the reading process, the voltage of the selected word line WL rises to the word line read voltage VBN (greater than the ground voltage VSS), which is equivalent to performing a write operation of "1" into the target OTS.

[0061] refer to Figure 3B During the process of writing data "0", the voltage of the selection line BL rises to a positive voltage Vp (greater than the ground voltage VSS). Therefore, when the target data is determined to be 0, after the reading is completed, the voltage of the selection line BL rises to the first compensation voltage VDD (greater than the ground voltage VSS), which is equivalent to performing a write operation of "0" to the target OTS. In other words, the data "0" stored in the target OTS is written back.

[0062] Understandably, when the voltage of the selected positioning line BL is less than the reference voltage Vref, that is, when the SOM device (target OTS) stores data "0", after reading the target data, the voltage of the selected positioning line BL is increased to a first compensation voltage VDD greater than the ground terminal voltage VSS. This is equivalent to writing "0" to the SOM device in the "0" state, i.e., writing back the data "0" stored in the target OTS. Therefore, the accuracy and validity of the data "0" stored in the SOM device can be guaranteed, reducing read interference experienced by the "0" state SOM device.

[0063] In some embodiments of this application, Figure 5 Following step S101, the data reading method further includes... Figure 7 S104 is shown. The steps will be explained in conjunction with each step.

[0064] S104. In response to the bit line reading voltage of the selected positioning line being greater than the reference voltage, the target data is read as 1.

[0065] In this embodiment of the application, reference is made to Figure 8 If, when the voltage of the selected word line WL rises to the word line read voltage VBN (i.e., during the "WL rise" phase), the bit line read voltage of the selected bit line BL rises to voltage VNR2 (greater than the reference voltage Vref), then it can be determined that... Figure 2 The target OTS is in a state with a small resistance value, meaning that the target data to be read can be determined to be 1. Then, the "data latching" stage can be executed to latch the determined target data.

[0066] In some embodiments of this application, in Figure 5 Following step S101, the data reading method further includes... Figure 9 Step S201 is shown. Each step will be explained in detail.

[0067] S201. In response to the voltage of the selected word line rising to the word line read voltage, the voltage of the unselected word line is raised to the second compensation voltage.

[0068] In this embodiment of the application, reference is made to Figure 2 Because multiple memory cells (OTSs) are connected to the selected word line WL, the voltage increase on the selected word line WL during the read process affects not only the target OTS connected to the selected word line BL, but also other OTSs connected to the unselected word line BL. In other words, the increased voltage on the selected word line WL will cause read interference to other OTSs.

[0069] It should be noted that during the writing process, a certain voltage difference needs to be applied across the OTS to change the state of the phase change material within the OTS, thereby writing the corresponding data. (Refer to...) Figure 3A During the writing of data "1", a positive voltage Vp is applied to the word line WL, and a negative voltage Vn is applied to the bit line BL; (Reference) Figure 3B During the writing of data "0", a negative voltage Vn is applied to the word line WL and a positive voltage Vp is applied to the bit line BL. In other words, if the voltage difference across the OTS reaches a certain level, it will change the stored data.

[0070] Combination Figure 2 and Figure 10When the voltage of the selected word line WL is increased to the word line read voltage VBN, the voltage of the unselected positioning line Use BL is increased to the second compensation voltage VC. This reduces the voltage difference between the unselected positioning line Use BL and the selected word line WL, thus reducing the voltage difference across other OTSs connected to the unselected positioning line Use BL. This counteracts the impact of the word line read voltage VBN on other OTSs, ensuring the accuracy of the data stored in those other OTSs.

[0071] In some embodiments of this application, the second compensation voltage VC is less than the word line read voltage VBN and greater than the ground voltage VSS. For example, the second compensation voltage VC can be 1.2V.

[0072] It should be noted that the voltage of the unselected positioning line Usel BL remains the same as the ground voltage VSS when it is idle. Therefore, the second compensation voltage VC needs to be greater than the ground voltage VSS in order to be effective.

[0073] In addition, the second compensation voltage VC should not be set too high. If the second compensation voltage VC is too high, it will cause an excessive voltage difference between the unselected positioning line Usel BL and the selected positioning line BL, which may lead to leakage between the unselected positioning line Usel BL and the selected positioning line BL. At the same time, an excessively high second compensation voltage VC will also result in greater power consumption.

[0074] In some embodiments of this application, the data reading method further includes Figure 11 Steps S301 and S302 are shown. Each step will be explained in detail.

[0075] S301. Discharge the selected bit line to the starting bit line voltage; the starting bit line voltage is less than the reference voltage.

[0076] In this embodiment of the application, reference is made to Figure 6 and Figure 8 At the beginning of the reading process, the selected positioning line BL needs to be discharged, that is, the "BL discharge" stage needs to be performed. This can prevent residual voltage on the selected positioning line BL from affecting the reading results.

[0077] In this embodiment, reference continues to be made to... Figure 6 and Figure 8 The selected positioning line BL can be discharged to the starting positioning line voltage VNR1; wherein, the starting positioning line voltage VNR1 is less than the reference voltage Vref, and the starting positioning line voltage VNR1 is also less than the grounding terminal voltage VSS.

[0078] S302. Ground the selected word line and the selected position line.

[0079] In this embodiment of the application, reference is made to Figure 6 and Figure 8 After reading the target data, the voltages of the selected word line WL and the selected position line BL need to be reset. Specifically, during the "data latch" phase, the selected word line WL can be grounded, thus resetting its voltage to the ground voltage VSS. During the "Weak Reset Back" or "Recovery" phase, the selected position line BL can be grounded, thus resetting its voltage to the ground voltage VSS.

[0080] Understandably, resetting the voltages of the selected word line WL and the selected location line BL can prevent residual voltages on the selected word line WL and the selected location line BL from affecting other operating processes of the memory.

[0081] Figure 12 This is an optional flowchart illustrating a data reading method provided in an embodiment of this application, which is applied to a selector-only memory. For example... Figure 12 As shown, the data reading method includes steps S401 to S405, which will be explained in conjunction with each step.

[0082] S401, Select position line BL to discharge to the starting position line voltage VNR1.

[0083] In this embodiment of the application, reference is made to Figure 6 and Figure 8 At the beginning of the reading process, the selected bit line BL needs to be discharged, that is, the "BL discharge" stage is performed. The selected bit line BL can be discharged to the starting bit line voltage VNR1.

[0084] S402. Select word line WL and raise it to the word line read voltage VBN.

[0085] In this embodiment of the application, reference is made to Figure 6 and Figure 8 The voltage of the selected word line WL can be increased to the word line read voltage VBN, that is, the "WL increase" phase is executed; and the voltage of the selected bit line BL during the "WL increase" phase (the bit line read voltage of the selected bit line BL) is detected.

[0086] S403, sense and restore the selected word line WL to the ground terminal voltage VSS.

[0087] In this embodiment of the application, reference is made to Figure 6 and Figure 8 After the voltage of the selected word line rises to the word line read voltage VBN, the voltage of the selected word line BL can be sensed, that is, the "data latch" phase is executed. At the same time, the selected word line WL can be restored to the ground terminal voltage VSS.

[0088] S404, Select positioning line BL to drive to the first compensation voltage VDD.

[0089] In this embodiment of the application, reference is made to Figure 6 After reading the target data as 0, the voltage of the selected positioning line BL can be increased to the first compensation voltage VDD, thereby compensating for the voltage difference across the target OTS and reducing the reading interference experienced by the target OTS.

[0090] S405, Select the voltage of the positioning line BL to restore it to the grounding terminal voltage VSS.

[0091] In this embodiment of the application, reference is made to Figure 6 and Figure 8 After reading the target data, the voltage of the selected positioning line BL can be restored to the ground terminal voltage VSS.

[0092] Understandably, when the voltage of the selected positioning line BL is less than the reference voltage Vref, that is, when the data "0" is stored in the SOM device (target OTS), after the target data is read, the voltage of the selected positioning line BL is increased to the first compensation voltage VDD. This compensation for the SOM device in the "0" state can specifically reduce read interference, thus solving the problem of read interference easily occurring in the "0" state SOM device and ensuring the accuracy of the stored data.

[0093] Figure 13 This is a schematic diagram illustrating an optional structure of the selector memory in an embodiment of this application. For example... Figure 13 As shown, the selector memory 10 includes: peripheral circuitry 110 and a memory cell array 120.

[0094] In this embodiment, the memory cell array 120 includes: multiple row word lines WL and multiple column bit lines BL, and memory cells coupled between the word lines WL and the bit lines BL. Peripheral circuitry 110 is coupled to the multiple row word lines WL and the multiple column bit lines BL. (Combined with...) Figure 2 The word line WL and the bit line BL extend in different directions, and the memory cell (OTS) is coupled between the word line WL and the bit line BL.

[0095] In this embodiment, the peripheral circuit 110 can perform operations to process data in the memory cell array 120. The peripheral circuit 110 can write data to the memory cell array 120 or read data from the memory cell array 120 based on the command CMD and the address ADDR.

[0096] In this embodiment, the peripheral circuit 110 is configured to raise the voltage of the selected word line to the word line read voltage and detect the bit line read voltage of the selected word line; and, in response to the bit line read voltage of the selected word line being less than the reference voltage, read the target data as 0; and raise the voltage of the selected word line to the first compensation voltage.

[0097] In some embodiments of this application, the first compensation voltage is greater than the voltage at the ground terminal.

[0098] In some embodiments of this application, the peripheral circuit 110 is also configured to read the target data as 1 in response to the bit line read voltage of the selected positioning line being greater than the reference voltage.

[0099] In some embodiments of this application, the peripheral circuit 110 is further configured to raise the voltage of an unselected word line to a second compensation voltage in response to the voltage of the selected word line rising to the word line read voltage; wherein the second compensation voltage is less than the word line read voltage and greater than the voltage of the ground terminal.

[0100] In some embodiments of this application, the peripheral circuit 110 is also configured to discharge the selected bit line to the starting bit line voltage; the starting bit line voltage is less than the reference voltage.

[0101] In some embodiments of this application, the peripheral circuit 110 is also configured to ground the selected word line and the selected position line.

[0102] Figure 14 This is a schematic diagram of an optional structure of the memory system in an embodiment of this application. For example... Figure 14 As shown, the memory system 30 includes: one or more selector-only memories 10, and a memory controller 20.

[0103] In this embodiment of the application, reference is made to Figure 14 The memory controller 20 is coupled to the selector-only memory 10 and the host, and is configured to control the selector-only memory 10. The host can be a processor (CPU) or a graphics processing unit (GPU). The host can be configured to send data to the selector-only memory 10, or to receive data from the selector-only memory 10.

[0104] Continue to refer to Figure 14 The memory controller 20 can manage the data in the selector memory 10 and communicate with the host. The memory controller 20 can be configured to control the operation of the selector memory 10, such as read and write operations.

[0105] In this embodiment of the application, reference is made to Figure 14The memory controller 20 can send data to the host and receive data from the host; and the memory controller 20 can send command CMD and address ADDR to the selector memory 10.

[0106] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0107] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this application can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined to obtain new method or device embodiments without conflict.

[0108] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A data reading method applied to a selector-only memory, characterized in that, comprising: raising a voltage of a selected word line to a word line read voltage, and detecting a bit line read voltage of a selected bit line; reading a target data as 0 in response to the bit line read voltage of the selected bit line being less than a reference voltage, and reading the target data as 1 in response to the bit line read voltage of the selected bit line being greater than the reference voltage; raising the voltage of the selected bit line to a first compensation voltage in response to reading the target data as 0; wherein the first compensation voltage is greater than a voltage of a ground terminal; raising a voltage of unselected bit lines to a second compensation voltage in response to the voltage of the selected word line being raised to the word line read voltage; the second compensation voltage is less than the word line read voltage and greater than the voltage of the ground terminal.

2. The data reading method according to claim 1, characterized by, the data reading method further comprises, before the raising the voltage of the selected word line to the word line read voltage: discharging the selected bit line to a starting bit line voltage; the starting bit line voltage is less than the reference voltage.

3. The data reading method according to claim 1, wherein, the data reading method further comprises, after the reading the target data: grounding the selected word line and the selected bit line.

4. A selective memory, characterized by comprising: a memory cell array and a peripheral circuit; wherein the memory cell array comprises: a plurality of rows of word lines and a plurality of columns of bit lines, and memory cells coupled between the word lines and the bit lines; the peripheral circuit is coupled to the plurality of rows of word lines and the plurality of columns of bit lines; the peripheral circuit is configured to raise a voltage of a selected word line to a word line read voltage, and detect a bit line read voltage of a selected bit line; and read a target data as 0 in response to the bit line read voltage of the selected bit line being less than a reference voltage, and read the target data as 1 in response to the bit line read voltage of the selected bit line being greater than the reference voltage; and raise the voltage of the selected bit line to a first compensation voltage in response to reading the target data as 0; wherein the first compensation voltage is greater than a voltage of a ground terminal; the peripheral circuit is further configured to raise a voltage of unselected bit lines to a second compensation voltage in response to the voltage of the selected word line being raised to the word line read voltage; the second compensation voltage is less than the word line read voltage and greater than the voltage of the ground terminal.

5. The selective memory of claim 4, wherein the peripheral circuit is further configured to raise a voltage of unselected bit lines to a second compensation voltage in response to the voltage of the selected word line being raised to the word line read voltage; wherein the second compensation voltage is less than the word line read voltage and greater than the voltage of the ground terminal.

6. A memory system, comprising: comprising: one or more selective memories as claimed in claim 4 or 5, and a memory controller; the memory controller is coupled to the selective memory; and the memory controller controls the selective memory.

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