Signal processing circuit and memory

Abstract

The invention provides a signal processing circuit and a memory, and the circuit comprises a pulse broadening circuit which is used for receiving a command signal and an address signal, broadening the pulse width of the address signal through the command signal, and generating an address broadening signal; the input end of the address decoding circuit is coupled to the output end of the pulse broadening circuit, and the address decoding circuit is used for receiving the address broadening signal so as to decode the address broadening signal and generate an address decoding signal corresponding to the address signal. According to the invention, pulse broadening can be carried out on the address signal so as to increase the pulse width of the address signal, more time sequence margin can be provided for address decoding, the command sampling accuracy can be ensured, and the command execution success rate is improved.

Description

Technical Field

[0001] The present application relates to but is not limited to a signal processing circuit and a memory. Background Art

[0002] In the memory, the command signal and address signal are needed to indicate the command operation to be performed and the address to perform the operation. For example, the command signal and address signal are used to indicate the execution of a precharge command for some or all rows in the target BA (Bank) in the target BG (bank group). Before the command signal and address signal reach the target BA of the target BG, a series of processing is required for the command signal and address signal.

[0003] In the prior art, an address decoding circuit is provided in the memory, and the address decoding circuit is used to receive an address signal to decode the address signal to obtain an address decoding signal, and then execute a command on the memory according to the address decoding signal and a command signal.

[0004] However, the above solution may result in command execution errors. Summary of the invention

[0005] An embodiment of the present application provides a signal processing circuit and a memory to reduce the error rate of command execution.

[0006] In a first aspect, the present application provides a signal processing circuit, comprising:

[0007] Pulse stretching circuit and address decoding circuit;

[0008] The pulse stretching circuit is used to receive a command signal and an address signal, and stretch the pulse width of the address signal through the command signal to generate an address stretching signal;

[0009] The input end of the address decoding circuit is coupled to the output end of the pulse stretching circuit, and is used for receiving the address stretching signal, decoding the address stretching signal, and generating an address decoding signal corresponding to the address signal.

[0010] In one embodiment, the pulse stretching circuit includes a first trigger;

[0011] The in-phase clock input terminal of the first trigger is used to receive a widening control signal, and the widening control signal is the command signal or an inverted signal of the command signal. The data input terminal of the first trigger is used to receive the address signal. The first trigger is used to widen the pulse width of the address signal under the control of the widening control signal, and generate and output the address widening signal.

[0012] In one embodiment, the pulse stretching circuit further includes an inverter and a transmission gate;

[0013] The input end of the inverter is used to receive the command signal, and the output end of the inverter is coupled to the inverting clock input end of the first trigger;

[0014] The input end of the transmission gate is used to receive the command signal, and the output end of the transmission gate is coupled to the in-phase clock input end of the first trigger.

[0015] In one embodiment, the pulse stretching circuit further includes an inverter and a transmission gate;

[0016] The input end of the inverter is used to receive the command signal, and the output end of the inverter is coupled to the in-phase clock input end of the first trigger;

[0017] The input end of the transmission gate is used to receive the command signal, and the output end of the transmission gate is coupled to the inverting clock input end of the first trigger.

[0018] In one embodiment, the signal processing circuit further includes: a pre-processing circuit;

[0019] The first output end of the preprocessing circuit is coupled to the input end of the pulse stretching circuit for receiving the command signal, and the second output end of the preprocessing circuit is coupled to the input end of the pulse stretching circuit for receiving the address signal. The preprocessing circuit is used to receive the command address signal to decode and amplify the command address signal to obtain the command signal and the address signal.

[0020] In one embodiment, it further includes: a synchronization circuit, wherein two input terminals of the synchronization circuit are respectively coupled to the output terminal of the address decoding circuit and the first output terminal of the preprocessing circuit, and are used to synchronize the address decoding signal with the command signal.

[0021] In one embodiment, the synchronization circuit includes a second trigger, a data input terminal of the second trigger is coupled to the output terminal of the address decoding circuit, and a clock input terminal of the second trigger is coupled to the first output terminal of the preprocessing circuit.

[0022] In one embodiment, it also includes: a delay circuit, wherein the input end of the delay circuit is coupled to the first output end of the preprocessing circuit, and the output end of the delay circuit is coupled to the input end of the synchronization circuit, and is used to delay the command signal and output it to the synchronization circuit to match the delay introduced by the pulse stretching circuit and the address decoding circuit.

[0023] In one embodiment, the address signal includes at least one of the following: a memory bank group address signal, a memory bank address signal; the command signal includes at least one of the following: a precharge command signal, a refresh command signal, and a refresh management command signal.

[0024] In a second aspect, the present application provides a memory, comprising the signal processing circuit described in the first aspect.

[0025] The embodiment of the present application provides a signal processing circuit and a memory, wherein the pulse stretching circuit is used to receive a command signal and an address signal, and to stretch the pulse width of the address signal through the command signal to generate an address stretching signal; the input end of the address decoding circuit is coupled to the output end of the pulse stretching circuit, and is used to receive the address stretching signal to decode the address stretching signal and generate an address decoding signal corresponding to the address signal. The present application can stretch the pulse of the address signal to increase the pulse width of the address signal. Pulse stretching can provide more timing margin for address decoding, help ensure the accuracy of command sampling, and improve the success rate of command execution. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0027] Figure 1 It is a schematic diagram of decoding address information of a memory provided by the prior art;

[0028] Figure 2 is a structural schematic diagram of a signal processing circuit provided in an embodiment of the present application;

[0029] Figure 3 This is a schematic diagram of the input terminal connection of a first trigger provided in an embodiment of the present application;

[0030] Figure 4 It is a schematic diagram of expanding an address signal through a command signal provided in an embodiment of the present application;

[0031] Figure 5 is another schematic diagram of input terminal connection of a first trigger provided in an embodiment of the present application;

[0032] Figure 6 It is another schematic diagram of expanding an address signal through a command signal provided in an embodiment of the present application;

[0033] Figure 7 and Figure 8 2 is a schematic diagram of the structures of two other signal processing circuits provided in the embodiments of the present application.

[0034] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0035] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0036] The embodiments of the present application are applicable to a memory, which is any semiconductor device used for data storage and data access. For example, DRAM (Dynamic Random Access Memory), DRAM may include but is not limited to: SDRAM (Synchronous Dynamic Random Access Memory), SDRAM may include but is not limited to: DDR (Double Data Rate SDRAM, double rate synchronous dynamic random access memory) 1 to DDR6, LPDDR (Low Power Double Data Rate SDRAM, low power double rate synchronous dynamic random access memory) 1 to LPDDR6.

[0037] The above memory can provide data storage and data access functions to the outside, and these functions need to rely on command signals and address signals to be implemented. Figure 1 As shown, the address signal needs to be decoded by an address decoding circuit provided in the memory to obtain an address decoding signal, and the address decoding signal and the command signal are used together to execute the command operation.

[0038] The above-mentioned address signal will be transmitted over a long distance, which may cause skew or increase in skew between the signals of multiple bits in the address signal. The skew between the signals of multiple bits refers to the time offset of the pulses of the signals of multiple bits. The larger the skew, the less the pulse overlap time between the signals of multiple bits. Conversely, the smaller the skew, the more the pulse overlap time between the signals of multiple bits.

[0039] In some scenarios, the external circuit sends a CA (Command Address) signal to the memory, which carries both an external command signal and an external address signal. For example, for a PRE (precharge) command, the first to fifth pins of the memory receive the external PRE command signal in the CA signal, and the sixth to eleventh pins of the memory receive the address signal in the CA signal, with each pin corresponding to a one-bit signal.

[0040] After receiving the external command signal, the memory processes the external command signal to obtain a command signal, and processes the external address signal to obtain an address signal. Therefore, the command signal and the address signal may also be signals of multiple bits. For the PRE command, the address signal includes a 5-bit BGBA signal. Before long-distance transmission, the rising edges of the 5-bit BGBA signals are aligned, and the falling edges are aligned, and the pulse overlap time between the 5-bit BGBA signals is long, that is, the skew between the 5-bit signals is small.

[0041] However, after long-distance transmission, the rising edges of the 5-bit BGBA signals are no longer aligned, and / or the falling edges are no longer aligned, and the pulse overlap time between the 5-bit BGBA signals is reduced, that is, the skew between the 5-bit signals is increased.

[0042] After the above-mentioned long-distance transmission causes the skew between the signals of multiple bits of the address signal to increase, the pulse width of the address signal will be reduced when decoding the address signal, resulting in subsequent command sampling errors, and further leading to command execution errors.

[0043] It should be noted that the skew between the signals of the multiple bits in the above-mentioned address signal will increase with the increase of the signal transmission distance, and / or, the smaller the pulse width of the address signal, the greater the impact of the above-mentioned skew, resulting in a greater probability of command execution errors. For example, in 1N mode, the pulse width of the command signal and the pulse width of the address signal are both 1TCK (1 clock cycle), and the sampling period of both is 1TCK. In 2N mode, the pulse width of the command signal and the pulse width of the address signal are both 2TCK, and the sampling period of both is 2TCK. Therefore, compared with the 2N mode, the pulse width of the 1N mode is smaller, and it is more likely to have command execution errors caused by the above-mentioned skew.

[0044] In order to solve the above technical problems, the embodiment of the present application can perform pulse stretching on the address signal to increase the pulse width of the address signal. When the address signal after pulse stretching is transmitted over a long distance, even if the pulse overlap time between signals of different bits is reduced due to the above-mentioned skew, the reduced pulse overlap time is still sufficient to ensure correct command sampling. In other words, pulse stretching can provide more pulse width surplus for address decoding, and even if the address decoding reduces its pulse width, the command sampling accuracy can still be guaranteed. Not only can the command execution success rate be guaranteed in low-frequency scenarios, but the command execution success rate can also be improved in high-frequency scenarios.

[0045] The embodiment of the present application can better improve the command sampling accuracy and command execution success rate in the 1N mode with a smaller pulse width.

[0046] It can be understood that the coupling involved in the embodiments of the present application can be a direct connection or an indirect connection, wherein a direct connection means that the two circuits are connected only through a circuit connection line, and an indirect connection means that both circuits are connected to another circuit to achieve the connection between the two circuits through the other circuit.

[0047] Figure 2 is a schematic diagram of a structure of a signal processing circuit provided in an embodiment of the present application. The signal processing circuit can be arranged in a memory. Figure 2 As shown, the signal processing circuit includes: a pulse stretching circuit and an address decoding circuit;

[0048] The pulse stretching circuit is used to receive the command signal and the address signal, and stretch the pulse width of the address signal through the command signal to generate an address stretching signal;

[0049] The input end of the address decoding circuit is coupled to the output end of the pulse stretching circuit, and is used for receiving the address stretching signal, decoding the address stretching signal, and generating an address decoding signal corresponding to the address signal.

[0050] In the embodiment of the present application, the above-mentioned command signal includes but is not limited to at least one of the following: a PRE command signal, a REF (Refresh) command signal or an RFM (Refresh Management) command signal.

[0051] The PRE command signal is used to precharge any row in any BA in any BG in the memory, and pull the voltages of the BL (Bit line) and BLB (Complementary bit line) of the row to the reference voltage. The PRE command signal corresponds to an address signal, which includes: a BG address signal, a BA address signal, and a row address signal.

[0052] The above-mentioned REF command signals are used to refresh data on the memory, including REFsb (Refresh Same Bank, specified memory bank refresh) command signal, REFab (Refresh All Bank, full memory bank refresh) command signal, SREF (Self Refresh, self refresh) command signal and AREF (Auto Refresh, automatic refresh) command signal.

[0053] The REFsb command signal is used to refresh the data of the specified BA of all BGs in the memory. Therefore, it does not carry the BG address signal but carries the BA address signal.

[0054] The REFab command signal is used to refresh the data of all BAs of all BGs in the memory, and therefore, it does not carry the BG address signal and the BA address signal. The above-mentioned RFM command signal is used to manage the data refresh of the memory, and is divided into two types: RFMsb (Refresh Management Same Bank, specified storage body refresh management) command signal and RFMab (RefreshManagement All Bank, full storage body refresh management) command signal. Similarly, the RFMsb command signal is used to perform data refresh management on the specified BA of all BGs in the memory, and therefore, it does not carry the BG address signal, but it carries the BA address signal. The RFMab command signal is used to perform data refresh management on all BAs of all BGs in the memory, and therefore, it does not carry the BG address signal and the BA address signal.

[0055] In addition, the address signal includes at least one of the following: a BG address signal and a BA address signal. The BG address signal may be a multi-bit BG address signal, and the BA address signal may be a multi-bit BA address signal. For some command signals, the corresponding address signal includes not only the BG address signal but also the BA address signal. For example, the above-mentioned PRE command signal. For some command signals, the corresponding address signal includes only the BA address signal, for example, the above-mentioned REFsb command signal and the above-mentioned RFMsb command signal.

[0056] In summary, the embodiments of the present application are applicable to command execution scenarios of command signals carrying address signals, in which the address signal can be pulse stretched to obtain an address stretched signal to execute the command together with the command signal. For command execution scenarios of command signals that do not carry address signals, there are no pulses in the address signal, so the results of pulse stretching the address signal and pulse stretching that are not performed on the address signal are the same, but for the sake of circuit unification, a pulse stretching circuit is provided before the address decoding circuit.

[0057] It can be understood that when the pulse width of the address signal is stretched by the command signal, the pulse width of the stretched address signal is associated with the frequency of the command signal. That is, the pulse width of the address stretch signal is the same as the time interval between two adjacent pulses of the command signal. For example, when the command signal is sent every 2 TCKs, the pulse width of the address signal can be stretched to 2TCK; when the command signal is sent every 5 TCKs, the pulse width of the address signal can be stretched to 5TCK. The generation process of the above-mentioned address stretch signal includes two cases.

[0058] In the first case, when a rising edge appears in the command signal and the rising edge samples the valid level of the address stretch signal, a pulse of the address stretch signal starts; when the next rising edge appears in the command signal and the rising edge does not sample the valid level of the address stretch signal, the pulse of the address stretch signal ends.

[0059] In the second case, when a falling edge appears in the command signal and the falling edge samples the valid level of the address stretch signal, a pulse of the address stretch signal starts; when the next rising edge appears in the command signal and the falling edge does not sample the valid level of the address stretch signal, the pulse of the address stretch signal ends.

[0060] In some embodiments, the pulse stretching circuit may include a first trigger, which may be any trigger, for example, a DFF (D flip-flop). Therefore, the embodiment of the present application can realize pulse stretching of the address signal through a simple trigger, which can reduce the circuit complexity as much as possible. The clock input end of the first trigger includes two in-phase clock input end and an inverted clock input end. The signal received by the in-phase clock input end is opposite in phase to the signal received by the inverted clock input end. The in-phase clock input end is used to perform data sampling through the rising edge of the received signal, and the inverted clock input end is used to perform data sampling through the falling edge of the received signal.

[0061] In the embodiment of the present application, the in-phase clock input terminal of the first trigger is used to receive the stretch control signal, and the inverting clock input terminal of the first trigger is used to receive the inverted signal of the stretch control signal.

[0062] Wherein, the above-mentioned widening control signal can be the above-mentioned command signal or the inverted signal of the command signal. When the widening control signal received by the in-phase clock input terminal of the first trigger is the command signal, the inverted signal of the widening control signal received by the inverted clock input terminal of the first trigger is the inverted signal of the command signal. When the widening control signal received by the in-phase clock input terminal of the first trigger is the inverted signal of the command signal, the inverted signal of the widening control signal received by the inverted clock input terminal of the first trigger is the command signal.

[0063] In addition, refer to Figure 3 or Figure 5 As shown, the first flip-flop DFF1 also has a data input terminal D for receiving an address signal. Therefore, the first flip-flop DFF1 can stretch the pulse width of the address signal under the control of the stretch control signal, generate and output an address stretch signal through the output terminal Q.

[0064] In order to obtain the inverted signal of the command signal, the signal processing circuit of the embodiment of the present application may include an inverter in addition to the first trigger. In order to allow the command signal and the inverted signal of the command signal to reach the first trigger at the same time, a transfer gate (TG) may be provided, and the transfer gate (TG) is used to transmit the input signal. The time required for the transfer gate to transmit the input signal is the same as the time required for the inverter to invert the input signal.

[0065] When the above-mentioned widening control signal is a command signal, refer to Figure 3 As shown, the input end of the inverter INV is used to receive the command signal, and the output end of the inverter INV is coupled to the inverting clock input end CLKB of the first flip-flop DFF1, so as to output the inverted signal of the command signal to the first flip-flop DFF1. At this time, the input end of the transmission gate TG is used to receive the command signal, and the output end of the transmission gate TG is coupled to the in-phase clock input end CLK of the first flip-flop DFF1, so as to output the command signal as the widening control signal to the first flip-flop DFF1.

[0066] based on Figure 3 The circuit shown, Figure 4 This is a schematic diagram of expanding an address signal through a command signal provided in an embodiment of the present application.

[0067] Reference Figure 3 As shown in FIG. 1 , since the command signal is input to the non-inverting input terminal CLK of the first flip-flop DFF1 , the command signal can perform pulse stretching on the address signal through the rising edge. Figure 4 As shown, when the command signal has a rising edge at time t1, the first trigger DFF1 samples the address signal to output a high-level address stretch signal. When the command signal has the next rising edge at time t2, the first trigger DFF1 samples the address signal to output a low-level address stretch signal.

[0068] Reference Figure 3 As shown, since the inverted signal of the command signal is input to the inverting input terminal CLKB of the first flip-flop DFF1, the inverted signal of the command signal can also perform pulse stretching on the address signal through the falling edge. Figure 4As shown, when the inverted signal of the command signal has a falling edge at time t1, the first trigger DFF1 samples the address signal to output a high-level address stretch signal. When the inverted signal of the command signal has the next falling edge at time t2, the first trigger DFF1 samples the address signal to output a low-level address stretch signal.

[0069] From the above Figure 4 It can be seen that the first trigger can realize pulse stretching of the address signal through the command signal or the inverted signal of the command signal, so that the pulse width of the address stretching signal is the same as the time interval between two adjacent rising edges of the command signal, or the same as the time interval between two adjacent falling edges of the inverted signal of the command signal.

[0070] When the above-mentioned widening control signal is an inverted signal of the command signal, refer to Figure 5 As shown, the input end of the inverter INV is used to receive the command signal, and the output end of the inverter INV is coupled to the in-phase clock input end CLK of the first flip-flop DFF1, so as to transmit the inverted signal of the command signal to the first flip-flop DFF1 as the stretch control signal. At this time, the input end of the transmission gate TG is used to receive the command signal, and the output end of the transmission gate TG is coupled to the inverted clock input end CLKB of the first flip-flop DFF1, so as to transmit the command signal to the first flip-flop DFF1.

[0071] based on Figure 5 The circuit shown, Figure 6 This is a schematic diagram of expanding an address signal through a command signal provided in an embodiment of the present application.

[0072] Reference Figure 5 As shown, since the inverted signal of the command signal is input to the non-inverting input terminal CLK of the first flip-flop DFF1, the inverted signal of the command signal can perform pulse stretching on the address signal through the rising edge. Figure 6 As shown, when the inverted signal of the command signal has a rising edge at time t3, the first trigger DFF1 samples the address signal to output a high-level address stretch signal. When the inverted signal of the command signal has the next rising edge at time t4, the first trigger DFF1 samples the address signal to output a low-level address stretch signal.

[0073] Reference Figure 5 As shown in FIG. 1 , since the command signal is input to the inverting input terminal CLKB of the first flip-flop DFF1 , the command signal can also perform pulse stretching on the address signal through the falling edge. Figure 6As shown, when the command signal has a falling edge at time t3, the first trigger DFF1 samples the address signal to output a high-level address stretch signal. When the command signal has the next falling edge at time t4, the first trigger DFF1 samples the address signal to output a low-level address stretch signal.

[0074] From the above Figure 6 It can be seen that the first trigger can realize pulse stretching of the address signal through the inverted signal of the command signal or the command signal, so that the pulse width of the address stretching signal is the same as the time interval between two adjacent rising edges of the inverted signal of the command signal, or the same as the time interval between two adjacent falling edges of the command signal.

[0075] In some embodiments, reference Figure 7 or Figure 8 As shown, the above-mentioned signal processing circuit also includes: a preprocessing circuit. The preprocessing circuit has a first output terminal and a second output terminal. The first output terminal of the preprocessing circuit is coupled to the input terminal of the pulse stretching circuit for receiving a command signal, and the second output terminal of the preprocessing circuit is coupled to the input terminal of the pulse stretching circuit for receiving an address signal. The preprocessing circuit is used to receive a command address signal (CA signal) sent by an external circuit to decode and amplify the CA signal to obtain a command signal and an address signal. In this way, the preprocessing circuit can output the command signal to the pulse stretching circuit through the first output terminal, and output the address signal to the pulse stretching circuit through the second output terminal.

[0076] Specifically, the CA signal includes a plurality of bit signals, some of which can be called external command signals, and the other bit signals can be called external address signals. The preprocessing circuit has a plurality of input terminals for receiving external command signals and external address signals, respectively, so as to decode and amplify the external command signals as command signals, and amplify the external address signals as address signals. The decoding here is a conventional decoding operation, and a conventional decoder can be used to implement the decoding. For example, a 5-bit signal can be decoded into a 32-bit signal.

[0077] The above-mentioned amplification can be understood as amplifying the amplitude of the received signal to obtain a full-swing signal.

[0078] The embodiment of the present application can achieve amplification of the CA signal through the above-mentioned preprocessing circuit, so as to avoid internal processing errors caused by signal attenuation, which helps to further improve the accuracy of command execution.

[0079] In some embodiments, reference Figure 7As shown, the above-mentioned signal processing circuit may also include: a synchronization circuit. The two input terminals of the synchronization circuit are respectively coupled to the output terminal of the address decoding circuit and the first output terminal of the preprocessing circuit, and are used to synchronize the address decoding signal and the command signal. The synchronization here can be understood as making the address decoding signal and the command signal independently transmitted by the synchronization circuit correspond to each other, so that the subsequent processing circuit of the memory can correspond and merge the address decoding signal and the command signal. The address decoding signal is used to indicate the address targeted when executing the corresponding command signal. After the synchronization of the synchronization circuit, the correspondence between the address decoding circuit and the command signal can be guaranteed to be accurate, which helps to further improve the accuracy of command execution.

[0080] The synchronization circuit may also include a second trigger. The data input terminal of the second trigger is coupled to the output terminal of the address decoding circuit to receive the address decoding signal output by the address decoding circuit. The clock input terminal of the second trigger is coupled to the first output terminal of the preprocessing circuit.

[0081] The second trigger may also be a DFF. The clock input terminal of the second trigger may be: a positive-phase clock input terminal of the second trigger, or a negative-phase clock input terminal of the second trigger.

[0082] From the above Figure 7 It can be seen that the input end of the above-mentioned synchronization circuit is directly connected to the first output end of the preprocessing circuit. However, the embodiment of the present application introduces a pulse stretching circuit and an address decoding circuit. When the preprocessing circuit outputs an address signal and a command signal at the same time, the delay introduced by the pulse stretching circuit and the address decoding circuit will cause the command signal to arrive at the synchronization circuit earlier than the address decoding signal. In this case, the synchronization accuracy of the synchronization circuit will be poor.

[0083] To solve the above problems, refer to Figure 8 As shown, the signal processing circuit further includes: a delay circuit. The input end of the delay circuit is coupled to the first output end of the preprocessing circuit. The first output end is the output end of the preprocessing circuit for outputting the command signal, so that the preprocessing circuit can output the command signal to the delay circuit.

[0084] The output end of the delay circuit is coupled to the input end of the synchronization circuit, and is used to delay the command signal and output it to the synchronization circuit to match the delay introduced by the pulse stretching circuit and the address decoding circuit (referred to as the first delay). The first delay is the sum of the delay introduced by the pulse stretching circuit and the delay introduced by the address decoding circuit.

[0085] Wherein, the delay circuit includes an even number of inverters connected in series, so that the output signal of the delay circuit can be guaranteed to be in phase with the input signal of the delay circuit. For example, the number of inverters included in the delay circuit can be determined based on the first delay so that the second delay of the delay circuit is as close as possible to the first delay. Ideally, the first delay and the second delay are the same. Therefore, the number of inverters in the delay circuit can be obtained by dividing the first delay by the delay of one inverter and rounding.

[0086] In summary, the embodiment of the present application can be based on the pre-processing circuit outputting the command signal and the address signal at the same time. Figure 8 The delay circuit shown enables the address decoding signal and the command signal to arrive at the synchronization circuit at the same time as much as possible, thereby improving the synchronization accuracy of the synchronization circuit for the address decoding signal and the delay signal.

[0087] In some embodiments, a post-processing circuit may be coupled to the synchronization circuit, and the post-processing circuit may include an even number of inverters connected in series, which is used to perform wave rectification or delay matching on the command signal and address stretching signal output by the synchronization circuit before executing the command operation.

[0088] It should be noted that the signal processing circuit of the embodiment of the present application is used to process each bit of the address signal. If the address signal has multiple bit signals, then each bit signal corresponds to one of the above signal processing circuits. For example, when the address signal is a 5-bit BGBA signal, then 5 of the above signal processing circuits are required to perform the above processing on the 5-bit BGBA signal respectively.

[0089] An embodiment of the present application also provides a memory, comprising the aforementioned signal processing circuit.

[0090] The detailed description of the memory can refer to the detailed description of the aforementioned signal processing circuit, which will not be repeated here.

[0091] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0092] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A signal processing circuit, characterized in that: include: Pulse stretching circuit and address decoding circuit; The pulse stretching circuit is used to receive a command signal and an address signal, and stretch the pulse width of the address signal through the command signal to generate an address stretching signal; The input end of the address decoding circuit is coupled to the output end of the pulse stretching circuit, and is used for receiving the address stretching signal, decoding the address stretching signal, and generating an address decoding signal corresponding to the address signal.

2. The signal processing circuit according to claim 1, characterized in that: The pulse stretching circuit includes a first trigger; The in-phase clock input terminal of the first trigger is used to receive a widening control signal, and the widening control signal is the command signal or an inverted signal of the command signal. The data input terminal of the first trigger is used to receive the address signal. The first trigger is used to widen the pulse width of the address signal under the control of the widening control signal, and generate and output the address widening signal.

3. The signal processing circuit according to claim 2, characterized in that: The pulse stretching circuit also includes an inverter and a transmission gate; The input end of the inverter is used to receive the command signal, and the output end of the inverter is coupled to the inverting clock input end of the first trigger; The input end of the transmission gate is used to receive the command signal, and the output end of the transmission gate is coupled to the in-phase clock input end of the first trigger.

4. The signal processing circuit according to claim 2, characterized in that: The pulse stretching circuit also includes an inverter and a transmission gate; The input end of the inverter is used to receive the command signal, and the output end of the inverter is coupled to the in-phase clock input end of the first trigger; The input end of the transmission gate is used to receive the command signal, and the output end of the transmission gate is coupled to the inverting clock input end of the first trigger.

5. The signal processing circuit according to any one of claims 1 to 4, characterized in that: The signal processing circuit further includes: a preprocessing circuit; The first output end of the preprocessing circuit is coupled to the input end of the pulse stretching circuit for receiving the command signal, and the second output end of the preprocessing circuit is coupled to the input end of the pulse stretching circuit for receiving the address signal. The preprocessing circuit is used to receive the command address signal to decode and amplify the command address signal to obtain the command signal and the address signal.

6. The signal processing circuit according to claim 5, characterized in that: Also includes: A synchronization circuit, wherein two input terminals of the synchronization circuit are respectively coupled to the output terminal of the address decoding circuit and the first output terminal of the preprocessing circuit, and is used for synchronizing the address decoding signal with the command signal.

7. The signal processing circuit according to claim 6, characterized in that: The synchronization circuit includes a second trigger, a data input terminal of the second trigger is coupled to the output terminal of the address decoding circuit, and a clock input terminal of the second trigger is coupled to the first output terminal of the pre-processing circuit.

8. The signal processing circuit according to claim 6, characterized in that: Also includes: A delay circuit, wherein the input end of the delay circuit is coupled to the first output end of the preprocessing circuit, and the output end of the delay circuit is coupled to the input end of the synchronization circuit, and is used to delay the command signal and output it to the synchronization circuit to match the delay introduced by the pulse stretching circuit and the address decoding circuit.

9. The signal processing circuit according to any one of claims 1 to 4, characterized in that: The address signal includes at least one of the following: a memory bank group address signal and a memory bank address signal; the command signal includes at least one of the following: a precharge command signal, a refresh command signal and a refresh management command signal.

10. A memory, characterized in that: The signal processing circuit comprises the signal processing circuit according to any one of claims 1 to 9.

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