Semiconductor devices and semiconductor systems

Abstract

This disclosure provides a semiconductor device and a semiconductor system. The semiconductor device includes at least one storage layer and peripheral circuitry coupled to the storage layer. Each storage layer includes a plurality of storage cells, a plurality of first conductive lines, and a plurality of second conductive lines. The storage cells are located between the first and second conductive lines in a first direction. A plurality of storage cells arranged along a second direction are coupled to a first conductive line, and a plurality of storage cells arranged along a third direction are coupled to a second conductive line. The plurality of storage cells are configured as a storage matrix. The peripheral circuitry is configured to: apply an input voltage to the plurality of first conductive lines in the storage layer based on input data; and obtain the result of the operation between the input data and the matrix stored in the plurality of storage cells in the storage layer based on the output current or output voltage of the second conductive lines in the storage layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor device and semiconductor system. Background Technology

[0002] In the classic von Neumann computing architecture, memory and processor are separate, with data transfer between them via a data bus. When executing instructions, the processor first reads data from memory, processes it, and then writes the updated data back to memory. This frequent data movement incurs significant power consumption and time overhead. Furthermore, due to limited memory bandwidth, the processor's processing speed is constrained by memory access speed, thus limiting performance improvements. With the rise of big data and artificial intelligence applications, the demand for processing massive amounts of data has made the bottlenecks of the von Neumann computing architecture increasingly prominent. Summary of the Invention

[0003] This disclosure provides a semiconductor device and a semiconductor system.

[0004] In a first aspect, embodiments of this disclosure provide a semiconductor device, including at least one memory layer and peripheral circuitry coupled to the memory layer; wherein,

[0005] Each of the storage layers includes multiple storage cells, multiple first conductive lines, and multiple second conductive lines; the storage cells are located between the first conductive lines and the second conductive lines in a first direction; multiple storage cells arranged along a second direction are coupled to one of the first conductive lines, and multiple storage cells arranged along a third direction are coupled to one of the second conductive lines; the second direction intersects the third direction and is perpendicular to the first direction; the multiple storage cells are configured as a storage matrix;

[0006] The peripheral circuit is configured to: apply an input voltage to a plurality of first conductive lines in the storage layer based on input data; and obtain the operation result of the input data and the matrix stored in a plurality of storage cells in the storage layer based on the output current or output voltage of the second conductive lines in the storage layer.

[0007] In one optional implementation, the memory cell has a first state and a second state; the threshold voltage of the memory cell in the first state is less than the threshold voltage of the memory cell in the second state and greater than the subthreshold voltage of the memory cell; the input voltage applied to a first conductive line includes a first voltage and a second voltage; the first voltage is greater than the subthreshold voltage of the memory cell and less than the threshold voltage of the memory cell in the second state; the second voltage is less than the subthreshold voltage of the memory cell.

[0008] The memory cell coupled to the first conductive line to which the first voltage is applied and in the first state is configured to output a first current or a first output voltage;

[0009] The memory cell coupled to the first conductive line to which the first voltage is applied and in the second state is configured to output a second current or a second output voltage; the second current is less than the first current, and the second output voltage is less than the first output voltage.

[0010] In one optional implementation, the peripheral circuit includes an input circuit and a counting circuit; wherein,

[0011] The input circuit is connected to the first conductive line and is configured to: apply the input voltage to multiple first conductive lines in multiple steps based on the input data, with the input voltage applied to one first conductive line each time;

[0012] The counting circuit is connected to the second conductive line and is configured to: count the number of times the output current of each second conductive line is greater than a preset current to obtain the operation result of the input data and the matrix, wherein the preset current is greater than the second current and less than the first current; or, count the number of times the output voltage of each second conductive line is greater than a preset voltage to obtain the operation result of the input data and the matrix, wherein the preset voltage is greater than the second output voltage and less than the first output voltage.

[0013] In one optional implementation, the peripheral circuitry includes an input circuit and a computing circuit; wherein,

[0014] The input circuit is connected to the first conductive line and is configured to simultaneously apply the input voltage to multiple first conductive lines in the storage layer based on the input data;

[0015] The computing circuit is connected to the second conductive line and is configured to: round the output current of each second conductive line to a multiple of the first current to obtain the operation result of the input data and the matrix; or, round the output voltage of each second conductive line to a multiple of the first output voltage to obtain the operation result of the input data and the matrix.

[0016] In one alternative implementation, the first voltage is less than the threshold voltage of the memory cell in the first state.

[0017] In one alternative implementation, the peripheral circuit is configured as follows:

[0018] Before applying an input voltage to the plurality of first conductive lines in the storage layer based on the input data, the storage cells in the storage layer are programmed to a first state or a second state based on the matrix, so as to write the matrix into the plurality of storage cells.

[0019] In one optional implementation, the input data includes a first bit and a second bit, wherein the value of the first bit is different from the value of the second bit;

[0020] The input circuit is configured to: apply a first voltage to the first conductive line corresponding to the first bit, and apply a second voltage to the first conductive line corresponding to the second bit; or,

[0021] The input circuit is configured to apply the first voltage only to the first conductive line corresponding to the first bit.

[0022] In one optional embodiment, the semiconductor device includes two storage layers stacked along the first direction and sharing the second conductive line; the peripheral circuitry is configured as follows:

[0023] Simultaneously, based on the input data, an input voltage is applied to the first conductive line of the two storage layers;

[0024] The result of the operation between the input data and the matrix stored in multiple storage cells in the two storage layers is obtained based on the output current or output voltage of the second conductive line.

[0025] In one alternative embodiment, the storage cell includes a gating element and a phase change element stacked along the first direction; the gating element is located between the first conductive line and the phase change element.

[0026] In a second aspect, embodiments of this disclosure provide a semiconductor system, including:

[0027] At least one semiconductor device according to any of the above embodiments;

[0028] A controller, coupled to at least one of the semiconductor devices and configured to send input data to the semiconductor devices and receive computation results from the semiconductor devices.

[0029] In the technical solution provided in this disclosure, the semiconductor device includes at least one storage layer and peripheral circuitry coupled to the storage layer. The peripheral circuitry can be configured to apply an input voltage to multiple first conductive lines in the storage layer based on input data; and to obtain the calculation result of the input data and the matrix stored in multiple storage cells in the storage layer based on the output current or output voltage of the second conductive line in the storage layer. Further, the calculation can be performed using a counting circuit and / or the subthreshold range of the storage cells. On the one hand, by applying the input voltage to the first conductive line multiple times and using a counting circuit to count the number of times the output current of the second conductive line is greater than a preset current or the number of times the output voltage is greater than a preset voltage to obtain the calculation result, the accuracy of the calculation can be improved. On the other hand, using the subthreshold range of the storage cells for calculation can further reduce the power consumption of the input circuit and reduce the risk of breakdown of the device coupled to the output terminal of the second conductive line, and the voltage settling time can also be shortened. In summary, the semiconductor device provided in this disclosure can reduce the power consumption of the calculation, reduce the risk of breakdown of the output terminal device, and improve the accuracy of the calculation while controlling the calculation time. Attached Figure Description

[0030] Figure 1 Schematic diagram of the composition of the semiconductor device provided in the embodiments of this disclosure Figure 1 ;

[0031] Figure 2 This is a three-dimensional structural diagram of a portion of the semiconductor device provided in the embodiments of this disclosure;

[0032] Figure 3 Current-voltage curve of the memory cell provided in the embodiments of this disclosure;

[0033] Figure 4 Schematic diagram of the composition of the semiconductor device provided in the embodiments of this disclosure Figure 2 ;

[0034] Figure 5 A schematic diagram of the input circuit provided in an embodiment of this disclosure;

[0035] Figure 6 A schematic diagram of the operation process provided as a specific example of this disclosure;

[0036] Figure 7 Schematic diagram of the composition of the semiconductor device provided in the embodiments of this disclosure Figure 3 ;

[0037] Figure 8 Current-voltage curve 2 for a storage cell provided in an embodiment of this disclosure;

[0038] Figure 9A three-dimensional structural diagram of a portion of the structure in two storage layers sharing a second conductive line, provided in an embodiment of this disclosure;

[0039] Figure 10 Schematic diagram of the composition of the semiconductor device provided in the embodiments of this disclosure Figure 4 ;

[0040] Figure 11 A schematic diagram of a semiconductor system provided in an embodiment of this disclosure;

[0041] Figure 12 This is a flowchart illustrating the operation method of a semiconductor device provided in an embodiment of this disclosure. Detailed Implementation

[0042] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0043] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0044] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0045] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0046] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0047] In the classic von Neumann computing architecture, the memory for storing data and the processor for data processing are separate, with data transfer between them via a data bus. When executing data processing commands, the processor first needs to read data from memory, process it, and then write the updated data back to memory. This requires frequent data transfer between memory and the processor, resulting in significant power consumption and time overhead. Furthermore, due to the limited bandwidth of memory, the processor's processing speed is limited by the memory access speed, thus restricting the improvement of computing performance. With the rise of applications such as big data and artificial intelligence, the demand for processing massive amounts of data has made the bottlenecks of the von Neumann computing architecture increasingly prominent.

[0048] To address the bottlenecks of the classic von Neumann computing architecture, in-memory computing chip architecture emerged. Its basic idea is to directly utilize memory for logical computation, thereby reducing the overhead caused by frequent data transfers between memory and processor, and improving computing performance while reducing power consumption.

[0049] In some embodiments, an in-memory computing chip may include one of the following types of memory: Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Phase Change Memory (PCM), and NAND Flash Memory. PCM is a type of Storage Class Memory (SCM) that is non-volatile and has a large storage capacity. In particular, three-dimensional PCM, with its three-dimensional structure, has the characteristics of high storage density and fast read / write speeds, making it a potential candidate for in-memory computing chips. The following section will introduce the relevant aspects of three-dimensional PCM.

[0050] Figure 1 Schematic diagram of the composition of the semiconductor device provided in this disclosure Figure 1 , Figure 2 This is a three-dimensional structural diagram of a portion of a semiconductor device provided in an embodiment of this disclosure. (Refer to...) Figure 1 and Figure 2 The semiconductor device includes at least one memory layer 10 and peripheral circuitry 20 coupled to the at least one memory layer 10. Each memory layer 10 includes a plurality of memory cells 100, a plurality of first conductive lines 121, and a plurality of second conductive lines 120. The memory cells 100 are located between the first conductive lines 121 and the second conductive lines 120 in a first direction. A plurality of memory cells 100 arranged along a second direction are coupled to one first conductive line 121, and a plurality of memory cells 100 arranged along a third direction are coupled to one second conductive line 120. The second direction intersects the third direction and is perpendicular to the first direction. Here, the first direction is taken as the Z direction, the second direction as the X direction, and the third direction as the Y direction, as an example.

[0051] It should be noted that the number of first conductive lines, the number of second conductive lines, and the number of storage cells shown in the figure are merely examples, and this disclosure does not impose any specific limitations on them.

[0052] In some embodiments, refer to Figure 2 The storage unit 100 includes a gating element 102 and a phase-change element 104 stacked along a first direction, with the gating element 102 located between the first conductive line 121 and the phase-change element 104. Furthermore, the storage unit 100 also includes a first electrode 101, a second electrode 103, and a third electrode 105. The first electrode 101 is located between the gating element 102 and the first conductive line 121, the second electrode 103 is located between the gating element 102 and the phase-change element 104, and the third electrode 105 is located between the phase-change element 104 and the second conductive line 120.

[0053] In some specific examples, the first electrode 101, the second electrode 103, and the third electrode 105 may include conductive materials and may serve as conductive paths. Here, the conductive material may be at least one of the following: doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metallic materials (e.g., tungsten, titanium, tantalum, aluminum, copper, etc.), and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0054] In some specific examples, the second electrode 103 may also include a thermally insulating material, thereby reducing thermal crosstalk between the gating element 102 and the phase change element 104. For example, the second electrode 103 may include amorphous carbon.

[0055] In some specific examples, the resistance of the gating element 102 can vary in response to a change in the selection voltage applied between the first electrode 101 and the second electrode 103. In some embodiments, the gating element 102 may comprise a material having an omnidirectional threshold switch (OTS) property. The material having the OTS property may include at least one element selected from oxygen, sulfur, selenium, tellurium, germanium, antimony, silicon, and arsenic, such as Zn. x Te y 、Ge x Te y 、Nb x O y Si x As y Te z When the voltage applied between the first electrode 101 and the second electrode 103 is lower than its threshold voltage, the gating element 102 can be in a high-resistance state that prevents current from flowing through, and when the voltage applied between the first electrode 101 and the second electrode 103 is higher than its threshold voltage, the gating element 102 can be in a low-resistance state that allows current to flow through.

[0056] In one specific example, the phase change element 104 can reversibly switch between a crystalline and amorphous state, and data storage can be achieved by utilizing the difference in resistivity between its crystalline and amorphous states. Specifically, the crystalline phase of the phase change element 104 can be changed by the Joule heating generated by the voltage applied between the second electrode 103 and the third electrode 105, thereby changing the resistance of the phase change element 104 and thus changing the data stored in the phase change storage unit 100. In some embodiments, the phase change element 104 may include a chalcogenide component, such as at least one of binary compounds like GaSb, InSb, InSe, SbTe, and GeTe; ternary compounds like GeSbTe, GaSeTe, InSbTe, SnSbTe, and InSbGe; and quaternary compounds like AgInSbTe, (GeSn)SbTe, GeSb(SeTe), and TeGeSbS.

[0057] The two ends of the memory cell 100 are connected to a first conductive line 121 and a second conductive line 120, respectively. A first electrode 101 is connected to the first conductive line 121, which can be a word line (WL). A third electrode 105 is connected to the second conductive line 120, which can be a bit line (BL). A memory layer 10 may include multiple first conductive lines 121 and multiple second conductive lines 120. The extending directions of the first conductive lines 121 and the second conductive lines 120 may intersect, and both are perpendicular to the extending direction of the memory cell 100. The first conductive lines 121 and the second conductive lines 120 may include conductive materials.

[0058] In some embodiments, when a semiconductor device including at least one memory layer 10 is used as an in-memory computing chip, a plurality of memory cells 100 in the memory layer 10 can be configured as a memory matrix. Specifically, each memory cell 100 can be configured as an element in the memory matrix.

[0059] In some embodiments, the peripheral circuit 20 can be configured to program the memory cells 100 in the storage layer 10 to a first state or a second state based on a matrix, so as to write the matrix into multiple memory cells 100. Here, the matrix can be a binary matrix including multiple 1s and multiple 0s, the first state can be a set state, where the value of the element stored in the memory cell 100 in the first state can be 1, and the second state can be a reset state, where the value of the element stored in the memory cell 100 in the second state can be 0.

[0060] In this embodiment of the disclosure, after the matrix is ​​written into multiple storage cells 100 in the storage layer 10 through programming operations, the peripheral circuit 20 can be configured to: apply an input voltage to multiple first conductive lines 121 in the storage layer 10 based on the input data; and obtain the operation result of the input data and the matrix stored in the multiple storage cells 100 in the storage layer 10 based on the output current or output voltage of the second conductive line 120 in the storage layer 10. The operation scheme provided by this disclosure will now be described with reference to specific examples.

[0061] Figure 3 The current-voltage curve of the memory cell provided in the embodiments of this disclosure. Figure 4 Schematic diagram of the composition of the semiconductor device provided in the embodiments of this disclosure Figure 2 . Reference Figure 3 The threshold voltage Vt1 of the memory cell in the first state is different from the threshold voltage Vt2 of the memory cell in the second state. Furthermore, when different input voltages are applied to the memory cell, the current curves of the memory cell in the first state and the memory cell in the second state are different. Specifically, the threshold voltage Vt1 of the memory cell in the first state is less than the threshold voltage Vt2 of the memory cell in the second state. When an input voltage less than the subthreshold voltage Vt0 is applied to the memory cell, neither the memory cell in the first state nor the memory cell in the second state outputs current. However, when an input voltage greater than the subthreshold voltage Vt0 and less than the threshold voltage Vt2 of the memory cell in the second state is applied to the memory cell, the current output by the memory cell in the first state is greater than the current output by the memory cell in the second state.

[0062] In a specific example, in conjunction with reference Figure 3 and Figure 4The input voltage applied to a first conductive line 121 can be a first voltage Vin1 or a second voltage Vin0. The first voltage Vin1 is greater than the subthreshold voltage Vt0 of the memory cell and less than the threshold voltage Vt2 of the memory cell in the second state. The second voltage Vin0 is less than the subthreshold voltage Vt0 of the memory cell. When the second voltage Vin0 is applied to the first conductive line 121, neither the memory cell in the first state nor the memory cell in the second state coupled to the first conductive line 121 outputs current. When the first voltage Vin1 is applied to the first conductive line 121, the memory cell coupled to the first conductive line 121 and in the first state is configured to output a first current Iout1, and the memory cell coupled to the first conductive line 121 and in the second state is configured to output a second current Iout0. The first current Iout1 is much greater than the second current Iout0.

[0063] In some embodiments, in conjunction with reference Figure 1 and Figure 4 The peripheral circuit 20 may include an input circuit 201 and a calculation circuit 202. The input circuit 201 is connected to the first conductive line 121 and is configured to simultaneously apply an input voltage to multiple first conductive lines 121 in the storage layer 10 based on the input data. The calculation circuit 202 is connected to the second conductive line 120 and is configured to round the output current of each second conductive line 120 relative to a multiple of the first current to obtain the calculation result of the input data and the matrix stored in the multiple storage cells 100.

[0064] The above embodiment uses the example of obtaining the calculation result of input data and a matrix stored in multiple memory cells in the storage layer based on the output current of the second conductive line 120. In other embodiments, the calculation result of input data and a matrix stored in multiple memory cells in the storage layer can also be obtained based on the output voltage of the second conductive line 120. Specifically, the memory cell coupled to the first conductive line 121 to which a first voltage Vin1 is applied and is in a first state is configured to output a first output voltage Vout1; the memory cell coupled to the first conductive line 121 to which a second voltage Vin0 is applied and is in a second state is configured to output a second output voltage Vout0, wherein the first output voltage Vout1 is greater than the second output voltage Vout0; the calculation circuit 202 is configured to round the output voltage of each second conductive line 120 relative to the first output voltage Vout1 to obtain the calculation result of the input data and the matrix.

[0065] In some embodiments, the input data can be a vector comprising multiple bits. Specifically, the input data can include multiple first bits and multiple second bits, and the value of the first bit is different from the value of the second bit. For example, the value of the first bit can be 1, and the value of the second bit can be 0.

[0066] In some specific examples, Figure 5 This is a schematic diagram of the input circuit provided in an embodiment of the present disclosure, in conjunction with reference to... Figure 4 and Figure 5 The input circuit 201 may include control logic 2011, a digital-to-analog converter (DAC) circuit 2012, a voltage generator 2013, and a word line driver circuit 2014, wherein the control logic 2011 is coupled to the DAC circuit 2012, the voltage generator 2013, and the word line driver circuit 2014. The DAC circuit 2012 can convert multiple first bits and multiple second bits in the input data into a first voltage signal corresponding to the first bit and a second voltage signal corresponding to the second bit, respectively. The voltage generator 2013 can be configured to generate an input voltage corresponding to the first bit in response to the first voltage signal and an input voltage corresponding to the second bit in response to the second voltage signal. The word line driver circuit 2014 can apply the input voltage corresponding to the first bit to the first conductive line 121 corresponding to the first bit and apply the input voltage corresponding to the second bit to the first conductive line 121 corresponding to the second bit.

[0067] In some specific examples, the output terminal of the second conductive line 120 can be coupled to a low voltage, for example, the output terminal of the second conductive line 120 can be coupled to a ground terminal. Then, when the memory cell coupled to the second conductive line 120 outputs current, the current will flow towards the ground terminal. The computing circuit 202 can be connected between the second conductive line 120 and the ground terminal, and can measure the output current or output voltage of the second conductive line 120.

[0068] In a specific example, in conjunction with reference Figure 3 and Figure 4The input circuit 201 can apply different input voltages to different first conductive lines 121. The input voltage corresponding to the first bit in the input data is different from the input voltage corresponding to the second bit in the input data. Here, the input voltage corresponding to the first bit can be the first voltage Vin1, and the input voltage corresponding to the second bit can be the second voltage Vin0. Then, any one of the input voltages V1, V2, V3 and V4 applied to the first conductive line 121 can be the first voltage Vin1 or the second voltage Vin0. For a cell that is subjected to a first voltage Vin1 and is in a first state, the output current is the first current Iout1 or the output voltage is the first output voltage Vout1. For a memory cell that is subjected to a first voltage Vin1 and is in a second state, the output current is the second current Iout0 or the output voltage is the second output voltage Vout0. Furthermore, the first current Iout1 is much greater than the second current Iout0, and the first output voltage Vout1 is much greater than the second output voltage Vout0. However, a memory cell that is subjected to a second voltage Vin0 and is in either the first or second state does not output current or voltage. Therefore, when the input circuit 201 simultaneously applies multiple input voltages to the first conductive line 121, the output of the second conductive line 120 is the multiple memory cells coupled to the second conductive line 120. The calculation circuit 202 can include a calculation unit 2020 connected to each second conductive line 120. It can be configured to round the output current on each second conductive line 120 to a multiple of the first current Iout1, or to round the output voltage on each second conductive line 120 to a multiple of the first output voltage Vout1. This allows the input data to be multiplied by a column of values ​​in the matrix stored in the storage unit coupled to the second conductive line 120 and the result of the multiplication and accumulation is obtained. This achieves the multiplication and accumulation operation. The combination of the operation results corresponding to the output current or output voltage of multiple second conductive lines 120 is the operation result of the input data and the matrix stored in multiple storage units 100 in the storage layer 10. This achieves the operation of vector and matrix.

[0069] In some specific examples, the computing unit 2020 may further include a sensing circuit, an analog-to-digital conversion circuit, and an arithmetic circuit. The sensing circuit may be configured to sense the output current or output voltage of the second conductive line 120, the analog-to-digital conversion circuit may be configured to convert the output current or output voltage into a corresponding digital signal, and the arithmetic circuit may be configured to calculate the multiple of the output current relative to the first current Iout1 and round it, or calculate the multiple of the output voltage relative to the first output voltage Vout1 and round it, so as to obtain the operation result of the input data and the matrix.

[0070] It should be noted that a computing circuit can also be any combination of circuit elements that can achieve the same function.

[0071] In a specific example, in conjunction with reference Figure 3 , Figure 4 and Figure 6 The input data can be a vector

[0111] . Then, the input voltage V1 can be the second voltage Vin0, and the input voltages V2, V3, and V4 can all be the first voltage Vin1. The matrix stored in the multiple storage cells 100 can include multiple 1s and multiple 0s, where the storage cell corresponding to 1 is in the first state, and the storage cell corresponding to 0 is in the second state. When the input circuit 201 simultaneously applies input voltages V1, V2, V3, and V4, if one of the multiple storage cells 100 coupled to the second conductive line 120 with output current I1 is in the first state and is subjected to the first voltage Vin1, then the calculation result corresponding to the output current I1 is 1, and the calculation process is 0*1+1*0+1*0+1*1=1; if one of the multiple storage cells 100 coupled to the second conductive line 120 with output current I2 is in the first state and is subjected to the first voltage Vin1, then the calculation result corresponding to the output current I2 is 1, and the calculation process is 0*0. +1*0+1*0+1*1=1; Among the multiple storage cells 100 coupled to the second conductive line 120 with output current I3, three storage cells are in the first state and are subjected to the first voltage Vin1. Then the operation result corresponding to the output current I3 is 3, and the operation process is 0*1+1*1+1*1+1*1=3; Among the multiple storage cells 100 coupled to the second conductive line 120 with output current I4, one storage cell is in the first state and is subjected to the first voltage Vin1. Then the operation result corresponding to the output current I4 is 1, and the operation process is 0*0+1*1+1*0+1*0=1. Then the operation result of the input data and the matrix stored in the multiple storage cells 100 is

[1131] .

[0072] In the foregoing embodiments, the input circuit 201 needs to simultaneously apply input voltages to multiple first conductive lines 121. The first voltage Vin1 corresponding to the first bit in the input data is greater than the threshold voltage Vt1 of the memory cell in the first state and less than the threshold voltage Vt2 of the memory cell in the second state. Therefore, the first current Iout1 output by the memory cell in the first state coupled to the first conductive line 121 to which the first voltage Vin1 is applied is relatively large. When multiple memory cells coupled to the same second conductive line 120 all output the first current Iout1, the current at the output terminal of the second conductive line 120 will be relatively large. In this case, the input circuit 201 will generate a large peak power consumption, and the device coupled to the current output terminal of the second conductive line 120 (e.g., the device in the computing circuit 202) faces a high risk of being broken down by a large current. To address this, the present disclosure further provides the following embodiments.

[0073] Figure 7 Schematic diagram of the composition of the semiconductor device provided in the embodiments of this disclosure Figure 3 Combined with reference Figure 1 and Figure 7 In some embodiments, the peripheral circuit 20 includes an input circuit 201 and a counting circuit 204. The input circuit 201 is connected to the first conductive line 121 and is configured to apply an input voltage to multiple first conductive lines 121 multiple times based on the input data, with the input voltage applied to one first conductive line 121 each time. The counting circuit 204 is connected to the second conductive line 120 and is configured to count the number of times the output current of each second conductive line 120 is greater than a preset current, or to count the number of times the output voltage of each second conductive line 120 is greater than a preset voltage, so as to obtain the operation result of the input data and the matrix stored in the multiple storage units 100.

[0074] In this embodiment of the disclosure, the input circuit 201 can be configured to apply only one input voltage to the corresponding first conductive line 121 at a time, thereby reducing the peak power consumption generated by the input circuit 201 and reducing the working pressure of the word line driving circuit 2014 in the input circuit 201.

[0075] In some specific examples, refer to Figure 7 The counting circuit 204 may include a plurality of counting units 2040 connected to the second conductive line 120. The counting unit 2040 may count the number of times the output current of the second conductive line 120 connected to it is greater than a preset current, or count the number of times the output voltage of the second conductive line 120 connected to it is greater than a preset voltage.

[0076] In a specific example, the counting unit 2040 in the counting circuit 204 can be triggered by current and can count the number of times the output current of the second conductive line 120 is greater than a preset current. (Return to reference) Figure 3 If the preset current can be greater than the second current Iout0 and less than the first current Iout1, then after the input circuit 201 applies an input voltage to a corresponding first conductive line 121, only the memory cell coupled to the first conductive line 121 with the applied first voltage Vin1 and in the first state will output a first current Iout1 greater than the preset current. The current output by the memory cell coupled to the first conductive line 121 with the applied second voltage Vin0 and in the first state, as well as the current output by the memory cell in the second state, are both less than the preset current. At this time, the second... The output current of the conductive line 120 is equal to the output current of a storage cell that is coupled to both the second conductive line 120 and the first conductive line 121 to which the input voltage is applied. Therefore, when the output current of the second conductive line 120 is greater than the preset current, it is counted as 1, which is equivalent to completing one 1*1=1. When the output current of the second conductive line 120 is less than the preset current, it is counted as 0, which is equivalent to completing one 1*0=0, 0*1=0, or 0*0=0. The total number of times the output current of the second conductive line 120 is greater than the preset current is equivalent to the result obtained by summing all the multiplications.

[0077] In another specific example, the counting unit 2040 in the counting circuit 204 can be voltage-triggered and can count the number of times the output voltage of the second conductive line 120 is greater than a preset voltage. The preset voltage can be greater than the second output voltage Vout0 and less than the first output voltage Vout1. Then, after the input circuit 201 applies an input voltage to a corresponding first conductive line 121, only the memory cell coupled to the first conductive line 121 to which the first voltage Vin1 is applied and is in the first state will output a first output voltage Vout1 greater than the preset voltage. The voltages output by the memory cell coupled to the first conductive line 121 to which the second voltage Vin0 is applied and is in the first state, as well as the voltages output by the memory cell in the second state, are both less than the preset voltage. The output voltage of the second conductive line 120 is equal to the output voltage of a storage cell that is coupled to both the second conductive line 120 and the first conductive line 121 to which the input voltage is applied. Therefore, when the output voltage of the second conductive line 120 is greater than the preset voltage, it is counted as 1, which is equivalent to completing one 1*1=1. When the output voltage of the second conductive line 120 is less than the preset voltage, it is counted as 0, which is equivalent to completing one 1*0=0, 0*1=0, or 0*0=0. The total number of times the output voltage of the second conductive line 120 is greater than the preset voltage is equivalent to the result obtained by summing all the multiplications.

[0078] In some specific examples, the counting circuit 204 can be configured to perform the conversion from analog signal (output current or output voltage of the second conductor) to digital signal (operation result) while performing the counting, so that there is no need to set up a dedicated analog-to-digital conversion circuit at the output to perform analog-to-digital signal conversion.

[0079] It should be noted that the counting circuit can also be any combination of circuit elements that can achieve the same function.

[0080] In some embodiments, the input circuit 201 can also be configured to apply a voltage only to the first conductive line 121 corresponding to the first bit in the input data. Specifically, in the foregoing embodiments, the input circuit 201 is configured to apply a first voltage Vin1 to the first conductive line 121 corresponding to the first bit in the input data and a second voltage Vin0 to the first conductive line 121 corresponding to the second bit in the input data, that is, the number of times the input circuit 201 applies the input voltage to the first conductive line 121 is equal to the total number of bits in the input data. In the embodiments of this disclosure, the input circuit 201 can also be configured to apply the first voltage Vin1 only to the first conductive line 121 corresponding to the first bit in the input data. This can shorten the computation time and reduce the total power consumption required for computation.

[0081] In a specific example, refer to Figure 5 The digital-to-analog converter circuit 2012 can convert only the first bit of the input data into the corresponding voltage signal, the voltage generator 2013 can generate only the first voltage Vin1, and the word line drive circuit 2014 can transmit only the first voltage Vin1 to the first conductive line 121 corresponding to the first bit of the input data.

[0082] In this embodiment, the input circuit is configured to apply an input voltage to the first conductive line multiple times, and the counting circuit is configured to count the number of times the output current of the second conductive line is greater than a preset current or the number of times the output voltage of the second conductive line is greater than a preset voltage. The counting result is the result of the operation of the input data and the matrix stored in multiple storage units. This operation method can not only reduce the peak power consumption of the input circuit and reduce the risk of device coupled to the output terminal of the second conductive line being broken down, but also improve the calculation accuracy.

[0083] In some embodiments, the semiconductor device including the three-dimensional PCM is further configured to perform computations using subthreshold ranges of memory cells. (Referring to reference...) Figure 4 and Figure 8The input voltage may include a first voltage Vina and a second voltage Vinb. The first voltage Vina is greater than the subthreshold voltage Vt0 of the memory cell 100 and less than the threshold voltage Vt1 of the memory cell in the first state. The second voltage Vinb is less than the subthreshold voltage Vt0 of the memory cell 100. In this case, the memory cell coupled to the first conductive line 121 to which the first voltage Vina is applied and in the first state is configured to output a first current Iouta or a first output voltage Vouta. The memory cell coupled to the first conductive line 121 to which the first voltage Vina is applied and in the second state is configured to output a second current Ioutb or a second output voltage Voutb. The second current Ioutb is less than the first current Iouta, and the second output voltage Voutb is less than the first output voltage Vouta. The input circuit 201 is configured to simultaneously apply an input voltage to multiple first conductive lines 121 in the storage layer 10 based on the input data; the calculation circuit 202 is configured to round the output current of each second conductive line 120 relative to a multiple of the first current Iouta, or round the output voltage of each second conductive line 120 relative to a multiple of the first output voltage Voutb, to obtain the calculation result of the input data and the matrix.

[0084] In this embodiment, when operations are performed using the subthreshold range of the memory cell, the magnitude of the first voltage can be reduced, thus decreasing the peak power consumption of the input circuit. Furthermore, the output current of the second conductive line can be reduced, thereby lowering the risk of breakdown of devices coupled to the output terminal of the second conductive line. However, since the difference between the first and second currents is relatively small within the subthreshold range of the memory cell, the accuracy of the calculation result may be low when the output current of the second conductive line is calculated and rounded relative to the first current to obtain the operation result of the input data and the matrix. Therefore, this embodiment is suitable for implementing robust artificial neural network algorithms.

[0085] In other embodiments, in conjunction with reference to Figure 7 and Figure 8The input circuit 201 is configured to apply a first voltage Vina corresponding to the first bit in the input data to multiple first conductive lines 121 in multiple stages based on the input data, applying the first voltage Vina to one first conductive line 121 each time, and not applying a voltage to the first conductive line 121 corresponding to the second bit in the input data; the counting circuit 204 is configured to count the number of times the output current of each second conductive line 120 is greater than a preset current or the number of times the output voltage of each second conductive line 120 is greater than a preset voltage, so as to obtain the operation result of the input data and the matrix. Here, the preset current can be greater than the second current Ioutb and less than the first current Iouta, and the preset voltage can be greater than the second output voltage Voutb and less than the first output voltage Vouta.

[0086] In this embodiment, the subthreshold range of the memory cell and the counting circuit can be used simultaneously to perform calculations. On one hand, by applying an input voltage to the first conductive line multiple times and using the counting circuit to count the number of times the output current of the second conductive line is greater than a preset current or the number of times the output voltage is greater than a preset voltage to obtain the calculation result, since only one memory cell among the multiple memory cells coupled to the same second conductive line participates in the calculation at a time, the accuracy of the calculation can be improved, compensating for the problem of reduced reliability of the current accumulation result caused by the relatively small difference between the current output by the memory cell in the first state and the current output by the memory cell in the second state in the subthreshold range. On the other hand, using the subthreshold range of the memory cell for calculation can further reduce the power consumption of the input circuit and reduce the risk of breakdown of the device coupled to the output terminal of the second conductive line, and the voltage settling time of the first voltage can also be shortened, thereby compensating for the problem of prolonged calculation time caused by applying the input voltage to the first conductive line multiple times. In summary, the semiconductor device provided by this disclosure can reduce the power consumption of the calculation, reduce the risk of breakdown of the output terminal device, and improve the accuracy of the calculation while controlling the calculation time.

[0087] In the above embodiments, a scheme for performing operations using a storage layer in a semiconductor device including a three-dimensional PCM was described. In some embodiments, the semiconductor device may include multiple storage layers stacked along a first direction, and at least two of the multiple storage layers include storage layers sharing a second conductive line.

[0088] In some embodiments, Figure 9 This is a three-dimensional structural diagram of a portion of the structure of two storage layers sharing a second conductive line, as provided in an embodiment of this disclosure. Figure 10 Schematic diagram of the composition of the semiconductor device provided in the embodiments of this disclosure Figure 4 Combined with reference Figure 9 and Figure 10Storage layers 10 and 11 are stacked along the first direction, and storage layers 10 and 11 can share the second conductive line 120.

[0089] In some specific examples, the storage layer 11 includes multiple storage cells 110. Each storage cell 110 includes a first electrode 111, a phase-change element 112, a second electrode 113, a gating element 114, and a third electrode 115. The storage cell 110 is located between a second conductive line 120 and a first conductive line 122. The specific structural composition of the storage cell 110 is similar to that of the storage cell 100 in the aforementioned embodiments, and will not be described again here.

[0090] In some embodiments, refer to Figure 10 The peripheral circuitry includes an input circuit 201 and a computing circuit 202, and multiple first conductive lines 121 in storage layer 10 and multiple first conductive lines 122 in storage layer 11 are coupled to the input circuit 201. The peripheral circuitry can be configured to: simultaneously apply an input voltage to the first conductive lines of two storage layers sharing a second conductive line 120 based on the input data; and obtain the computational result of the input data and the matrix stored in multiple storage cells of the two storage layers based on the output current or output voltage of the shared second conductive line 120, thereby improving the computing power of the semiconductor device.

[0091] In this embodiment, for two memory layers sharing a second conductive line 120, the input circuit 201 can apply an input voltage in parallel to multiple first conductive lines in the two memory layers, thereby obtaining the operation result of the input data and the matrix stored in multiple memory cells in the two memory layers. This allows for the operation of input data with more elements and matrices with more elements, thereby improving the computing power of the semiconductor device.

[0092] In other embodiments, the two memory layers stacked along the first direction may not share a second conductive line, and the second conductive line in each memory layer may be coupled to a counting circuit. In this case, the input circuit may be configured to apply an input voltage to one of the first conductive lines of the multiple memory layers at a time, and the counting circuit may be configured to count the number of times the output current of the second conductive line in the multiple memory layers is greater than a preset current or to count the number of times the output voltage of the second conductive line in the multiple memory layers is greater than a preset voltage. This allows for the simultaneous acquisition of the input data and the operation results of different matrices stored in multiple memory cells in different memory layers, thereby further improving the parallelism of the operation and increasing the computing power of the semiconductor device.

[0093] Based on the above-described semiconductor device, this disclosure also provides a semiconductor system. Figure 11This is a schematic diagram of a semiconductor system provided in an embodiment of the present disclosure. The semiconductor system may include at least one semiconductor device 1000 and a controller 2000. The semiconductor device 1000 may be the semiconductor device in any of the above embodiments. The controller 2000 is coupled to at least one semiconductor device 1000 and configured to send input data to the semiconductor device 1000 and receive the calculation results of the semiconductor device 1000.

[0094] In some specific examples, the semiconductor device 1000 may be a memory including a three-dimensional PCM, and the controller 2000 may be a memory controller. The semiconductor device 1000 and the controller 2000 may be integrated into a single package.

[0095] In other specific examples, the controller 2000 may be located outside the package containing the semiconductor device 1000. For example, the controller 2000 may be the central processing unit (CPU) of a terminal device. Here, the terminal device may include, but is not limited to, mobile phones, smart TVs, smart speakers, wearable devices, tablets, desktop computers, all-in-one computers, handheld computers, laptops, servers, ultra-mobile personal computers (UMPCs), netbooks, personal digital assistants (PDAs), laptops, mobile computers, augmented reality (AR) devices, virtual reality (VR) devices, artificial intelligence (AI) devices, and any other terminal device or portable terminal device.

[0096] Based on the above-described semiconductor device, this disclosure also provides a method for operating the semiconductor device. Figure 12 This is a flowchart illustrating the operation method of the semiconductor device provided in the embodiments of this disclosure, such as... Figure 12 As shown, the operation method of the semiconductor device includes: applying an input voltage to a plurality of first conductive lines in the storage layer based on input data; and obtaining the calculation result of the input data and the matrix stored in the plurality of storage cells in the storage layer based on the output current or output voltage of the second conductive lines in the storage layer.

[0097] In some embodiments, the memory cell has a first state and a second state; the threshold voltage of the memory cell in the first state is less than the threshold voltage of the memory cell in the second state and greater than the subthreshold voltage of the memory cell; the input voltage applied to a first conductive line includes a first voltage and a second voltage; the first voltage is greater than the subthreshold voltage of the memory cell; the second voltage is less than the subthreshold voltage of the memory cell; the memory cell coupled to the first conductive line to which the first voltage is applied and in the first state outputs a first current or a first output voltage; the memory cell coupled to the first conductive line to which the first voltage is applied and in the second state outputs a second current or a second output voltage; the second current is less than the first current, and the second output voltage is less than the first output voltage.

[0098] In some embodiments, the step of applying an input voltage to a plurality of first conductive lines in the storage layer based on input data and obtaining the operation result of the input data and the matrix stored in the storage cells of the storage layer based on the output current or output voltage of the second conductive lines in the storage layer includes: applying the input voltage to a plurality of first conductive lines multiple times, each time applying the input voltage to one first conductive line; counting the number of times the output current of each second conductive line is greater than a preset current, wherein the preset current is greater than the second current and less than the first current; or, counting the number of times the output voltage of each second conductive line is greater than a preset voltage to obtain the operation result of the input data and the matrix, wherein the preset voltage is greater than the second output voltage and less than the first output voltage.

[0099] In some embodiments, the step of applying an input voltage to a plurality of first conductive lines in the storage layer based on input data and obtaining the operation result of the input data and the matrix stored in the storage cells of the storage layer based on the output current or output voltage of the second conductive lines in the storage layer includes: simultaneously applying the input voltage to a plurality of first conductive lines in the storage layer; rounding the output current of each second conductive line to a multiple of the first current to obtain the operation result of the input data and the matrix; or, rounding the output voltage of each second conductive line to a multiple of the first output voltage to obtain the operation result of the input data and the matrix.

[0100] In some embodiments, the first voltage is less than the threshold voltage of the memory cell in the first state.

[0101] In some embodiments, the method of operating the semiconductor device further includes: before applying an input voltage to a plurality of first conductive lines in the storage layer based on input data, programming the memory cells in the storage layer to a first state or a second state based on the matrix, so as to write the matrix into the plurality of memory cells.

[0102] In some embodiments, the input data includes a first bit and a second bit; the value of the first bit is different from the value of the second bit; the operation method of the semiconductor device includes: applying the first voltage to the first conductive line corresponding to the first bit and applying the second voltage to the first conductive line corresponding to the second bit; or, applying the first voltage only to the first conductive line corresponding to the first bit.

[0103] In some embodiments, the step of applying an input voltage to a plurality of first conductive lines in a storage layer based on input data and obtaining the operation result of the input data and the matrix stored in the storage cells of the storage layer based on the output current or output voltage of the second conductive line in the storage layer includes: simultaneously applying an input voltage to two first conductive lines in two storage layers sharing the second conductive line based on the input data; and obtaining the operation result of the input data and the matrix stored in the storage cells of the two storage layers based on the output current or output voltage of the second conductive line.

[0104] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0105] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0106] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor device, characterized in that, It includes at least one memory layer and peripheral circuitry coupled to the memory layer; wherein, Each of the memory layers includes a plurality of memory cells, a plurality of first conductive lines, and a plurality of second conductive lines; the memory cells are located between the first conductive lines and the second conductive lines in a first direction; a plurality of memory cells arranged along a second direction are coupled to one of the first conductive lines, and a plurality of memory cells arranged along a third direction are coupled to one of the second conductive lines; the second direction intersects the third direction and is perpendicular to the first direction; the plurality of memory cells are configured as a memory matrix; the memory cells have a first state and a second state; the threshold voltage of the memory cell in the first state is less than the threshold voltage of the memory cell in the second state and greater than the subthreshold voltage of the memory cell; The peripheral circuit is configured to: apply an input voltage to a plurality of first conductive lines in the storage layer based on input data; obtain the operation result of the input data and the matrix stored in a plurality of storage cells in the storage layer based on the output current or output voltage of the second conductive line in the storage layer; the input voltage applied to a first conductive line includes a first voltage and a second voltage; the first voltage is greater than the subthreshold voltage of the storage cell and less than the threshold voltage of the storage cell in the second state; the second voltage is less than the subthreshold voltage of the storage cell.

2. The semiconductor device according to claim 1, characterized in that, The memory cell coupled to the first conductive line to which the first voltage is applied and in the first state is configured to output a first current or a first output voltage; The memory cell coupled to the first conductive line to which the first voltage is applied and in the second state is configured to output a second current or a second output voltage; The second current is less than the first current, and the second output voltage is less than the first output voltage.

3. The semiconductor device according to claim 2, characterized in that, The peripheral circuit includes an input circuit and a counting circuit; wherein... The input circuit is connected to the first conductive line and is configured to: apply the input voltage to multiple first conductive lines in multiple steps based on the input data, with the input voltage applied to one first conductive line each time; The counting circuit is connected to the second conductive line and is configured to: count the number of times the output current of each second conductive line is greater than a preset current to obtain the operation result of the input data and the matrix, wherein the preset current is greater than the second current and less than the first current; or, count the number of times the output voltage of each second conductive line is greater than a preset voltage to obtain the operation result of the input data and the matrix, wherein the preset voltage is greater than the second output voltage and less than the first output voltage.

4. The semiconductor device according to claim 2, characterized in that, The peripheral circuitry includes an input circuit and a computing circuit; wherein... The input circuit is connected to the first conductive line and is configured to simultaneously apply the input voltage to multiple first conductive lines in the storage layer based on the input data; The computing circuit is connected to the second conductive line and is configured to: round the output current of each second conductive line to a multiple of the first current to obtain the operation result of the input data and the matrix; or, round the output voltage of each second conductive line to a multiple of the first output voltage to obtain the operation result of the input data and the matrix.

5. The semiconductor device according to any one of claims 2 to 4, characterized in that, The first voltage is less than the threshold voltage of the memory cell in the first state.

6. The semiconductor device according to claim 1, characterized in that, The peripheral circuit is configured as follows: Before applying an input voltage to the plurality of first conductive lines in the storage layer based on the input data, the storage cells in the storage layer are programmed to either the first state or the second state based on the matrix, so as to write the matrix into the plurality of storage cells.

7. The semiconductor device according to claim 1, characterized in that, The input data includes a first bit and a second bit, and the value of the first bit is different from the value of the second bit. The input circuit is configured to: apply the first voltage to the first conductive line corresponding to the first bit, and apply the second voltage to the first conductive line corresponding to the second bit; or, The input circuit is configured to apply the first voltage only to the first conductive line corresponding to the first bit.

8. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes two storage layers stacked along the first direction and sharing the second conductive line; the peripheral circuitry is configured as follows: Simultaneously, based on the input data, an input voltage is applied to the first conductive line of the two storage layers; The result of the operation between the input data and the matrix stored in multiple storage cells in the two storage layers is obtained based on the output current or output voltage of the second conductive line.

9. The semiconductor device according to claim 1, characterized in that, The storage unit includes a gating element and a phase change element stacked along the first direction; the gating element is located between the first conductive line and the phase change element.

10. A semiconductor system, characterized in that, include: At least one semiconductor device as described in any one of claims 1 to 9; A controller, coupled to at least one of the semiconductor devices and configured to send input data to the semiconductor devices and receive computation results from the semiconductor devices.

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