High-precision delay adjusting circuit and method suitable for FPGA (Field Programmable Gate Array)

Abstract

The invention relates to the technical field of signal processing, and discloses a high-precision delay adjusting circuit suitable for an FPGA, the high-precision delay adjusting circuit comprises a PARTA and a PARTB, the PARTA is used for coarsely adjusting the delay difference between signals, the PARTB is used for finely adjusting the delay difference between the signals, the signals are input through the input end of the PARTA, output through the output end of the PARTA, input through the input end of the PARTB and output through the output end of the PARTB, and the PARTA is used for coarsely adjusting the delay difference between the signals. The PARTA and the PARTB are both of a vertically symmetrical structure, and the PARTA comprises a first time delay module DELAY, a second time delay module DELAY, a first selection controller MUX, a second selection controller MUX and a time delay judgment module. According to the high-precision delay adjusting circuit and method suitable for the FPGA, by flexibly adjusting and selecting signals, the output of the delay circuit can be accurately controlled, different numbers of delay modules can be selected, delay effects of different degrees can be achieved, various requirements and application scenes can be met, the design endows the circuit with high customizability and flexibility, and the high-precision delay adjusting circuit is suitable for the FPGA. The method is suitable for various situations requiring rapid and accurate delay adjustment.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing, and in particular to a high-precision delay adjustment circuit and method suitable for FPGA. Background Art

[0002] In electronic systems and communication systems, signal transmission usually needs to go through multiple links, including different circuits and transmission media. These links inevitably introduce certain transmission delays. Due to the influence of factors such as the propagation speed of electronic signals, the response time of circuit elements, and the transmission medium, these delays may affect the timing requirements of the system. In order to ensure the timing correctness of the system, these transmission delays need to be adjusted and managed, which includes estimating and optimizing the delays in the design phase, as well as compensating and adjusting the delays during system operation to ensure that the signal arrival time meets the timing requirements of the system. Therefore, the adjustment and management of transmission delays is an important link in the design of electronic systems and communication systems, and has a direct impact on the performance and stability of the system. Understanding and considering the characteristics of signal transmission is a crucial part of the design and implementation of electronic systems and communication systems, which directly affects the timing correctness, data integrity, and performance stability of the system.

[0003] Due to the flexibility and programmability of FPGA modules, they have become a key technology platform for realizing fast customization, high-performance communication systems and equipment. They have occupied an increasingly important strategic position in the development of the electronic communication industry. In terms of communication protocol implementation, FPGA modules provide a flexible hardware implementation platform that can quickly implement various communication protocols and standards, such as Ethernet, Wi-Fi, Bluetooth, etc., and in terms of signal processing and modulation and demodulation, FPGA modules can be used for high-speed signal processing and digital signal modulation and demodulation, including frequency filtering, signal modulation, demodulation, channel coding, etc. The above functions will be negatively affected by the inevitable electrical signal delay. Therefore, with the help of high-precision delay adjustment circuits, we can greatly optimize the performance and stability of the system. Through appropriate delay adjustment, we can reduce signal distortion and noise, and improve the signal quality and transmission efficiency of the system. Therefore, a high-precision delay adjustment circuit and method suitable for FPGA are proposed to solve the above problems. Summary of the invention

[0004] In view of the deficiencies in the prior art, the present invention provides a high-precision delay adjustment circuit and method suitable for FPGA, which has the advantages of quickly compensating for the delay error of electrical signals and achieving picosecond level accuracy, thus solving the problems mentioned in the above background technology.

[0005] In order to realize the above-mentioned rapid compensation of the delay error of the electrical signal and achieve the purpose of picosecond level accuracy, the present invention provides the following technical solutions: a high-precision delay adjustment circuit suitable for FPGA, comprising region PART_A and region PART_B; Area PART_A is used to roughly adjust the delay difference between signals, and area PART_B is used to finely adjust the delay difference between signals. The signal is input from the input end of area PART_A and output from the output end of area PART_A, and input from the input end of area PART_B and output from the output end of area PART_B. The region PART_A and the region PART_B are both vertically symmetrical structures.

[0006] Preferably, the area PART_A includes a first delay module DELAY, a second delay module DELAY, a first selection controller MUX, a second selection controller MUX, and a delay judgment module, and the signals A1 and A2 enter from the input end of the first selection controller MUX; The input end of the first selection controller MUX is electrically connected to the output end of the second delay module DELAY, the output end of the first selection controller MUX is electrically connected to the input end of the first delay module DELAY, the output end of the first delay module DELAY is electrically connected to the input end of the second selection controller MUX, the output end of the second selection controller MUX is electrically connected to the input end of the delay judgment module, the input end of the second selection controller MUX is electrically connected to the output end of the delay judgment module, the output end of the delay judgment module is electrically connected to the input end of the second delay module DELAY, the output end of the coarse adjustment controller is electrically connected to the input end of the first selection controller MUX and the second selection controller MUX, and the input end of the coarse adjustment controller is electrically connected to the output end of the delay judgment module; The first selection controller MUX is used to select whether the signal entering the delay judgment module is an adjusted signal, the first delay module DELAY and the second delay module DELAY are both used to receive signals and delay signals, the second selection controller MUX is used to select different delay paths, the delay judgment module is used to accurately measure the delay difference between signals, and the coarse adjustment controller is used to control the first selection controller MUX and the second selection controller MUX to select a suitable path.

[0007] Preferably, the area PART_B includes a PDL module, a third delay module DELAY and a fine-tuning controller; The input end of the third delay module DELAY is electrically connected to the output end of the delay judgment module, the output end of the third delay module DELAY is electrically connected to the input end of the PDL module, the input end of the fine adjustment controller is electrically connected to the output end of the delay judgment module, and the output end of the fine adjustment controller is electrically connected to the input end of the PDL module; The third delay module DELAY is used to delay the signal, the PDL module is used to fine-tune the signal, and the fine-tuning controller is used to select a suitable fine-tuning path.

[0008] Preferably, the number of the first delay modules DELAY is n, where n is a positive integer, and the number of the PDL modules is 2n, where n is a positive integer.

[0009] Preferably, a high-precision delay adjustment method suitable for FPGA comprises the following steps: S1: Signal A1 and signal A2 enter the area PART_A through the input end of the first selection controller MUX. When signal A1 and signal A2 enter the area PART_A for the first time, the area PART_A is in a default state, and signal A1 and signal A2 do not pass through the first delay module DELAY, but are directly output to the delay judgment module; S2: The delay judgment module judges and calculates the delay difference P between signal A1 and signal A2. , if the delay difference P < the delay Q of the single first delay module DELAY, then the signal A1 and the signal A2 are output to the area PART_B, and the process goes to step S5; if the delay difference P > the delay Q of the single first delay module DELAY, then the signal A1 and the signal A2 are output to the second delay module DELAY, and the process goes to step S3; S3: Calculate the delay difference P / delay Q=R...T, where R is the quotient and T is the remainder, and determine whether the quotient R is greater than the total number U of the first delay modules DELAY. If so, adjust the delay Q of the U first delay modules DELAY and enter step S5. If not, enter step S4. S4: Select R first delay modules DELAY for delay according to the value of the quotient R, and output the signal A1 and the signal A2 to the area PART_B, and proceed to step S6; S5: The delay determination module determines and calculates the delay difference P between the signal A1 and the signal A2. , calculate the delay difference P / delay Q=R……T, where R is the quotient and T is the remainder, and determine whether the quotient R is greater than the total number U of the first delay modules DELAY. If so, adjust the delay Q of U first delay modules DELAY and loop step S5. If not, go to step S4; S6: The fine-tuning controller selects a suitable delay path according to the specific value of the remainder T to complete high-precision adjustment of the signal.

[0010] Compared with the prior art, the present invention provides a high-precision delay adjustment circuit and method suitable for FPGA, which has the following beneficial effects: The high-precision delay adjustment circuit and method suitable for FPGA can accurately control the output of the delay circuit by flexibly adjusting the selection signal. By selecting different numbers of delay modules, different degrees of delay effects can be achieved to meet various needs and application scenarios. This design gives the circuit high customizability and flexibility, and is suitable for various scenarios that require fast and accurate delay adjustment. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A high-precision delay adjustment circuit structure diagram suitable for FPGA proposed by the present invention; Figure 2 This is a detailed diagram of the internal structure of a programmable delay line of a high-precision delay adjustment circuit suitable for FPGA proposed by the present invention; Figure 3 This is a diagram of an instantiation of an input LUT of a PDL module in a high-precision delay adjustment circuit suitable for FPGA proposed by the present invention. DETAILED DESCRIPTION

[0012] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0013] See also Figure 1-3 , a high-precision delay adjustment circuit suitable for FPGA, including area PART_A and area PART_B; Area PART_A is used to roughly adjust the delay difference between signals, and area PART_B is used to finely adjust the delay difference between signals. The signal is input from the input end of area PART_A and output from the output end of area PART_A. The signal is input from the input end of area PART_B and output from the output end of area PART_B. Both area PART_A and area PART_B have upper and lower symmetrical structures.

[0014] Area PART_A includes a first delay module DELAY, a second delay module DELAY, a first selection controller MUX, a second selection controller MUX, and a delay judgment module. Signals A1 and A2 enter from the input end of the first selection controller MUX. The delay range that the counter method can measure is very large, but the accuracy is low and cannot reach the picosecond level. The TDL delay measurement method has extremely high accuracy, but the measured delay range is limited. Therefore, this delay judgment module uses the counter method and the TDL delay measurement method to work together to achieve a large range and high-precision delay measurement.

[0015] In this delay judgment module, the counter measurement and TDL measurement modules are turned on at the same time. When the upper limit of the TDL module is exceeded, the delay difference measured by the counter module will be used. When the upper limit of the TDL module is not exceeded, the delay difference measured by the counter module will be used.

[0016] Two measurement methods are introduced below.

[0017] The counter method is a method for determining signal delay by recording the number of clock cycles that a signal passes through during propagation. This method is simple and easy to implement and is widely used in digital systems, especially for measuring longer signal delays. In practical applications, the counter runs at a high-speed clock frequency. The delay of the signal in the system is calculated by starting and stopping the counter at the arrival module time points of the two signal transmissions. The core idea of ​​the counter method is to use a clock source to quantify time and express the transmission time of the signal in the number of clock cycles. When the signal passes through the circuit, the counter starts counting until the signal reaches the target position and stops counting. The signal delay can be calculated by multiplying the clock frequency by the counter value.

[0018] The basic workflow of the counter method: 1. Initialize the counter: Before the signal transmission starts, clear the counter and keep it in standby state, waiting for the trigger of signal transmission.

[0019] 2. Start counting: When the rising edge or falling edge of any of the two signal lines is detected, the trigger circuit starts the counter, and the counter starts counting at the clock frequency.

[0020] 3. Stop counting: When the rising edge or falling edge of another signal line is detected, the trigger circuit acts again and stops the counter. At this time, the value recorded by the counter represents the number of clock cycles N experienced during the signal transmission process.

[0021] 4. Calculate the delay: Based on the recorded counter value N and clock frequency f, the signal delay t can be calculated, and the relationship is t=N / f.

[0022] The TDL delay measurement method allows two signals to pass through many delay lines with known delay times connected in series, and then compares the delay difference between the two signals when capturing their arrival times. This method processes the two signals through the same path and can accurately measure the relative delay difference between the two signals.

[0023] 1. The signal input that arrives at the delay judgment module first: The faster signal will enter the TDL delay measurement module first and begin to pass through the preset known multi-segment delay line; 2. Through the delay line: The delay line is composed of a series of delay lines with known delay times, for example, the delay of each delay line is 50ps. The faster signal will pass through many such delay line segments with known delay times and continue to transmit until the slower signal arrives; 3. The signal input that arrives at the delay judgment module later: After a period of time, the slower signal also arrives at the delay judgment module; 4. Counter counts and calculates the difference: When the slower signal reaches the delay judgment module, the TDL delay measurement module will latch the position of the last delay line that the faster signal passes through, and then the counter will start counting until it reaches the latched delay line position. Then the counter value is multiplied by the delay of a single delay line to get the delay error between the two signals.

[0024] If the slower signal still does not reach the delay measurement module until the faster signal has traveled through all the delay line groups with known delays, it is considered that the current sampling has exceeded the measurement upper limit of TDL, the counter value is cleared, and the next measurement is awaited.

[0025] The input end of the first selection controller MUX is electrically connected to the output end of the second delay module DELAY, the output end of the first selection controller MUX is electrically connected to the input end of the first delay module DELAY, the output end of the first delay module DELAY is electrically connected to the input end of the second selection controller MUX, the output end of the second selection controller MUX is electrically connected to the input end of the delay judgment module, the input end of the second selection controller MUX is electrically connected to the output end of the delay judgment module, the output end of the delay judgment module is electrically connected to the input end of the second delay module DELAY, the output end of the coarse adjustment controller is electrically connected to the input end of the first selection controller MUX and the second selection controller MUX, and the input end of the coarse adjustment controller is electrically connected to the output end of the delay judgment module; The first selection controller MUX is used to select whether the signal entering the delay judgment module is an adjusted signal, the first delay module DELAY and the second delay module DELAY are both used to receive signals and delay signals, the second selection controller MUX is used to select different delay paths, the delay judgment module is used to accurately measure the delay difference between signals, and the coarse adjustment controller is used to control the first selection controller MUX and the second selection controller MUX to select a suitable path.

[0026] Area PART_B includes a PDL module, a third delay module DELAY and a fine-tuning controller, and the PDL module is a programmable delay line; The fine-tuning controller can accurately identify the impact of different output signals on the upstream and downstream delay paths, and thus quickly adjust the delay matching of the two paths based on the feedback from the delay measurement module.

[0027] Taking fine tuning as an example, the PDL module has different delay characteristics under different input conditions. For example, when the input of the PDL module is 000, the delay is 1000ps; when the input is 001, the delay increases to 1050ps; when the input is 002, the delay is 1100ps, and so on, when the input is 111, the delay reaches 1350ps. Based on this information, it can be deduced that the delay step between the two PDL modules is 50ps, the maximum delay difference is 350ps, and the selection bits of a single PDL module can be set according to the selection bits. The more selection bits, the more delay paths can be selected.

[0028] Assuming two input signals A1 and A2, the arrival time of signal A1 is 12.65ns faster than that of signal A2, that is, 12650ps. Based on this difference, the fine-tuning controller determines that the path of signal A1 should be extended by 12650ps. By calculating 12650 / 350=36 remainder 50, 12650ps is equivalent to the delay adjustment of 37 PDL modules. Therefore, in order to achieve the synchronization of signals A1 and A2, the inputs of 36 PDL modules in the PDL module path of signal A1 can be set to 111, the input of the 37th PDL module can be set to 001, and the inputs of the remaining PDL modules can be set to 000; while the PDL module path of signal A2 is all 000. This configuration can effectively achieve the synchronization of the two signals.

[0029] The input end of the third delay module DELAY is electrically connected to the output end of the delay judgment module, the output end of the third delay module DELAY is electrically connected to the input end of the PDL module, the input end of the fine adjustment controller is electrically connected to the output end of the delay judgment module, and the output end of the fine adjustment controller is electrically connected to the input end of the PDL module; The third delay module DELAY is used to delay the signal, the PDL module is used to fine-tune the signal, and the fine-tuning controller is used to select a suitable fine-tuning path.

[0030] The number of the first delay module DELAY is n, where n is a positive integer, and the number of the PDL module is 2n, where n is a positive integer. To ensure the consistency between the delayed signal and the original signal, the number of times the PDL is used must be an even number, so that the delayed signal and the original signal only differ in time.

[0031] The length of the signal reaching each selector is different, so the delay is also different. According to the change of the selection bit, the input signal will pass through different delay paths and achieve different degrees of delay. By adjusting the control signal value of the PDL module, the delay characteristics of the circuit can be flexibly adjusted.

[0032] Although a single PDL module may produce nanosecond delays through the gate structure, the delay difference of the non-gate circuit will be completely offset because the circuit structure is completely symmetrical in the up and down directions, and only the delay difference caused by the change of the control signal is retained. Therefore, different PDL modules can achieve different delay effects. With this method, the module can achieve delay differences accurate to the picosecond level to meet the strict requirements for high-precision delay adjustment of electrical signals.

[0033] A high-precision delay adjustment method suitable for FPGA includes the following steps: S1: Signal A1 and signal A2 enter the area PART_A through the input end of the first selection controller MUX. When signal A1 and signal A2 enter the area PART_A for the first time, the area PART_A is in a default state, and signal A1 and signal A2 do not pass through the first delay module DELAY, but are directly output to the delay judgment module; S2: The delay judgment module judges and calculates the delay difference P between signal A1 and signal A2. , if the delay difference P < the delay Q of the single first delay module DELAY, then the signal A1 and the signal A2 are output to the area PART_B, and the process goes to step S5; if the delay difference P > the delay Q of the single first delay module DELAY, then the signal A1 and the signal A2 are output to the second delay module DELAY, and the process goes to step S3; S3: Calculate the delay difference P / delay Q=R...T, where R is the quotient and T is the remainder, and determine whether the quotient R is greater than the total number U of the first delay modules DELAY. If so, adjust the delay Q of the U first delay modules DELAY and enter step S5. If not, enter step S4. S4: Select R first delay modules DELAY for delay according to the value of the quotient R, and output the signal A1 and the signal A2 to the area PART_B, and proceed to step S6; S5: The delay determination module determines and calculates the delay difference P between the signal A1 and the signal A2. , calculate the delay difference P / delay Q=R……T, where R is the quotient and T is the remainder, and determine whether the quotient R is greater than the total number U of the first delay modules DELAY. If so, adjust the delay Q of U first delay modules DELAY and loop step S5. If not, go to step S4; S6: The fine-tuning controller selects a suitable delay path according to the specific value of the remainder T to complete high-precision adjustment of the signal.

[0034] exist Figure 3 In the circuit, the H1 signal is used as the input to control each selector in the first row, the H2 signal is used to control each selector in the second row, and so on. When the H1 signal enters the circuit, it enters each selector in the first row through the wire, and these selectors will send out opposite potential signals according to the value of the H1 signal.

[0035] Specifically, when H1 is "1", the selector outputs "0", and when H1 is "0", the selector outputs "1", showing the effect of an inverter.

[0036] The H2, H3, and Hn signals are used to determine the direction of the electrical signal. For example, when the H2 signal is "1", all selectors in the second row will output the signal from the port with the selection bit of 1, and so on. After multiple levels of selection, until the last level, the final delayed signal is output. In short, all selection signals are used to determine which selector in the first row will output the final delayed signal.

[0037] As can be seen from the figure, the line length from H1 to each selector is different, so the delay generated is also different. According to the change of the selection bit, the input signal will pass through different delay paths and achieve different degrees of delay. By adjusting the control signal value of the PDL module, the delay characteristics of the circuit can be flexibly adjusted.

[0038] In summary, the high-precision delay adjustment circuit and method suitable for FPGA can accurately control the output of the delay circuit by flexibly adjusting the selection signal. By selecting different numbers of delay units, different degrees of delay effects can be achieved to meet various needs and application scenarios. This design gives the circuit high customizability and flexibility, and is suitable for various scenarios that require fast and accurate delay adjustment.

[0039] It should be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0040] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A high-precision delay adjustment circuit suitable for FPGA, characterized in that: Includes area PART_A and area PART_B; Area PART_A is used to roughly adjust the delay difference between signals, and area PART_B is used to finely adjust the delay difference between signals. The signal is input from the input end of area PART_A and output from the output end of area PART_A, and input from the input end of area PART_B and output from the output end of area PART_B. The area PART_A and the area PART_B are both vertically symmetrical structures; The area PART_A includes a first delay module DELAY, a second delay module DELAY, a first selection controller MUX, a second selection controller MUX, a coarse adjustment controller and a delay judgment module, and signals A1 and A2 enter from the input end of the first selection controller MUX; The input end of the first selection controller MUX is electrically connected to the output end of the second delay module DELAY, the output end of the first selection controller MUX is electrically connected to the input end of the first delay module DELAY, the output end of the first delay module DELAY is electrically connected to the input end of the second selection controller MUX, the output end of the second selection controller MUX is electrically connected to the input end of the delay judgment module, the input end of the second selection controller MUX is electrically connected to the output end of the delay judgment module, the output end of the delay judgment module is electrically connected to the input end of the second delay module DELAY, the output end of the coarse adjustment controller is electrically connected to the input end of the first selection controller MUX and the second selection controller MUX, and the input end of the coarse adjustment controller is electrically connected to the output end of the delay judgment module; The first selection controller MUX is used to select whether the signal entering the delay judgment module is an adjusted signal, the first delay module DELAY and the second delay module DELAY are both used to receive signals and delay signals, the second selection controller MUX is used to select different delay paths, the delay judgment module is used to accurately measure the delay difference between signals, and the coarse adjustment controller is used to control the first selection controller MUX and the second selection controller MUX to select a suitable path.

2. The high-precision delay adjustment circuit and method suitable for FPGA according to claim 1, characterized in that: The area PART_B includes a PDL module, a third delay module DELAY and a fine-tuning controller; The input end of the third delay module DELAY is electrically connected to the output end of the delay judgment module, the output end of the third delay module DELAY is electrically connected to the input end of the PDL module, the input end of the fine adjustment controller is electrically connected to the output end of the delay judgment module, and the output end of the fine adjustment controller is electrically connected to the input end of the PDL module; The third delay module DELAY is used to delay the signal, the PDL module is used to fine-tune the signal, and the fine-tuning controller is used to select a suitable fine-tuning path.

3. A high-precision delay adjustment method suitable for FPGA according to any one of claims 1-2, characterized in that: The following steps are involved: S1: Signal A1 and signal A2 enter the area PART_A through the input end of the first selection controller MUX. When signal A1 and signal A2 enter the area PART_A for the first time, the area PART_A is in a default state, and signal A1 and signal A2 do not pass through the first delay module DELAY, but are directly output to the delay judgment module; S2: The delay judgment module judges and calculates the delay difference P between signal A1 and signal A2. , if the delay difference P < the delay Q of the single first delay module DELAY, then the signal A1 and the signal A2 are output to the area PART_B, and the process goes to step S5; if the delay difference P > the delay Q of the single first delay module DELAY, then the signal A1 and the signal A2 are output to the second delay module DELAY, and the process goes to step S3; S3: Calculate the delay difference P / delay Q=R...T, where R is the quotient and T is the remainder, and determine whether the quotient R is greater than the total number U of the first delay modules DELAY. If so, adjust the delay Q of the U first delay modules DELAY and enter step S5. If not, enter step S4. S4: Select R first delay modules DELAY for delay according to the value of the quotient R, and output the signal A1 and the signal A2 to the area PART_B, and proceed to step S6; S5: The delay determination module determines and calculates the delay difference P between the signal A1 and the signal A2. , calculate the delay difference P / delay Q=R……T, where R is the quotient and T is the remainder, and determine whether the quotient R is greater than the total number U of the first delay modules DELAY. If so, adjust the delay Q of U first delay modules DELAY and loop step S5. If not, go to step S4; S6: The fine-tuning controller selects a suitable delay path according to the specific value of the remainder T to complete high-precision adjustment of the signal.

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