ADC input circuit, ADC and GPIO pin multiplexing circuit and chip
By designing gate voltage bootstrap switching circuit and gate clamp circuit in the SOC chip, combining the ADC enable control circuit and sampling clock gate circuit, the overvoltage and input range problems of ADC module in the high voltage mode of the GPIO module are solved, and high voltage is achieved The guarantee of resistance and linearity reduces power consumption and area consumption.
Patent Information
- Application Number
- CN202411343278.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-25
- Publication Date
- 2025-01-03
AI Technical Summary
When the GPIO module in the SOC chip works in high voltage mode, the ADC module has a risk of overvoltage, and it is difficult to ensure the input range and linearity of the ADC, and it is necessary to save power consumption and area.
The design includes gate voltage bootstrap switching circuit, gate clamping circuit and ADC enable control circuit. The gate voltage bootstrap switching circuit and gate clamping circuit enable the ADC module to avoid overvoltage in high voltage mode, and enable it through ADC. The control circuit and the sampling clock gate circuit ensure the linearity of the ADC input range.
It realizes the guarantee of the voltage withstandability and input range of the ADC module in high voltage mode, reduces power consumption and area occupation, and improves the flatness and linearity of the ADC input circuit.
Smart Images
Figure CN119254229A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of chip technology, and in particular, to an ADC input circuit, an ADC and GPIO pin multiplexing circuit using the ADC input circuit, and a chip using the ADC and GPIO pin multiplexing circuit. Background Art
[0002] Chips such as SOC have complex functions and many pins. In order to save area and pin resources, it is generally considered to reuse the pins of the built-in ADC module and the GPIO module of the chip. However, this multiplexing method may have the following scenarios: when the GPIO module works in high-voltage mode, the ADC module does not work, and the ADC module will be at risk of overvoltage. Therefore, considering this scenario, three issues need to be considered during design: the first is to solve the overvoltage problem at the ADC input switch (or channel selection switch) when the GPIO works in high-voltage mode; the second is to ensure the input range and linearity of the ADC when it is working; the third is not to increase excessive power consumption and area.
[0003] Therefore, a more optimized circuit structure design needs to be considered. Summary of the invention
[0004] The first object of the present invention is to provide an ADC input circuit that can withstand high voltage and ensure the input range and linearity of the ADC module.
[0005] The second object of the present invention is to provide an ADC and GPIO pin multiplexing circuit that can withstand high voltage and ensure the input range and linearity of the ADC module.
[0006] The third object of the present invention is to provide a chip that can withstand high voltage and ensure the input range and linearity of the ADC module.
[0007] In order to achieve the above-mentioned first purpose, the ADC input circuit provided by the present invention includes a gate voltage bootstrap switch circuit, a gate terminal clamp circuit and an ADC enable control circuit; the gate voltage bootstrap switch circuit includes a sampling input terminal, a sampling output terminal, a sampling NMOS tube and a bootstrap circuit, the output terminal of the bootstrap circuit is electrically connected to the gate of the sampling NMOS tube, the drain of the sampling NMOS tube is electrically connected to the sampling input terminal, and the source of the sampling NMOS tube is electrically connected to the sampling output terminal; the gate terminal clamp circuit includes a first clamp circuit and a first control switch, the output terminal of the first clamp circuit is electrically connected to the gate of the sampling NMOS tube through the first control switch, the control terminal of the first control switch is electrically connected to the ADC enable control circuit, and the ADC enable control circuit is used to send an inverted signal of an ADC enable signal to the control terminal of the first control switch.
[0008] It can be seen from the above scheme that the ADC input circuit of the present invention can set a gate voltage bootstrap switch circuit and a gate terminal clamp circuit so that when the GPIO module works in a high-voltage mode, the gate terminal clamp circuit clamps the gate terminal of the sampling NMOS tube in the gate voltage bootstrap switch circuit to a threshold voltage. Even if the sampling input terminal is a high voltage, the input terminal of the ADC module will be pulled below this voltage, thereby ensuring that the voltage at the sampling output terminal is less than the withstand voltage value of the input switch of the ADC module, so that high voltage resistance can be achieved.
[0009] In a further scheme, the bootstrap circuit includes a first NMOS tube, a second NMOS tube, a first PMOS tube, a third NMOS tube, a second PMOS tube, a third PMOS tube, a fourth NMOS tube, a fifth NMOS tube and a bootstrap capacitor, the source of the first NMOS tube is grounded, the drain of the first NMOS tube is electrically connected to the source of the third NMOS tube, the gate of the first NMOS tube is electrically connected to the first clock terminal, the source of the second NMOS tube is electrically connected to the path between the drain of the first NMOS tube and the source of the third NMOS tube, the drain of the second NMOS tube is electrically connected to the drain of the first PMOS tube, the source of the first PMOS tube is electrically connected to the power supply terminal, the gate of the second NMOS tube and the gate of the first PMOS tube are both electrically connected to the second clock terminal, the signals of the first clock terminal and the second clock terminal are opposite, and the third NMOS tube The drain of the second PMOS tube is electrically connected to the drain of the sampling NMOS tube, the source of the second PMOS tube is electrically connected to the power supply terminal, the drain of the second PMOS tube is electrically connected to the first end of the bootstrap capacitor, the second end of the bootstrap capacitor is electrically connected to the drain of the first NMOS tube, the first end of the bootstrap capacitor is also electrically connected to the source of the third PMOS tube, the gate of the third PMOS tube is electrically connected to the path between the drain of the second NMOS tube and the drain of the first PMOS tube, the gate of the third NMOS tube, the gate of the sampling NMOS tube, the gate of the second PMOS tube and the drain of the fourth NMOS tube are all electrically connected to the drain of the third PMOS tube, the gate of the fourth NMOS tube is electrically connected to the power supply terminal, the source of the fourth NMOS tube is electrically connected to the drain of the fifth NMOS tube, the gate of the fifth NMOS tube is electrically connected to the first clock terminal, and the source of the fifth NMOS tube is grounded.
[0010] It can be seen that by setting up a bootstrap circuit, the voltage across the gate and source of the sampling NMOS tube will not change suddenly, so that the flatness of the on-resistance within the input range is improved and the harmonic distortion introduced by the sampling NMOS tube is reduced.
[0011] In a further solution, the ADC enable control circuit includes an ADC enable terminal, a first inverter and an ADC enable inverting terminal, the ADC enable terminal is electrically connected to the input terminal of the first inverter, the output terminal of the first inverter is electrically connected to the ADC enable inverting terminal; the control terminal of the first control switch is electrically connected to the ADC enable inverting terminal.
[0012] It can be seen that by setting the ADC enable control circuit to control the on and off of the first control switch, it is convenient to control the gate clamp circuit. When the GPIO module is working, the ADC enable inverting terminal is high level, the gate clamp circuit is turned on, and the gate voltage of the sampling NMOS tube is clamped to a certain voltage value. When the ADC module is working, the ADC enable inverting terminal is low level, the gate clamp circuit is turned off, and the normal operation of the gate voltage bootstrap switch circuit is not affected.
[0013] In a further embodiment, the ADC input circuit further includes a sampling clock gate circuit, which includes a clock input terminal, a second inverter, a NAND gate, a third inverter and a fourth inverter, wherein the input terminal of the second inverter is electrically connected to the clock input terminal, the output terminal of the second inverter is electrically connected to the first input terminal of the NAND gate, the second input terminal of the NAND gate is electrically connected to the ADC enable terminal, the output terminal of the NAND gate is electrically connected to the input terminal of the third inverter, the output terminal of the third inverter is electrically connected to the input terminal of the fourth inverter, the output terminal of the fourth inverter is electrically connected to the second clock terminal, and the first clock terminal is electrically connected to the output terminal of the third inverter.
[0014] It can be seen that by setting a sampling clock gate circuit to control the gate voltage bootstrap switch circuit, when the ADC module is working, the gate voltage bootstrap switch circuit is controlled by the ADC sampling clock, ensuring that the ADC input range is not limited and maintaining a high linearity.
[0015] In a further scheme, the ADC input circuit also includes a bootstrap capacitor mode switching module, the bootstrap capacitor mode switching module includes a second clamping circuit, a second control switch and a third control switch, the first end of the third control switch is electrically connected to the second end of the bootstrap capacitor, the second end of the third control switch is electrically connected to the drain of the first NMOS tube, the control end of the third control switch is electrically connected to the ADC enable end, the output end of the second clamping circuit is electrically connected to the first end of the second control switch, the second end of the second control switch is electrically connected to the path between the first end of the third control switch and the second end of the bootstrap capacitor, and the control end of the second control switch is electrically connected to the ADC enable inverting end.
[0016] It can be seen that by setting the bootstrap capacitor mode switching module, when the GPIO module is working, due to the presence of the bootstrap capacitor, when the GPIO input or output signal jumps back and forth between 0 and high voltage, the signal will be transmitted to the gate of the sampling NMOS tube through the third NMOS tube, the bootstrap capacitor and the third PMOS tube. If the effect of the first clamping circuit is relatively weak, the voltage of the gate of the sampling NMOS tube will also jump, which may make the voltage of the sampling output end close to the high voltage, resulting in an overvoltage problem in the input switch of the ADC module. Therefore, for the sake of insurance, the third control switch is used to disconnect the connection between the lower end of the bootstrap capacitor and the source of the third NMOS tube, and the second control switch is used to pull the second end of the bootstrap capacitor to the second clamping circuit to disconnect this coupling path, so as to ensure that the flip of the GPIO module input or output will not affect the gate of the sampling NMOS tube. When the ADC module is working, the second control switch is disconnected and the third control switch is turned on. At this time, the gate voltage bootstrap switch circuit works, thereby ensuring the normal operation of the ADC module.
[0017] In order to achieve the above-mentioned second purpose, the ADC and GPIO pin multiplexing circuit provided by the present invention includes IO pins, an ADC module and a GPIO module, and the ADC module and the GPIO module multiplex the IO pins; an ADC input circuit is arranged between the ADC module and the GPIO module; the ADC input circuit adopts the above-mentioned ADC input circuit; the sampling input end is electrically connected to the GPIO module, and the sampling output end is electrically connected to the input end of the ADC module.
[0018] In order to achieve the third purpose mentioned above, the chip provided by the present invention is provided with an ADC and GPIO pin multiplexing circuit, and the ADC and GPIO pin multiplexing circuit adopts the above-mentioned ADC and GPIO pin multiplexing circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 It is a circuit principle diagram of an embodiment of an ADC and GPIO pin multiplexing circuit of the present invention.
[0020] Figure 2 It is a circuit principle diagram of an ADC input circuit in an embodiment of an ADC and GPIO pin multiplexing circuit of the present invention.
[0021] The present invention is further described below in conjunction with the accompanying drawings and embodiments. DETAILED DESCRIPTION
[0022] ADC and GPIO pin multiplexing circuit implementation example:
[0023] In this embodiment, Figure 1As shown, the ADC and GPIO pin multiplexing circuit includes an IO pin 1, an ADC module 2 and a GPIO module 3. The ADC module 2 and the GPIO module 3 multiplex the IO pin 1. An ADC input circuit 4 is provided between the ADC module 2 and the GPIO module 3. The ADC module 2 and the GPIO module 3 adopt well-known circuit modules, which will not be described in detail here.
[0024] In this embodiment, the ADC input circuit 4 includes a gate voltage bootstrap switch circuit, a gate terminal clamp circuit 41 , an ADC enable control circuit 42 , a sampling clock gate circuit 43 and a bootstrap capacitor mode switching module 44 .
[0025] The gate voltage bootstrap switch circuit includes a sampling input terminal Vin, a sampling output terminal Vout, a sampling NMOS tube M5 and a bootstrap circuit, wherein the output terminal of the bootstrap circuit is electrically connected to the gate of the sampling NMOS tube M5, the drain of the sampling NMOS tube M5 is electrically connected to the sampling input terminal Vin, and the source of the sampling NMOS tube M5 is electrically connected to the sampling output terminal Vout. The sampling input terminal Vin is electrically connected to the GPIO module 3, and the sampling output terminal Vout is electrically connected to the input terminal of the ADC module 2.
[0026] In this embodiment, the bootstrap circuit includes a first NMOS transistor M1, a second NMOS transistor M2, a first PMOS transistor M3, a third NMOS transistor M4, a second PMOS transistor M6, a third PMOS transistor M7, a fourth NMOS transistor M8, a fifth NMOS transistor M9 and a bootstrap capacitor C1. The source of the first NMOS transistor M1 is grounded, the drain of the first NMOS transistor M1 is electrically connected to the source of the third NMOS transistor M4, the gate of the first NMOS transistor M1 is electrically connected to the first clock terminal clkq, the source of the second NMOS transistor M2 is electrically connected to the path between the drain of the first NMOS transistor M1 and the source of the third NMOS transistor M4, the drain of the second NMOS transistor M2 is electrically connected to the drain of the first PMOS transistor M3, the source of the first PMOS transistor M3 is electrically connected to the power supply terminal VCC, the gate of the second NMOS transistor M2 and the gate of the first PMOS transistor M3 are both electrically connected to the second clock terminal clk, and the first clock terminal clk The signal of kq is opposite to that of the second clock terminal clk, the drain of the third NMOS tube M4 is electrically connected to the drain of the sampling NMOS tube M5, the source of the second PMOS tube M6 is electrically connected to the power supply terminal VCC, the drain of the second PMOS tube M6 is electrically connected to the first end of the bootstrap capacitor C1, the second end of the bootstrap capacitor C1 is electrically connected to the drain of the first NMOS tube M1, the first end of the bootstrap capacitor C1 is also electrically connected to the source of the third PMOS tube M7, the gate of the third PMOS tube M7 is electrically connected to the path between the drain of the second NMOS tube M2 and the drain of the first PMOS tube M3, the gate of the third NMOS tube M4, the gate of the sampling NMOS tube M5, the gate of the second PMOS tube M6 and the drain of the fourth NMOS tube M8 are all electrically connected to the drain of the third PMOS tube M7, the gate of the fourth NMOS tube M8 is electrically connected to the power supply terminal VCC, the source of the fourth NMOS tube M8 is electrically connected to the drain of the fifth NMOS tube M9, the gate of the fifth NMOS tube M9 is electrically connected to the first clock terminal clk kq is electrically connected, and the source of the fifth NMOS tube M9 is grounded.
[0027] In this embodiment, the gate clamp circuit 41 includes a first clamp circuit 411 and a first control switch S1. The output end of the first clamp circuit 411 is electrically connected to the gate of the sampling NMOS tube M5 through the first control switch S1. The control end of the first control switch S1 is electrically connected to the ADC enable control circuit 42. The ADC enable control circuit 42 is used to send an inverted signal of an ADC enable signal to the control end of the first control switch S1. The first clamp circuit 411 is used to provide a threshold voltage. The first clamp circuit 411 adopts a well-known circuit and is not described in detail here.
[0028] In this embodiment, the ADC enable control circuit 42 includes an ADC enable terminal en_adc, a first inverter F1 and an ADC enable inverting terminal enb_adc, the ADC enable terminal en_adc is electrically connected to the input terminal of the first inverter F1, the output terminal of the first inverter F1 is electrically connected to the ADC enable inverting terminal enb_adc, and the control terminal of the first control switch S1 is electrically connected to the ADC enable inverting terminal enb_adc. By setting the ADC enable control circuit 42 to control the on and off of the first control switch S1, it is convenient to control the gate clamp circuit 41. When the GPIO module 3 is working, the ADC enable inverting terminal enb_adc is at a high level, the gate clamp circuit 41 is turned on, and the gate voltage of the sampling NMOS tube M5 is clamped to the threshold voltage. When the ADC module 2 is working, the ADC enable inverting terminal enb_adc is at a low level, the gate clamp circuit 41 is turned off, and the normal operation of the gate voltage bootstrap switch circuit is not affected.
[0029] In this embodiment, the sampling clock gate circuit 43 includes a clock input terminal clk_s, a second inverter F2, a NAND gate U1, a third inverter F3 and a fourth inverter F4, the input terminal of the second inverter F2 is electrically connected to the clock input terminal clk_s, the output terminal of the second inverter F2 is electrically connected to the first input terminal of the NAND gate U1, the second input terminal of the NAND gate U1 is electrically connected to the ADC enable terminal en_adc, the output terminal of the NAND gate U1 is electrically connected to the input terminal of the third inverter F3, the output terminal of the third inverter F3 is electrically connected to the input terminal of the fourth inverter F4, the output terminal of the fourth inverter F4 is electrically connected to the second clock terminal clk, and the first clock terminal clkq is electrically connected to the output terminal of the third inverter F3. By setting the sampling clock gate circuit 43 to control the gate voltage bootstrap switch circuit, when the ADC module 2 is working, the gate voltage bootstrap switch circuit is controlled by the ADC sampling clock, ensuring that the ADC input range is not limited and can maintain a high linearity.
[0030] In this embodiment, the bootstrap capacitor mode switching module 44 includes a second clamping circuit 441, a second control switch S2 and a third control switch S3, a first end of the third control switch S3 is electrically connected to the second end of the bootstrap capacitor C1, a second end of the third control switch S3 is electrically connected to the drain of the first NMOS tube M1, a control end of the third control switch S3 is electrically connected to the ADC enable end en_adc, an output end of the second clamping circuit 441 is electrically connected to the first end of the second control switch S2, a second end of the second control switch S2 is electrically connected to the path between the first end of the third control switch S3 and the second end of the bootstrap capacitor C1, and a control end of the second control switch S2 is electrically connected to the ADC enable inverting end enb_adc.
[0031] By setting the bootstrap capacitor mode switching module 44, when the GPIO module 3 is working, due to the existence of the bootstrap capacitor C1, when the input or output signal of the GPIO module 3 jumps back and forth between 0 and high voltage, the signal will be transmitted to the gate of the sampling NMOS tube M5 through the third NMOS tube M4, the bootstrap capacitor C1 and the third PMOS tube M7. If the effect of the first clamping circuit 411 is relatively weak, the voltage of the gate of the sampling NMOS tube M5 will also jump, which may make the voltage of the sampling output terminal Vout close to the high voltage, resulting in an overvoltage problem in the input switch of the ADC module 2. Therefore, the third control switch S3 is used to disconnect the connection between the lower end of the bootstrap capacitor C1 and the source of the third NMOS tube M4, and the second control switch S2 is used to pull the second end of the bootstrap capacitor C1 to the voltage of the second clamping circuit 441 to disconnect this coupling path, thereby ensuring that the input or output voltage flip of the GPIO module 3 will not affect the voltage of the gate of the sampling NMOS tube M5. When the ADC module 2 is working, the second control switch S2 is turned off and the third control switch S3 is turned on. At this time, the gate voltage bootstrap switch circuit works, thereby ensuring the normal operation of the ADC module 2.
[0032] In this embodiment, the working process of the gate voltage bootstrap switch circuit includes two processes: pre-charging and bootstrap conduction. In the pre-charging stage, clk is low level, the gate of the sampling NMOS tube M5 is grounded, and it is in the off state. The upper and lower plates of the bootstrap capacitor C1 are connected to VCC and ground respectively. After the bootstrap capacitor C1 is charged, the voltage difference between the upper and lower plates is VCC. In the bootstrap conduction stage, clk is high, the third PMOS tube M7 is turned on, and the third NMOS tube M4 and the sampling NMOS tube M5 are both in the on state. At this time, the upper and lower plates of the bootstrap capacitor C1 are respectively connected to the gate and drain of the sampling NMOS tube M5. Since the voltage at both ends of the bootstrap capacitor C1 will not change suddenly, the voltage at both ends of the gate and drain of the sampling NMOS tube M5 is always kept constant, thereby improving the flatness of the on-resistance within the input range and reducing the harmonic distortion introduced by the sampling NMOS tube M5.
[0033] As can be seen from the above, the ADC input circuit 4 of the present invention can be configured with a gate voltage bootstrap switch circuit and a gate terminal clamp circuit 41, so that when the GPIO module 3 works in a high-voltage mode, the gate terminal clamp circuit 41 clamps the gate terminal of the sampling NMOS tube M5 in the gate voltage bootstrap switch circuit to a threshold voltage, and even if the sampling input terminal Vin is a high voltage, the input terminal of the ADC module 2 will be pulled below the threshold voltage, thereby ensuring that the voltage of the sampling output terminal Vout is less than the withstand voltage value of the input switch of the ADC module 2, so that high voltage resistance can be achieved.
[0034] Chip Example:
[0035] In this embodiment, the chip is provided with an ADC and GPIO pin multiplexing circuit, and the ADC and GPIO pin multiplexing circuit adopts the ADC and GPIO pin multiplexing circuit in the above embodiment.
[0036] It should be noted that the above are only preferred embodiments of the present invention, but the design concept of the invention is not limited thereto, and any non-substantial modifications made to the present invention using this concept also fall within the protection scope of the present invention.
Claims
1. An ADC input circuit, characterized in that: It includes a gate voltage bootstrap switch circuit, a gate terminal clamp circuit and an ADC enable control circuit; The gate voltage bootstrap switch circuit comprises a sampling input terminal, a sampling output terminal, a sampling NMOS tube and a bootstrap circuit, wherein the output terminal of the bootstrap circuit is electrically connected to the gate of the sampling NMOS tube, the drain of the sampling NMOS tube is electrically connected to the sampling input terminal, and the source of the sampling NMOS tube is electrically connected to the sampling output terminal; The gate-end clamping circuit includes a first clamping circuit and a first control switch, wherein the output end of the first clamping circuit is electrically connected to the gate of the sampling NMOS tube through the first control switch, and the control end of the first control switch is electrically connected to the ADC enable control circuit, and the ADC enable control circuit is used to send an inverted signal of an ADC enable signal to the control end of the first control switch.
2. The ADC input circuit according to claim 1, characterized in that: The bootstrap circuit includes a first NMOS tube, a second NMOS tube, a first PMOS tube, a third NMOS tube, a second PMOS tube, a third PMOS tube, a fourth NMOS tube, a fifth NMOS tube and a bootstrap capacitor, the source of the first NMOS tube is grounded, the drain of the first NMOS tube is electrically connected to the source of the third NMOS tube, the gate of the first NMOS tube is electrically connected to a first clock terminal, the source of the second NMOS tube is electrically connected to a path between the drain of the first NMOS tube and the source of the third NMOS tube, the drain of the second NMOS tube is electrically connected to the drain of the first PMOS tube, the source of the first PMOS tube is electrically connected to a power supply terminal, the gate of the second NMOS tube and the gate of the first PMOS tube are both electrically connected to a second clock terminal, the signals of the first clock terminal and the second clock terminal are opposite, the drain of the third NMOS tube is electrically connected to the sampling NMOS tube, and the gate of the second NMOS tube is electrically connected to the sampling NMOS tube. The drain of the second PMOS tube is electrically connected to the first end of the bootstrap capacitor, the second end of the bootstrap capacitor is electrically connected to the drain of the first NMOS tube, the first end of the bootstrap capacitor is also electrically connected to the source of the third PMOS tube, the gate of the third PMOS tube is electrically connected to the path between the drain of the second NMOS tube and the drain of the first PMOS tube, the gate of the third NMOS tube, the gate of the sampling NMOS tube, the gate of the second PMOS tube and the drain of the fourth NMOS tube are all electrically connected to the drain of the third PMOS tube, the gate of the fourth NMOS tube is electrically connected to the power supply terminal, the source of the fourth NMOS tube is electrically connected to the drain of the fifth NMOS tube, the gate of the fifth NMOS tube is electrically connected to the first clock terminal, and the source of the fifth NMOS tube is grounded.
3. The ADC input circuit according to claim 2, characterized in that: The ADC enable control circuit comprises an ADC enable terminal, a first inverter and an ADC enable inverting terminal, wherein the ADC enable terminal is electrically connected to the input terminal of the first inverter, and the output terminal of the first inverter is electrically connected to the ADC enable inverting terminal; The control end of the first control switch is electrically connected to the ADC enable inverting end.
4. The ADC input circuit according to claim 3, characterized in that: The ADC input circuit further includes a sampling clock gate circuit, which includes a clock input terminal, a second inverter, a NAND gate, a third inverter and a fourth inverter, wherein the input terminal of the second inverter is electrically connected to the clock input terminal, the output terminal of the second inverter is electrically connected to the first input terminal of the NAND gate, the second input terminal of the NAND gate is electrically connected to the ADC enable terminal, the output terminal of the NAND gate is electrically connected to the input terminal of the third inverter, the output terminal of the third inverter is electrically connected to the input terminal of the fourth inverter, the output terminal of the fourth inverter is electrically connected to the second clock terminal, and the first clock terminal is electrically connected to the output terminal of the third inverter.
5. The ADC input circuit according to claim 4, characterized in that: The ADC input circuit also includes a bootstrap capacitor mode switching module, which includes a second clamping circuit, a second control switch and a third control switch, wherein a first end of the third control switch is electrically connected to the second end of the bootstrap capacitor, a second end of the third control switch is electrically connected to the drain of the first NMOS tube, a control end of the third control switch is electrically connected to the ADC enable end, an output end of the second clamping circuit is electrically connected to a first end of the second control switch, a second end of the second control switch is electrically connected to a path between the first end of the third control switch and the second end of the bootstrap capacitor, and a control end of the second control switch is electrically connected to the ADC enable inverting end.
6. An ADC and GPIO pin multiplexing circuit, comprising an IO pin, an ADC module and a GPIO module, wherein the ADC module and the GPIO module multiplex the IO pin; Features: An ADC input circuit is provided between the ADC module and the GPIO module; The ADC input circuit adopts the ADC input circuit according to any one of claims 1 to 5; The sampling input end is electrically connected to the GPIO module, and the sampling output end is electrically connected to the input end of the ADC module.
7. A chip, provided with an ADC and GPIO pin multiplexing circuit, characterized in that: The ADC and GPIO pin multiplexing circuit adopts the ADC and GPIO pin multiplexing circuit described in claim 6.