Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and is applied to the technical field of semiconductors. According to the invention, by changing the width of the interval between the adjacent bit line structures, the widths of the connecting pad structures formed between the different adjacent bit line structures are different in the horizontal direction, so that the positions of part of the second isolation structures are shifted, and the purpose of communicating part of the adjacent connecting pad structures is achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Dynamic random access memory (DRAM) is a type of volatile memory, including an array area consisting of multiple memory cells and a peripheral area consisting of a control circuit. Each memory cell is composed of a transistor and a capacitor electrically connected to the transistor, and the transistor controls the storage or release of the charge in the capacitor to achieve the purpose of storing data. The control circuit can address each memory cell to control the access of data to each memory cell through word lines (WL) and bit lines (BL) that span the array area and are electrically connected to each memory cell. However, due to the limitations of process technology, the existing dynamic random access memory still has many defects, and further improvements are needed to effectively enhance the performance and reliability of related memory components. Summary of the invention

[0003] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to improve the reliability and performance of the semiconductor device.

[0004] In a first aspect, in order to solve the above technical problems, the present invention provides a semiconductor device, which may at least include:

[0005] substrate;

[0006] A plurality of bit line structures, including a first bit line structure and a second bit line structure disposed on a substrate separately from each other;

[0007] A plurality of connection pad structures are arranged between adjacent bit line structures;

[0008] A plurality of isolation structures are arranged between adjacent connection pad structures, and the isolation structures include:

[0009] a first isolation structure directly contacting the first bit line structure and the connection pad structure;

[0010] The second isolation structure is located between the first bit line structure and the second bit line structure, and the bottom surface of the second isolation structure is completely covered by the connection pad structure.

[0011] Optionally, a first interval between adjacent first bit line structures may be smaller than a second interval between adjacent first bit line structures and second bit line structures.

[0012] Optionally, the connection pad structure may further include:

[0013] A first connection pad structure, disposed between adjacent first bit line structures;

[0014] The second connection pad structure is disposed between the first bit line structure and the second bit line structure, and the bottom surface of the second isolation structure is completely covered by the second connection pad structure.

[0015] Optionally, the second connection pad structure is connected to the first connection pad structure adjacent to it.

[0016] Optionally, the second isolation structure may be isolated from the first bit line structure and the second bit line structure.

[0017] Optionally, there is a first distance between adjacent first isolation structures, and there is a second distance between adjacent first isolation structures and second isolation structures, and the first distance is smaller than the second distance.

[0018] Optionally, the semiconductor device may further include:

[0019] A plurality of contact structures are arranged under the connection pad structure, and the width of the contact structure under the first connection pad structure in the horizontal direction is smaller than the width of the contact structure under the second connection pad structure in the horizontal direction.

[0020] Optionally, a width of the first bit line structure in the horizontal direction may be smaller than a width of the second bit line structure in the horizontal direction.

[0021] Optionally, the semiconductor device may further include:

[0022] The third bit line structure is located between the first bit line structure and the second bit line structure, and at least one of the connection pad structures is sandwiched between the top surface of the third bit line structure and the bottom surface of the second isolation structure.

[0023] Optionally, the third bit line structure may include a semiconductor layer and a metal layer stacked in sequence from bottom to top, and the connection pad structure is in direct contact with the metal layer.

[0024] In a second aspect, based on the same inventive concept, the present invention also provides a method for manufacturing a semiconductor device, comprising at least:

[0025] providing a substrate;

[0026] forming a plurality of bit line structures, the bit line structures including a first bit line structure and a second bit line structure disposed on a substrate spaced apart from each other;

[0027] forming a plurality of connection pad structures, wherein the connection pad structures are arranged between adjacent bit line structures;

[0028] A plurality of isolation structures are formed and arranged between adjacent connection pad structures, wherein the isolation structures include a first isolation structure directly contacting the first bit line structure and the connection pad structure, and a second isolation structure located between the first bit line structure and the second bit line structure, and the bottom surface of the second isolation structure is completely covered by the connection pad structure.

[0029] Optionally, a first interval between adjacent first bit line structures may be smaller than a second interval between adjacent first bit line structures and second bit line structures.

[0030] Optionally, the connection pad structure may include:

[0031] A first connection pad structure, disposed between adjacent first bit line structures;

[0032] The second connection pad structure is disposed between the first bit line structure and the second bit line structure, and the bottom surface of the second isolation structure is completely covered by the second connection pad structure.

[0033] Optionally, the second connection pad structure is connected to the first connection pad structure adjacent to it.

[0034] Optionally, the second isolation structure may be isolated from the first bit line structure and the second bit line structure.

[0035] Optionally, the method for manufacturing the semiconductor device may further include:

[0036] A plurality of contact structures are formed, wherein the contact structures are arranged under the connection pad structures, and the width of the contact structures under the first connection pad structures in the horizontal direction is smaller than the width of the contact structures under the second connection pad structures in the horizontal direction.

[0037] Optionally, the bit line structure may further include:

[0038] The third bit line structure is located between the first bit line structure and the second bit line structure, and at least one of the connection pad structures is sandwiched between the top surface of the third bit line structure and the bottom surface of the second isolation structure.

[0039] Optionally, the third bit line structure includes a semiconductor layer and a metal layer stacked in sequence from bottom to top, and the connection pad structure is in direct contact with the metal layer.

[0040] In the present invention, by setting the interval between the adjacent first bit line structure and the second bit line structure to be larger than the interval between the adjacent first bit line structures, the width of the connection pad structure formed between the two adjacent first bit line structures in the horizontal direction is smaller than the width of the connection pad structure formed between the adjacent first bit line structure and the second bit line structure in the horizontal direction, thereby causing the second isolation structure in the connection pad structure formed between the adjacent first bit line structure and the second bit line structure to be offset in a direction close to the second bit line structure, so as to achieve the purpose of connecting the connection pad structure between the adjacent first bit line structure and the second bit line structure to be connected with the connection pad structure adjacent to it and located between the adjacent first bit line structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present application but do not constitute a limitation to the present application. In the accompanying drawings:

[0042] Figure 1 to Figure 7 The semiconductor device provided in the first embodiment of the present invention is prepared along the Figure 6 The schematic diagram of the structure of a partial area of ​​the AA' tangent line in the top view is shown.

[0043] Figure 6 A semiconductor device provided in the first embodiment of the present invention Figure 5 A top view of the structure shown.

[0044] Figure 8 to Figure 14 The semiconductor device provided in the second embodiment of the present invention is prepared along the Fig.13 The schematic diagram of the structure of a partial area of ​​the AA' tangent line in the top view is shown.

[0045] Fig.13 A semiconductor device provided in the second embodiment of the present invention Fig.12 A top view of the structure shown.

[0046] Wherein, the accompanying drawings are marked as follows:

[0047] 100-substrate, 110-trench isolation, 120-insulating layer, 130-bit line material layer, 131-semiconductor layer, 132-barrier layer, 133-metal layer, 134-capping layer, BL-bit line structure, BL1-first bit line structure, BL2-second bit line structure, BL3-third bit line structure, SP1-first spacer, SP2-second spacer, SP3-third spacer, SP4-fourth spacer, 140-sidewall structure, 141-first sidewall, 142-second sidewall, 150-contact structure, 160-silicide layer, 170-connection pad structure, 170.1-first connection pad layer, 170.2-second connection pad layer, 171-first connection pad structure, 172-second connection pad structure, 180-isolation structure, 181-first isolation structure, 182-second isolation structure, d1-first spacing, d2-second spacing.

[0048] In the drawings, the same reference numerals are used for the same components, and the drawings are not drawn to scale. DETAILED DESCRIPTION

[0049] The semiconductor device and the method for manufacturing the same proposed by the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention can also be implemented in other ways different from those described herein, so the present invention is not limited to the specific embodiments disclosed below.

[0050] Please refer to Figure 5 and Figure 6 , Figure 6 FIG. 1 is a partial top view of a semiconductor device according to a first embodiment of the present invention. Figure 5 FIG. 1 is a diagram of a semiconductor device according to a first embodiment of the present invention. Figure 6 The semiconductor device of the present invention can be used to manufacture dynamic random access memory (DRAM). Without departing from the spirit of the present invention, the present invention can also be applied to other types of memory.

[0051] like Figure 5As shown, the semiconductor device includes a substrate 100, a plurality of bit line structures BL, a plurality of connection pad structures 170 and a plurality of isolation structures 180. The substrate 100 is any suitable substrate material known in the art, for example, it may be a silicon substrate, a silicon-containing substrate (such as SiC, SiGe) or a silicon-on-insulator substrate or a substrate composed of other suitable materials, etc., but not limited thereto. In one embodiment, a plurality of trench isolations 110 (for example, including silicon oxide) may be further provided in the substrate 100 to define a plurality of active regions (not shown) extending in the same direction (not shown) in the substrate 100. Exemplarily, the trench isolations 110 in this embodiment may be in the shape of long strips. In addition, an insulating layer 120 is further provided on the substrate 100. Specifically, the insulating layer 120 may be a single-layer structure, such as a silicon oxide layer or a silicon nitride layer, or a composite layer, such as an ONO composite layer composed of a silicon oxide layer, a silicon nitride layer and a silicon oxide layer, but not limited thereto. Exemplarily, the insulating layer 120 in this embodiment is a single-layer structure (eg, including a silicon nitride layer).

[0052] In the present embodiment, the bit line structure BL is disposed on the substrate 100, and includes a plurality of first bit line structures BL1 and a second bit line structure BL2 which are separated from each other and have different widths and intervals. Specifically, the plurality of first bit line structures BL1 are sequentially arranged along a direction parallel to the surface of the substrate 100 (hereinafter referred to as the horizontal direction), and the second bit line structure BL2 is located outside one side of the plurality of first bit line structures BL1; specifically, if the width of the first bit line structure BL1 in the horizontal direction is the first width, and the width of the second bit line structure BL2 in the horizontal direction is the second width, then the first width is smaller than the second width; if the interval between adjacent first bit line structures BL1 is the first interval SP1, and the interval between adjacent first bit line structures BL1 and second bit line structures BL2 is the second interval SP2, then the first interval SP1 is smaller than the second interval SP2. In one embodiment, the first bit line structure BL1 and the second bit line structure BL2 have the same multi-layer bit line material layer, for example, a bit line material layer 130 composed of a semiconductor layer 131, a barrier layer 132, a metal layer 133 and a cap layer 134 stacked in sequence from bottom to top. The material of the semiconductor layer 131 may include single crystal silicon (crystalline silicon), polycrystalline silicon (poly silicon), amorphous silicon (amorphous silicon), doped silicon (doped silicon), silicon germanium (SiGe), or other suitable semiconductor materials, but not limited thereto. The material of the barrier layer 132 may include metal, metal silicide or metal nitride, such as titanium (Ti), titanium nitride (TiN), tungsten silicide (WSi), cobalt silicide (CoSi), tungsten nitride (WN), but not limited thereto. The material of the metal layer 133 may include tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the above metal materials, but not limited thereto. The cap layer 134 may include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or a combination thereof, but is not limited thereto. Exemplarily, the material of the semiconductor layer 131 is polysilicon, the material of the barrier layer 132 is cobalt silicide (CoSi), the material of the metal layer 133 is tungsten (W), and the material of the cap layer 134 is silicon nitride (SiN).

[0053] In addition, the sidewalls of the first bit line structure BL1 and the second bit line structure BL2 in this embodiment may also be provided with a sidewall structure 140. The sidewall structure 140 may also have a multi-layer structure, for example Figure 5The first sidewall 141 and the second sidewall 142 are stacked in sequence in the horizontal direction, and the first sidewall 141 is in direct contact with the sidewall of the first bit line structure BL1 or the second bit line structure BL2. Specifically, the first sidewall 141 and the second sidewall 134 may respectively include dielectric materials, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or a combination of the above materials, but not limited thereto. Exemplarily, the material of the first sidewall 141 is silicon oxide (SiO2), and the material of the second sidewall 142 is silicon nitride (SiN).

[0054] Continue to refer to Figure 5 As shown, the semiconductor device in this embodiment may further include a plurality of contact structures 150 and a silicide layer 160. A contact structure 150 and a silicide layer 160 located on the contact structure 150 are respectively formed in the first interval SP1 between the adjacent first bit line structures BL1 and in the second interval SP2 between the first bit line structure BL1 and the second bit line structure BL2. The two sides of the contact structure 150 are separated from the bit line structure BL by the sidewall structure 140 without direct contact, and vertically extend in the substrate 100 between the adjacent bit line structures BL along a direction perpendicular to the surface of the substrate 100 (hereinafter referred to as the vertical direction) to be electrically connected to the substrate 100. In one embodiment, the material of the contact structure 150 may include single crystal silicon (crystalline silicon), polycrystalline silicon (poly silicon), amorphous silicon (amorphous silicon), doped silicon (doped silicon), silicon germanium (SiGe), or other suitable silicon-containing semiconductor materials, but is not limited thereto. Exemplarily, the material of the contact structure 150 is phosphorus-doped silicon (SiP).

[0055] Further, the connection pad structure 170 in this embodiment is specifically disposed between adjacent bit line structures BL and conformally covers the top surface of the silicide layer 160, the top surface of the sidewall structure 140 and the top surface of the bit line structure BL, and the isolation structure 180 is specifically disposed between adjacent connection pad structures 170. In one embodiment, the connection pad structure 170 may include a first connection pad layer 170.1 and a second connection pad layer 170.2 stacked in sequence from bottom to top; wherein the material of the first connection pad layer 170.1 may include a conductive barrier material such as titanium and / or titanium nitride (TiN), tantalum (Ta) and / or tantalum oxide (TaN), and is preferably titanium nitride (TiN), but is not limited thereto; the material of the second connection pad layer 170.2 may include a metal, such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), nitrides, silicides, alloys, and / or composite layers of the aforementioned materials, and is preferably tungsten (W), but is not limited thereto.

[0056] In the present embodiment, since the first interval SP1 between adjacent first bit line structures BL1 and the second interval SP2 between adjacent first bit line structures BL1 and second bit line structures BL2 are different, that is, the first interval SP1<second interval SP2, the connection pad structure 170 located between adjacent first bit line structures BL1 and the connection pad structure 170 located between adjacent first bit line structures BL1 and second bit line structures BL2 and the silicide layer 160 and contact structure 150 thereunder are also different in horizontal width. For the sake of distinction, in the present embodiment, the connection pad structure located between adjacent first bit line structures BL1 is named as the first connection pad structure 171, and the connection pad structure located between adjacent first bit line structures BL1 and second bit line structures BL2 is named as the second connection pad structure 172 (e.g. Figure 4 Therefore, the width of the second connection pad structure 172 in the embodiment of the present invention in the horizontal direction is greater than the width of the first connection pad structure 171 in the horizontal direction, and the width of the contact structure 150 located below the first connection pad structure 171 in the horizontal direction is also smaller than the width of the contact structure 150 located below the second connection pad structure 172 in the horizontal direction.

[0057] Under this configuration, the isolation structure 180 in this embodiment can also be divided into a first isolation structure 181 and a second isolation structure 182 due to the difference between the first interval SP1 between adjacent first bit line structures BL1 and the second interval SP2 between adjacent first bit line structures BL1 and second bit line structures BL2. Figure 5As shown; specifically, the first isolation structure 181 passes through the first connection pad structure 171 in the vertical direction and directly contacts the first bit line structure BL1, and the second isolation structure 182 passes through the second connection pad structure 172 in the vertical direction and its bottom surface is completely covered by the second connection pad structure 172, so that the second isolation structure 182 is isolated from the first bit line structure BL1 and the second bit line structure BL2 located on both sides of the second connection pad structure 172 through which it passes; in other words, if the spacing between adjacent first isolation structures 181 is the first spacing d1, and the spacing between adjacent first isolation structures 181 and second isolation structures 182 is the second spacing d2, then the first spacing d1 is smaller than the second spacing d2. In one embodiment, the material of the isolation structure 180 (including the first isolation structure 181 and the second isolation structure 182) may be the same and may specifically include nitride, such as silicon nitride, or may include oxide, such as silicon oxide, and is preferably silicon nitride, but is not limited thereto.

[0058] In the conventional technology, the adjacent first connection pad structure 171 and the second connection pad structure 172 usually need to be isolated by a second isolation structure 182 to avoid short circuit between the two contact structures 150 located below the adjacent first connection pad structure 171 and the second connection pad structure 172. However, since the first bit line structure BL1 and the second bit line structure BL2 adjacent thereto located at the edge are often used as dummy structures for adjusting the pattern density of the semiconductor device in actual applications, the second isolation structure 182 located in the second spacer SP2 between the adjacent first bit line structure BL1 and the second bit line structure BL2 is process-shifted in a horizontal direction close to the second bit line structure BL2 in an embodiment of the present invention, so that the first connection pad structure 171 and the second connection pad structure 172 located above the adjacent first bit line structure BL1 and the second bit line structure BL2 are connected, thereby avoiding the technical problem of some contact structures being peeled off during processes such as photolithography due to differences in pattern density, thereby improving the reliability and performance of the semiconductor device.

[0059] In addition, please refer to Figure 7 As shown, the semiconductor device in this embodiment may further include a capacitor structure CAP disposed on the first connection pad structure 171 between adjacent first bit line structures BL1, wherein the capacitor structure CAP includes a lower electrode BE, a dielectric layer DL and an upper electrode TE. The lower electrode BE is disposed on the first connection pad structure 171, the upper electrode TE is disposed on the lower electrode BE, and the dielectric layer DL is disposed between the upper electrode TE and the lower electrode BE.

[0060] It should be understood that the “common shape” in the embodiments of the present invention refers to constructing a continuous structural shape by utilizing the morphological similarities and associations between two or more shapes.

[0061] A person skilled in the art of the present invention should be able to easily understand that, in order to meet the actual product requirements, the semiconductor device of the present invention may also have other aspects and is not limited to the above. Other embodiments or variations of the semiconductor device of the present invention will be further described below. In order to simplify the description, the following description mainly describes the differences between the embodiments, and does not repeat the same aspects. In addition, the same components in the embodiments of the present invention are marked with the same reference numerals to facilitate comparison between the embodiments.

[0062] Please refer to Fig.12 and Fig.13 , Fig.13 FIG. 1 is a partial top view of a semiconductor device according to a second embodiment of the present invention. Fig.12 FIG. 1 is a diagram showing a semiconductor device according to a second embodiment of the present invention. Fig.13 The schematic cross-sectional view of a portion of the area along the AA' cut line is shown. The structure of the semiconductor device of this embodiment is substantially the same as that of the semiconductor device in the aforementioned first embodiment, such as the semiconductor device also includes a plurality of first bit line structures BL1 disposed on the substrate 100 and spaced apart from each other in the horizontal direction, and a second bit line structure BL2 disposed on the outer side of one side of the plurality of first bit line structures BL1, a plurality of contact structures 150, etc., and the same parts are not repeated here. The main difference between the semiconductor device of this embodiment and the aforementioned first embodiment is that at least one third bit line structure BL3 is further disposed in the plurality of bit line structures BL of the semiconductor device, and the top surface of the third bit line structure BL3 is at a different level from the top surfaces of the first bit line structure BL1 and the second bit line structure BL2, so that the second isolation structure 182 disposed on the top surface of the third bit line structure BL3 is also different.

[0063] Specifically, if Fig.12As shown, the semiconductor device in this embodiment is a third bit line structure BL3 arranged between the adjacent first bit line structure BL1 and the second bit line structure BL2, so that a plurality of the first bit line structures BL1, one third bit line structure BL3 and one second bit line structure BL2 are arranged in a horizontal direction with spacing from each other, and the top surface of the third bit line structure BL3 is lower than the top surfaces of the first bit line structure BL1 and the second bit line structure BL2. In one embodiment, the third bit line structure BL3 has the same multi-layer bit line material layer, for example, the semiconductor layer 131 (for example, polysilicon), the barrier layer 132 (for example, cobalt silicide) and the metal layer 133 (for example, tungsten) stacked in sequence from bottom to top; the third interval SP3 between the third bit line structure BL3 and the first bit line structure BL1 adjacent thereto may be the same as the first interval SP1 between the adjacent first bit line structures BL1, and the fourth interval SP4 between the third bit line structure BL3 and the second bit line structure BL2 adjacent thereto may be smaller than the third structure SP3.

[0064] It should be particularly noted that the connection pad structure 170 in the present embodiment is still divided into a first connection pad structure 171 and a second connection pad structure, and the isolation structure 180 is also still divided into a first isolation structure 181 and a second isolation structure 182; since the multi-layer bit line material layer of the third bit line structure BL3 does not include the cap layer 134, the connection pad structure 170 in the present embodiment located in the adjacent first bit line structure BL1 and the second bit line structure BL2 is changed from one in the aforementioned first embodiment to two in the present embodiment, namely, a second connection pad structure 172 located in the third interval SP3 on the top surface of the third bit line structure BL3 and between the first bit line structure BL1 adjacent thereto (at this time, the first connection pad layer 170.1 in the second connection pad structure 172 is in direct contact with the metal layer 134 of the third bit line structure BL3), and a second connection pad structure 172 located in the fourth interval SP4 between the third bit line structure BL3 and the second bit line structure BL2 adjacent thereto and on the top surface of the second bit line structure BL2.

[0065] Under this setting, the isolation structure 180 located between the first bit line structure BL1 and the second bit line structure BL2 in this embodiment is also changed from a second isolation structure 182 in the aforementioned first embodiment whose bottom is completely covered by the second connection pad structure 172 to a second isolation structure 182 located above the third bit line structure BL3 and isolated from the third bit line structure BL3 and the bit line structures BL on both sides thereof, and a second isolation structure 182 located above the second bit line structure BL2 and in direct contact with the second bit line structure BL2.

[0066] Obviously, in this embodiment, the second isolation structure 182 located above the third bit line structure BL3 has undergone a process shift, so that the two adjacent second connection pad structures 172 located above the third bit line structure BL3 are connected, thereby avoiding the technical problem of some contact structures being peeled off during processes such as lithography due to large differences in graphic density, thereby improving the reliability and performance of semiconductor devices.

[0067] Furthermore, based on the same inventive concept, an embodiment of the present invention also provides a method for manufacturing the semiconductor device, which may specifically include the following steps:

[0068] Step S100, providing a substrate 100;

[0069] Step S200, forming a plurality of bit line structures BL, wherein the bit line structures BL include a first bit line structure BL1 and a second bit line structure BL2 which are separated from each other and disposed on a substrate 100;

[0070] Step S300, forming a plurality of connection pad structures 170, wherein the connection pad structures 170 are arranged between adjacent bit line structures BL;

[0071] Step S400, forming a plurality of isolation structures 180, which are arranged between adjacent connection pad structures 170, wherein the isolation structure 180 includes a first isolation structure 181 directly contacting the first bit line structure BL1 and the connection pad structure 170, and a second isolation structure 182 located between the first bit line structure BL1 and the second bit line structure BL2, and the bottom surface of the second isolation structure 182 is completely covered by the connection pad structure 170.

[0072] In order to enable a person skilled in the art to which the present invention relates to easily understand the method for manufacturing a semiconductor device in an embodiment of the present invention, the method for manufacturing a semiconductor device proposed in the present invention will be further described below in conjunction with various structural schematic diagrams of the manufacturing method during the preparation process.

[0073] Please refer to Figure 1 to Figure 7 As shown, Figure 1 to Figure 7 It is a structural schematic diagram of the manufacturing method of the semiconductor device provided in the first embodiment of the present invention during the preparation process.

[0074] Please refer to Figure 1, perform the above steps S100 and S200: provide a substrate 100, and use an etching process to form a plurality of trenches in the substrate 100, and then use a deposition process, such as at least one of a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process, to fill the plurality of trenches with insulating materials (such as silicon oxide, silicon nitride, etc.) to form a plurality of trench isolations 110, wherein the plurality of trench isolations 110 define a plurality of active regions in the substrate 100. Then, an insulating layer 120 (such as a silicon oxide layer or a silicon nitride layer) and a plurality of bit line material layers on the insulating layer 120 are formed on the substrate 100. Specifically, forming the multi-layer bit line material layer can include forming a semiconductor layer 131, a barrier layer 132, a metal layer 133 and a cap layer 134 in sequence from bottom to top on the substrate 100. Exemplarily, the material of the semiconductor layer 131 is polysilicon, the material of the barrier layer 132 is cobalt silicide (CoSi), the material of the metal layer 133 is tungsten (W), and the material of the cap layer 134 is silicon nitride (SiN). Subsequently, the multilayer structure of the bit line material layer is sequentially etched along the vertical direction using an etching process, thereby forming a plurality of mutually separated bit line structures BL therein; specifically, the bit line structure BL comprises a plurality of the first bit line structures BL1 and a second bit line structure BL2, the plurality of first bit line structures BL1 are sequentially arranged along the horizontal direction, the second bit line structure BL2 is located on one side outside of the plurality of first bit line structures BL1, and the width of the first bit line structure BL1 in the horizontal direction is smaller than the width of the second bit line structure BL2 in the horizontal direction, and the first interval SP1 between adjacent first bit line structures BL1 is smaller than the second interval SP2 between adjacent first bit line structures BL1 and second bit line structures BL2.

[0075] Please refer to Figure 2 , following the above step S200, a sidewall structure 140 self-aligned to the sidewalls of the first bit line structure BL1 and the second bit line structure BL2 is formed on both sides of the multiple first bit line structures BL1 and the second bit line structure BL2; in one embodiment, the sidewall structure 140 has a multi-layer structure, for example, a first sidewall 141 (such as silicon oxide) and a second sidewall 142 (such as silicon nitride) stacked in sequence along a horizontal direction.

[0076] Please refer to Figure 3, following the above step S200: utilizing an etching process, etching downward along the vertical direction to form a storage node contact groove (not shown) on the outside of the sidewall structure 140 after removing the insulating layer 120 and part of the substrate 100, and then forming a contact material layer (not shown) to fully cover the substrate 100 and fill the storage node contact groove, and then utilizing an etching or planarization process to remove the contact material layer outside the storage node contact groove until the top surfaces of the bit line structure BL and the sidewall structure 140 are exposed, thereby obtaining contact structures 150 respectively located in the storage node contact groove. Among them, the contact material layer may be a silicon-containing semiconductor material, such as phosphorus-doped silicon. Subsequently, a metal material layer (not shown) is deposited on the substrate 100, and the metal material layer and the substrate 100 and other structures are silicidized so that the top of the contact structure 150, whose material is a silicon-containing semiconductor material, such as phosphorus-doped silicon, reacts with the metal material layer to form a silicide layer 160, thereby obtaining Figure 3 At this time, since the first interval SP1 between the adjacent first bit line structures BL1 and the second interval SP2 between the adjacent first bit line structures BL1 and the second bit line structures BL2 are different, that is, the first interval SP1<the second interval SP2, the width of the contact structure 150 and the silicide layer 160 thereon located between the adjacent first bit line structures BL1 in the horizontal direction is also different from the width of the contact structure 150 and the silicide layer 160 thereon located between the adjacent first bit line structures BL1 and the second bit line structures BL2 in the horizontal direction, that is, the width of the contact structure 150 and the silicide layer 160 thereon located between the adjacent first bit line structures BL1 in the horizontal direction is smaller than the width of the contact structure 150 and the silicide layer 160 located between the adjacent first bit line structures BL1 and the second bit line structures BL2 in the horizontal direction.

[0077] Please refer to Figure 4, perform the above step S300: use a deposition process to deposit a first connection pad material layer (for example, titanium nitride) and a second connection pad material layer (for example, metal tungsten) of the connection pad structure 170 on the substrate 100, and etch them to form a first connection pad layer 170.1 wrapped on the surface of the silicide layer 160, the first bit line structure BL1 and the second bit line structure BL2, and a second connection pad layer 170.2 that fills the gap between the adjacent first bit line structure BL1 and the second bit line structure BL2 and has a top surface higher than the top surface of the first bit line structure BL1, thereby forming a connection pad structure 170 including a first connection pad layer 170.1 and a second connection pad layer 170.2 arranged in sequence from bottom to top. Similarly, due to the difference between the first interval SP1 between adjacent first bit line structures BL1 and the second interval SP2 between adjacent first bit line structures BL1 and second bit line structures BL2, the multiple connection pad structures 170 in this embodiment can be specifically divided into first connection pad structures 171 and second connection pad structures 172 according to their different widths in the horizontal direction, wherein the first connection pad structure 171 is located between adjacent first bit line structures BL1, the second connection pad structure 172 is located between adjacent first bit line structures BL1 and second bit line structures BL2, and the width of the first connection pad structure 171 in the horizontal direction is smaller than the width of the second connection pad structure 172 in the horizontal direction.

[0078] Please refer to Figure 5 , perform the above step S400: form a mask layer (not shown) on the connection pad structure 180, wherein the mask layer has an isolation structure pattern, and use the mask layer as a mask, and use an etching process to form a plurality of isolation structures 180 on the connection pad structure 170 on one side of the bit line structure BL and part of the bit line structure BL along the vertical direction. Specifically, the isolation structure 180 includes a first isolation structure 181 and a second isolation structure 182 that are separated from each other and arranged in sequence along the horizontal direction, wherein the first isolation structure 181 passes through the first connection pad structure 171, and its bottom surface extends to the first bit line structure BL1 to directly contact the corresponding first bit line structure BL1, and the second isolation structure 182 passes through the second connection pad structure 172 and its bottom surface is completely covered by the second connection pad structure 172, so that the second isolation structure 182 is isolated from the first bit line structure BL1 and the second bit line structure BL2 located on both sides of the second connection pad structure 172 through which it passes. In one embodiment, the material of the isolation structure 180 (including the first isolation structure 181 and the second isolation structure 182) may be the same and may specifically include nitride, such as silicon nitride, or may include oxide, such as silicon oxide, and is preferably silicon nitride, but is not limited thereto.

[0079] Please refer to Figure 7, following the above step S400: a capacitor structure CAP may be formed on the first connection pad structure 171 between the adjacent first bit line structures BL1, wherein the capacitor structure CAP includes a lower electrode BE, a dielectric layer DL and an upper electrode TE. The lower electrode BE is disposed on the first connection pad structure 171, the upper electrode TE is disposed on the lower electrode BE, and the dielectric layer DL is disposed between the upper electrode TE and the lower electrode BE.

[0080] It should be particularly noted that, since the embodiment of the present invention is based on the fact that the first bit line structure BL1 located at the edge of the cell area and the second bit line structure BL2 located on the peripheral area are often used as dummy structures for adjusting the pattern density of the cell area in actual applications, the second isolation structure 182 located in the second interval SP2 between the adjacent first bit line structure BL1 and the second bit line structure BL2 is process-shifted in the horizontal direction close to the second bit line structure BL2, so that the first connection pad structure 171 and the second connection pad structure 172 located above the adjacent first bit line structure BL1 and the second bit line structure BL2 are connected, therefore, when the isolation structure 180 is formed by using the above step S400, When the manufacturing process adopted by the present invention forms isolation trenches (not shown, at the same position as the isolation structures) in the first connection pad structure 171 and the second connection pad structure 172, the isolation trenches in the second connection pad structure 172 need to be offset along the horizontal direction close to the second bit line structure BL2, and then the entire bottom surface of the second isolation structure 182 formed after filling the isolation trench with insulating material (such as silicon nitride) using a deposition process is covered by the second connection pad structure 172, thereby achieving the connection between the first connection pad structure 171 and the second connection pad structure 172 located above the adjacent first bit line structure BL1 and the second bit line structure BL2.

[0081] Please refer to Figure 8 to Figure 14 As shown, Figure 8 to Figure 14 It is a structural schematic diagram of the manufacturing method of the semiconductor device provided in the second embodiment of the present invention during the preparation process.

[0082] The structure of the semiconductor device of this embodiment is substantially the same as the manufacturing method of the semiconductor device in the first embodiment, and the similarities are not repeated here. The main difference between the manufacturing method of the semiconductor device of this embodiment and the manufacturing method of the first embodiment is that after performing the above step S200 to form a plurality of first bit line structures BL1 and a second bit line structure BL2 sequentially spaced from each other in the horizontal direction, the cap layer 134 of a first bit line structure BL1 adjacent to the second bit line structure BL2 can be further removed by an etching process such as a dry etching process to form a third bit line structure BL3 between the adjacent first bit line structure BL1 and the second bit line structure BL2, such as Figure 8 It should be understood that in other embodiments, the sidewall structure 140 may be formed on the sidewalls of the first bit line structure BL1 and the second bit line structure BL2, and then an etching process may be used to form the sidewall structure 140. Fig. 9 The structure described above is not limited thereto.

[0083] To sum up, in the present invention, by setting the interval between the adjacent first bit line structure and the second bit line structure to be larger than the interval between the adjacent first bit line structures, the width of the connection pad structure formed between the two adjacent first bit line structures in the horizontal direction is smaller than the width of the connection pad structure formed between the adjacent first bit line structure and the second bit line structure in the horizontal direction, thereby causing the second isolation structure in the connection pad structure formed between the adjacent first bit line structure and the second bit line structure to be offset in a direction close to the second bit line structure, thereby achieving the purpose of allowing the connection pad structure between the adjacent first bit line structure and the second bit line structure to be connected with the connection pad structure adjacent to it and located between the adjacent first bit line structures.

[0084] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0085] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device, electronic device, and computer-readable storage medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0086] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: substrate; A plurality of bit line structures, including a first bit line structure and a second bit line structure disposed on a substrate separately from each other; A plurality of connection pad structures are arranged between adjacent bit line structures; A plurality of isolation structures are arranged between adjacent connection pad structures, and the isolation structures include: a first isolation structure directly contacting the first bit line structure and the connection pad structure; The second isolation structure is located between the first bit line structure and the second bit line structure, and the bottom surface of the second isolation structure is completely covered by the connection pad structure.

2. The semiconductor device according to claim 1, wherein A first spacing between adjacent first bit line structures is smaller than a second spacing between adjacent first bit line structures and second bit line structures.

3. The semiconductor device according to claim 2, wherein: The connection pad structure comprises: a first connection pad structure, arranged between adjacent first bit line structures; The second connection pad structure is disposed between the first bit line structure and the second bit line structure, and the bottom surface of the second isolation structure is completely covered by the second connection pad structure.

4. The semiconductor device according to claim 3, characterized in that The second connection pad structure is connected to the first connection pad structure adjacent to it.

5. The semiconductor device according to claim 1, wherein: The second isolation structure is isolated from the first bit line structure and the second bit line structure.

6. The semiconductor device according to claim 1, wherein: There is a first distance between adjacent first isolation structures, and there is a second distance between adjacent first isolation structures and second isolation structures, and the first distance is smaller than the second distance.

7. The semiconductor device according to claim 3, wherein: Also includes: A plurality of contact structures are arranged under the connection pad structure, and the width of the contact structure under the first connection pad structure in the horizontal direction is smaller than the width of the contact structure under the second connection pad structure in the horizontal direction.

8. The semiconductor device according to claim 1, wherein A width of the first bit line structure in the horizontal direction is smaller than a width of the second bit line structure in the horizontal direction.

9. The semiconductor device according to claim 1, wherein: Also includes: The third bit line structure is located between the first bit line structure and the second bit line structure, and at least one of the connection pad structures is sandwiched between the top surface of the third bit line structure and the bottom surface of the second isolation structure.

10. The semiconductor device according to claim 9, wherein: The third bit line structure includes a semiconductor layer and a metal layer stacked in sequence from bottom to top, and the connection pad structure is in direct contact with the metal layer.

11. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate; forming a plurality of bit line structures, the bit line structures including a first bit line structure and a second bit line structure disposed on a substrate spaced apart from each other; forming a plurality of connection pad structures, wherein the connection pad structures are arranged between adjacent bit line structures; A plurality of isolation structures are formed and arranged between adjacent connection pad structures, wherein the isolation structures include a first isolation structure directly contacting the first bit line structure and the connection pad structure, and a second isolation structure located between the first bit line structure and the second bit line structure, and the bottom surface of the second isolation structure is completely covered by the connection pad structure.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: A first spacing between adjacent first bit line structures is smaller than a second spacing between adjacent first bit line structures and second bit line structures.

13. The method for manufacturing a semiconductor device according to claim 11, wherein: The connection pad structure comprises: A first connection pad structure, disposed between adjacent first bit line structures; The second connection pad structure is disposed between the first bit line structure and the second bit line structure, and the bottom surface of the second isolation structure is completely covered by the second connection pad structure.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: The second connection pad structure is connected to the first connection pad structure adjacent to it.

15. The method for manufacturing a semiconductor device according to claim 11, wherein: The second isolation structure is isolated from the first bit line structure and the second bit line structure.

16. The method for manufacturing a semiconductor device according to claim 15, wherein: Also includes: A plurality of contact structures are formed, wherein the contact structures are arranged under the connection pad structures, and the width of the contact structures under the first connection pad structures in the horizontal direction is smaller than the width of the contact structures under the second connection pad structures in the horizontal direction.

17. The method for manufacturing a semiconductor device according to claim 11, wherein: The bit line structure further comprises: The third bit line structure is located between the first bit line structure and the second bit line structure, and at least one of the connection pad structures is sandwiched between the top surface of the third bit line structure and the bottom surface of the second isolation structure.

18. The method for manufacturing a semiconductor device according to claim 17, wherein: The third bit line structure includes a semiconductor layer and a metal layer stacked in sequence from bottom to top, and the connection pad structure is in direct contact with the metal layer.

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