Display device

Abstract

A display device is provided. The display device includes a base layer having a display area and a non-display area, a circuit layer on the base layer, and an element layer on the circuit layer and including a light emitting element and a light receiving element corresponding to the display area. The circuit layer includes pixel driving circuits connected to the light emitting elements, sensor driving circuits connected to the light receiving elements, read-out lines connected to the sensor driving circuits, first data lines connected to a first group of pixel driving circuits among the pixel driving circuits, and second data lines connected to a second group of pixel driving circuits among the pixel driving circuits. Second data lines spaced apart from the first data lines in the first direction and connected to a second group of pixel driving circuits among the pixel driving circuits; and data connection lines electrically connected to the second data lines, respectively, in the display area.

Description

Technical Field

[0001] One or more embodiments of the present disclosure described herein relate to a display device in which an area of ​​a non-display region is reduced. Background Art

[0002] The display device provides various functions that enable the user to interact with the display device. For example, the display device can display an image to provide information to the user, or can sense the user's input. Recent display devices include a function of sensing the user's biometric information.

[0003] Bio-information may be recognized by using a capacitive sensing technology for sensing a change in capacitance between electrodes, a light sensing technology for sensing incident light using an optical sensor, and / or an ultrasonic sensing technology for sensing vibration using a piezoelectric element. Summary of the invention

[0004] One or more embodiments of the present disclosure provide a display device in which an area of ​​a non-display region is reduced and has a biometric information recognition function.

[0005] According to one or more embodiments, a display device includes a base layer having a display area and a non-display area, a circuit layer located on the base layer, an element layer located on the circuit layer and including a light emitting element and a light receiving element corresponding to the display area, and a data driver electrically connected to the circuit layer.

[0006] The circuit layer includes a pixel driving circuit connected to the light emitting element, a sensor driving circuit connected to the light receiving element, a readout line connected to the sensor driving circuit, a first data line connected to a first group of pixel driving circuits among the pixel driving circuits, a second data line spaced apart from the first data line in a first direction and connected to a second group of pixel driving circuits among the pixel driving circuits, and data connection lines electrically connected to the second data lines in the display area, respectively. The first data line is connected to the data driver, and the second data line is connected to the data driver through the data connection line.

[0007] According to one or more embodiments, a display device includes a display panel including a display area and a non-display area adjacent to the display area, a driver chip connected to the display panel, and a sensor chip connected to the display panel.

[0008] The display panel includes a light emitting element, a light receiving element, a pixel driving circuit connected to the light emitting element, a sensor driving circuit connected to the light receiving element, a readout line connected to the sensor driving circuit and the sensor chip, a first data line connected to a first group of pixel driving circuits among the pixel driving circuits, a second data line spaced apart from the first data line in a first direction and connected to a second group of pixel driving circuits among the pixel driving circuits, and data connection lines electrically connected to the second data lines respectively in the display area.

[0009] The first data line is connected to the driver chip, and the second data line is connected to the driver chip through the data connection line. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects and features of embodiments of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0011] Figure 1 is a perspective view of a display device according to one or more embodiments of the present disclosure.

[0012] Figure 2A is an exploded perspective view of a display device according to one or more embodiments of the present disclosure.

[0013] Figure 2B is a cross-sectional view of a display device according to one or more embodiments of the present disclosure.

[0014] Figure 3 is a block diagram of a display device according to one or more embodiments of the present disclosure.

[0015] Figure 4A is a circuit diagram showing a pixel and a sensor according to one or more embodiments of the present disclosure.

[0016] Figure 4B It is used to explain Figure 4A The waveform diagram of the operation of the pixel and sensor is shown in FIG.

[0017] Figure 5 is a plan view of a display panel according to one or more embodiments of the present disclosure.

[0018] Figure 6 is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure.

[0019] Figure 7 is an enlarged plan view showing a portion of a display panel according to one or more embodiments of the present disclosure.

[0020] Fig. 8A yes Figure 7 An enlarged view of portion AA1 is shown in FIG.

[0021] Figure 8B is along Fig. 8A A cross-sectional view taken along line II' shown in FIG.

[0022] Fig. 9A yes Figure 7 An enlarged view of portion BB1 is shown in FIG.

[0023] Fig. 9Bis along Fig. 9A A cross-sectional view taken along line II-II' shown in FIG.

[0024] Fig.10 is a plan view of a display panel according to one or more embodiments of the present disclosure.

[0025] Fig.11 is an enlarged plan view showing a portion of a display panel according to one or more embodiments of the present disclosure.

[0026] Fig. 12A yes Fig.11 An enlarged view of portion AA2 is shown in FIG.

[0027] Fig. 12B is along Fig. 12A A cross-sectional view taken along line III-III' shown in FIG.

[0028] Fig.13A yes Fig.11 An enlarged view of portion BB2 is shown in FIG.

[0029] Fig. 13B is along Fig.13A A cross-sectional view taken along line IV-IV' shown in FIG.

[0030] Fig.14A is a plan view showing a 2-1 th initialization voltage line according to one or more embodiments of the present disclosure.

[0031] Fig. 14B is a plan view showing a 2-2 th initialization voltage line according to one or more embodiments of the present disclosure.

[0032] Fig. 14C is a plan view illustrating a first initialization voltage line according to one or more embodiments of the present disclosure.

[0033] Fig.14D is a plan view illustrating a second driving voltage line according to one or more embodiments of the present disclosure.

[0034] FIG. 15A to FIG. 15I is a plan view showing a manufacturing process of a circuit layer according to one or more embodiments of the present disclosure.

[0035] FIG. 16A to FIG. 16D is a plan view showing a manufacturing process of a circuit layer according to one or more embodiments of the present disclosure.

[0036] Fig.17A and Fig. 17B is a cross-sectional view showing a light emitting element and a light receiving element of a display panel according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0037] In the present disclosure, when a component (or region, layer, portion, etc.) is referred to as being “on,” “connected to” or “coupled to” another component, this means that the component may be directly on, connected to or coupled to the other component or a third component may be present therebetween.

[0038] The same reference numerals indicate the same components. Additionally, in the drawings, the thickness, proportion and size of the components are exaggerated for effective description. As used herein, the term "and / or" includes all of one or more combinations defined by the relevant components.

[0039] Terms such as first, second, etc. may be used to describe various components, but these components should not be limited by these terms. Terms may only be used to distinguish one component from other components. For example, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component without departing from the spirit and scope of the present disclosure. Unless otherwise specified, terms in the singular may include plural forms.

[0040] In addition, terms such as "below", "below", "above", and "on" are used to describe the relationship of components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0041] It should be understood that terms such as “includes,” “comprising,” and “having,” when used in this document, specify the presence of stated features, quantities, steps, operations, components, parts, or a combination thereof, but do not preclude the presence or addition of one or more other features, quantities, steps, operations, components, parts, or a combination thereof.

[0042] Unless otherwise defined, all terms (including technical or scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. Such terms as those defined in commonly used dictionaries should be interpreted as having the same meaning as the contextual meaning in the relevant technical field, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined as having such a meaning in this application.

[0043] Hereinafter, one or more embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0044] Figure 1 is a perspective view of a display device according to one or more embodiments of the present disclosure. Figure 2A is an exploded perspective view of a display device according to one or more embodiments of the present disclosure. Figure 2B is a cross-sectional view of a display device according to one or more embodiments of the present disclosure.

[0045] Reference Figure 1 , Figure 2A and Figure 2B , the display device DD according to one or more embodiments of the present disclosure may have a rectangular shape including short sides parallel to the first direction DR1 and long sides parallel to the second direction DR2 crossing the first direction DR1. However, not limited thereto, the display device DD may have various shapes, such as a circular shape, other polygonal shapes, and / or the like.

[0046] The display device DD may be activated according to the electrical signal. The display device DD may include one or more embodiments. For example, the display device DD may be applied to electronic devices such as smart watches, computers (eg, tablet computers and notebook computers), smart TVs, and / or the like.

[0047] Hereinafter, a normal direction substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. The expression "when viewed from above a plane" used herein may mean that it is viewed in the third direction DR3.

[0048] An upper surface of the display device DD may be defined as a display surface IS and may be parallel to a plane defined by the first direction DR1 and the second direction DR2. An image IM generated by the display device DD may be provided to a user through the display surface IS.

[0049] The display surface IS may be divided into a transmission area TA and a frame area BZA. The transmission area TA may be an area on which an image IM is displayed. A user visually recognizes the image IM through the transmission area TA. In one or more embodiments, the transmission area TA is shown as a rounded quadrilateral shape. However, this is illustrative, and the transmission area TA may have various shapes and is not limited to any one embodiment.

[0050] The border area BZA is adjacent to the transmission area TA and may be arranged around the transmission area TA along the edge or periphery of the transmission area TA. The border area BZA may have a suitable color (e.g., a predetermined color). The border area BZA may surround the transmission area TA. Therefore, the shape of the transmission area TA may be substantially defined by the border area BZA. However, this is illustrative, and the border area BZA may be arranged adjacent to only one side of the transmission area TA, or may be omitted.

[0051] The display device DD can sense external input applied from the outside. The external input may include various forms of input provided from outside the display device DD. For example, the external input may include not only contact by a part of the user's body (e.g., the user's hand US_F) or contact by a separate device (e.g., an active pen or a digitizer), but also external input applied near the display device DD or applied adjacent to the display device DD at a suitable distance (e.g., a predetermined distance) (e.g., hovering). In addition, the external input may have various forms, such as force, pressure, temperature, light, and / or the like.

[0052] The display device DD can sense the user's biological information applied from the outside. A biological information sensing area capable of sensing the user's biological information may be provided on the display surface IS of the display device DD. The biological information sensing area may be provided in the entire area of ​​the transmission area TA, or may be provided in a partial area of ​​the transmission area TA. Figure 1 An example is shown in which the entire transmission area TA is used as the bio-information sensing area.

[0053] The display device DD may include a window WM, a display module DM, and a case EDC. In one or more embodiments, the window WM and the case EDC are coupled to form an appearance of the display device DD.

[0054] The front surface of the window WM defines the display surface IS of the display device DD. The window WM may include an optically transparent insulating material. For example, the window WM may include glass or plastic. The window WM may have a multilayer structure or a single-layer structure. For example, the window WM may include a plurality of plastic films coupled by an adhesive, or may include a glass substrate and a plastic film coupled by an adhesive.

[0055] The display module DM may include a display panel DP and an input sensing layer ISL. The display panel DP may display an image IM according to an electrical signal, and the input sensing layer ISL may sense an external input applied from the outside. The external input may be provided in various forms.

[0056] The display panel DP according to one or more embodiments of the present disclosure may be an emissive display panel, but is not particularly limited. For example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel and / or a quantum dot light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material, and the light-emitting layer of the inorganic light-emitting display panel may include an inorganic light-emitting material. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots or quantum rods. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0057] Reference Figure 2B, the display panel DP includes a base layer BL, a circuit layer DP_CL, an element layer DP_ED and an encapsulation layer TFE. The display panel DP according to the present disclosure may be a flexible display panel. However, the present disclosure is not limited thereto. For example, the display panel DP may be a foldable display panel folded around a folding axis, or a rigid display panel.

[0058] The base layer BL may include a synthetic resin layer. The synthetic resin layer may be a polyimide-based resin layer, and its material is not particularly limited. In addition, the base layer BL may include a glass substrate, a metal substrate, or an organic and / or inorganic composite substrate.

[0059] The circuit layer DP_CL is arranged on the base layer BL. The circuit layer DP_CL is arranged between the base layer BL and the element layer DP_ED. The circuit layer DP_CL includes at least one insulating layer and / or a circuit element. Hereinafter, the insulating layer included in the circuit layer DP_CL is referred to as an intermediate insulating layer. The intermediate insulating layer includes at least one intermediate inorganic film and at least one intermediate organic film. The circuit element may include a pixel driving circuit included in each of a plurality of pixels for displaying an image and a sensor driving circuit included in each of a plurality of sensors for identifying external information. The external information may be biological information. In one or more embodiments of the present disclosure, the sensor may be a fingerprint recognition sensor, a proximity sensor, an iris recognition sensor, a blood pressure measurement sensor, an illumination sensor, and / or the like. Alternatively, the sensor may be an optical sensor for optically identifying biological information. The circuit layer DP_CL may also include a signal line connected to the pixel driving circuit and / or the sensor driving circuit.

[0060] The element layer DP_ED may include a light emitting element included in each of the pixels and a light receiving element included in each of the sensors. In one or more embodiments of the present disclosure, the light receiving element may be a photodiode. The light receiving element may be a sensor that senses light reflected by the user's fingerprint or reacts to light reflected by the user's fingerprint. Figures 6 to 16D The circuit layer DP_CL and the element layer DP_ED are described in detail.

[0061] The encapsulation layer TFE seals the element layer DP_ED. The encapsulation layer TFE may include at least one organic film and / or at least one inorganic film. The inorganic film may include an inorganic material and may protect the element layer DP_ED from moisture and / or oxygen. The inorganic film may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer and / or an aluminum oxide layer, but is not particularly limited thereto. The organic film may include an organic material and may protect the element layer DP_ED from foreign matter such as dust particles.

[0062] The input sensing layer ISL may be formed on the display panel DP. The input sensing layer ISL may be directly disposed on the encapsulation layer TFE. According to one or more embodiments of the present disclosure, the input sensing layer ISL may be formed on the display panel DP by a continuous process. That is, when the input sensing layer ISL is directly disposed on the display panel DP, an adhesive film is not disposed between the input sensing layer ISL and the encapsulation layer TFE. Alternatively, an adhesive film may be disposed between the input sensing layer ISL and the display panel DP. In this case, the input sensing layer ISL may not be manufactured together with the display panel DP by a continuous process, but may be manufactured separately from the display panel DP, and then fixed to the upper surface of the display panel DP by an adhesive film.

[0063] The input sensing layer ISL may sense an external input (e.g., a user's touch), may change the sensed external input into an input signal (e.g., a predetermined input signal), and may provide the input signal to the display panel DP. The input sensing layer ISL may include a plurality of sensing electrodes for sensing the external input. The sensing electrodes may sense the external input in a capacitive type. The display panel DP may receive the input signal from the input sensing layer ISL, and may generate an image corresponding to the input signal.

[0064] The display module DM may further include a color filter layer CFL. In one or more embodiments of the present disclosure, the color filter layer CFL may be arranged on the input sensing layer ISL. However, the present disclosure is not limited thereto. The color filter layer CFL may be arranged between the display panel DP and the input sensing layer ISL. The color filter layer CFL may include a plurality of color filters and a black matrix.

[0065] The structures of the input sensing layer ISL and the color filter layer CFL will be described in detail below.

[0066] The display device DD according to one or more embodiments of the present disclosure may further include an adhesive layer AL. The window WM may be attached to the input sensing layer ISL through the adhesive layer AL. The adhesive layer AL may include an optically transparent adhesive, an optically transparent adhesive resin, and / or a pressure sensitive adhesive (PSA).

[0067] The display module DM may further include a driver chip DIC and sensor chips SIC1 and SIC2. In one or more embodiments of the present disclosure, the driver chip DIC and the sensor chips SIC1 and SIC2 may be mounted on the display panel DP. The driver chip DIC and the sensor chips SIC1 and SIC2 may be arranged adjacent to one end portion (hereinafter referred to as the first end portion) of the display panel DP. Figure 2A, a structure in which the driver chip DIC and the sensor chips SIC1 and SIC2 are arranged adjacent to the first end of the display panel DP is shown, but the present disclosure is not limited thereto. For example, the driver chip DIC may be arranged adjacent to the first end of the display panel DP, and the sensor chips SIC1 and SIC2 may be arranged adjacent to the second end of the display panel DP that is opposite to the first end (e.g., opposite to the first end).

[0068] In one or more embodiments of the present disclosure, the sensor chips SIC1 and SIC2 may include a first sensor chip SIC1 disposed on one side (hereinafter referred to as the first side) of the driver chip DIC and a second sensor chip SIC2 disposed on a second side of the driver chip DIC different from the first side. However, alternatively, only one of the first sensor chip SIC1 and the second sensor chip SIC2 may be disposed on one side of the driver chip DIC. In the present disclosure, the number of sensor chips SIC1 and SIC2 and the number of driver chips DIC are not particularly limited.

[0069] The housing EDC is coupled to the window WM. The housing EDC is coupled to the window WM and provides an internal space (e.g., a predetermined internal space). The display module DM may be accommodated in the internal space. The housing EDC may include a material having relatively high rigidity. For example, the housing EDC may include glass, plastic, and / or metal, or may include a plurality of frames and / or plates formed by a combination thereof. The housing EDC may stably protect the components of the display device DD accommodated in the internal space from external impacts. Although not shown, a battery module for supplying power required for the overall operation of the display device DD may be arranged between the display module DM and the housing EDC.

[0070] Figure 3 is a block diagram of a display device according to one or more embodiments of the present disclosure.

[0071] Reference Figure 3 The display device DD includes a display panel DP, a panel driver and a driving controller 100. In one or more embodiments of the present disclosure, the panel driver includes a data driver 200, a scan driver 300, an emission driver 350, a voltage generator 400 and a readout circuit 500.

[0072] The driving controller 100 receives the image signal RGB and the control signal CTRL. The driving controller 100 generates the image data DATA by converting the data format of the image signal RGB according to the specification of the interface with the data driver 200. The driving controller 100 outputs the first control signal SCS, the second control signal ECS, the third control signal DCS and the fourth control signal RCS.

[0073] The data driver 200 receives the third control signal DCS and the image data DATA from the driving controller 100. The data driver 200 converts the image data DATA into a data signal and outputs the data signal to a plurality of data lines DL1 to DLm to be described below. The data signal is an analog voltage corresponding to the grayscale value of the image data DATA. In one or more embodiments of the present disclosure, the data driver 200 may be embedded in Figure 2A The driver chip shown in DIC.

[0074] The scan driver 300 receives a first control signal SCS from the driving controller 100. The scan driver 300 may output a scan signal to the scan line in response to the first control signal SCS.

[0075] The voltage generator 400 generates voltages required for operation of the display panel DP. In one or more embodiments, the voltage generator 400 generates a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage Vint, a second initialization voltage Vaint, a bias voltage Vbias, and a reset voltage Vrst.

[0076] The display panel DP may include ( Figure 1 The display area DA corresponding to the transmission area TA and the display area DA corresponding to the transmission area TA Figure 1 The border area BZA shown in FIG. 1 corresponds to the non-display area NDA.

[0077] The display panel DP may include a plurality of pixels PX arranged in the display area DA and a plurality of sensors FX arranged in the display area DA. In one or more embodiments of the present disclosure, each of the plurality of sensors FX may be arranged between two pixels PX adjacent to each other. The plurality of pixels PX and the plurality of sensors FX may be arranged alternately along the first direction DR1 and the second direction DR2. However, the present disclosure is not limited thereto. That is, two or more pixels PX may be arranged between two sensors FX adjacent to each other in the first direction DR1 among the plurality of sensors FX, or two or more pixels PX may be arranged between two sensors FX adjacent to each other in the second direction DR2 among the plurality of sensors FX.

[0078] The display panel DP further includes initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, emission control lines EML1 to EMLn, data lines DL1 to DLm, and readout lines RL1 to RLh. The initialization scan lines SIL1 to SILn, the compensation scan lines SCL1 to SCLn, the write scan lines SWL1 to SWLn, the black scan lines SBL1 to SBLn, and the emission control lines EML1 to EMLn extend in the first direction DR1. The initialization scan lines SIL1 to SILn, the compensation scan lines SCL1 to SCLn, the write scan lines SWL1 to SWLn, the black scan lines SBL1 to SBLn, and the emission control lines EML1 to EMLn are arranged to be spaced apart from each other along the second direction DR2. The data lines DL1 to DLm and the readout lines RL1 to RLh extend in the second direction DR2 and are arranged to be spaced apart from each other along the first direction DR1. Here, "n", "m", and "h" are natural numbers of 1 or more.

[0079] The plurality of pixels PX are electrically connected to initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn, black scan lines SBL1 to SBLn, emission control lines EML1 to EMLn, and data lines DL1 to DLm, respectively. For example, each of the plurality of pixels PX may be electrically connected to four scan lines. However, this is not limited thereto, and the number of scan lines connected to each pixel PX may vary.

[0080] The plurality of sensors FX are electrically connected to the write scan lines SWL1 to SWLn and the readout lines RL1 to RLh, respectively. Each of the plurality of sensors FX may be electrically connected to one scan line. However, the present disclosure is not limited thereto. The number of scan lines connected to each sensor FX may vary. In one or more embodiments of the present disclosure, the number of readout lines RL1 to RLh may be less than or equal to the number of data lines DL1 to DLm. For example, the number of readout lines RL1 to RLh may correspond to 1 / 2, 1 / 4, or 1 / 8 of the number of data lines DL1 to DLm.

[0081] The scan driver 300 may be arranged in the non-display area NDA of the display panel DP. The scan driver 300 receives a first control signal SCS from the drive controller 100. In response to the first control signal SCS, the scan driver 300 outputs an initialization scan signal to the initialization scan lines SIL1 to SILn, and outputs a compensation scan signal to the compensation scan lines SCL1 to SCLn. In addition, in response to the first control signal SCS, the scan driver 300 may output a write scan signal to the write scan lines SWL1 to SWLn, and may output a black scan signal to the black scan lines SBL1 to SBLn. Alternatively, the scan driver 300 may include a first scan driver and a second scan driver. The first scan driver may output an initialization scan signal and a compensation scan signal, and the second scan driver may output a write scan signal and a black scan signal.

[0082] The emission driver 350 may be arranged in the non-display area NDA of the display panel DP. The emission driver 350 receives the second control signal ECS from the drive controller 100. The emission driver 350 may output the emission control signal to the emission control lines EML1 to EMLn in response to the second control signal ECS. Alternatively, the scan driver 300 may be connected to the emission control lines EML1 to EMLn. In this case, the emission driver 350 may be omitted, and the scan driver 300 may output the emission control signal to the emission control lines EML1 to EMLn.

[0083] The readout circuit 500 receives the fourth control signal RCS from the driving controller 100. In response to the fourth control signal RCS, the readout circuit 500 may receive the detection signal from the readout lines RL1 to RLh. The readout circuit 500 may process the detection signal received from the readout lines RL1 to RLh, and may provide the processed detection signal S_FS to the driving controller 100. The driving controller 100 may recognize the biological information based on the processed detection signal S_FS. In one or more embodiments of the present disclosure, the readout circuit 500 may be embedded in Figure 2A The sensor chips SIC1 and SIC2 are shown in FIG.

[0084] Figure 4A is a circuit diagram showing a pixel and a sensor according to one or more embodiments of the present disclosure, and Figure 4B It is used to explain Figure 4A The waveform diagram of the pixel and sensor operation is shown in FIG.

[0085] exist Figure 4A In the Figure 31 is an equivalent circuit diagram of one pixel PXij among the plurality of pixels PX shown in . Each of the plurality of pixels PX has the same circuit structure. Therefore, the description of the circuit structure of the pixel PXij is applicable to the remaining pixels, and the detailed description of the remaining pixels will be omitted. Figure 4A In the Figure 3 . The plurality of sensors FX have the same circuit structure. Therefore, the description of the circuit structure of the sensor FXdj is applicable to the remaining sensors, and the detailed description of the remaining sensors will be omitted.

[0086] Reference Figure 4A , the pixel PXij is connected to the i-th data line DLi among the data lines DL1 to DLm, the j-th initialization scan line SILj among the initialization scan lines SIL1 to SILn, the j-th compensation scan line SCLj among the compensation scan lines SCL1 to SCLn, the j-th write scan line SWLj among the write scan lines SWL1 to SWLn, the j-th black scan line SBLj among the black scan lines SBL1 to SBLn, and the j-th emission control line EMLj among the emission control lines EML1 to EMLn.

[0087] The pixel PXij includes a light emitting element ED and a pixel driving circuit P_PD. The light emitting element ED may be a light emitting diode. In one or more embodiments of the present disclosure, the light emitting element ED may be an organic light emitting diode (OLED) including an organic light emitting layer.

[0088] The pixel driving circuit P_PD includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8 and a capacitor Cst. At least one of the first transistor T1 to the eighth transistor T8 may be a transistor having a low temperature polycrystalline silicon (LTPS) semiconductor layer. Some of the first transistor T1 to the eighth transistor T8 may be P-type transistors, while the others may be N-type transistors. At least one of the first transistor T1 to the eighth transistor T8 may be a transistor having an oxide semiconductor layer. For example, the third transistor T3 and the fourth transistor T4 may be oxide semiconductor transistors, and the first transistor T1, the second transistor T2 and the fifth transistor T5 to the eighth transistor T8 may be LTPS transistors. The third transistor T3 and the fourth transistor T4 may be NMOS transistors.

[0089] The configuration of the pixel driving circuit P_PD according to the present disclosure is not limited to Figure 4A The embodiment shown in . Figure 4AThe pixel driving circuit P_PD shown in FIG. 1 is only an example, and various changes and modifications may be made to the configuration of the pixel driving circuit P_PD. For example, the first transistor T1 to the eighth transistor T8 may all be P-type transistors or N-type transistors.

[0090] The jth initialization scan line SILj, the jth compensation scan line SCLj, the jth write scan line SWLj, the jth black scan line SBLj, and the jth emission control line EMLj can transmit the jth initialization scan signal SIj, the jth compensation scan signal SCj, the jth write scan signal SWj, the jth black scan signal SBj, and the jth emission control signal EMj to the pixel PXij, respectively. The i-th data line DLi transmits the i-th data signal Di to the pixel PXij. The i-th data signal Di may have a signal similar to that input to the display device DD (refer to Figure 3 ) of the image signal RGB (refer to Figure 3 ) corresponds to the voltage level.

[0091] In one or more embodiments of the present disclosure, the pixel PXij may be connected to a first driving voltage line VL1 and a second driving voltage line VL2, a first initialization voltage line VIL and a second initialization voltage line VAIL, and a bias voltage line VBL. The first driving voltage line VL1 may transmit a first driving voltage ELVDD to the pixel PXij, and the second driving voltage line VL2 may transmit a second driving voltage ELVSS to the pixel PXij. In addition, the first initialization voltage line VIL may transmit a first initialization voltage Vint to the pixel PXij, and the second initialization voltage line VAIL may transmit a second initialization voltage Vaint to the pixel PXij. The bias voltage line VBL may transmit a bias voltage Vbias to the pixel PXij.

[0092] The first transistor T1 is connected between the first driving voltage line VL1 receiving the first driving voltage ELVDD and the light emitting element ED. The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 via a fifth transistor T5, a second electrode connected to the anode of the light emitting element ED via a sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to one end of the capacitor Cst (e.g., the first node N1). The first transistor T1 can receive the i-th data signal Di transmitted by the i-th data line DLi according to the switching operation of the second transistor T2, and can supply the driving current Id to the light emitting element ED.

[0093] The second transistor T2 is connected between the i-th data line DLi and the first electrode of the first transistor T1. The second transistor T2 includes a first electrode connected to the i-th data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th write scan line SWLj. The second transistor T2 may be turned on in response to a j-th write scan signal SWj transmitted through the j-th write scan line SWLj, and may transmit an i-th data signal Di transmitted from the i-th data line DLi to the first electrode of the first transistor T1.

[0094] The third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 includes a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th compensation scan line SCLj. The third transistor T3 may be turned on in response to the j-th compensation scan signal SCj transmitted through the j-th compensation scan line SCLj, and may be diode-connected to the first transistor T1 by connecting the third electrode and the second electrode of the first transistor T1 to each other.

[0095] The fourth transistor T4 is connected between the first initialization voltage line VIL to which the first initialization voltage Vint is applied and the first node N1. The fourth transistor T4 includes a first electrode connected to the first initialization voltage line VIL transmitting the first initialization voltage Vint, a second electrode connected to the first node N1, and a third electrode (e.g., a gate electrode) connected to the jth initialization scan line SILj. The fourth transistor T4 is turned on in response to the jth initialization scan signal SIj transmitted through the jth initialization scan line SILj. The turned-on fourth transistor T4 initializes the potential of the third electrode (e.g., the gate electrode) of the first transistor T1 (i.e., the potential of the first node N1) by transmitting the first initialization voltage Vint to the first node N1.

[0096] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (eg, a gate electrode) connected to the j-th emission control line EMLj.

[0097] The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode of the light emitting element ED, and a third electrode (eg, a gate electrode) connected to the jth emission control line EMLj.

[0098] The fifth transistor T5 and the sixth transistor T6 are simultaneously (e.g., synchronously) turned on in response to the jth emission control signal EMj transmitted through the jth emission control line EMLj. The first driving voltage ELVDD applied by the turned-on fifth transistor T5 can be compensated by the first transistor T1 connected in a diode manner, and then can be transmitted to the light emitting element ED.

[0099] The seventh transistor T7 includes a first electrode connected to a second initialization voltage line VAIL transmitting a second initialization voltage Vaint, a second electrode connected to the second electrode of the sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to the j-th black scan line SBLj. The second initialization voltage Vaint may have a voltage level lower than or equal to the voltage level of the first initialization voltage Vint.

[0100] The eighth transistor T8 includes a first electrode connected to a bias voltage line VBL transmitting a bias voltage Vbias, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (eg, a gate electrode) connected to the j-th black scan line SBLj.

[0101] The seventh transistor T7 and the eighth transistor T8 are simultaneously (e.g., synchronously) turned on in response to the jth black scan signal SBj transmitted through the jth black scan line SBLj. The second initialization voltage Vaint applied by the turned-on seventh transistor T7 may be transmitted to the anode of the light emitting element ED. Therefore, the anode of the light emitting element ED may be initialized to the second initialization voltage Vaint. The bias voltage Vbias applied by the turned-on eighth transistor T8 may be transmitted to the first electrode of the first transistor T1. Therefore, the bias voltage Vbias may be periodically applied to the first electrode of the first transistor T1. As a result, the degradation of the display quality caused by the potential difference between the first electrode and the second electrode of the first transistor T1 increasing to a level (e.g., a predetermined level) or higher due to the hysteresis phenomenon may be prevented or reduced.

[0102] As described above, one end of the capacitor Cst is connected to the third electrode (e.g., the first node N1) of the first transistor T1, and the opposite end of the capacitor Cst is connected to the first driving voltage line VL1. The cathode of the light emitting element ED may be connected to the second driving voltage line VL2 transmitting the second driving voltage ELVSS. The second driving voltage ELVSS may have a voltage level lower than the voltage level of the first driving voltage ELVDD. In one or more embodiments of the present disclosure, the second driving voltage ELVSS may have a voltage level lower than the voltage levels of the first initialization voltage Vint and the second initialization voltage Vaint.

[0103] Reference Figure 4A and Figure 4B, the j-th emission control signal EMj has a high level during the non-light emission period NEP. During the non-light emission period NEP, the j-th initialization scan signal SIj is activated. When the j-th initialization scan signal SIj having a high level is provided through the j-th initialization scan line SILj during the activation period AP1 (hereinafter referred to as the first activation period) of the j-th initialization scan signal SIj, the fourth transistor T4 is turned on in response to the j-th initialization scan signal SIj having a high level. The first initialization voltage Vint is transmitted to the third electrode (e.g., the gate electrode) of the first transistor T1 through the turned-on fourth transistor T4, and the first node N1 is initialized to the first initialization voltage Vint. Therefore, the first activation period AP1 can be defined as the initialization period of the pixel PXij.

[0104] Next, when the jth compensation scan signal SCj is activated during an activation period AP2 (hereinafter referred to as a second activation period) of the jth compensation scan signal SCj and the jth compensation scan signal SCj having a high level is supplied through the jth compensation scan line SCLj, the third transistor T3 is turned on. The first transistor T1 is diode-connected by the turned-on third transistor T3 and is forward biased. The first activation period AP1 may not overlap with the second activation period AP2.

[0105] During the second activation period AP2, the jth write scan signal SWj is activated. The jth write scan signal SWj has a low level during the activation period AP4 (hereinafter referred to as the fourth activation period). During the fourth activation period AP4, the second transistor T2 is turned on by the jth write scan signal SWj having a low level. Then, the compensation voltage "Di-Vth" obtained by subtracting the threshold voltage (Vth) of the first transistor T1 from the i-th data signal Di supplied by the i-th data line DLi is applied to the third electrode of the first transistor T1. That is, the potential of the third electrode of the first transistor T1 may be the compensation voltage "Di-Vth". The fourth activation period AP4 may overlap with the second activation period AP2. The duration of the second activation period AP2 may be greater than the duration of the fourth activation period AP4.

[0106] The first driving voltage ELVDD and the compensation voltage "Di-Vth" may be applied to opposite ends of the capacitor Cst, and charges corresponding to the difference between the voltages at the opposite ends of the capacitor Cst may be stored in the capacitor Cst. Here, the period in which the j-th compensation scan signal SCj has a high level may be referred to as a compensation period of the pixel PXij.

[0107] In one or more embodiments, the jth black scan signal SBj is activated in the second activation period AP2 of the jth compensation scan signal SCj. The jth black scan signal SBj has a low level during the activation period AP3 (hereinafter referred to as the third activation period). During the third activation period AP3, the seventh transistor T7 is turned on by receiving the jth black scan signal SBj having a low level via the jth black scan line SBLj. A portion of the drive current Id may escape through the seventh transistor T7 as a bypass current Ibp. The third activation period AP3 may overlap with the second activation period AP2. The duration of the second activation period AP2 may be greater than the duration of the third activation period AP3. The third activation period AP3 may be before the fourth activation period AP4 and may not overlap with the fourth activation period AP4.

[0108] When the pixel PXij displays a black image, if the light-emitting element ED emits light even if the minimum driving current of the first transistor T1 flows as the driving current Id, the pixel PXij cannot display the black image normally. Therefore, the seventh transistor T7 in the pixel PXij according to one or more embodiments of the present disclosure can allocate a part of the minimum driving current of the first transistor T1 as a bypass current Ibp to a current path other than the current path toward the light-emitting element ED. Here, the minimum driving current of the first transistor T1 means the current flowing to the first transistor T1 under the condition that the gate-source voltage of the first transistor T1 is lower than the threshold voltage so that the first transistor T1 is turned off. The minimum driving current (for example, a current of about 10pA or less) flowing to the first transistor T1 under the condition that the first transistor T1 is turned off is transmitted to the light-emitting element ED and displays a black grayscale image. When the pixel PXij displays a black image, the bypass current Ibp has a relatively large effect on the minimum driving current, while when the pixel PXij displays an image such as a general image or a white image, the bypass current Ibp has a small effect on the driving current Id. Therefore, when the pixel PXij displays a black image, the current obtained by subtracting the bypass current Ibp escaped by the seventh transistor T7 from the driving current Id (i.e., the light emission current Ied) can be provided to the light emitting element ED, so that the pixel PXij clearly represents the black image. Therefore, the pixel PXij can use the seventh transistor T7 to achieve an accurate black grayscale image, thereby improving the contrast.

[0109] Thereafter, the j-th emission control signal EMj supplied from the j-th emission control line EMLj changes from a high level to a low level. The fifth transistor T5 and the sixth transistor T6 are turned on in response to the j-th emission control signal EMj having a low level. Then, a driving current Id depending on the difference between the voltage of the third electrode of the first transistor T1 and the first driving voltage ELVDD is generated. The driving current Id is supplied to the light emitting element ED through the sixth transistor T6, and the light emission current Ied flows through the light emitting element ED.

[0110] Refer again Figure 4A The sensor FXdj is connected to the dth readout line RLd, the jth write scan line SWLj, and the reset control line SRL among the readout lines RL1 to RLh.

[0111] The sensor FXdj includes a light receiving element OPD and a sensor driving circuit O_SD. In one or more embodiments of the present disclosure, the light receiving element OPD may be an organic photodiode including an organic material as a photoelectric conversion layer. Figure 4A , a structure in which the sensor FXdj includes one light receiving element OPD is shown. However, the present disclosure is not limited thereto. For example, the sensor FXdj may include a plurality of light receiving elements OPD connected in parallel.

[0112] The anode of the light receiving element OPD may be connected to the first sensing node SN1, and the cathode of the light receiving element OPD may be connected to the second driving voltage line VL2 transmitting the second driving voltage ELVSS. The cathode of the light receiving element OPD may be electrically connected to the cathode of the light emitting element ED. In one or more embodiments of the present disclosure, the cathode of the light receiving element OPD may be integrally formed with the cathode of the light emitting element ED, and a common cathode C_CE may be formed (refer to Figure 6 ).

[0113] The sensor driving circuit O_SD includes three transistors ST1, ST2 and ST3. The three transistors ST1, ST2 and ST3 may include a reset transistor ST1, an amplifying transistor ST2 and an output transistor ST3. At least one of the reset transistor ST1, the amplifying transistor ST2 and the output transistor ST3 may be an oxide semiconductor transistor. In one or more embodiments of the present disclosure, the reset transistor ST1 may be an oxide semiconductor transistor, and the amplifying transistor ST2 and the output transistor ST3 may be LTPS transistors. However, not limited thereto, at least the reset transistor ST1 and the output transistor ST3 may be oxide semiconductor transistors, and the amplifying transistor ST2 may be an LTPS transistor.

[0114] In addition, some of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 may be P-type transistors, and the rest of them may be N-type transistors. In one or more embodiments of the present disclosure, the amplifying transistor ST2 and the output transistor ST3 may be PMOS transistors, and the reset transistor ST1 may be an NMOS transistor. However, not limited to this, the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 may all be N-type transistors or P-type transistors.

[0115] Some (e.g., reset transistor ST1) of the reset transistor ST1, the amplifying transistor ST2, and the output transistor ST3 may be transistors of the same type (e.g., the same kind) as the third transistor T3 and the fourth transistor T4 of the pixel PXij. The amplifying transistor ST2 and the output transistor ST3 may be transistors of the same type (e.g., the same kind) as the first transistor T1, the second transistor T2, and the fifth to eighth transistors T5 to T8 of the pixel PXij.

[0116] The circuit configuration of the sensor driving circuit O_SD according to the present disclosure is not limited to Figure 4A The circuit configuration shown in . Figure 4A The sensor driving circuit O_SD shown in FIG. 1 is merely illustrative, and various changes and modifications may be made to the configuration of the sensor driving circuit O_SD.

[0117] The reset transistor ST1 includes a first electrode receiving a reset voltage Vrst, a second electrode connected to the first sensing node SN1, and a third electrode receiving a reset control signal SR. The reset transistor ST1 may reset the potential of the first sensing node SN1 to the reset voltage Vrst in response to the reset control signal SR. The reset control signal SR may be a signal provided by a reset control line SRL. However, the present disclosure is not limited thereto. Alternatively, the reset control signal SR may be a jth compensation scan signal SCj supplied by a jth compensation scan line SCLj. That is, the reset transistor ST1 may receive the jth compensation scan signal SCj supplied from the jth compensation scan line SCLj as the reset control signal SR. In one or more embodiments of the present disclosure, at least during the activation period of the reset control signal SR, the reset voltage Vrst may have a voltage level lower than the voltage level of the second drive voltage ELVSS. The reset voltage Vrst may be transmitted to the sensor FXdj through the reset voltage line VRL. The reset voltage Vrst may be a DC voltage maintained at a voltage level lower than the voltage level of the second drive voltage ELVSS.

[0118] The reset transistor ST1 may include a plurality of sub-reset transistors connected in series. For example, the reset transistor ST1 may include two sub-reset transistors (hereinafter, referred to as a first sub-reset transistor and a second sub-reset transistor). In this case, a third electrode of the first sub-reset transistor and a third electrode of the second sub-reset transistor are connected to a reset control line SRL. In addition, a second electrode of the first sub-reset transistor and a first electrode of the second sub-reset transistor may be electrically connected to each other. In addition, a reset voltage Vrst may be applied to a first electrode of the first sub-reset transistor, and a second electrode of the second sub-reset transistor may be electrically connected to the first sensing node SN1. However, the number of sub-reset transistors is not limited thereto, and various modifications may be made.

[0119] The amplifier transistor ST2 includes a first electrode receiving a sensing drive voltage SLVD, a second electrode connected to the second sensing node SN2, and a third electrode connected to the first sensing node SN1. The amplifier transistor ST2 may be turned on in response to the potential of the first sensing node SN1, and the sensing drive voltage SLVD may be applied to the second sensing node SN2. In one or more embodiments of the present disclosure, the sensing drive voltage SLVD may be one of the first drive voltage ELVDD, the first initialization voltage Vint, and the second initialization voltage Vaint. When the sensing drive voltage SLVD is the first drive voltage ELVDD, the first electrode of the amplifier transistor ST2 may be electrically connected to the first drive voltage line VL1. When the sensing drive voltage SLVD is the first initialization voltage Vint, the first electrode of the amplifier transistor ST2 may be electrically connected to the first initialization voltage line VIL, and when the sensing drive voltage SLVD is the second initialization voltage Vaint, the first electrode of the amplifier transistor ST2 may be electrically connected to the second initialization voltage line VAIL.

[0120] The output transistor ST3 includes a first electrode connected to the second sensing node SN2, a second electrode connected to the dth readout line RLd, and a third electrode receiving an output control signal. In response to the output control signal, the output transistor ST3 can transmit the detection signal FSd to the dth readout line RLd. The output control signal can be the jth write scan signal SWj supplied through the jth write scan line SWLj. That is, the output transistor ST3 can receive the jth write scan signal SWj supplied from the jth write scan line SWLj as the output control signal.

[0121] The light receiving element OPD of the sensor FXdj may be exposed to light during the light emission period of the light emitting element ED. The light may be light output from the light emitting element ED.

[0122] If the user's hand US_F (refer to Figure 1 ) Touch display surface IS (refer to Figure 1), the light receiving element OPD generates a photocharge corresponding to the light reflected by the ridges of the fingerprint or the valleys between the ridges. The amount of current flowing through the light receiving element OPD changes according to the generated photocharge. When the light receiving element OPD receives the light reflected by the ridges of the fingerprint, the current flowing through the light receiving element OPD may be referred to as a first current, and when the light receiving element OPD receives the light reflected by the valleys of the fingerprint, the current flowing through the light receiving element OPD may be referred to as a second current. The amount of light reflected by the ridges of the fingerprint and the amount of light reflected by the valleys of the fingerprint are different from each other, and the difference between the amounts of light is expressed as the difference between the first current and the second current. When the first current flows through the light receiving element OPD, the potential of the first sensing node SN1 may be referred to as a first potential, and when the second current flows through the light receiving element OPD, the potential of the first sensing node SN1 may be referred to as a second potential. In one or more embodiments of the present disclosure, the first current may be greater than the second current. In this case, the first potential may be lower than the second potential.

[0123] The amplifying transistor ST2 may be a source follower amplifier that generates a source-drain current proportional to the potential of the first sensing node SN1 input to the third electrode of the amplifying transistor ST2 .

[0124] During the fourth activation period AP4, the jth write scan signal SWj having a low level is supplied to the output transistor ST3 through the jth write scan line SWLj. When the output transistor ST3 is turned on in response to the jth write scan signal SWj having a low level, the detection signal FSd corresponding to the current flowing through the amplifying transistor ST2 may be output to the dth readout line RLd.

[0125] When a reset control signal SR having a high level is supplied through the reset control line SRL during the reset period, the reset transistor ST1 is turned on. The reset period may be defined as an activation period (i.e., a high level period) of the reset control signal SR. Alternatively, when the reset transistor ST1 is implemented by a P-type transistor, a reset control signal SR having a low level may be supplied to the reset control line SRL during the reset period. During the reset period, the first sensing node SN1 may be reset to a potential corresponding to the reset voltage Vrst. In one or more embodiments of the present disclosure, the reset voltage Vrst may have a voltage level lower than the voltage level of the second drive voltage ELVSS.

[0126] When the reset period ends, the light receiving element OPD may generate photo charges corresponding to the received light, and the generated photo charges may be accumulated in the first sensing node SN1.

[0127] Figure 5 is a plan view of a display panel according to one or more embodiments of the present disclosure. For the convenience of description, the scanning lines are omitted, and Figure 5Only the readout lines and data lines are shown.

[0128] Reference Figure 5 The display panel DP includes a display area DA and a non-display area NDA. Figure 3 ) and multiple sensor FX (refer to Figure 3 ) are arranged in the display area DA. The driver chip DIC and the sensor chips SIC1 and SIC2 are mounted in the non-display area NDA.

[0129] Data lines DL1 to DLm (refer to Figure 3 ) are connected to a plurality of pixels PX in the display area DA, and are connected to a driver chip DIC in the non-display area NDA. Figure 3 ) is connected to a plurality of sensors FX in the display area DA, and is connected to sensor chips SIC1 and SIC2 in the non-display area NDA.

[0130] The data lines DL1 to DLm may be divided into a first group and a second group. The first group includes a plurality of first data lines DL_G1, and the second group includes a plurality of second data lines DL_G2. The plurality of first data lines DL_G1 are arranged along a first direction DR1, and the plurality of second data lines DL_G2 are arranged along the first direction DR1. The plurality of first data lines DL_G1 are spaced apart from the plurality of second data lines DL_G2 in the first direction DR1.

[0131] The plurality of first data lines DL_G1 are connected to the pixel driving circuit P_PD of the first group of pixels among the plurality of pixels PX (refer to Figure 4A ), and a plurality of second data lines DL_G2 are connected to a pixel driving circuit P_PD of a second group of pixels among a plurality of pixels PX. The first group of pixels and the first data line DL_G1 are arranged in the first area A1, and the second group of pixels and the second data line DL_G2 are arranged in the second area A2. The first area A1 includes a 1-1 area A1-1 defined on a first side of a center line parallel to the second direction DR2 relative to the display panel DP and a 1-2 area A1-2 defined on a second side relative to the center line. The second area A2 includes a 2-1 area A2-1 arranged between the 1-1 area A1-1 and the non-display area NDA and a 2-2 area A2-2 arranged between the 1-2 area A1-2 and the non-display area NDA.

[0132] The plurality of first data lines DL_G1 include 1-1 data lines DL1-11 to DL1-13 arranged in the 1-1 area A1-1 and 1-2 data lines DL1-21 to DL1-23 arranged in the 1-2 area A1-2. The plurality of second data lines DL_G2 include 2-1 data lines DL2-11 to DL2-13 arranged in the 2-1 area A2-1 and 2-2 data lines DL2-21 to DL2-23 arranged in the 2-2 area A2-2.

[0133] The 1-1st data lines DL1-11 to DL1-13 and the 1-2nd data lines DL1-21 to DL1-23 are connected to the driver chip DIC. Figure 5 An example is shown in which the 1-1 data lines DL1-11 to DL1-13 and the 1-2 data lines DL1-21 to DL1-23 are connected to the same driver chip DIC, but the present disclosure is not limited thereto. For example, the 1-1 data lines DL1-11 to DL1-13 and the 1-2 data lines DL1-21 to DL1-23 may be connected to different driver chips.

[0134] The display panel DP further includes data link lines connecting the second data lines DL_G2 to the driver chip DIC. The data link lines include a plurality of vertical data link lines V_DCL extending along the first data lines DL_G1 and a plurality of horizontal data link lines H_DCL extending in a first direction DR1.

[0135] The plurality of horizontal data link lines H_DCL include first horizontal data link lines H_DCL1 including H_DCL11 to H_DCL13 and second horizontal data link lines H_DCL2 including H_DCL21 to H_DCL23. The first horizontal data link lines H_DCL11 to H_DCL13 are connected to the 2-1 data lines DL2-11 to DL2-13, and the second horizontal data link lines H_DCL21 to H_DCL23 are connected to the 2-2 data lines DL2-21 to DL2-23. The plurality of vertical data link lines V_DCL include first vertical data link lines V_DCL1 including V_DCL11 to V_DCL13 and second vertical data link lines V_DCL2 including V_DCL21 to V_DCL23. The first vertical data link lines V_DCL11 to V_DCL13 are connected to the first horizontal data link lines H_DCL11 to H_DCL13 , and the second vertical data link lines V_DCL21 to V_DCL23 are connected to the second horizontal data link lines H_DCL21 to H_DCL23 .

[0136] Therefore, the first vertical data link lines V_DCL11 to V_DCL13 are electrically connected to the 2-1st data lines DL2-11 to DL2-13 through the first horizontal data link lines H_DCL11 to H_DCL13. The second vertical data link lines V_DCL21 to V_DCL23 are electrically connected to the 2-2nd data lines DL2-21 to DL2-23 through the second horizontal data link lines H_DCL21 to H_DCL23.

[0137] The first vertical data link lines V_DCL11 to V_DCL13 alternate with the 1-1 data lines DL1-11 to DL1-13 in the 1-1 area A1-1. The second vertical data link lines V_DCL21 to V_DCL23 alternate with the 1-2 data lines DL1-21 to DL1-23 in the 1-2 area A1-2.

[0138] Portions of a plurality of horizontal data link lines H_DCL (H_DCL1 and H_DCL2) and vertical data link lines V_DCL (V_DCL1 and V_DCL2) may be arranged in the display area DA. That is, portions of the data link lines for connecting the second data line DL_G2 and the driver chip DIC are arranged in the display area DA. Therefore, the area of ​​the area occupied by the data link lines in the non-display area NDA may be reduced, and thus the area of ​​the dead zone of the display panel DP may be reduced.

[0139] Figure 6 is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure.

[0140] Reference Figure 6 , the display panel DP may include a base layer BL, a circuit layer DP_CL and an element layer DP_ED.

[0141] The base layer BL may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. In particular, the synthetic resin layer may be a polyimide-based resin layer, and its material is not particularly limited. The synthetic resin layer may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane-based resin, cellulose resin, siloxane-based resin, polyamide resin, and perylene-based resin. In addition, the base layer BL may include a glass substrate, a metal substrate, and / or an organic and / or inorganic composite substrate.

[0142] At least one inorganic layer is formed on the upper surface of the base layer BL. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed of multiple layers. The plurality of inorganic layers may constitute a barrier layer BRL and / or a buffer layer BFL to be described below. The barrier layer BRL and the buffer layer BFL may be selectively arranged.

[0143] The circuit layer DP_CL may include a barrier layer BRL and / or a buffer layer BFL. The barrier layer BRL prevents penetration of foreign matter from the outside. The barrier layer BRL may include a silicon oxide layer and / or a silicon nitride layer. A plurality of silicon oxide layers and a plurality of silicon nitride layers may be provided. The silicon oxide layers and the silicon nitride layers may be alternately stacked on top of each other.

[0144] The buffer layer BFL may be disposed on the barrier layer BRL. The buffer layer BFL improves the coupling force between the base layer BL and the semiconductor pattern and / or the conductive pattern. The buffer layer BFL may include a silicon oxide layer and / or a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked on each other.

[0145] The semiconductor pattern is arranged on the buffer layer BFL. Hereinafter, the semiconductor pattern directly arranged on the buffer layer BFL is defined as a first semiconductor pattern. The first semiconductor pattern may include a silicon semiconductor. The first semiconductor pattern may include polycrystalline silicon. However, not limited thereto, the first semiconductor pattern may include amorphous silicon.

[0146] Figure 6 Only a portion of the first semiconductor pattern is shown, and the first semiconductor pattern may be additionally arranged in the pixel PXij (refer to Figure 4A ). The first semiconductor pattern has different electrical properties depending on whether the first semiconductor pattern is doped. The first semiconductor pattern may include a doped region and a non-doped region. The doped region may be doped with an N-type dopant or a P-type dopant. The P-type transistor includes a doped region doped with a P-type dopant, and the N-type transistor includes a doped region doped with an N-type dopant.

[0147] The doped region has a higher conductivity than that of the non-doped region and is substantially used as an electrode or a signal line. The non-doped region substantially corresponds to an active region (or a channel) of a transistor. In other words, a portion of the first semiconductor pattern may be an active region of a transistor, another portion may be a source or a drain of the transistor, and another portion may be a connection signal line (or a connection electrode).

[0148] like Figure 6 As shown in FIG. 1 , a first electrode S1 , a channel portion A1 , and a second electrode D1 of a first transistor T1 are formed of a first semiconductor pattern. The first electrode S1 and the second electrode D1 of the first transistor T1 extend from the channel portion A1 in opposite directions.

[0149] exist Figure 6 , a portion of a connection signal line CSL formed by a semiconductor pattern is shown. In one or more embodiments, the connection signal line CSL may be connected to the sixth transistor T6 (refer to Figure 4A )'s second electrode.

[0150] A first insulating layer 10 is disposed on the buffer layer BFL. The first insulating layer 10 is connected to a plurality of pixels PX (see Figure 3 ) overlap in common and cover the first semiconductor pattern. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In one or more embodiments, the first insulating layer 10 may be a single silicon oxide layer. Not only the first insulating layer 10, but also the insulating layer of the circuit layer DP_CL to be described below may also be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the above materials.

[0151] The third electrode G1 of the first transistor T1 is disposed on the first insulating layer 10. The third electrode G1 may be a first gate pattern layer GAT1 (refer to Fig. 15C The third electrode G1 of the first transistor T1 overlaps the channel portion A1 of the first transistor T1 in the third direction DR3. The third electrode G1 of the first transistor T1 may be used as a mask in a process of doping the first semiconductor pattern.

[0152] The second insulating layer 20 is arranged on the first insulating layer 10 and covers the third electrode G1 of the first transistor T1. The second insulating layer 20 overlaps the plurality of pixels PX in common. The second insulating layer 20 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. In one or more embodiments, the second insulating layer 20 may be a single silicon oxide layer.

[0153] An upper electrode UE may be disposed on the second insulating layer 20. The upper electrode UE may overlap the third electrode G1 of the first transistor T1 in the third direction DR3. The upper electrode UE may be a second gate pattern layer GAT2 (see Fig.15D ) or may be a portion of the doped semiconductor pattern. A portion of the third electrode G1 and the upper electrode UE overlapping the portion of the third electrode G1 may define a capacitor Cst (refer to Figure 4A ). In one or more embodiments of the present disclosure, the upper electrode UE may be omitted.

[0154] In one or more embodiments of the present disclosure, the second insulating layer 20 may be replaced with an insulating pattern. The upper electrode UE is disposed on the insulating pattern. The upper electrode UE may be used as a mask for forming the insulating pattern from the second insulating layer 20.

[0155] The third insulating layer 30 is arranged on the second insulating layer 20 and covers the upper electrode UE. In one or more embodiments, the third insulating layer 30 may be a single silicon oxide layer. The semiconductor pattern is arranged on the third insulating layer 30. Hereinafter, the semiconductor pattern directly arranged on the third insulating layer 30 is defined as the second semiconductor pattern. The second semiconductor pattern may include a metal oxide. The oxide semiconductor may include a crystalline or amorphous oxide semiconductor. For example, the oxide semiconductor may include a metal oxide of zinc (Zn), indium (In), gallium (Ga), tin (Sn) and / or titanium (Ti), or may include a mixture of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn) and / or titanium (Ti) and their oxides. The oxide semiconductor may include indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium zinc tin oxide (IZTO) and / or zinc tin oxide (ZTO).

[0156] Figure 6 Only a portion of the second semiconductor pattern is shown, and the second semiconductor pattern may be additionally arranged in another region of the pixel PXij. The second semiconductor pattern may include a plurality of regions distinguished according to whether the metal oxide is reduced. The region where the metal oxide is reduced (hereinafter referred to as the reduction region) has a higher conductivity than the region where the metal oxide is not reduced (hereinafter referred to as the non-reduction region). The reduction region is substantially used as an electrode or a signal line. The non-reduction region substantially corresponds to the channel portion of the transistor. In other words, a portion of the second semiconductor pattern may be the channel portion of the transistor, and another portion may be the first electrode or the second electrode of the transistor.

[0157] The circuit layer DP_CL may further include a pixel driving circuit P_PD (refer to Figure 4A ) of a plurality of semiconductor patterns and a sensor drive circuit O_SD (refer to Figure 4A) is a part of a plurality of semiconductor patterns. For the convenience of description, a semiconductor pattern of a third transistor T3 of a pixel driving circuit P_PD and a semiconductor pattern of a reset transistor ST1 of a sensor driving circuit O_SD are shown. A first electrode S3, a channel portion A3, and a second electrode D3 of the third transistor T3 are formed by a second semiconductor pattern, and a first electrode STS1, a channel portion STA1, and a second electrode STD1 of the reset transistor ST1 are formed by a second semiconductor pattern. In one or more embodiments of the present disclosure, the second semiconductor pattern may include a metal oxide. The first electrode S3, the second electrode D3, the first electrode STS1, and the second electrode STD1 include a metal reduced from a metal oxide semiconductor. The first electrode S3, the second electrode D3, the first electrode STS1, and the second electrode STD1 may include a metal layer having a suitable thickness (e.g., a predetermined thickness) from an upper surface of the second semiconductor pattern and including a reduced metal.

[0158] A fourth insulating layer 40 is disposed on the third insulating layer 30 to cover the first electrode S3, the channel portion A3, and the second electrode D3 of the third transistor T3 and the first electrode STS1, the channel portion STA1, and the second electrode STD1 of the reset transistor ST1. The third electrode G3 of the third transistor T3 and the third electrode STG1 of the reset transistor ST1 are disposed on the fourth insulating layer 40. In one or more embodiments, the third electrode G3 of the third transistor T3 and the third electrode STG1 of the reset transistor ST1 may be a third gate pattern layer GAT3 (refer to Fig.15F ). The third electrode G3 of the third transistor T3 overlaps the channel portion A3 of the third transistor T3 in the third direction DR3, and the third electrode STG1 of the reset transistor ST1 overlaps the channel portion STA1 of the reset transistor ST1 in the third direction DR3. Although one third electrode STG1 is shown in the present embodiment for convenience of description, the reset transistor ST1 may include two third electrodes.

[0159] The fifth insulating layer 50 is arranged on the fourth insulating layer 40 and covers the third electrode G3 of the third transistor T3 and the third electrode STG1 of the reset transistor ST1. In one or more embodiments, the fifth insulating layer 50 may include a silicon oxide layer and / or a silicon nitride layer. The fifth insulating layer 50 may include a plurality of silicon oxide layers and a plurality of silicon nitride layers alternately stacked on each other.

[0160] At least one insulating layer is additionally arranged on the fifth insulating layer 50. As in the present embodiment, a sixth insulating layer 60 and a seventh insulating layer 70 may be sequentially arranged on the fifth insulating layer 50. Each of the sixth insulating layer 60 and the seventh insulating layer 70 may be an organic layer, and may have a single layer structure or a multilayer structure. Each of the sixth insulating layer 60 and the seventh insulating layer 70 may be a single polyimide-based resin layer. Without being limited thereto, the sixth insulating layer 60 and the seventh insulating layer 70 may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane-based resin, cellulose resin, siloxane-based resin, polyamide resin, and perylene-based resin.

[0161] A first connection electrode CNE10 may be disposed on the fifth insulating layer 50. The first connection electrode CNE10 is connected to the connection signal line CSL through a first contact hole CH1 penetrating the first insulating layer 10 to the fifth insulating layer 50. The second connection electrode CNE20 may be connected to the first connection electrode CNE10 through a second contact hole CH2 penetrating the sixth insulating layer 60. In one or more embodiments of the present disclosure, at least one of the fifth insulating layer 50 to the seventh insulating layer 70 may be omitted, and one of the first connection electrode CNE10 and the second connection electrode CNE20 may be omitted.

[0162] A third connection electrode CNE11 may be additionally disposed on the fifth insulating layer 50. The third connection electrode CNE11 is connected to the second electrode STD1 of the reset transistor ST1 through a third contact hole CH3 penetrating the fourth insulating layer 40 and the fifth insulating layer 50. The fourth connection electrode CNE21 may be connected to the third connection electrode CNE11 through a fourth contact hole CH4 penetrating the sixth insulating layer 60.

[0163] The first link electrode CNE10 and the third link electrode CNE11 may be a first data pattern layer SD1 (refer to Figure 15G ), and the second connection electrode CNE20 and the fourth connection electrode CNE21 may be a second data pattern layer SD2 (refer to Fig.15H ) part.

[0164] Horizontal data connection line H_DCL (refer to Figure 5 ) may be arranged on the same layer (e.g., at the same layer) on which the first connection electrode CNE10 and the third connection electrode CNE11 are arranged (i.e., on the fifth insulating layer 50). However, the present disclosure is not limited thereto. The horizontal data link line H_DCL may be arranged on the same layer (e.g., at the same layer) on which the third electrode G1 of the first transistor T1 is arranged (i.e., on the first insulating layer 10).

[0165] The readout wiring RL may be arranged on the same layer (eg, at the same layer) as the layer on which the second connection electrode CNE20 and the fourth connection electrode CNE21 are arranged (ie, on the sixth insulating layer 60). The readout wiring RL may be Figure 3 The second and fourth connection electrodes CNE20 and CNE21 and the readout wiring RL are covered by the seventh insulating layer 70 .

[0166] The data wiring DL and the vertical data connection line V_DCL may be arranged on (eg, at) the seventh insulating layer 70. The data wiring DL may be Figure 3 , one of the data lines DL1 to DLm shown in . A fifth connection electrode CNE30 and a sixth connection electrode CNE31 may be additionally arranged on the seventh insulating layer 70. The fifth connection electrode CNE30 may be connected to the second connection electrode CNE20 through a fifth contact hole CH5 penetrating the seventh insulating layer 70. The sixth connection electrode CNE31 may be connected to the fourth connection electrode CNE21 through a sixth contact hole CH6 penetrating the seventh insulating layer 70. The data wiring DL and the vertical data connection line V_DCL may be arranged on the same layer (e.g., at the same layer) on which the fifth connection electrode CNE30 and the sixth connection electrode CNE31 are arranged (i.e., on the seventh insulating layer 70), but may be electrically insulated from each other. The data wiring DL, the vertical data connection line V_DCL, the fifth connection electrode CNE30, and the sixth connection electrode CNE31 are covered by the eighth insulating layer 80.

[0167] The element layer DP_ED is arranged on the circuit layer DP_CL. The element layer DP_ED may include a light emitting element ED (refer to Figure 4A ) of the anode P_AE and the light receiving element OPD (refer to Figure 4A ) of the anode O_AE. Figure 6 As shown in FIG. 1 , the anode P_AE of the light emitting element ED may be connected to the fifth connection electrode CNE30 through the seventh contact hole CH7 penetrating the eighth insulating layer 80. The anode O_AE of the light receiving element OPD may be connected to the sixth connection electrode CNE31 through the eighth contact hole CH8 penetrating the eighth insulating layer 80.

[0168] Despite Figure 6 , a structure in which the circuit layer DP_CL includes the fifth connection electrode CNE30 and the sixth connection electrode CNE31 is shown, but the present disclosure is not limited thereto. Alternatively, the fifth connection electrode CNE30 and the sixth connection electrode CNE31 may be omitted from the circuit layer DP_CL. In this case, the anode P_AE may be directly connected to the second connection electrode CNE20, and the anode O_AE may be directly connected to the fourth connection electrode CNE21.

[0169] The element layer DP_ED further includes a pixel defining layer PDL disposed on the circuit layer DP_CL. The pixel defining layer PDL may include a light emitting opening OP1 corresponding to the light emitting element ED and a light receiving opening OP2 corresponding to the light receiving element OPD. The light emitting opening OP1 exposes at least a portion of the anode P_AE of the light emitting element ED. The light emitting opening OP1 of the pixel defining layer PDL may define a light emitting area PXA. For example, a plurality of pixels PX (refer to Figure 3 ) may be arranged on the display panel DP (refer to Figure 3 ) on a plane (e.g., in a plan view). An area where a plurality of pixels PX are arranged may be defined as a pixel area, and one pixel area may include a light-emitting area PXA and a non-light-emitting area NPXA adjacent to the light-emitting area PXA. The non-light-emitting area NPXA may be around the light-emitting area PXA (e.g., may surround the light-emitting area PXA).

[0170] The light receiving opening OP2 exposes the anode O_AE of the light receiving element OPD. The light receiving opening OP2 of the pixel defining layer PDL may define a light receiving area SA. For example, a plurality of sensors FX (refer to Figure 3 ) may be arranged on a plane of the display panel DP (e.g., in a plan view) according to a rule (e.g., a predetermined rule). An area in which a plurality of sensors FX are arranged may be defined as a sensing area, and one sensing area may include a light receiving area SA and a non-light receiving area NSA adjacent to the light receiving area SA. The non-light receiving area NSA may be around the light receiving area SA (e.g., may surround the light receiving area SA).

[0171] The light emitting layer P_EL is arranged to correspond to the light emitting opening OP1 defined in the pixel defining layer PDL, and the photoelectric conversion layer O_RL is provided to correspond to the light receiving opening OP2 defined in the pixel defining layer PDL. Although a patterned light emitting layer P_EL is shown in the present embodiment, the present disclosure is not limited thereto. A common light emitting layer may be arranged in common for a plurality of pixels PX. In this case, the common light emitting layer may generate white light or blue light. A common cathode C_CE is arranged in common in the light emitting element ED and the light receiving element OPD. The common cathode C_CE may face the anode O_AE and the anode P_AE. The common cathode C_CE is arranged on the light emitting layer P_EL and the photoelectric conversion layer O_RL. The common cathode C_CE is arranged in common for a plurality of pixels PX and a plurality of sensors FX.

[0172] Figure 7 is an enlarged plan view showing a portion of a display panel according to one or more embodiments of the present disclosure. On a plane (eg, in a plan view), the conductive pattern and the semiconductor pattern of the display panel may be repeatedly arranged according to a rule (eg, a predetermined rule). Figure 7, some of the pixel driving circuits P_PD and some of the sensor driving circuits O_SD are shown.

[0173] The circuit layer DP_CL includes a plurality of reference circuit units RCU, and at least one sensor driving circuit O_SD and at least one pixel driving circuit P_PD are included in each of the reference circuit units RCU. Figure 7 , a structure is shown in which one sensor driving circuit O_SD and three pixel driving circuits P_PD are included in one reference circuit unit RCU. However, the number of sensor driving circuits O_SD and pixel driving circuits P_PD included in each reference circuit unit RCU is not particularly limited.

[0174] Reference Figure 5 and Figure 7 , the display area DA of the display panel DP (refer to Figure 3 ) can be divided into a first area A1 in which the first data line DL_G1 is arranged and a second area A2 in which the second data line DL_G2 is arranged. The first area A1 is an area in which vertical data link lines V_DCL1 and V_DCL2 connected to the second data line DL_G2 are arranged together with the first data line DL_G1.

[0175] exist Figure 7 , a portion of the 1-2 data lines DL1-21 to DL1-23, a portion of the 2-2 data lines DL2-21 to DL2-23, a portion of the second vertical data link line V_DCL2, and a portion of the second horizontal data link line H_DCL2 are shown. However, the 1-1 data lines DL1-11 to DL1-13, the 2-1 data lines DL2-11 to DL2-13, the first vertical data link line V_DCL1, and the first horizontal data link line H_DCL1 also have similar structures, and therefore repeated descriptions will be omitted.

[0176] In the 2-2 area A2-2, the data line DL2-23 among the 2-2 data lines DL2-21 to DL2-23 may be connected to the corresponding 2-3 horizontal data link line H_DCL23 among the second horizontal data link lines H_DCL21 to H_DCL23. In the 1-2 area A1-2, the 2-3 horizontal data link line H_DCL23 may be connected to the corresponding 2-3 vertical data link line V_DCL23 among the second vertical data link lines V_DCL21 to V_DCL23.

[0177] Fig. 8A yes Figure 7 is an enlarged view of the portion AA1 shown in FIG. Figure 8B is along Fig. 8A A cross-sectional view taken along line II' shown in FIG. Fig. 9A yes Figure 7 is an enlarged view of the portion BB1 shown in FIG. Fig. 9B is along Fig. 9A A cross-sectional view taken along line II-II' shown in FIG.

[0178] Reference Figure 7 , Fig. 8A and Figure 8B , the second horizontal data link lines H_DCL21 to H_DCL23 are arranged on a layer different from the layer on which the 1-2 data lines DL1-21 to DL1-23 are arranged. The second horizontal data link lines H_DCL21 to H_DCL23 are arranged on a layer different from the layer on which the second vertical data link lines V_DCL21 to V_DCL23 are arranged. The 1-2 data lines DL1-21 to DL1-23 and the second vertical data link lines V_DCL21 to V_DCL23 are arranged on the same layer (e.g., at the same layer).

[0179] The 2-3rd horizontal data link line H_DCL23 is arranged on the fifth insulating layer 50 , but the 2-3rd vertical data link line V_DCL23 and the 1-2nd data lines DL1 - 21 to DL1 - 23 are arranged on the seventh insulating layer 70 .

[0180] In the 1-2 area A1-2, the 2-3 horizontal data link line H_DCL23 may be electrically connected to the 2-3 vertical data link line V_DCL23 through the first data bridge electrode D_BCE1. The first data bridge electrode D_BCE1 may be disposed on the sixth insulating layer 60. The first data bridge electrode D_BCE1 is directly connected to the 2-3 horizontal data link line H_DCL23 through the first data bridge contact hole D_BCNT1 provided in the sixth insulating layer 60. The 2-3 vertical data link line V_DCL23 is directly connected to the first data bridge electrode D_BCE1 through the second data bridge contact hole D_BCNT2 provided in the seventh insulating layer 70.

[0181] In one or more embodiments of the present disclosure, the 2nd-3rd horizontal data link line H_DCL23 includes a first horizontal line portion G1_HCL arranged on the first insulating layer 10 and a second horizontal line portion D1_HCL arranged on the fifth insulating layer 50. The first horizontal line portion G1_HCL and the second horizontal line portion D1_HCL partially overlap each other on a plane (e.g., in a plan view). The second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 are interposed between the first horizontal line portion G1_HCL and the second horizontal line portion D1_HCL. The second horizontal line portion D1_HCL can be connected to the first horizontal line portion G1_HCL through a contact hole CNT1 formed through the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50.

[0182] The reset voltage line VRL and the readout wiring RL may be arranged on the sixth insulating layer 60, and the shielding reset wiring RSE may be arranged on the seventh insulating layer 70. The shielding reset wiring RSE may overlap the reset voltage line VRL and the readout wiring RL on a plane (e.g., in a plan view). The data line DL1-23 and the readout wiring RL may be arranged between the shielding reset wiring RSE and the 2nd-3rd vertical data link line V_DCL23.

[0183] The shield reset wiring RSE can shield the readout wiring RL so that the detection signal output from the readout wiring RL is not coupled with the data signal. Therefore, the sensor FX (see Figure 3 ) sensing accuracy.

[0184] Reference Figure 7 , Fig. 9A and Fig. 9B , in the 2-2 area A2-2, the 2-3 horizontal data link line H_DCL23 may be electrically connected to the corresponding data line DL2-23 through the second data bridging electrode D_BCE2. The second data bridging electrode D_BCE2 may be disposed on the sixth insulating layer 60. The second data bridging electrode D_BCE2 is directly connected to the 2-3 horizontal data link line H_DCL23 through the third data bridging contact hole D_BCNT3 provided in the sixth insulating layer 60. The data line DL2-23 is directly connected to the second data bridging electrode D_BCE2 through the fourth data bridging contact hole D_BCNT4 provided in the seventh insulating layer 70.

[0185] The first data bridge contact hole D_BCNT1 and the third data bridge contact hole D_BCNT3 are formed through the same patterning process, and the second data bridge contact hole D_BCNT2 and the fourth data bridge contact hole D_BCNT4 are formed through the same patterning process.

[0186] Fig.10is a plan view of a display panel according to one or more embodiments of the present disclosure. For the convenience of description, the scanning lines are omitted, and Fig.10 Only the data lines and readout lines are shown. Fig.10 The data lines shown in Figure 5 The structure of the data line shown in FIG. 1 is the same as that of FIG. 1 , and thus repeated description will be omitted.

[0187] Reference Fig.10 , read lines RL1 to RLh (refer to Figure 3 ) is connected to a plurality of sensors FX in the display area DA of the display panel DPa (refer to Figure 3 ), and is connected to the sensor chips SIC1 and SIC2 in the non-display area NDA.

[0188] The readout lines RL1 to RLh may be divided into a first group and a second group. The first group includes a plurality of first readout lines RL_G1, and the second group includes a plurality of second readout lines RL_G2. The plurality of first readout lines RL_G1 are arranged along a first direction DR1, and the plurality of second readout lines RL_G2 are arranged along the first direction DR1. The plurality of first readout lines RL_G1 are spaced apart from the plurality of second readout lines RL_G2 in the first direction DR1.

[0189] The plurality of first readout lines RL_G1 are connected to the sensor drive circuit O_SD of the first group of sensors among the plurality of sensors FX (see Figure 4A ), and the plurality of second readout lines RL_G2 are connected to the sensor driving circuit O_SD of the second group of sensors among the plurality of sensors FX. The first group of sensors and the first readout lines RL_G1 are arranged in the second area A2, and the second group of sensors and the second readout lines RL_G2 are arranged in the first area A1.

[0190] The plurality of first readout lines RL_G1 include 1-1st readout lines RL1-11 to RL1-13 and 1-2nd readout lines RL1-21 to RL1-23. The 1-1st readout lines RL1-11 to RL1-13 are arranged in the 2-1st area A2-1 and connected to the first sensor chip SIC1. The 1-2nd readout lines RL1-21 to RL1-23 are arranged in the 2-2nd area A2-2 and connected to the second sensor chip SIC2.

[0191] The plurality of second readout lines RL_G2 include 2-1st readout lines RL2-11 to RL2-13 and 2-2nd readout lines RL2-21 to RL2-23. The 2-1st readout lines RL2-11 to RL2-13 are arranged in the 1-1st area A1-1 and are electrically connected to the first sensor chip SIC1. The 2-2nd readout lines RL2-21 to RL2-23 are arranged in the 1-2nd area A1-2 and are electrically connected to the second sensor chip SIC2. The plurality of second readout lines RL_G2 may be arranged between the 1-1st readout lines RL1-11 to RL1-13 and the 1-2nd readout lines RL1-21 to RL1-23.

[0192] The display panel DPa further includes connection lines electrically connected to the second readout lines RL_G2. The connection lines include a plurality of vertical connection lines V_RL extending along the first readout lines RL_G1 and a plurality of horizontal connection lines H_RL extending in the first direction DR1. The vertical connection lines V_RL may include a first vertical connection line V_RL1 electrically connected to the first sensor chip SIC1 and a second vertical connection line V_RL2 electrically connected to the second sensor chip SIC2.

[0193] The first vertical connection line V_RL1 including V_RL11 to V_RL13 may alternate with the 1-1th readout lines RL1-11 to RL1-13 in the first direction DR1. The second vertical connection line V_RL2 including V_RL21 to V_RL23 may alternate with the 1-2nd readout lines RL1-21 to RL1-23 in the first direction DR1.

[0194] The horizontal connection line H_RL electrically connects the vertical connection line V_RL to the second readout line RL_G2. The horizontal connection line H_RL includes a first horizontal connection line H_RL1 including H_RL11 to H_RL13 connecting the first vertical connection line V_RL1 to the 2-1st readout lines RL2-11 to RL2-13, respectively, and a second horizontal connection line H_RL2 including H_RL21 to H_RL23 connecting the second vertical connection line V_RL2 to the 2-2nd readout lines RL2-21 to RL2-23, respectively.

[0195] Portions of the plurality of horizontal connection lines H_RL and the vertical connection lines V_RL may be arranged in the display area DA. That is, portions of the connection lines for connecting the second readout line RL_G2 with the first and second sensor chips SIC1 and SIC2 are arranged in the display area DA. Therefore, the area of ​​the area occupied by the connection lines in the non-display area NDA may be reduced, and thus the area of ​​the dead zone of the display panel DPa may be reduced.

[0196] Fig.11is an enlarged plan view showing a portion of a display panel according to one or more embodiments of the present disclosure.

[0197] exist Fig.11 , a portion of the 1-2 readout lines RL1-21 to RL1-23, a portion of the 2-2 readout lines RL2-21 to RL2-23, a portion of the second vertical connection line V_RL2, and a portion of the second horizontal connection line H_RL2 are shown. However, the 1-1 readout lines RL1-11 to RL1-13, the 2-1 readout lines RL2-11 to RL2-13, the first vertical connection line V_RL1, and the first horizontal connection line H_RL1 also have similar structures, and therefore repeated descriptions will be omitted.

[0198] In the 1-2 area A1-2, the readout line RL2-23 among the 2-2 readout lines RL2-21 to RL2-23 may be connected to the corresponding 2-3 horizontal connection line H_RL23 among the second horizontal connection lines H_RL2. In the 1-2 area A1-2, the readout line RL2-22 among the 2-2 readout lines RL2-21 to RL2-23 may be connected to the corresponding 2-2 horizontal connection line H_RL22 among the second horizontal connection lines H_RL2 (for example, see Fig.10 In the 1-2 area A1-2, the readout line RL2-21 among the 2-2 readout lines RL2-21 to RL2-23 may be connected to the corresponding 2-1 horizontal connection line H_RL21 among the second horizontal connection lines H_RL2 (for example, see Fig.10 ).

[0199] In the 2-2nd area A2-2, the 2-3rd horizontal connection line H_RL23 may be connected to the corresponding 2-3rd vertical connection line V_RL23 among the second vertical connection lines V_RL2. In the 2-2nd area A2-2, the 2-2nd horizontal connection line H_RL22 may be connected to the corresponding 2-2nd vertical connection line V_RL22 among the second vertical connection lines V_RL2 (for example, see Fig.10 In the 2-2 area A2-2, the 2-1st horizontal connection line H_RL21 may be connected to the corresponding 2-1st vertical connection line V_RL21 among the second vertical connection lines V_RL2 (for example, see Fig.10 ).

[0200] Fig. 12A yes Fig.11 is an enlarged view of portion AA2 shown in FIG. Fig. 12B is along Fig. 12A A cross-sectional view taken along line III-III' shown in FIG. Fig.13A yes Fig.11 is an enlarged view of the portion BB2 shown in FIG. Fig. 13Bis along Fig.13A A cross-sectional view taken along line IV-IV' shown in FIG.

[0201] Reference Fig.11 , Fig. 12A and Fig. 12B The second horizontal connection line H_RL2 is arranged on a layer different from the layer on which the 2-2nd readout lines RL2-21 to RL2-23 are arranged. The second horizontal connection line H_RL2 is arranged on a layer different from the layer on which the second vertical connection line V_RL2 is arranged.

[0202] The 2-3rd horizontal connection line H_RL23 is disposed on the fifth insulating layer 50, but the 2-3rd vertical connection line V_RL23 is disposed on the seventh insulating layer 70. The 1-2nd readout lines RL1-21 to RL1-23 and the 2-2nd readout lines RL2-21 to RL2-23 are disposed on the sixth insulating layer 60.

[0203] In the 2-2 area A2-2, the 2-3 horizontal connection line H_RL23 may be electrically connected to the 2-3 vertical connection line V_RL23 through a bridge contact electrode BCE. The bridge contact electrode BCE may be disposed on the sixth insulating layer 60. The bridge contact electrode BCE is directly connected to the 2-3 horizontal connection line H_RL23 through a first bridge contact hole BCNT1 provided in the sixth insulating layer 60. The 2-3 vertical connection line V_RL23 is directly connected to the bridge contact electrode BCE through a second bridge contact hole BCNT2 provided in the seventh insulating layer 70.

[0204] Reference Fig.11 , Fig.13A and Fig. 13B In the 1-2 area A1-2, the 2-3rd horizontal connection line H_RL23 may be electrically connected to the corresponding readout line RL2-23. The readout line RL2-23 is directly connected to the 2-3rd horizontal connection line H_RL23 through a third bridge contact hole BCNT3 provided in the sixth insulating layer 60.

[0205] The first bridge contact hole BCNT1 and the third bridge contact hole BCNT3 may be formed by the same patterning process.

[0206] The shielding reset wiring RSE may be arranged above the readout lines RL1-23 and RL2-23. The shielding reset wiring RSE may overlap the readout lines RL1-23 and RL2-23 on a plane (eg, in a plan view). The data wiring DL may be arranged between the shielding reset wiring RSE and the second vertical connection line V_RL2.

[0207] The shield reset wiring RSE can shield the readout lines RL1-23 and RL2-23 so that the detection signals output from the readout lines RL1-23 and RL2-23 are not coupled with the data signal. Therefore, the sensor FX (refer to Figure 3 ) sensing accuracy.

[0208] Fig.14A is a plan view showing a 2-1 th initialization voltage line according to one or more embodiments of the present disclosure. Fig. 14B is a plan view showing a 2-2 th initialization voltage line according to one or more embodiments of the present disclosure. Fig. 14C is a plan view illustrating a first initialization voltage line according to one or more embodiments of the present disclosure. Fig.14D is a plan view illustrating a second driving voltage line according to one or more embodiments of the present disclosure.

[0209] The second initialization voltage line VAIL (refer to Figure 4A ) includes a 2-1st initialization voltage line VAIL1 and a 2-2nd initialization voltage line VAIL2. The 2-1st initialization voltage line VAIL1 is connected to Figure 3 At least one pixel among the multiple pixels PX shown in (specifically, the first light-emitting element of the first pixel), and the 2-2 initialization voltage line VAIL2 is connected to another pixel among the multiple pixels PX (for example, the second light-emitting element of the second pixel and the third light-emitting element of the third pixel). In one or more embodiments of the present disclosure, the first pixel includes a first light-emitting element configured to output a first color light (for example, red light), the second pixel includes a second light-emitting element configured to output a second color light (for example, green light), and the third pixel includes a third light-emitting element configured to output a third color light (for example, blue light).

[0210] Reference Fig.14A , the 2-1st initialization voltage line VAIL1 includes the 2-1st horizontal initialization voltage line H_VAIL1 and the 2-1st vertical initialization voltage line V_VAIL1. The 2-1st horizontal initialization voltage line H_VAIL1 extends in the first direction DR1, and the 2-1st vertical initialization voltage line V_VAIL1 extends in the second direction DR2. Therefore, the 2-1st initialization voltage line VAIL1 may be arranged in the display panel DP (refer to Figure 3 ) display area DA (refer to Figure 3 )middle.

[0211] The 2-1st horizontal initialization voltage line H_VAIL1 and the 2-1st vertical initialization voltage line V_VAIL1 may be arranged on different layers. For example, the 2-1st horizontal initialization voltage line H_VAIL1 may be arranged on the fourth insulating layer 40 (refer to Figure 6), and the 2-1st vertical initialization voltage line V_VAIL1 may be arranged on the seventh insulating layer 70 (refer to Figure 6 ). The 2-1st horizontal initialization voltage line H_VAIL1 and the 2-1st vertical initialization voltage line V_VAIL1 may be electrically connected to each other through the 2-1st connection pattern C_VAIL1. The 2-1st connection pattern C_VAIL1 may be disposed on the sixth insulating layer 60 (refer to Figure 6 ) and may be used as a bridge electrically connecting the 2-1st horizontal initialization voltage line H_VAIL1 and the 2-1st vertical initialization voltage line V_VAIL1.

[0212] Reference Fig. 14B , the 2-2 initialization voltage line VAIL2 includes a 2-2 horizontal initialization voltage line H_VAIL2 and a 2-2 vertical initialization voltage line V_VAIL2. The 2-2 horizontal initialization voltage line H_VAIL2 extends in the first direction DR1, and the 2-2 vertical initialization voltage line V_VAIL2 extends in the second direction DR2. Therefore, the 2-2 initialization voltage line VAIL2 may be arranged in the form of a grid on the display panel DP (refer to Figure 3 ) display area DA (refer to Figure 3 )middle.

[0213] The 2-2nd horizontal initialization voltage line H_VAIL2 and the 2-2nd vertical initialization voltage line V_VAIL2 may be arranged on different layers. For example, the 2-2nd horizontal initialization voltage line H_VAIL2 may be arranged on the fourth insulating layer 40 (refer to Figure 6 ), and the 2-2nd vertical initialization voltage line V_VAIL2 may be arranged on the seventh insulating layer 70 (refer to Figure 6 The 2-2nd horizontal initialization voltage line H_VAIL2 and the 2-2nd vertical initialization voltage line V_VAIL2 may be electrically connected to each other through the 2-2nd connection pattern C_VAIL2. The 2-2nd connection pattern C_VAIL2 may be disposed on the sixth insulating layer 60 (refer to Figure 6 ) and may be used as a bridge electrically connecting the 2-2nd horizontal initialization voltage line H_VAIL2 and the 2-2nd vertical initialization voltage line V_VAIL2.

[0214] Reference Fig.14A and Fig. 14B , the 2-1st horizontal initialization voltage line H_VAIL1 and the 2-2nd horizontal initialization voltage line H_VAIL2 may be arranged on the same layer (e.g., the fourth insulating layer 40) (e.g., at the same layer). However, the present disclosure is not limited thereto. The 2-1st horizontal initialization voltage line H_VAIL1 and the 2-2nd horizontal initialization voltage line H_VAIL2 may be arranged on different layers.

[0215] The 2-1st vertical initialization voltage line V_VAIL1 and the 2-2nd vertical initialization voltage line V_VAIL2 may be arranged on (e.g., at) the same layer (e.g., the seventh insulating layer 70). The 2-1st vertical initialization voltage line V_VAIL1 and the 2-2nd vertical initialization voltage line V_VAIL2 may be spaced apart from each other in the first direction DR1. At least two columns of the pixel driving circuits P_PD and one column of the sensor driving circuits O_SD may be arranged between the 2-1st vertical initialization voltage line V_VAIL1 and the 2-2nd vertical initialization voltage line V_VAIL2.

[0216] Reference Fig. 14C , the first initialization voltage line VIL includes a first horizontal initialization voltage line H_VIL and a first vertical initialization voltage line V_VIL. The first horizontal initialization voltage line H_VIL extends in a first direction DR1, and the first vertical initialization voltage line V_VIL extends in a second direction DR2. Therefore, the first initialization voltage lines VIL may be arranged in a grid form on the display panel DP (refer to Figure 3 ) display area DA (refer to Figure 3 )middle.

[0217] The first horizontal initialization voltage line H_VIL and the first vertical initialization voltage line V_VIL may be arranged on different layers. For example, the first horizontal initialization voltage line H_VIL may be arranged on the fifth insulating layer 50 (refer to Figure 6 ), and the first vertical initialization voltage line V_VIL may be arranged on the seventh insulating layer 70 (refer to Figure 6 ). The first horizontal initialization voltage line H_VIL and the first vertical initialization voltage line V_VIL may be electrically connected to each other through the first connection pattern C_VIL. The first connection pattern C_VIL may be arranged on the sixth insulating layer 60 (refer to Figure 6 ) and may serve as a bridge electrically connecting the first horizontal initialization voltage line H_VIL and the first vertical initialization voltage line V_VIL.

[0218] Reference Fig.14D , the second driving voltage line VL2 includes a horizontal driving voltage line H_VL2 and a vertical driving voltage line V_VL2. The horizontal driving voltage line H_VL2 extends in the first direction DR1, and the vertical driving voltage line V_VL2 extends in the second direction DR2. Therefore, the second driving voltage line VL2 may be arranged in a grid form on the display panel DP (refer to Figure 3 ) display area DA (refer to Figure 3 )middle.

[0219] The horizontal driving voltage line H_VL2 and the vertical driving voltage line V_VL2 may be arranged on different layers. For example, the horizontal driving voltage line H_VL2 may be arranged on the second insulating layer 20 (refer to Figure 6 ), and the vertical driving voltage line V_VL2 may be arranged on the seventh insulating layer 70 (refer to Figure 6 ). The horizontal driving voltage line H_VL2 and the vertical driving voltage line V_VL2 may be electrically connected to each other through the second connection pattern C_VL2. The second connection pattern C_VL2 may be arranged on the sixth insulating layer 60 (refer to Figure 6 ) and can be used as a bridge member that electrically connects the horizontal driving voltage line H_VL2 and the vertical driving voltage line V_VL2.

[0220] Reference FIG. 14A to FIG. 14D , the 2-1st vertical initialization voltage line V_VAIL1, the 2-2nd vertical initialization voltage line V_VAIL2, the first vertical initialization voltage line V_VIL, and the vertical driving voltage line V_VL2 may be arranged on the same layer (e.g., the seventh insulating layer 70) (e.g., at the same layer). The 2-1st vertical initialization voltage line V_VAIL1, the 2-2nd vertical initialization voltage line V_VAIL2, the first vertical initialization voltage line V_VIL, and the vertical driving voltage line V_VL2 may be spaced apart from each other in the first direction DR1. At least two columns of the pixel driving circuit P_PD may be arranged between the first vertical initialization voltage line V_VIL and the 2-2nd vertical initialization voltage line V_VAIL2. At least two columns of the pixel driving circuit P_PD and at least one column of the sensor driving circuit O_SD may be arranged between the vertical driving voltage line V_VL2 and the first vertical initialization voltage line V_VIL.

[0221] exist FIG. 14A to FIG. 14D , a structure is shown in which the 2-1st vertical initialization voltage line V_VAIL1, the 2-2nd vertical initialization voltage line V_VAIL2, the first vertical initialization voltage line V_VIL, and the vertical driving voltage line V_VL2 are sequentially arranged along the first direction DR1. However, the arrangement order of the voltage lines is not limited thereto and may be modified in various ways.

[0222] As described above, since the display panel DP (refer to Figure 3 ) are arranged in a grid structure, so that the voltage can be uniformly supplied to the entire display area DA of the display panel DP (refer to Figure 3 In particular, since the voltage lines connected to the sensor are arranged in a grid structure, it is possible to prevent the voltage applied to the sensor FX (refer to Figure 3 ) voltage drop resulting in degradation of sensing accuracy.

[0223] FIG. 15A to FIG. 15Iis a plan view showing the arrangement order of circuit layers according to one or more embodiments of the present disclosure.

[0224] Reference FIG. 15A to FIG. 15I , the conductive patterns and the semiconductor patterns may be repeatedly arranged on a plane according to a rule (eg, a predetermined rule). FIG. 15A to FIG. 15I , some of the pixel driving circuits P_PD and some of the sensor driving circuits O_SD are shown.

[0225] Circuit layer DP_CL (refer to Figure 6 ) may include a first reference circuit unit RCU1 and a second reference circuit unit RCU2. The first reference circuit unit RCU1 and the second reference circuit unit RCU2 may be symmetrical to each other with respect to a reference line parallel to the second direction DR2. The first reference circuit unit RCU1 and the second reference circuit unit RCU2 may be alternately arranged along the first direction DR1. At least one sensor driving circuit O_SD and at least one pixel driving circuit P_PD are included in each of the first reference circuit unit RCU1 and the second reference circuit unit RCU2. FIG. 15A to FIG. 15I , a structure in which one sensor driving circuit O_SD and three pixel driving circuits P_PD are included in one reference circuit unit RCU1 or RCU2 is shown. However, the number of sensor driving circuits O_SD and pixel driving circuits P_PD included in each reference circuit unit RCU1 or RCU2 is not particularly limited.

[0226] Despite FIG. 15A to FIG. 15I , the first reference circuit unit RCU1 and the second reference circuit unit RCU2 are shown symmetrical to each other (eg, mirror images of each other), but the circuit layer DP_CL may have a structure in which the first reference circuit unit RCU1 is repeated or a structure in which the second reference circuit unit RCU2 is repeated.

[0227] Reference Fig.15A A light-blocking pattern layer BML may be formed on the buffer layer BFL. The light-blocking pattern layer BML may be a conductive pattern having a function of blocking light. The light-blocking pattern layer BML may be arranged between transistors T1 to T8 (refer to Figure 4A ) and can block light incident from the outside to the transistors T1 to T8.

[0228] Reference Fig.15A and Fig. 15B, a first semiconductor pattern layer ACT1 may be arranged on the light blocking pattern layer BML and the buffer layer BFL. The first semiconductor pattern layer ACT1 may overlap the light blocking pattern layer BML on the buffer layer BFL. The first semiconductor pattern layer ACT1 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon and / or polycrystalline silicon. For example, the first semiconductor pattern layer ACT1 may include low temperature polycrystalline silicon (LTPS).

[0229] The first semiconductor pattern layer ACT1 includes a first semiconductor pattern P_ACT1 included in the pixel driving circuit P_PD and a second semiconductor pattern S_ACT1 included in the sensor driving circuit O_SD.

[0230] Reference Fig. 15C , the first gate pattern layer GAT1 may be arranged on the first insulating layer 10. The first gate pattern layer GAT1 may include a metal, an alloy, a conductive metal oxide, and / or a transparent conductive material. For example, the first gate pattern layer GAT1 may include silver (Ag), an alloy including silver, molybdenum (Mo), an alloy including molybdenum, aluminum (Al), an alloy including aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), and / or indium zinc oxide (IZO), but is not particularly limited thereto.

[0231] The first gate pattern layer GAT1 may include a first gate wiring SBL, a second gate wiring EML, a third gate wiring SWL, a first gate electrode GE1, and a second gate electrode GE2.

[0232] Each of the first gate wiring SBL, the second gate wiring EML, and the third gate wiring SWL may extend in the first direction DR1. The first gate wiring SBL corresponds to Figure 4A For example, the j-th black scan signal SBj (refer to Figure 4A ) may be provided to the first gate wiring SBL. The first gate wiring SBL may constitute together with the first semiconductor pattern P_ACT1 Figure 4A The seventh transistor T7.

[0233] The second gate wiring EML corresponds to Figure 4A For example, the j-th emission control signal EMj (refer to Figure 4A ) may be provided to the second gate wiring EML. The second gate wiring EML may constitute together with the first semiconductor pattern P_ACT1 Figure 4A The fifth transistor T5 and the sixth transistor T6.

[0234] The third gate wiring SWL corresponds to Figure 4A For example, the j-th write scan signal SWj (refer to Figure 4A ) may be provided to the third gate wiring SWL. The third gate wiring SWL may constitute together with the first semiconductor pattern P_ACT1 Figure 4A The second transistor T2 and the second semiconductor pattern S_ACT1 may constitute Figure 4A The output transistor ST3.

[0235] The first gate electrode GE1 and the second gate electrode GE2 may be arranged in an island shape. The first gate electrode GE1 may constitute a first semiconductor pattern P_ACT1 together with the first gate electrode GE1. Figure 4A The first gate electrode GE1 may correspond to the first transistor T1. Figure 6 The second gate electrode GE2 may constitute a third electrode G1 of the first transistor T1 shown in FIG. Figure 4A Amplifying transistor ST2.

[0236] The first gate pattern layer GAT1 further includes a first horizontal line portion G1_HCL. The first horizontal line portion G1_HCL may extend in the first direction DR1. In one or more embodiments of the present disclosure, the first horizontal line portion G1_HCL may have a structure extending to overlap with two pixel driving circuits P_PD. The first horizontal line portion G1_HCL may be included in the horizontal data connection line H_DCL (refer to Figure 5 ) in the components.

[0237] Reference Fig. 15C and Fig.15D The second insulating layer 20 may cover the first gate pattern layer GAT1 and may be disposed on the first insulating layer 10. The second gate pattern layer GAT2 may be disposed on the second insulating layer 20. The second gate pattern layer GAT2 may include metal, alloy, conductive metal oxide and / or transparent conductive material.

[0238] The second gate pattern layer GAT2 may include a fourth gate wiring G2_SRL, a fifth gate wiring G2_SCL, a sixth gate wiring G2_SIL, a capacitor electrode CSE, and a horizontal driving voltage line H_VL2.

[0239] The fourth gate wiring G2_SRL, the fifth gate wiring G2_SCL, and the sixth gate wiring G2_SIL may extend in the first direction DR1. The fourth gate wiring G2_SRL corresponds to the reset control line SRL (refer to Figure 4A ) (or included in the reset control line SRL). The fifth gate wiring G2_SCL may correspond to the j-th compensation scan line SCLj (refer to Figure 4A ) (or may be included in the j-th compensation scan line SCLj). The sixth gate wiring G2_SIL may correspond to the j-th initialization scan line SILj (refer to Figure 4A)(or may be included in the jth initialization scan line SILj).

[0240] The capacitor electrode CSE may overlap with the first gate electrode GE1 and may be arranged in an island shape. For example, the capacitor electrode CSE may constitute a capacitor Cst together with the first gate electrode GE1 (refer to Figure 4A ). The capacitor electrode CSE may correspond to Figure 6 An opening CSE_OP penetrating the capacitor electrode CSE may be formed in the capacitor electrode CSE, and the first gate electrode GE1 may be partially exposed through the opening CSE_OP.

[0241] The horizontal driving voltage line H_VL2 may extend in the first direction DR1. The horizontal driving voltage line H_VL2 may include Figure 4A The second driving voltage line VL2 is connected to the second driving voltage line VL2. The second driving voltage ELVSS (refer to Figure 4A ) can be applied to the horizontal driving voltage line H_VL2.

[0242] Reference Fig.15D and Fig.15E , the third insulating layer 30 may cover the second gate pattern layer GAT2 and may be arranged on the second insulating layer 20. A second semiconductor pattern layer ACT2 may be arranged on the third insulating layer 30. The second semiconductor pattern layer ACT2 may include an oxide semiconductor. The second semiconductor pattern layer ACT2 may be arranged in a different layer from the first semiconductor pattern layer ACT1 and may not overlap with the first semiconductor pattern layer ACT1.

[0243] The second semiconductor pattern layer ACT2 includes a third semiconductor pattern P_ACT2 included in the pixel driving circuit P_PD and a fourth semiconductor pattern S_ACT2 included in the sensor driving circuit O_SD.

[0244] Reference FIG. 15E to FIG. 15G The fourth insulating layer 40 may cover the second semiconductor pattern layer ACT2 and may be disposed on the third insulating layer 30. The third gate pattern layer GAT3 may be disposed on the fourth insulating layer 40. The third gate pattern layer GAT3 may include metal, alloy, conductive metal oxide and / or transparent conductive material.

[0245] The third gate pattern layer GAT3 may include seventh to eighth gate wirings G3_SRL to G3_SCL to G3_SIL to 2-1st and 2-2nd horizontal initialization voltage lines H_VAIL1 and H_VAIL2. The 2-1st and 2-2nd horizontal initialization voltage lines H_VAIL1 and H_VAIL2 may be referred to as second horizontal initialization voltage lines.

[0246] The seventh gate wiring G3_SRL, the eighth gate wiring G3_SCL, and the ninth gate wiring G3_SIL may extend in the first direction DR1. The seventh gate wiring G3_SRL may overlap the fourth semiconductor pattern S_ACT2. The seventh gate wiring G3_SRL may constitute a semiconductor pattern S_ACT2 together with the fourth semiconductor pattern S_ACT2. Figure 4A The seventh gate wiring G3_SRL can be connected to the reset transistor ST1. Fig.15D The fourth gate wiring G2_SRL shown in FIG. 1 is electrically connected to the gate wiring G2_SRL.

[0247] The eighth gate wiring G3_SCL may overlap the fifth gate wiring G2_SCL and the third semiconductor pattern P_ACT2. In one or more embodiments, the eighth gate wiring G3_SCL may contact the fifth gate wiring G2_SCL through a contact portion. Therefore, the j-th compensation scan signal SCj applied to the fifth gate wiring G2_SCL may be provided to the eighth gate wiring G3_SCL. The fifth gate wiring G2_SCL, the third semiconductor pattern P_ACT2, and the eighth gate wiring G3_SCL may constitute Figure 4A The third transistor T3.

[0248] The ninth gate wiring G3_SIL may overlap the sixth gate wiring G2_SIL and the third semiconductor pattern P_ACT2. The ninth gate wiring G3_SIL may be electrically connected to the sixth gate wiring G2_SIL. The j-th initialization scan signal SIj may be provided to the ninth gate wiring G3_SIL through the sixth gate wiring G2_SIL. The sixth gate wiring G2_SIL, the third semiconductor pattern P_ACT2, and the ninth gate wiring G3_SIL may constitute Figure 4A The fourth transistor T4.

[0249] The 2-1st horizontal initialization voltage line H_VAIL1 and the 2-2nd horizontal initialization voltage line H_VAIL2 are included in the second initialization voltage line VAIL (refer to Figure 4A ). The 2-1st horizontal initialization voltage line H_VAIL1 is connected to Figure 3 , and the 2-2 th horizontal initialization voltage line H_VAIL2 is connected to the second pixel and the third pixel among the plurality of pixels PX.

[0250] The 2-1st horizontal initialization voltage line H_VAIL1 applies the 2-1st initialization voltage to the first pixel as the second initialization voltage Vaint (refer to Figure 4A ), and the 2-2nd horizontal initialization voltage line H_VAIL2 applies the 2-2nd initialization voltage to the second pixel and the third pixel as the second initialization voltage Vaint. The 2-2nd initialization voltage may have a voltage level different from that of the 2-1st initialization voltage.

[0251] Reference Fig.15F and Figure 15G , the fifth insulating layer 50 may cover at least a portion of the third gate pattern layer GAT3 and may be disposed on the fourth insulating layer 40. The first data pattern layer SD1 may be disposed on the fifth insulating layer 50. The first data pattern layer SD1 may include, for example, a metal, an alloy, a conductive metal oxide, and / or a transparent conductive material. Figure 15G Only some of the components included in the first data pattern layer SD1 are shown in FIG.

[0252] The first data pattern layer SD1 may include a horizontal reset voltage line H_VRL, a bias voltage line VBL, a first horizontal initialization voltage line H_VIL, and a plurality of first connection electrode patterns C_CNE1.

[0253] The horizontal reset voltage line H_VRL, the bias voltage line VBL, and the first horizontal initialization voltage line H_VIL may extend in the first direction DR1. The horizontal reset voltage line H_VRL, the bias voltage line VBL, and the first horizontal initialization voltage line H_VIL may be spaced apart from each other in the second direction DR2.

[0254] The horizontal reset voltage line H_VRL may be included in Figure 4A The reset voltage Vrst (refer to Figure 4A ) can be provided to the horizontal reset voltage line H_VRL. The horizontal reset voltage line H_VRL can be electrically connected to the reset transistor ST1. The reset transistor ST1 can receive the reset voltage Vrst through the horizontal reset voltage line H_VRL. The bias voltage line VBL can correspond to Figure 4A The bias voltage line VBL. Figure 4A ) may be provided to a bias voltage line VBL. The bias voltage line VBL may be connected to the eighth transistor T8 through a contact portion. The eighth transistor T8 may receive a bias voltage Vbias through the bias voltage line VBL.

[0255] The first horizontal initialization voltage line H_VIL may include Figure 4A The first initialization voltage Vint (refer to Figure 4A ) can be provided to the first horizontal initialization voltage line H_VIL. The first horizontal initialization voltage line H_VIL can be connected to the fourth transistor T4 through the contact portion. The fourth transistor T4 can receive the first initialization voltage Vint through the first horizontal initialization voltage line H_VIL.

[0256] The plurality of first connection electrode patterns C_CNE1 may make contact with one of the first semiconductor pattern P_ACT1, the second semiconductor pattern S_ACT1, the third semiconductor pattern P_ACT2, and the fourth semiconductor pattern S_ACT2. The plurality of first connection electrode patterns C_CNE1 may perform a function of electrically connecting one of the first semiconductor pattern P_ACT1, the second semiconductor pattern S_ACT1, the third semiconductor pattern P_ACT2, and the fourth semiconductor pattern S_ACT2 to other lines. The plurality of first connection electrode patterns C_CNE1 may be connected to one of the first semiconductor pattern P_ACT1, the second semiconductor pattern S_ACT1, the third semiconductor pattern P_ACT2, and the fourth semiconductor pattern S_ACT2 through a contact portion. The plurality of first connection electrode patterns C_CNE1 may include Figure 6 The first link electrode CNE10 and the third link electrode CNE11 are shown in FIG.

[0257] The first data pattern layer SD1 may further include a second horizontal line portion D1_HCL. The second horizontal line portion D1_HCL may extend in the first direction DR1. In one or more embodiments of the present disclosure, the second horizontal line portion D1_HCL may have a structure extending to overlap with one sensor driving circuit O_SD. The second horizontal line portion D1_HCL may include Figure 5 The opposite end of the second horizontal line portion D1_HCL may overlap with the first horizontal line portion G1_HCL. The opposite end of the second horizontal line portion D1_HCL may be connected to the overlapped first horizontal line portion G1_HCL. A horizontal data connection line H_DCL (refer to Figure 5 ) can be provided by connecting the first horizontal line portion G1_HCL and the second horizontal line portion D1_HCL.

[0258] Reference Figure 15G and Fig.15H , the sixth insulating layer 60 may cover at least a portion of the first data pattern layer SD1 and may be disposed on the fifth insulating layer 50. The second data pattern layer SD2 may be disposed on the sixth insulating layer 60. The second data pattern layer SD2 may include, for example, a metal, an alloy, a conductive metal oxide, and / or a transparent conductive material.

[0259] The second data pattern layer SD2 includes a readout wiring RL, a vertical reset voltage line V_VRL, a first driving voltage line VL1, and a plurality of connection patterns.

[0260] The readout wiring RL and the vertical reset voltage line V_VRL extend in the second direction DR2 and are spaced apart from each other in the first direction DR1. The readout wiring RL may correspond to Figure 3The readout wiring RL can be connected to the readout wiring RL1 to RLh shown in FIG. Figure 4A The sensor drive circuit O_SD (particularly, the output transistor ST3) shown in FIG.

[0261] The vertical reset voltage line V_VRL may be included in Figure 4A The vertical reset voltage line V_VRL may be connected to the horizontal reset voltage line H_VRL. Through the connection of the vertical reset voltage line V_VRL and the horizontal reset voltage line H_VRL, the reset voltage line VRL may have a mesh form.

[0262] The first driving voltage line VL1 may overlap with the pixel driving circuit P_PD. The first driving voltage line VL1 may correspond to Figure 4A The first driving voltage line VL1 is a first driving voltage line. The first driving voltage ELVDD (refer to Figure 4A ) can be provided to the first driving voltage line VL1. The first driving voltage line VL1 can be arranged in a grid form in the display area DA of the display panel DP (refer to Figure 3 ). The first driving voltage line VL1 can be connected to Figure 4A The fifth transistor T5 shown in FIG. 1 is connected to the capacitor Cst.

[0263] The plurality of connection patterns may include a 2-1st connection pattern C_VAIL1 , a 2-2nd connection pattern C_VAIL2 , a first connection pattern C_VIL, and a second connection pattern C_VL2 .

[0264] The second data pattern layer SD2 may further include a plurality of second connection electrode patterns C_CNE2. The plurality of second connection electrode patterns C_CNE2 may include Figure 6 The second link electrode CNE20 and the fourth link electrode CNE21 are shown in FIG.

[0265] The second data pattern layer SD2 may further include a first data bridge electrode D_BCE1 and a second data bridge electrode D_BCE2. The first data bridge electrode D_BCE1 performs a function of connecting the first horizontal line portion G1_HCL to the corresponding vertical data link line V_DCL. The second data bridge electrode D_BCE2 performs a function of connecting the second horizontal line portion D1_HCL to the corresponding data wiring DL.

[0266] Reference Fig.15H and Fig.15I The seventh insulating layer 70 may cover at least a portion of the second data pattern layer SD2 and may be disposed on the sixth insulating layer 60. A third data pattern layer SD3 may be disposed on the seventh insulating layer 70. The third data pattern layer SD3 may include, for example, metal, alloy, conductive metal oxide, and / or a transparent conductive material.

[0267] The third data pattern layer SD3 may include data wirings DL, vertical data link wirings D3_VCL, shielding reset wirings RSE, 2-1st vertical initialization voltage lines V_VAIL1, 2-2nd vertical initialization voltage lines V_VAIL2, first vertical initialization voltage lines V_VIL, vertical driving voltage lines V_VL2, and a plurality of third connection electrode patterns C_CNE3.

[0268] The data wiring DL, the vertical data connection wiring D3_VCL, the 2-1st vertical initialization voltage line V_VAIL1, the 2-2nd vertical initialization voltage line V_VAIL2, the first vertical initialization voltage line V_VIL, the vertical driving voltage line V_VL2, and the shielding reset wiring RSE may extend in the second direction DR2. The data wiring DL, the vertical data connection wiring D3_VCL, the 2-1st vertical initialization voltage line V_VAIL1, the 2-2nd vertical initialization voltage line V_VAIL2, the first vertical initialization voltage line V_VIL, the vertical driving voltage line V_VL2, and the shielding reset wiring RSE may be spaced apart from each other in the first direction DR1.

[0269] The data wiring DL may correspond to Figure 3 The data wiring DL can be connected to the data lines DL1 to DLm shown in FIG. Figure 4A The pixel driving circuit P_PD (particularly, the second transistor T2) shown in FIG. Figure 5 The vertical data connection wiring D3_VCL can be connected to Fig. 15C The first horizontal line portion G1_HCL and Figure 15G The second horizontal line portion D1_HCL shown in FIG. 1 is electrically connected.

[0270] The 2-1st vertical initialization voltage line V_VAIL1 and the 2-2nd vertical initialization voltage line V_VAIL2 may be referred to as second vertical initialization voltage lines. The 2-1st vertical initialization voltage line V_VAIL1 and the 2-2nd vertical initialization voltage line V_VAIL2 may be included in the second initialization voltage line VAIL (refer to Figure 4A ). The 2-1st vertical initialization voltage line V_VAIL1 is electrically connected to Fig.15F , and the 2-2nd vertical initialization voltage line V_VAIL2 is electrically connected to the 2-1st horizontal initialization voltage line H_VAIL1 shown in FIG. Fig.15F The 2-2 th horizontal initialization voltage line H_VAIL2 is shown in FIG.

[0271] The first vertical initialization voltage line V_VIL may include Figure 4AThe first vertical initialization voltage line V_VIL is connected to the first vertical initialization voltage line VIL. Figure 15G The first horizontal initialization voltage line H_VIL shown in FIG. 1 is electrically connected to the first horizontal initialization voltage line H_VIL.

[0272] The vertical driving voltage line V_VL2 may be included in Figure 4A The vertical driving voltage line V_VL2 is connected to the second driving voltage line VL2. Fig.15D The horizontal driving voltage line H_VL2 shown in FIG. 1 is electrically connected.

[0273] The shielding reset wiring RSE may extend in the second direction DR2. The shielding reset wiring RSE may extend along the readout wiring RL. On a plane (e.g., in a plan view), the shielding reset wiring RSE may overlap with the readout wiring RL. The shielding reset wiring RSE may make contact with the reset voltage line VRL through a contact portion. Therefore, the reset voltage applied to the reset voltage line VRL may be applied to the shielding reset wiring RSE.

[0274] The shielding reset wiring RSE may be arranged to partially cover the sensor driving circuit O_SD. In particular, the shielding reset wiring RSE may be arranged to cover the reset transistor ST1, the amplifying transistor ST2, and all or part of the output transistor ST3.

[0275] The plurality of third connection electrode patterns C_CNE3 may include Figure 6 The fifth connection electrode CNE30 and the sixth connection electrode CNE31 are shown in FIG.

[0276] FIG. 16A to FIG. 16D is a plan view showing the arrangement order of circuit layers according to one or more embodiments of the present disclosure. FIG. 16A to FIG. 16D Among the components shown in FIG. 15A to FIG. 15I The same components as those shown in FIG. 1 will be given the same reference numerals and detailed description thereof will be omitted.

[0277] Reference Fig.16A , the first gate pattern layer GAT1a may be disposed on the first insulating layer 10. The first gate pattern layer GAT1a may include a first gate wiring SBL, a second gate wiring EML, a third gate wiring SWL, a first gate electrode GE1, and a second gate electrode GE2.

[0278] and Fig. 15C Unlike the first gate pattern layer GAT1 shown in FIG. 1 , the first gate pattern layer GAT1 a does not further include a first horizontal line portion G1_HCL.

[0279] Reference Fig.16A and Fig. 16BThe second insulating layer 20 may cover the first gate pattern layer GAT1a and may be disposed on the first insulating layer 10. The second gate pattern layer GAT2 may be disposed on the second insulating layer 20. The second gate pattern layer GAT2 may include metal, alloy, conductive metal oxide and / or transparent conductive material.

[0280] The second gate pattern layer GAT2 may include a fourth gate wiring G2_SRL, a fifth gate wiring G2_SCL, a sixth gate wiring G2_SIL, a capacitor electrode CSE, and a horizontal driving voltage line H_VL2.

[0281] The second gate pattern layer GAT2 has Fig.15D The structure of the second gate pattern layer GAT2 shown in FIG.

[0282] Reference Fig. 16B and Fig. 16C The fourth insulating layer 40 may cover the second semiconductor pattern layer ACT2 (refer to Fig.15E ), and may be disposed on the third insulating layer 30. The third gate pattern layer GAT3 may be disposed on the fourth insulating layer 40. The third gate pattern layer GAT3 may include a seventh gate wiring G3_SRL, an eighth gate wiring G3_SCL, a ninth gate wiring G3_SIL, a 2-1st horizontal initialization voltage line H_VAIL1, and a 2-2nd horizontal initialization voltage line H_VAIL2. The third gate pattern layer GAT3 has Fig.15F The structure of the third gate pattern layer GAT3 shown in FIG.

[0283] Reference Fig. 16C and Fig.16D The fifth insulating layer 50 may cover at least a portion of the third gate pattern layer GAT3 and may be disposed on the fourth insulating layer 40. The first data pattern layer SD1a may be disposed on the fifth insulating layer 50.

[0284] The first data pattern layer SD1 a may include a horizontal reset voltage line H_VRL, a bias voltage line VBL, a first horizontal initialization voltage line H_VIL, and a plurality of first connection electrode patterns C_CNE1 .

[0285] The first data pattern layer SD1a may further include a horizontal data connection wiring D_HCL. The horizontal data connection wiring D_HCL may extend in the first direction DR1. The horizontal data connection wiring D_HCL may correspond to Figure 5 The horizontal data connection wiring D_HCL can be connected to Fig.15H The first data bridge electrode D_BCE1 and the second data bridge electrode D_BCE2 shown in FIG. Fig.15I The vertical data connection wiring D3_VCL shown in FIG. 1 is electrically connected.

[0286] Fig.17A and Fig. 17B is a cross-sectional view showing a light emitting element and a light receiving element of a display panel according to one or more embodiments of the present disclosure.

[0287] Reference Fig.17A and Fig. 17B , a first electrode layer is arranged on the circuit layer DP_CL. A pixel defining layer PDL is formed on the first electrode layer. The first electrode layer may include a red anode R_AE, a green anode G_AE, and a blue anode B_AE. The first light emitting opening OP1_1, the second light emitting opening OP1_2, and the third light emitting opening OP1_3 of the pixel defining layer PDL expose at least a portion of the red anode R_AE, the green anode G_AE, and the blue anode B_AE, respectively. In one or more embodiments of the present disclosure, the pixel defining layer PDL may further include a black material. The pixel defining layer PDL may further include a black organic dye / pigment, such as carbon black, aniline black, and / or the like. The pixel defining layer PDL may be formed by mixing a blue organic material and a black organic material. The pixel defining layer PDL may further include a liquid-repellent organic material.

[0288] like Fig.17A As shown in , the display panel DP may include a first emission area PXA-R, a second emission area PXA-G, and a third emission area PXA-B, and a first non-emission area NPXA-R, a second non-emission area NPXA-G, and a third non-emission area NPXA-B adjacent to the first emission area PXA-R, the second emission area PXA-G, and the third emission area PXA-B. The non-emission areas NPXA-R, NPXA-G, and NPXA-B may be around the corresponding emission areas PXA-R, PXA-G, and PXA-B, respectively (for example, may surround the corresponding emission areas PXA-R, PXA-G, and PXA-B). In one or more embodiments, the first emission area PXA-R is defined as a partial area corresponding to the red anode R_AE exposed by the first light emitting opening OP1_1. The second emission area PXA-G is defined as a partial area corresponding to the green anode G_AE exposed by the second light emitting opening OP1_2. The third emission region PXA-B is defined as a partial region corresponding to the blue anode B_AE exposed by the third light emitting opening OP1_3. A non-pixel region NPA may be defined between the first non-emission region NPXA-R, the second non-emission region NPXA-G, and the third non-emission region NPXA-B.

[0289] The emission layer may be arranged on the first electrode layer. The emission layer may include a red light emitting layer R_EL, a green light emitting layer G_EL, and a blue light emitting layer B_EL. The red light emitting layer R_EL, the green light emitting layer G_EL, and the blue light emitting layer B_EL may be arranged in regions corresponding to the first light emitting opening OP1_1, the second light emitting opening OP1_2, and the third light emitting opening OP1_3, respectively. The red light emitting layer R_EL, the green light emitting layer G_EL, and the blue light emitting layer B_EL may be formed to be separated from each other. Each of the red light emitting layer R_EL, the green light emitting layer G_EL, and the blue light emitting layer B_EL may include an organic material and / or an inorganic material. The red light emitting layer R_EL, the green light emitting layer G_EL, and the blue light emitting layer B_EL may generate a light beam having a suitable color (e.g., a predetermined color). For example, the red light emitting layer R_EL may generate red light, the green light emitting layer G_EL may generate green light, and the blue light emitting layer B_EL may generate blue light.

[0290] Although the patterned red light emitting layer R_EL, green light emitting layer G_EL and blue light emitting layer B_EL are shown in the present embodiment, one emission layer may be commonly arranged in the first emission region PXA-R, the second emission region PXA-G and the third emission region PXA-B. In this case, the emission layer may generate white light or blue light. In addition, the emission layer may have a multilayer structure called a series connection.

[0291] Each of the red light emitting layer R_EL, the green light emitting layer G_EL and the blue light emitting layer B_EL may include a low molecular weight organic material or a high molecular weight organic material as a light emitting material. Alternatively, each of the red light emitting layer R_EL, the green light emitting layer G_EL and the blue light emitting layer B_EL may include a quantum dot material as a light emitting material. The core of the quantum dot may be selected from II-VI group compounds, III-V group compounds, IV-VI group compounds, IV group elements, IV group compounds and / or combinations thereof.

[0292] A second electrode layer is arranged on the red light emitting layer R_EL, the green light emitting layer G_EL and the blue light emitting layer B_EL. The second electrode layer may include a red cathode R_CE, a green cathode G_CE and a blue cathode B_CE. The red cathode R_CE, the green cathode G_CE and the blue cathode B_CE may be electrically connected to each other. In one or more embodiments of the present disclosure, the red cathode R_CE, the green cathode G_CE and the blue cathode B_CE may be formed integrally. In this case, the red cathode R_CE, the green cathode G_CE and the blue cathode B_CE may be commonly arranged in the first emission area PXA-R, the second emission area PXA-G and the third emission area PXA-B, the first non-emission area NPXA-R, the second non-emission area NPXA-G and the third non-emission area NPXA-B and the non-pixel area NPA.

[0293] The element layer DP_ED may further include a light receiving element OPD. The light receiving element OPD may be a photodiode. The pixel defining layer PDL may further include a light receiving opening OP2 provided to correspond to the light receiving element OPD.

[0294] The light receiving element OPD may include a sensing anode O_AE, a photoelectric conversion layer O_RL, and a sensing cathode O_CE. The sensing anode O_AE and the first electrode layer may be arranged on the same layer (e.g., at the same layer). That is, the sensing anode O_AE may be arranged on the circuit layer DP_CL and may be formed simultaneously (e.g., synchronously) by the same process as the process of the red anode R_AE, the green anode G_AE, and the blue anode B_AE.

[0295] The light receiving opening OP2 of the pixel defining layer PDL exposes at least a portion of the sensing anode O_AE. The photoelectric conversion layer O_RL is arranged on the sensing anode O_AE exposed by the light receiving opening OP2. The photoelectric conversion layer O_RL may include an organic photosensitive material. The sensing cathode O_CE may be arranged on the photoelectric conversion layer O_RL. The sensing cathode O_CE may be formed simultaneously (e.g., synchronously) by the same process as the process of the red cathode R_CE, the green cathode G_CE, and the blue cathode B_CE. In one or more embodiments of the present disclosure, the sensing cathode O_CE may be formed integrally with the red cathode R_CE, the green cathode G_CE, and the blue cathode B_CE to form a common cathode C_CE (refer to Figure 6 ).

[0296] The encapsulation layer TFE is arranged on the element layer DP_ED. The encapsulation layer TFE includes at least an inorganic layer and / or an organic layer. In one or more embodiments of the present disclosure, the encapsulation layer TFE may include two inorganic layers and an organic layer arranged therebetween. In one or more embodiments of the present disclosure, the encapsulation layer TFE may include a plurality of inorganic layers and a plurality of organic layers alternately stacked on top of each other.

[0297] The inorganic layer protects the red light emitting element ED_R, the green light emitting element ED_G, the blue light emitting element ED_B and the light receiving element OPD from moisture / oxygen, and the organic layer protects the red light emitting element ED_R, the green light emitting element ED_G, the blue light emitting element ED_B and the light receiving element OPD from foreign matter such as dust particles. The inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer and / or an aluminum oxide layer, but is not particularly limited thereto. The organic layer may include an acrylic organic layer, but is not particularly limited thereto.

[0298] Display device DD (refer to Figure 1) includes an input sensing layer ISL disposed on the display panel DP and a color filter layer CFL disposed on the input sensing layer ISL.

[0299] The input sensing layer ISL may be directly disposed on the encapsulation layer TFE. The input sensing layer ISL includes a first conductive layer ICL1, an insulating layer IL, a second conductive layer ICL2, and a protective layer PL. The first conductive layer ICL1 may be disposed on the encapsulation layer TFE. Fig.17A and Fig. 17B A structure in which the first conductive layer ICL1 is directly arranged on the encapsulation layer TFE is shown, but the present disclosure is not limited thereto. The input sensing layer ISL may further include a basic insulating layer arranged between the first conductive layer ICL1 and the encapsulation layer TFE. In this case, the encapsulation layer TFE may be covered by the basic insulating layer, and the first conductive layer ICL1 may be arranged on the basic insulating layer. In one or more embodiments of the present disclosure, the basic insulating layer may include an inorganic insulating material.

[0300] The insulating layer IL may cover the first conductive layer ICL1. The second conductive layer ICL2 is disposed on the insulating layer IL. Fig.17A and Fig. 17B A structure in which the input sensing layer ISL includes the first conductive layer ICL1 and the second conductive layer ICL2 is shown, but the present disclosure is not limited thereto. For example, the input sensing layer ISL may include only one of the first conductive layer ICL1 and the second conductive layer ICL2.

[0301] The protective layer PL may be disposed on the second conductive layer ICL2. The protective layer PL may include an organic insulating material. The protective layer PL may be used to protect the first conductive layer ICL1 and the second conductive layer ICL2 from moisture / oxygen and may be used to protect the first conductive layer ICL1 and the second conductive layer ICL2 from foreign matter.

[0302] The color filter layer CFL may be arranged on the input sensing layer ISL. The color filter layer CFL may be arranged directly on the protection layer PL. The color filter layer CFL may include a first color filter CF_R, a second color filter CF_G, and a third color filter CF_B. The first color filter CF_R has a first color, the second color filter CF_G has a second color, and the third color filter CF_B has a third color. In one or more embodiments of the present disclosure, the first color may be red, the second color may be green, and the third color may be blue.

[0303] The color filter layer CFL may further include a dummy color filter DCF. In one or more embodiments of the present disclosure, when the area where the photoelectric conversion layer O_RL is arranged is defined as the sensing area SA and the area around the sensing area SA is defined as the non-sensing area NSA, the dummy color filter DCF may be arranged to correspond to the sensing area SA. The dummy color filter DCF may overlap the sensing area SA and the non-sensing area NSA. In one or more embodiments of the present disclosure, the dummy color filter DCF may have the same color as one of the first color filter CF_R, the second color filter CF_G, and the third color filter CF_B. In one or more embodiments of the present disclosure, the dummy color filter DCF may have the same green color as the second color filter CF_G.

[0304] The color filter layer CFL may further include a black matrix BM. The black matrix BM may be arranged to correspond to the non-pixel area NPA. The black matrix BM may be arranged to overlap with the first conductive layer ICL1 and the second conductive layer ICL2 in the third direction DR3 in the non-pixel area NPA. In one or more embodiments of the present disclosure, the black matrix BM may overlap with the non-pixel area NPA and the first non-emission area NPXA-R, the second non-emission area NPXA-G, and the third non-emission area NPXA-B. The black matrix BM may not overlap with the first emission area PXA-R, the second emission area PXA-G, and the third emission area PXA-B.

[0305] The color filter layer CFL may further include an outer coating OCL. The outer coating OCL may include an organic insulating material. The outer coating OCL may have a thickness sufficient to remove the steps between the first color filter CF_R, the second color filter CF_G, and the third color filter CF_B. Without any particular restrictions, the outer coating OCL may include any material having a suitable thickness (e.g., a predetermined thickness) and capable of flattening the upper surface of the color filter layer CFL. For example, the outer coating OCL may include an acrylate-based organic material.

[0306] Reference Fig. 17B , when the display device DD (refer to Figure 1 ) when operating, the red light emitting element ED_R, the green light emitting element ED_G, and the blue light emitting element ED_B can output light. The red light emitting element ED_R outputs red light in a red wavelength band, the green light emitting element ED_G outputs green light in a green wavelength band, and the blue light emitting element ED_B outputs blue light in a blue wavelength band.

[0307] In one or more embodiments of the present disclosure, the light receiving element OPD may receive light from a specific light emitting element (e.g., green light emitting element ED_G) among the red light emitting element ED_R, the green light emitting element ED_G, and the blue light emitting element ED_B. That is, the second light Lg1 may be output from the green light emitting element ED_G, and the light receiving element OPD may receive the second reflected light Lg2 obtained by reflecting the second light Lg1 by the fingerprint of the user. The second light Lg1 and the second reflected light Lg2 may be green light in a green wavelength band. The dummy color filter DCF is arranged above the light receiving element OPD. The color of the dummy color filter DCF may be green. Therefore, the second reflected light Lg2 may pass through the dummy color filter DCF and may be incident on the light receiving element OPD.

[0308] In one or more embodiments, the red light output from the red light emitting element ED_R and the blue light output from the blue light emitting element ED_B may also be reflected by the user's hand US_F. For example, when the light obtained by reflecting the red light Lr1 output from the red light emitting element ED_R by the user's hand US_F is defined as the first reflected light Lr2, the first reflected light Lr2 may not be able to pass through the dummy color filter DCF and may be absorbed by the dummy color filter DCF. Therefore, the first reflected light Lr2 cannot pass through the dummy color filter DCF and cannot be incident on the light receiving element OPD. Similarly, even if the blue light is reflected by the user's hand US_F, the blue light may be absorbed by the dummy color filter DCF. Therefore, only the second reflected light Lg2 can be provided to the light receiving element OPD.

[0309] As described above, a portion of the data connection line for connecting the second data line and the driver chip and a portion of the connection line for connecting the second readout line and the sensor chip can be arranged in the display area. Therefore, the area occupied by the data connection line and the connection line in the non-display area can be reduced, and thus the area of ​​the dead zone of the display panel can be reduced.

[0310] In addition, the voltage lines included in the display panel may be arranged in a grid structure. Therefore, the voltage may be uniformly supplied to the entire display area of ​​the display panel. In particular, the voltage lines connected to the sensor may be arranged in a grid structure. Therefore, the degradation of the sensing accuracy due to the drop in the voltage applied to the sensor may be prevented.

[0311] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure as set forth in the appended claims.

Claims

1. A display device, comprising: A base layer, the base layer having a display area and a non-display area; A circuit layer, the circuit layer is located on the base layer; an element layer, the element layer being located on the circuit layer, the element layer comprising a plurality of light emitting elements and a plurality of light receiving elements corresponding to the display area; as well as a data driver electrically connected to the circuit layer, Wherein, the circuit layer includes: a plurality of pixel driving circuits connected to the plurality of light emitting elements; a plurality of sensor driving circuits connected to the plurality of light receiving elements; a plurality of readout lines connected to the plurality of sensor drive circuits; a plurality of first data lines connected to a first group of pixel driving circuits among the plurality of pixel driving circuits; a plurality of second data lines spaced apart from the plurality of first data lines in a first direction and connected to a second group of pixel driving circuits among the plurality of pixel driving circuits; and a plurality of data connection lines, the plurality of data connection lines being electrically connected to the plurality of second data lines in the display area respectively, and The plurality of first data lines are connected to the data driver, and the plurality of second data lines are connected to the data driver through the plurality of data connection lines.

2. The display device according to claim 1, wherein: The plurality of data connection lines include: a plurality of vertical data connection lines, the plurality of vertical data connection lines being configured to extend along the first data line; and a plurality of horizontal data connection lines, the plurality of horizontal data connection lines being configured to extend in the first direction, and The plurality of horizontal data connection lines electrically connect the plurality of vertical data connection lines to the plurality of second data lines.

3. The display device according to claim 2, wherein: The plurality of horizontal data link lines are located at a layer different from a layer where the plurality of vertical data link lines are located.

4. The display device according to claim 3, wherein: The plurality of horizontal data connection lines include: a plurality of first horizontal data connection lines, the plurality of first horizontal data connection lines being configured to overlap with the sensor driving circuit; and a plurality of second horizontal data connection lines, the plurality of second horizontal data connection lines being configured to overlap with the pixel driving circuit and being electrically connected to the plurality of first horizontal data connection lines, and The plurality of first horizontal data link lines are located at a layer different from a layer where the plurality of second horizontal data link lines are located.

5. The display device according to claim 3, wherein: The plurality of vertical data connection lines are located at the same layer as the plurality of first data lines, and The plurality of vertical data connection lines are located at a layer different from a layer where the plurality of readout lines are located.

6. The display device according to claim 3, wherein: The circuit layer also includes: a first data bridging electrode configured to electrically connect each of the plurality of horizontal data link lines with a corresponding vertical data link line among the plurality of vertical data link lines; and The second data bridging electrode is configured to electrically connect each of the plurality of horizontal data link lines with a corresponding second data line among the plurality of second data lines.

7. The display device according to claim 6, wherein: The first data bridge electrode, the second data bridge electrode, and the plurality of readout lines are located at the same layer.

8. The display device according to claim 2, wherein: The plurality of readout lines include: a plurality of first sense lines connected to a first group of sensor drive circuits among the plurality of sensor drive circuits; and a plurality of second readout lines spaced apart from the plurality of first readout lines in the first direction and connected to a second group of sensor drive circuits among the plurality of sensor drive circuits, and The circuit layer further includes a plurality of readout connection lines electrically connected to the plurality of second readout lines in the display area respectively.

9. The display device according to claim 8, wherein: The plurality of readout connection lines include: a plurality of vertical readout connection lines, the plurality of vertical readout connection lines being configured to extend along the first readout line; and a plurality of horizontal readout connection lines, the plurality of horizontal readout connection lines being configured to extend in the first direction, and The plurality of horizontal readout connection lines electrically connect the plurality of vertical readout connection lines to the plurality of second readout lines.

10. The display device according to claim 9, wherein: The plurality of horizontal readout connection lines are located at a layer different from a layer where the plurality of vertical readout connection lines are located, wherein the plurality of vertical readout connection lines are located at a layer different from a layer where the plurality of second readout lines are located, and The plurality of vertical readout connection lines, the plurality of first data lines, and the plurality of second data lines are located at the same layer.

11. The display device according to claim 10, wherein: The circuit layer further includes a bridge contact electrode configured to electrically connect each of the plurality of horizontal readout connection lines with a corresponding vertical readout connection line among the plurality of vertical readout connection lines.

12. The display device according to claim 11, wherein: The bridge contact electrode and the plurality of second readout lines are arranged at the same layer.

13. The display device according to claim 9, wherein: The plurality of horizontal readout connection lines and the plurality of horizontal data connection lines are located at the same layer, and The plurality of vertical readout connection lines and the plurality of vertical data connection lines are located at the same layer.

14. The display device according to claim 1, wherein: The circuit layer also includes: a first driving voltage line, the first driving voltage line being connected to the pixel driving circuit; a second driving voltage line connected to the light emitting element and the light receiving element; and A reset voltage line is connected to the sensor driving circuit.

15. The display device according to claim 14, wherein: The plurality of readout lines, the first driving voltage line, and the reset voltage line are located at the same layer.

16. The display device according to claim 15, further comprising: a shielding reset wiring, the shielding reset wiring overlapping the reset voltage line, The shielding reset wiring, the plurality of first data lines, and the plurality of second data lines are located at the same layer.

17. The display device according to claim 14, wherein: The second driving voltage line comprises: a horizontal driving voltage line extending in the first direction; and a vertical driving voltage line extending in a second direction intersecting the first direction, and The vertical driving voltage line is located at a layer different from a layer where the horizontal driving voltage line is located.

18. The display device according to claim 1, wherein: The circuit layer also includes: a first initialization voltage line connected to the pixel driving circuit and configured to apply a first initialization voltage; and A second initialization voltage line is connected to the pixel driving circuit and is configured to apply a second initialization voltage.

19. The display device according to claim 18, wherein: The first initialization voltage line comprises: a first horizontal initialization voltage line extending in the first direction; and A first vertical initialization voltage line extends in a second direction crossing the first direction, wherein the first vertical initialization voltage line and the first horizontal initialization voltage line are located at different layers.

20. The display device according to claim 19, wherein: The second initialization voltage line comprises: a second horizontal initialization voltage line extending in the first direction; and A second vertical initialization voltage line extending in the second direction, wherein the second vertical initialization voltage line is located at a layer different from a layer where the second horizontal initialization voltage line is located.

21. The display device according to claim 18, wherein: The plurality of light emitting elements include: a first light emitting element configured to output a first color light; a second light emitting element configured to output light of a second color; and a third light emitting element configured to output a third color light, and Wherein, the second initialization voltage line comprises: a 2-1st initialization voltage line connected to at least one of the first to third light emitting elements and configured to apply a 2-1st initialization voltage; and A 2-2 initialization voltage line connected to the other light emitting elements among the first to third light emitting elements and configured to apply a 2-2 initialization voltage.

22. The display device according to claim 21, wherein: The 2-1st initialization voltage has a voltage level different from a voltage level of the 2-2nd initialization voltage.

23. The display device according to claim 18, wherein: Each of the plurality of sensor driving circuits comprises: a reset transistor including a first electrode configured to receive a reset voltage, a second electrode connected to the first sensing node, and a third electrode configured to receive a reset control signal; an amplifying transistor including a first electrode configured to receive a sensor driving voltage, a second electrode connected to a second sensing node, and a third electrode connected to the first sensing node; and An output transistor includes a first electrode connected to the second sensing node, a second electrode connected to a corresponding readout line among the plurality of readout lines, and a third electrode configured to receive an output control signal.

24. The display device according to claim 23, wherein: The second initialization voltage line is connected to the first electrode of the amplification transistor, and applies the second initialization voltage as the sensor driving voltage.

25. A display device comprising: A display panel, the display panel comprising a display area and a non-display area adjacent to the display area; a driver chip connected to the display panel; as well as a sensor chip connected to the display panel, Wherein, the display panel comprises: a plurality of light emitting elements; a plurality of light receiving elements; a plurality of pixel driving circuits connected to the plurality of light emitting elements; a plurality of sensor driving circuits connected to the plurality of light receiving elements; a plurality of readout lines connected to the plurality of sensor driving circuits and the sensor chip; a plurality of first data lines connected to a first group of pixel driving circuits among the plurality of pixel driving circuits; a plurality of second data lines spaced apart from the plurality of first data lines in a first direction and connected to a second group of pixel driving circuits among the plurality of pixel driving circuits; and a plurality of data connection lines, the plurality of data connection lines being electrically connected to the plurality of second data lines in the display area respectively, and The plurality of first data lines are connected to the driver chip, and the plurality of second data lines are connected to the driver chip through the plurality of data connection lines.

26. The display device according to claim 25, wherein: The driver chip and the sensor chip are adjacent to one side of the display area.

27. The display device according to claim 25, wherein: The plurality of data connection lines include: a plurality of vertical data connection lines extending along the first data line; and a plurality of horizontal data connection lines extending in the first direction, and The plurality of horizontal data connection lines electrically connect the plurality of vertical data connection lines to the plurality of second data lines.

28. The display device according to claim 27, wherein: The display panel further includes: a first data bridging electrode configured to electrically connect each of the plurality of horizontal data link lines with a corresponding vertical data link line among the plurality of vertical data link lines; and The second data bridging electrode is configured to electrically connect each of the plurality of horizontal data link lines with a corresponding second data line among the plurality of second data lines.

29. The display device according to claim 25, wherein: The plurality of readout lines include: a plurality of first sense lines connected to a first group of sensor drive circuits among the plurality of sensor drive circuits; and a plurality of second readout lines spaced apart from the plurality of first readout lines in the first direction and connected to a second group of sensor drive circuits among the plurality of sensor drive circuits, and The display panel further includes a plurality of connection lines electrically connected to the plurality of second readout lines in the display area respectively.

30. The display device according to claim 29, wherein: The plurality of connecting lines include: a plurality of vertical connection lines extending along the first readout line; and a plurality of horizontal connection lines extending in the first direction, and The plurality of horizontal connection lines electrically connect the plurality of vertical connection lines to the plurality of second readout lines.

31. The display device according to claim 30, wherein: The display panel further includes a bridge contact electrode configured to electrically connect each of the plurality of horizontal connection lines with a corresponding vertical connection line among the plurality of vertical connection lines.

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