Array substrate and display panel

Abstract

This application provides an array substrate and a display panel. The array substrate includes a substrate; N+1 data line groups located on the substrate, where N is an integer greater than or equal to 1; multiple pixels arranged along the row and column directions, with one data line group located within one column of pixels; each data line group includes a first data line and a second data line, where pixels located in odd-numbered rows and odd-numbered columns are connected to the first data line, and pixels located in odd-numbered rows and even-numbered columns are connected to the second data line; pixels located in even-numbered rows and odd-numbered columns are connected to the second data line, and pixels located in even-numbered rows and even-numbered columns are connected to the first data line; the first data line and the second data line have opposite polarities; each pixel includes a first pixel electrode, which includes a first vertical backbone and a second vertical backbone extending along the column direction, and the first and second vertical backbones are staggered; adjacent first pixel electrodes are mirror images of each other along the row direction and along the column direction.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] In related technologies, there are generally two options for the arrangement of the array substrate. The first option is to place a shielding electrode in the array substrate to prevent the liquid crystal molecules from being affected by the data lines and gate electric fields. The second option is to remove the shielding electrode and move the pixel electrodes away from the data lines to increase the aperture ratio. However, regardless of which method is used, certain problems exist:

[0003] The first option, setting a shielding electrode, can effectively prevent liquid crystal molecules from being deflected by the data line, but the presence of the shielding electrode will reduce the aperture ratio of the pixel.

[0004] The second option, although removing the shielding electrode and moving the pixel electrode away from the data line can improve the aperture ratio, may cause the data line in the array substrate to affect the deflection of liquid crystal molecules, resulting in inconsistent brightness in the image displayed on the array substrate, or even dark lines in some areas. Summary of the Invention

[0005] In view of this, this application provides an array substrate and a display panel to improve the problem of array substrates sacrificing aperture ratio in order to solve the dark pattern problem.

[0006] The technical solution adopted in this application to solve the above-mentioned technical problems is as follows:

[0007] In a first aspect, embodiments of this application provide an array substrate, comprising:

[0008] Substrate;

[0009] There are N+1 data line groups, where the data line groups are located on the substrate, and N is an integer greater than or equal to 1;

[0010] Multiple pixels, the pixels being arranged along row and column directions, and a group of data lines being located within a column of the pixels;

[0011] The data line group includes a first data line and a second data line. Pixels located in odd-numbered rows and odd-numbered columns are connected to the first data line, and pixels located in odd-numbered rows and even-numbered columns are connected to the second data line; pixels located in even-numbered rows and odd-numbered columns are connected to the second data line, and pixels located in even-numbered rows and even-numbered columns are connected to the first data line; the first data line and the second data line have opposite polarities.

[0012] The pixel includes a first pixel electrode, the first pixel electrode includes a first vertical backbone and a second vertical backbone extending along the column direction, and the first vertical backbone and the second vertical backbone are staggered. Along the row direction, adjacent first pixel electrodes are mirror images of each other. Along the column direction, adjacent first pixel electrodes are mirror images of each other.

[0013] In some embodiments of this application, at least a portion of the first longitudinal trunk and the first data line overlap, and at least a portion of the second longitudinal trunk and the second data line overlap.

[0014] In some embodiments of this application, the first data line in the Nth data line group and the first data line in the (N+M)th data line group are connected in parallel, where M is an integer multiple of 3.

[0015] In some embodiments of this application, the first pixel electrode further includes a first lateral trunk and a plurality of first branches. The first vertical trunk and the second vertical trunk are respectively connected to both sides of the first lateral trunk in the column direction, and the plurality of first branches are connected to the first vertical trunk, the second vertical trunk and the first lateral trunk.

[0016] In some embodiments of this application, a pixel further includes a second pixel electrode. Along the column direction, the first pixel electrode and the second pixel electrode are arranged alternately. The second pixel electrode includes a third vertical main trunk, a fourth vertical main trunk, a second horizontal main trunk, and a plurality of second branches. The third vertical main trunk and the fourth vertical main trunk are respectively disposed on both sides of the second horizontal main trunk in the column direction. The plurality of second branches connect the second horizontal main trunk, the third vertical main trunk, and the fourth vertical main trunk.

[0017] Wherein, adjacent second pixel electrodes are mirror images of each other along the row direction, and adjacent second pixel electrodes are mirror images of each other along the column direction.

[0018] In some embodiments of this application, the array substrate further includes multiple scan lines, a first thin-film transistor, a second thin-film transistor, and voltage divider lines; wherein

[0019] The scan line extends along the row direction;

[0020] The first thin-film transistor and the second thin-film transistor are located between the first pixel electrode and the second pixel electrode. The source of the first thin-film transistor is connected to the corresponding first data line or second data line. The first pixel electrode is connected to the drain of the first thin-film transistor, and the second pixel electrode is connected to the drain of the second thin-film transistor.

[0021] The voltage divider line extends along the column direction and is located between two adjacent columns of pixels. The voltage divider line is connected to the source of the second thin-film transistor, and the voltage divider line is disposed on the same layer as the data line group.

[0022] In some embodiments of this application, two adjacent columns of pixels share a single voltage divider line.

[0023] In some embodiments of this application, the array substrate further includes a third thin-film transistor, the source of which is connected to the source of the first thin-film transistor, and the drain of which is connected to the drain of the second thin-film transistor.

[0024] In some embodiments of this application, the first thin-film transistor and the third thin-film transistor are located on the same side of the data line group.

[0025] In some embodiments of this application, the first thin-film transistor and the third thin-film transistor are located on opposite sides of the first data line or the second data line of the corresponding data line group.

[0026] Secondly, embodiments of this application provide a display panel, the display panel comprising an array substrate as described in the first aspect, and

[0027] Opposing substrate, located on one side of the array substrate;

[0028] A liquid crystal layer is disposed between the array substrate and the opposing substrate.

[0029] In summary, due to the adoption of the above technical solution, this application includes at least the following beneficial effects:

[0030] Embodiments of this application provide an array substrate and a display panel. By connecting pixels in odd-numbered rows and columns to a first data line, and pixels in odd-numbered rows and even-numbered columns to a second data line; and pixels in even-numbered rows and odd-numbered columns to the second data line, and pixels in even-numbered rows and even-numbered columns to the first data line, and by staggering the first and second vertical backbones, a portion of the first data line is blocked by the first vertical backbone, and a portion of the second data line is blocked by the second vertical backbone, thereby achieving a higher pixel aperture ratio. Furthermore, by making the polarities of the first and second data lines opposite, and by mirroring adjacent first pixel electrodes along the row direction and along the column direction, the influence of the data lines on the deflection of liquid crystal molecules is avoided, which helps to improve the brightness uniformity of the array substrate. In detail, firstly, by setting a first data line and a second data line in the data line group, pixels located in odd-numbered rows and columns are connected to the first data line, and pixels located in odd-numbered rows and even-numbered columns are connected to the second data line; pixels located in even-numbered rows and odd-numbered columns are connected to the second data line, and pixels located in even-numbered rows and even-numbered columns are connected to the first data line, with the first and second data lines having opposite polarities, thereby balancing the coupling caused by positive and negative frames. Then, by making the first pixel electrode include a first vertical backbone and a second vertical backbone, with the first and second vertical backbones staggered, a portion of the first data line can be blocked by the first vertical backbone, and a portion of the second data line can be blocked by the second vertical backbone, allowing the vertical backbone to act as a signal shield and increasing the aperture ratio. Furthermore, by mirroring adjacent first pixel electrodes along the row direction and also mirroring adjacent first pixel electrodes along the column direction, the mirrored and adjacent pixels can balance the influence of data lines with opposite polarities on the liquid crystal molecules, achieving brightness difference compensation between adjacent pixels and improving the brightness uniformity of the array substrate. Attached Figure Description

[0031] Figure 1 A schematic diagram of an array substrate provided for an embodiment of this application;

[0032] Figure 2 A schematic diagram of a pixel electrode in an array substrate provided for an embodiment of this application;

[0033] Figure 3 A schematic diagram showing the connection between a thin-film transistor and a data line group in an array substrate, provided for an embodiment of this application;

[0034] Figure 4 A schematic diagram of the connection between the gate layer and the common electrode in an array substrate provided for an embodiment of this application;

[0035] Figure 5A schematic diagram of a pixel electrode in another array substrate provided for an embodiment of this application;

[0036] Figure 6 A schematic diagram showing the connection between a thin-film transistor and a data line group in another array substrate provided for an embodiment of this application;

[0037] Figure 7 A schematic diagram of the gate layer and common electrode connection in another array substrate provided for an embodiment of this application;

[0038] Figure 8 This is a schematic diagram of a pixel unit provided for an embodiment of this application.

[0039] Explanation of reference numerals in the attached figures:

[0040] 100, Array substrate; 110, Pixel; 111, First pixel electrode; 1111, First vertical backbone; 1112, Second vertical backbone; 1113, First horizontal backbone; 1114, First branch; 1115, Display domain region; 112, Second pixel electrode; 1121, Third vertical backbone; 1122, Fourth vertical backbone; 1123, Second horizontal backbone; 1124, Second branch; 113, Gate layer; 1131 1132, First gate electrode; 114, Second gate electrode; 115, Common electrode; 1161, Vertical electrode line; 11711, First segment line; 11812, Second segment line; 1192, Lateral electrode line; 110, Gate region; 121, Data line group; 122, First data line; 123, Second data line; 140, First thin-film transistor; 150, Second thin-film transistor; 160, Voltage divider line. Detailed Implementation

[0041] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0042] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or specifying the number of technical features indicated. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0043] In this application, the term "exemplary" is used to mean "used as an example, illustration, or illustration." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments.

[0044] Please see Figures 1 to 7Embodiments of this application provide an array substrate 100, which includes:

[0045] Substrate;

[0046] N+1 data line groups 120, the data line groups 120 are located on the substrate, and N is an integer greater than or equal to 1;

[0047] Multiple pixels 110 are arranged along the row and column directions, and a data line group 120 is located within a column of pixels 110;

[0048] A data line group 120 includes a first data line 121 and a second data line 122. Pixels 110 located in odd-numbered rows and odd-numbered columns are connected to the first data line 121, and pixels 110 located in odd-numbered rows and even-numbered columns are connected to the second data line 122; pixels 110 located in even-numbered rows and odd-numbered columns are connected to the second data line 122, and pixels 110 located in even-numbered rows and even-numbered columns are connected to the first data line 121; the first data line 121 and the second data line 122 have opposite polarities.

[0049] A pixel 110 includes a first pixel electrode, which includes a first vertical backbone 1111 and a second vertical backbone 1112 extending along the column direction. The first vertical backbone 1111 and the second vertical backbone 1112 are staggered. Adjacent first pixel electrodes are mirror images along the row direction and along the column direction.

[0050] Two data lines of opposite polarity are disposed in different layers from the pixel 110 electrode, and the two data lines are arranged to at least partially overlap with the vertical backbone. The two data lines carry opposite electrical signals to drive the pixel 110. Furthermore, multiple pixels 110 are arranged along the row and column directions, with adjacent pixels 110 mirror images of each other along the row and column directions, to balance the electric field and signal transmission, and reduce interference and brightness differences.

[0051] The technical solution provided in this application connects pixels 110 in odd-numbered rows and columns to the first data line 121, and pixels 110 in odd-numbered rows and even-numbered columns to the second data line 122; pixels 110 in even-numbered rows and odd-numbered columns are connected to the second data line 122, and pixels 110 in even-numbered rows and even-numbered columns are connected to the first data line 121. Furthermore, the first vertical backbone 1111 and the second vertical backbone 1112 are staggered, so that a portion of the first data line 121 is blocked by the first vertical backbone 1111, and a portion of the second data line 122 is blocked by the second vertical backbone 1112, thereby achieving the purpose of increasing the aperture ratio of the pixels 110. Moreover, by making the polarities of the first data line 121 and the second data line 122 opposite, and by mirroring adjacent first pixel electrodes along the row direction and along the column direction, the influence of the data lines on the deflection of liquid crystal molecules is avoided, which is beneficial to improving the brightness uniformity of the array substrate 100. In detail, firstly, a first data line 121 and a second data line 122 are set in the data line group 120, and the pixels 110 located in odd-numbered rows and odd-numbered columns are connected to the first data line 121, and the pixels 110 located in odd-numbered rows and even-numbered columns are connected to the second data line 122; the pixels 110 located in even-numbered rows and odd-numbered columns are connected to the second data line 122, and the pixels 110 located in even-numbered rows and even-numbered columns are connected to the first data line 121, and the first data line 121... The first data line 121 and the second data line 122 are opposite in polarity, thus balancing the coupling caused by positive and negative frames. Furthermore, by having the first pixel electrode include a first vertical backbone 1111 and a second vertical backbone 1112, with the first vertical backbone 1111 and the second vertical backbone 1112 offset, a portion of the first data line 121 can be blocked by the first vertical backbone 1111, and a portion of the second data line 122 can be blocked by the second vertical backbone 1112. This allows the vertical backbone to act as a signal shield, increasing the aperture ratio. Additionally, by mirroring adjacent first pixel electrodes along the row direction and also mirroring adjacent first pixel electrodes along the column direction, the mirrored and adjacent pixels 110 can balance the influence of data lines with opposite polarities on the liquid crystal molecules, achieving brightness difference compensation between adjacent pixels 110 and improving the brightness uniformity of the array substrate 100.

[0052] Further, please see Figure 1 and Figure 2The first vertical backbone 1111 and the second vertical backbone 1112 are staggered and spaced apart. The first data line 121 is aligned with the first vertical backbone 1111 so that the first vertical backbone 1111 covers at least a portion of the first data line 121, and the second data line 122 is aligned with the second vertical backbone 1112 so that the second vertical backbone 1112 covers at least a portion of the second data line 122. The first vertical backbone 1111 and the second vertical backbone 1112 are arranged parallel to each other in the vertical direction, which helps to ensure a uniform electric field distribution of the pixel 110 electrodes. Here, "covering" refers to overlapping, that is, at least a portion of the first vertical backbone 1111 overlaps with the first data line 121, and at least a portion of the second vertical backbone 1112 overlaps with the second data line 122. This helps to minimize electric field interference of the data lines, improves the display effect, and reduces dark lines. Furthermore, due to the reasonable layout of the vertical backbone and data lines, the vertical backbone can play a shielding role, avoiding the use of shielding electrodes in traditional designs, thereby increasing the aperture ratio of pixel 110 and allowing more light to pass through the pixel 110 area, thus improving display brightness.

[0053] Furthermore, the first pixel electrode also includes a first lateral trunk 1113 and a plurality of first branches 1114. A first vertical trunk 1111 and a second vertical trunk 1112 are respectively connected to both sides of the first lateral trunk 1113 in the column direction. The plurality of first branches 1114 connect the first vertical trunk 1111, the second vertical trunk 1112, and the first lateral trunk 1113. Specifically, the first lateral trunk 1113 intersects with both the first vertical trunk 1111 and the second vertical trunk 1112 to define a plurality of display domain regions 1115. A plurality of first branches 1114 are provided within each display domain region 1115, and the first branches 1114 are connected to the first lateral trunk 1113, the first vertical trunk 1111, and the second vertical trunk 1112. In addition, the first branches 1114 within adjacent display domain regions 1115 are arranged in a mirror image. In this embodiment, the first pixel electrode includes a first lateral trunk 1113 and two longitudinal trunks, namely the first longitudinal trunk 1111 and the second longitudinal trunk 1112. The first lateral trunk 1113 intersects with both longitudinal trunks to form multiple display domain regions 1115. Within each display domain region 1115, multiple first branches 1114 are provided, and the first branches 1114 are connected to both the first lateral trunk 1113 and the two longitudinal trunks. The first branches 1114 in adjacent display domain regions 1115 are mirror images of each other, that is, the first branch 1114 in one display domain region 1115 extends to the left, and the first branch 1114 in another display domain region 1115 extends to the right. This mirror image arrangement can balance the electric field and reduce the non-uniform deflection of liquid crystal molecules. By setting a first lateral trunk 1113, a first vertical trunk 1111, and a second vertical trunk 1112 in the first pixel electrode, and setting a first branch 1114 in the display domain region 1115, the uniform distribution of the electric field within the pixel 110 region can be ensured. This helps reduce the interference of the electric field on the liquid crystal molecules and improves the uniformity of display brightness. The setting of the first branch 1114 makes the electric field within the display domain region 1115 more uniform, which can reduce unnecessary light-blocking areas and improve the aperture ratio of the pixel 110. By mirroring the first branches 1114 in adjacent display domain regions 1115, the force of the electric field on the liquid crystal molecules can be balanced, reducing brightness differences and dark lines caused by uneven electric fields.

[0054] Please see Figure 2 or Figure 5In some embodiments, a pixel 110 further includes a second pixel electrode. Along the column direction, the first pixel electrode and the second pixel electrode are arranged alternately. The second pixel electrode includes a third vertical main branch 1121, a fourth vertical main branch 1122, a second horizontal main branch 1123, and a plurality of second branches 1124. The third vertical main branch 1121 and the fourth vertical main branch 1122 are respectively disposed on both sides of the second horizontal main branch 1123 in the column direction, and the plurality of second branches 1124 connect the second horizontal main branch 1123, the third vertical main branch 1121, and the fourth vertical main branch 1122. Adjacent second pixel electrodes are mirror images along the row direction and along the column direction. The structure of the second pixel electrode is the same as that of the first pixel electrode, and the beneficial effects are also the same; therefore, the specific details of the second pixel electrode will not be described in detail here.

[0055] However, it should be noted that the first pixel electrode and the second pixel electrode are arranged in the column direction and are mirror images of each other. Specifically, the first branch 1114 of the first pixel electrode is mirrored with the second branch 1124 of the second pixel electrode, and the portions of the first vertical trunk 1111 and the second vertical trunk 1112 that respectively cover the first data line 121 and the second data line 122 are also mirrored with the portions of the third vertical trunk 1121 and the fourth vertical trunk 1122 that respectively cover the first data line 121 and the second data line 122.

[0056] In some embodiments, see Figures 1 to 4In two adjacent pixels 110, the pixel electrodes of one pixel 110 are mirror images of those of the other pixel 110, and the two data lines of one pixel 110 are mirror images of the two data lines of the other pixel 110. For example, if the first vertical backbone 1111 in one pixel 110 is located on the left, then in the other pixel 110, the first vertical backbone 1111 will be located on the right. This ensures a uniform electric field distribution between adjacent pixels 110 and reduces electric field interference. Similarly, in the horizontal direction, the vertical backbones of the two pixels 110 are mirror images, and the branch electrodes of the two pixels 110 are also mirror images in both the vertical and horizontal directions. For the mirrored data lines, for example, if the first data line 121 in one pixel 110 is located on the left and the second data line 122 is located on the right, then in the other pixel 110, the first data line 121 will be located on the right and the second data line 122 will be located on the left. This mirroring arrangement can balance the electric field effect of the data lines and reduce brightness differences. The mirrored setup reduces mutual interference between the data lines and electrodes, resulting in a more balanced electric field. This reduces brightness differences and dark lines, improving display stability and clarity. Because the mirrored setup of the electrodes and data lines reduces electric field interference, additional shielding electrodes are no longer needed to prevent liquid crystal molecule deflection, thus increasing the aperture ratio of pixel 110.

[0057] In some embodiments, see Figure 4 or Figure 7 Pixel 110 also includes a gate layer 113 and a common electrode 114. The common electrode 114 is disposed on the same layer as the gate layer 113, but on a different layer than the data lines and the pixel 110 electrodes. A parasitic capacitance is formed between the common electrode 114 and the gate layer 113. In each pixel 110, the gate layer 113 and the common electrode 114 are on the same layer. The gate layer 113 controls the switching state of the liquid crystal molecules, while the common electrode 114 provides a reference voltage. The gate layer 113 and the common electrode 114 are connected to the data lines and the pixel 110 electrodes, respectively, to ensure correct signal transmission and display. The common electrode 114 is on the same layer as the gate layer 113, but on a different layer than the data lines and the pixel 110 electrodes. This reduces mutual interference between electrodes and improves the uniformity and stability of the electric field distribution. The fact that the common electrode 114 is on the same layer as the gate layer 113 reduces mutual interference between electrodes, especially between the data lines and the pixel 110 electrodes. This balances the electric field effect and reduces brightness differences and dark lines.

[0058] Furthermore, in two adjacent pixels 110, the gate layer 113 in one pixel 110 is mirrored with the gate layer 113 in the other pixel 110, and the common electrode 114 in one pixel 110 is mirrored with the common electrode 114 in the other pixel 110. The gate layer 113 structure of one pixel 110 is mirrored with the gate layer 113 structure of the other adjacent pixel 110. For example, if the gate layer 113 in one pixel 110 is on the left, then in the other adjacent pixel 110, the gate layer 113 will be on the right. This ensures a uniform electric field distribution between adjacent pixels 110, reducing electric field interference. The common electrode 114 in one pixel 110 is mirrored with the common electrode 114 in the other adjacent pixel 110. For example, if the common electrode 114 in one pixel 110 is on the left, then in the other adjacent pixel 110, the common electrode 114 will be on the right. This mirroring arrangement balances the electric field effect, reducing brightness differences and dark lines.

[0059] In some embodiments, the common electrode 114 includes two opposing longitudinal electrode lines 1141 and two opposing transverse electrode lines 1142. The longitudinal electrode lines 1141 include first segment lines 11411 and second segment lines 11412 arranged opposite each other along the longitudinal direction. One transverse electrode line 1142 has its two ends connected to one end of each of the two first segment lines 11411. The other transverse electrode line 1142 has its two ends connected to one end of each of the two second segment lines 11412. A gate layer 113 is disposed in the region surrounded by the two transverse electrode lines 1142, the two first segment lines 11411, and the two second segment lines 11412; this region is the gate region 115. This arrangement further optimizes the structure of the common electrode 114, improving the uniformity and stability of the electric field distribution.

[0060] In this embodiment, the two ends of a horizontal electrode line 1142 are respectively connected to one end of two first segment lines 11411, and the two ends of another horizontal electrode line 1142 are respectively connected to the ends of two second segment lines 11412 near the first segment lines 11411, so that the two first segment lines 11411 connected to a horizontal electrode line form a U-shape, and the two second segment lines 11412 connected to another horizontal electrode line form an inverted U-shape. The gate region 115 can be defined between the two U-shapes, that is, between the two horizontal electrode lines 1142. The gate layer 113 can be directly electrically connected to the two horizontal electrode lines 1142. The two vertical electrode lines 1141 can also be connected through the horizontal electrode lines 1142, thereby forming a circuit connecting the gate layer 113 and the common electrode 114, which is used to control the switching state of the liquid crystal molecules.

[0061] In some embodiments, see Figure 1 and Figure 5 The common electrode 114 includes two opposing longitudinal electrode lines 1141 and two opposing transverse electrode lines 1142. The longitudinal electrode lines 1141 include a first segment line 11411 and a second segment line 11412 that are opposite each other along the longitudinal direction. The two first segment lines 11411 and the two second segment lines 11412 together define the gate region 115. The gate layer 113 is disposed in the gate region 115. The two transverse electrode lines 1142 are respectively located on both sides of the gate layer 113 along the longitudinal direction. The two ends of one transverse electrode line 1142 are respectively connected to the ends of the two first segment lines 11411 that are away from the second segment lines 11412. The two ends of the other transverse electrode line 1142 are respectively connected to the ends of the two second segment lines 11412 that are away from the first segment lines 11411.

[0062] In each pixel 110, the common electrode 114 includes two vertical electrode lines 1141 and two horizontal electrode lines 1142. The two vertical electrode lines 1141 are arranged opposite to each other and are connected by the two horizontal electrode lines 1142 respectively. The two first segment lines 11411 and the two second segment lines 11412 together define a gate region 115, in which a gate layer 113 is disposed for controlling the switching state of liquid crystal molecules. By moving the two horizontal electrode lines 1142 away from each other, so that the two horizontal electrodes are located at the ends of the first segment lines 11411 and the second segment lines 11412 that are away from each other, compared to the two horizontal electrode lines 1142 being arranged close together, the area occupied by the horizontal electrode lines in the display domain region 1115 can be effectively reduced, thereby reducing the area of ​​light shading by the black matrix corresponding to the gate and further improving the aperture ratio.

[0063] In some embodiments, see Figures 2 to 4 , or see Figures 5 to 7The array substrate 100 also includes multiple scan lines, a first thin-film transistor 130, a second thin-film transistor 140, and a voltage divider line 160; wherein the scan lines extend along the row direction. The first thin-film transistor 130 and the second thin-film transistor 140 are located between the first pixel electrode and the second pixel electrode. The source of the first thin-film transistor 130 is connected to the corresponding first data line 121 or second data line 122. In other words, the source of a portion of the first thin-film transistor 130 is connected to the first data line 121, and the source of another portion of the first thin-film transistor 130 is connected to the second data line 122. Specifically, in odd-numbered rows and odd-numbered columns, the source of the first thin-film transistor 130 is connected to the first data line 121; in even-numbered rows and odd-numbered columns, the source of the first thin-film transistor 130 is connected to the second data line 122; in odd-numbered rows and even-numbered columns, the source of the first thin-film transistor 130 is connected to the second data line 122; and in even-numbered rows and even-numbered columns, the source of the first thin-film transistor 130 is connected to the first data line 121. This allows the first thin-film transistor 130 in adjacent pixels 110 along the row and column directions to be connected to different data lines, thereby causing adjacent pixels 110 along the row and column directions to have opposite charges. In another embodiment, the first thin-film transistor 130 in even-row odd-column and odd-row even-column positions is connected to the first data line 121, and the first thin-film transistor 130 in odd-row odd-column and even-row even-column positions is connected to the second data line 122. Similarly, the first thin-film transistor 130 in adjacent pixels 110 along the row and column directions is connected to different data lines, thereby making the electrical properties of adjacent pixels 110 along the row and column directions opposite.

[0064] In both of the above embodiments, the connection relationship between the first pixel electrode and the drain of the first thin-film transistor 130, and the connection between the second pixel electrode and the drain of the second thin-film transistor 140 are satisfied.

[0065] The voltage divider line 160 extends along the column direction and is located between two adjacent columns of pixels 110. The voltage divider line 160 is connected to the source of the second thin film transistor 140, and the voltage divider line 160 is disposed on the same layer as the data line group 120.

[0066] Furthermore, two adjacent columns of pixels 110 share a single voltage divider line 160, meaning the voltage divider line 160 runs along the seam between two adjacent pixels 110 in the row direction. The voltage divider line 160 is disposed on a different layer from the common electrode 114, but on the same layer as the first data line 121 and the second data line 122, and is connected to the common electrode 114 via a circuit. This facilitates the uniform distribution of the common voltage between adjacent pixels 110, ensuring a stable electric field between the pixel 110 electrode and the common electrode 114, and reducing the impact of uneven electric field on the liquid crystal molecules.

[0067] In some embodiments, the array substrate 100 further includes a third thin-film transistor 150. The source of the third thin-film transistor 150 is connected to the source of the first thin-film transistor 130, and the drain of the third thin-film transistor 150 is connected to the drain of the second thin-film transistor 140, thereby connecting the second thin-film transistor 140 and the first thin-film transistor 130, so that the second thin-film transistor 140 and the first thin-film transistor 130 are both electrically connected to the same data line.

[0068] Furthermore, in the row direction, the first thin-film transistor 130 in adjacent pixels 110 is mirrored about the voltage divider line 160, the second thin-film transistor 140 in adjacent pixels 110 is mirrored about the voltage divider line 160, and the third thin-film transistor 150 in adjacent pixels 110 is mirrored about the voltage divider line 160. Similarly, in the column direction, the first thin-film transistor 130, the second thin-film transistor 140, and the third thin-film transistor 150 in adjacent pixels 110 are all mirrored about the voltage divider line 160.

[0069] In some embodiments, see Figure 3 The first thin-film transistor 130 and the third thin-film transistor 150 are located on the same side of a data line group 120. The fact that both the first thin-film transistor 130 and the third thin-film transistor 150 are located on the same side of the data line group 120 is mainly determined by the structure of the gate layer 113. The gate layer 113 includes a first gate electrode 1131. When both the first thin-film transistor 130 and the third thin-film transistor 150 are connected to the first gate electrode 1131, the first thin-film transistor 130 and the third thin-film transistor 150 are located on the same side of the data line group 120, facilitating the connection between the thin-film transistors and the gate electrode.

[0070] In some embodiments, see Figure 6The first thin-film transistor 130 and the third thin-film transistor 150 are located on opposite sides of the first data line 121 or the second data line 122 of the corresponding data line group 120. The gate layer 113 includes a first gate electrode 1131 and a second gate electrode 1132. The first gate electrode 1131 and the second gate electrode 1132 are offset from each other, and the first gate electrode 1131 and the second gate electrode 1132 are located on opposite sides of the projection of the first data line 121 or the second data line 122 in the data line group 120 toward the substrate. Since the first thin-film transistor 130 is connected to the first gate electrode 1131 and the third thin-film transistor 150 is connected to the second gate electrode 1132, the first thin-film transistor 130 and the third thin-film transistor 150 are located on opposite sides of the first data line 121 or the second data line 122 of the corresponding data line group 120. Specifically, along the row direction, if the first thin-film transistor 130 and the third thin-film transistor 150 in one pixel 110 are located on both sides of the first data line 121, then the first thin-film transistor 130 and the third thin-film transistor 150 in the other pixel 110 are located on both sides of the second data line 122. Similarly, along the column direction, if the first thin-film transistor 130 and the third thin-film transistor 150 in one pixel 110 are located on both sides of the first data line 121, then the first thin-film transistor 130 and the third thin-film transistor 150 in the other pixel 110 are located on both sides of the second data line 122.

[0071] In some embodiments, see Figure 1 and Figure 8The plurality of pixels 110 includes a plurality of first pixels, a plurality of second pixels, and a plurality of third pixels. The first, second, and third pixels are all of different colors. In this embodiment, the first pixel is red, the second pixel is green, and the third pixel is blue. By utilizing the three primary colors, a multi-color display is achieved. A first pixel, a second pixel, and a third pixel are sequentially arranged adjacently to form a pixel unit 110. Multiple pixel units 110 are arranged adjacently. In two pixels 110 of the same color within adjacent pixel units 110, the two pixels 110 share two data lines, and one data line is connected to one pixel 110. The two data lines connecting the two pixels 110 have opposite polarities. In other words, in two adjacent pixels 110 of the same color, there are two data lines located within these two pixels 110. However, each pixel 110 is only connected to one of these data lines. The other data line located in that pixel 110 is not connected to that pixel 110, but is connected to another adjacent pixel 110 of the same color. This arrangement ensures that there are two data lines with opposite polarities within a single pixel 110, effectively balancing the positive and negative frame coupling within the pixel 110. Furthermore, adjacent pixels 110 share two data lines, which helps reduce the number of data lines and maintain a constant driving cost.

[0072] In some embodiments, the first data line 121 in the Nth data line group 120 and the first data line 121 in the (N+M)th data line group 120 are connected in parallel, where M is an integer multiple of 3. Specifically, in this embodiment, a pixel unit 110 includes six pixels 110, namely a first pixel, a second pixel, a third pixel, a fourth pixel, a fifth pixel, and a sixth pixel. The six pixels 110 are arranged sequentially along the row direction, and the first and fourth pixels are the same color, both red; the second and fifth pixels are the same color, both green; and the third and sixth pixels are the same color, both blue. The two data lines in the first pixel are connected to the two data lines in the fourth pixel, the two data lines in the second pixel are connected to the two data lines in the fifth pixel, and the two data lines in the third pixel are connected to the two data lines in the sixth pixel, which helps to reduce driving costs. Furthermore, by connecting pixels 110 of the same color to the same data line, it is ensured that pixels 110 of the same color receive consistent data signals, thereby improving the uniformity of displayed colors and avoiding color distortion.

[0073] This application also provides a display panel, which includes an array substrate, a counter substrate, and a liquid crystal layer. The array substrate is the array substrate described in any of the foregoing embodiments, and its specific structure will not be described in detail here. The counter substrate is located on one side of the array substrate, and the liquid crystal layer is disposed between the array substrate and the counter substrate. Because the display panel provided in this embodiment includes the array substrate described in any of the foregoing embodiments, the display panel has the same structure and beneficial effects as the array substrate, and will not be described in detail here.

[0074] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic associated with at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0075] Similarly, it should be noted that, in order to simplify the description of the embodiments of this application and thus aid in the understanding of one or more embodiments, the foregoing description of the embodiments of this application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of this application requires more features than those mentioned in the claims. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

Claims

1. An array substrate, characterized in that, include: Substrate; There are N+1 data line groups, where the data line groups are located on the substrate, and N is an integer greater than or equal to 1; Multiple pixels, the pixels being arranged along row and column directions, and a group of data lines being located within a column of the pixels; The data line group includes a first data line and a second data line. Pixels located in odd-numbered rows and odd-numbered columns are connected to the first data line, and pixels located in odd-numbered rows and even-numbered columns are connected to the second data line; pixels located in even-numbered rows and odd-numbered columns are connected to the second data line, and pixels located in even-numbered rows and even-numbered columns are connected to the first data line; the first data line and the second data line have opposite polarities. A pixel includes a first pixel electrode, the first pixel electrode includes a first vertical backbone and a second vertical backbone extending along the column direction, and the first vertical backbone and the second vertical backbone are staggered, the first vertical backbone and at least a portion of the first data line overlap, and the second vertical backbone and at least a portion of the second data line overlap. Along the row direction, adjacent first pixel electrodes are mirror images of each other, and along the column direction, adjacent first pixel electrodes are mirror images of each other.

2. The array substrate as described in claim 1, characterized in that, The first data line in the Nth data line group and the first data line in the (N+M)th data line group are connected in parallel, where M is an integer multiple of 3.

3. The array substrate as described in claim 1, characterized in that, The first pixel electrode further includes a first lateral trunk and a plurality of first branches. The first vertical trunk and the second vertical trunk are respectively connected to the two sides of the first lateral trunk in the column direction, and the plurality of first branches are connected to the first vertical trunk, the second vertical trunk and the first lateral trunk.

4. The array substrate as described in claim 3, characterized in that, The pixel further includes a second pixel electrode. Along the column direction, the first pixel electrode and the second pixel electrode are arranged alternately. The second pixel electrode includes a third vertical main trunk, a fourth vertical main trunk, a second horizontal main trunk, and a plurality of second branches. The third vertical main trunk and the fourth vertical main trunk are respectively disposed on both sides of the second horizontal main trunk in the column direction. The plurality of second branches connect the second horizontal main trunk, the third vertical main trunk, and the fourth vertical main trunk. Wherein, adjacent second pixel electrodes are mirror images of each other along the row direction, and adjacent second pixel electrodes are mirror images of each other along the column direction.

5. The array substrate as described in claim 4, characterized in that, The array substrate also includes multiple scan lines, a first thin-film transistor, a second thin-film transistor, and voltage divider lines; in The scan line extends along the row direction; The first thin-film transistor and the second thin-film transistor are located between the first pixel electrode and the second pixel electrode. The source of the first thin-film transistor is connected to the corresponding first data line or second data line. The first pixel electrode is connected to the drain of the first thin-film transistor, and the second pixel electrode is connected to the drain of the second thin-film transistor. The voltage divider line extends along the column direction and is located between two adjacent columns of pixels. The voltage divider line is connected to the source of the second thin-film transistor, and the voltage divider line is disposed on the same layer as the data line group.

6. The array substrate as described in claim 5, characterized in that, The pixels in two adjacent columns share a single voltage divider line.

7. The array substrate as described in claim 5, characterized in that, The array substrate further includes a third thin-film transistor, the source of which is connected to the source of the first thin-film transistor, and the drain of which is connected to the drain of the second thin-film transistor.

8. The array substrate as claimed in claim 7, characterized in that, The first thin-film transistor and the third thin-film transistor are located on the same side of the data line group.

9. The array substrate as claimed in claim 7, characterized in that, The first thin-film transistor and the third thin-film transistor are located on opposite sides of the first data line or the second data line of the corresponding data line group.

10. A display panel, characterized in that, The display panel includes an array substrate as described in any one of claims 1 to 9, and Opposing substrate, located on one side of the array substrate; A liquid crystal layer is disposed between the array substrate and the opposing substrate.

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