An OCL-LDO circuit

Abstract

The present invention discloses an OCL-LDO circuit, comprising a bandgap reference unit, a super source follower, a bias circuit, a power transistor M P This invention introduces a unique output capacitor-less low-dropout (OCL-LDO) regulator consisting of a super source follower (SSF) and a high-pass network. The core of this design is a push-pull capable flip voltage follower (FVF) with an embedded super source follower (SSF) and a high-pass network. This structure cleverly integrates the super source follower (SSF) with a high-pass network and embeds it within the flip voltage follower (FVF), significantly improving transient response.

Description

Technical Field

[0001] The present invention relates to the field of voltage stabilizers, in particular to an OCL-LDO circuit. Background Art

[0002] With the rapid advancement of technology, portable electronic devices are playing an increasingly critical role in our daily lives and work, driving the continuous innovation and development of power management technology. A wide variety of power solutions have emerged on the market to meet the stable and reliable power needs of various portable electronic devices, enriching the entire electronics ecosystem.

[0003] As a highly efficient and commonly used step-down (step-down) IC, low-dropout linear regulators (LDOs) are widely used in small electronic devices due to their excellent noise control capabilities, compact size, and ease of integration. In particular, in system-on-chip (SoC) designs, LDOs are a preferred option for many design engineers due to their ability to provide a stable power supply and effectively reduce electromagnetic interference (EMI). Furthermore, LDOs achieve high performance without the need for complex external components, further simplifying the design process and reducing costs, making them a key component in portable device design.

[0004] Traditional linear low-dropout (LDO) regulator designs typically require large external capacitors, often in the microfarad range. These off-chip capacitors are crucial for ensuring output voltage stability, particularly during sudden changes in load current. They effectively dampen output voltage fluctuations and prevent significant voltage swings. However, this reliance on external bulk capacitors also presents significant limitations, such as increased board space, higher costs, and potentially impacting overall system response speed.

[0005] While the use of bulk capacitors is crucial for ensuring output voltage stability, they also present several significant challenges. First, these capacitors occupy a significant amount of space, posing a design challenge for modern electronic devices striving for miniaturization and thinness. Second, the use of bulk capacitors increases system cost, as they are not only relatively expensive but also require additional space. Furthermore, these large capacitors can increase the overall weight of the power module, which, for portable devices, not only affects portability but also potentially impacts battery life, as heavier devices consume more power to operate. Therefore, finding alternatives to reduce reliance on external bulk capacitors has become a crucial challenge for designers. Summary of the Invention

[0006] The purpose of the present invention is to provide an OCL-LDO circuit, including a bandgap reference unit, a super source follower, a bias circuit, a power transistor M P , error amplifier, flip voltage follower, frequency compensation unit and high-pass network;

[0007] The bandgap reference unit generates a reference voltage and a reference current;

[0008] The bandgap reference unit outputs a reference voltage to the flip voltage follower and the inverting input terminal of the error amplifier, and outputs a reference current to the bias circuit;

[0009] The super source follower and the power transistor M P The gate connection pushes the parasitic capacitance of the gate to high frequency, ensuring the stability of the output voltage of the power transistor MP;

[0010] The bias circuit provides a bias voltage for the current source in the OCL-LDO circuit;

[0011] The power transistor M P Perform charge and discharge operations; when the power transistor is discharging, the power transistor M P The drain of the LDO circuit serves as the output terminal, outputting voltage to the outside.

[0012] The error amplifier is used to generate a first-order gain voltage based on the input reference voltage and feedback voltage. The feedback voltage is generated at the gate of the error amplifier transistor M1 and comes from transistors M5, M12, and M14. A current mirror formed by transistor M11 in the flipped voltage follower and transistor M12 in the error amplifier replicates the first-order gain voltage to generate an output voltage of the same magnitude as the reference voltage VREF, which is then output externally.

[0013] The flip voltage follower forms a local loop for detecting changes in the voltage at the output end of the LDO circuit and suppressing undershoot and overshoot phenomena at the output end;

[0014] The frequency compensation unit is connected across the output end of the LDO circuit and the input end of the super source follower to optimize the stability of the system. Specifically, Miller compensation is used to increase the distance between the main pole at the gate of the transistor M22 and the parasitic pole at the output end, thereby increasing the phase margin and achieving high stability of the system.

[0015] The high-pass network is used to detect the voltage change at the output end of the LDO circuit and feed it back to the super source follower.

[0016] Furthermore, it also includes a power supply V IN ;

[0017] The power supply V INIt powers the super source follower, error amplifier, flip voltage follower, and bias circuit.

[0018] Furthermore, the super source follower includes a transistor M 21 , transistor M 22 , transistor M 23 and resistor R2;

[0019] One end of the resistor R2 is connected to the transistor M 23 The gate of the resistor R2 is grounded;

[0020] Transistor M 21 The drain of transistor M 23 The drain of transistor M 22 The source of the power transistor M P Gate connection;

[0021] Transistor M 21 The source is connected to the power supply V IN , transistor M 21 The gate of the transistor M in the bias circuit is connected B3 The gate;

[0022] Transistor M 22 The gates of the transistors M of the flip voltage follower are connected to 15 and transistor M 16 The drain of transistor M 22 The drain of transistor M 23 The gate of transistor M 23 The source is grounded.

[0023] Furthermore, the error amplifier includes a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M 12 , transistor M 14 ;

[0024] The sources of transistors M3 and M4 are connected to the power supply voltage V IN , the gates of transistors M3 and M4 are short-circuited with the drain of M3 and then connected to the drain of transistor M1;

[0025] The drain of the transistor M4 is connected to the drain of the transistor M2 and the gate of the transistor M5, and outputs a first-level gain voltage;

[0026] The gate of transistor M1 is connected to the drain of transistor M5 and the drain of transistor M 12 The source connection;

[0027] The gate of the transistor M2 is connected to the bandgap reference unit for receiving a reference voltage;

[0028] The source of transistors M1 and M2 is connected to the drain of transistor M6, the source of transistor M6 is grounded, and the gate of transistor M6 is connected to the bias circuit of transistor M1. B1 The gate;

[0029] The source of transistor M5 is connected to the power supply V IN ;

[0030] Transistor M 12 After the drain and gate are shorted, connect the transistor M 14 The drain;

[0031] Transistor M 14 The gate of the transistor M in the bias circuit is connected B1 The gate of transistor M 14 The source is grounded.

[0032] Furthermore, the flip voltage follower includes a transistor M 11 , transistor M 13 , transistor M 15 , transistor M 16 ;

[0033] Transistor M 11 , transistor M 13 The drain of transistor M is connected 15 The source of

[0034] Transistor M 11 The source of the power transistor M is connected P The drain of transistor M 11 The gate of the error amplifier transistor M is connected 12 The gate;

[0035] Transistor M 13 The gate of the transistor M in the bias circuit is connected B1 The gate of transistor M 13 The source is grounded;

[0036] Transistor M 15 The gate of transistor M is connected to the bandgap reference unit for receiving the reference voltage; 15 The drain of transistor M is connected 16 The drain;

[0037] Transistor M 16 The gate of the bias circuit is connected to the transistor M B3 The gate of transistor M 16 The source terminal is connected to the power supply.

[0038] Furthermore, the bias circuit includes a transistor M B1 , transistor M B2 , transistor MB3 ;

[0039] Transistor M B1 , transistor M B2 The source of transistor M is grounded. B1 The drain of the bandgap reference unit is connected to receive the reference current I bias ;

[0040] Transistor M B1 The gate and drain of the device are short-circuited and connected to one end of the resistor R1 in the high-pass network;

[0041] Transistor M B2 The gate is connected to the other end of the resistor R1;

[0042] Transistor M B3 The gate and drain of the transistor M are short-circuited. B2 The drain of transistor M B3 The source terminal is connected to the power supply.

[0043] Furthermore, transistor M B1 , transistor M B2 Form a current mirror.

[0044] Furthermore, the frequency compensation unit includes a capacitor C m ;

[0045] Capacitor C m One end is connected to the input of the super source follower, and the other end is connected to the output of the LDO circuit;

[0046] The input of the super source follower is transistor M 22 of the gate.

[0047] Furthermore, the high-pass network includes a resistor R1 and a capacitor C1;

[0048] One end of resistor R1 is connected to transistor M in the bias circuit B1 The other end of resistor R1 is connected to the gate of transistor M in the bias circuit. B2 The gate;

[0049] One end of capacitor C1 is connected to the output end of the LDO circuit, and the other end of capacitor C1 is connected to the transistor M in the bias circuit. B2 of the gate.

[0050] The technical benefits of this invention are undeniable. It introduces a unique output capacitor-less low-dropout (OCL-LDO) regulator, the core of which is a flip-voltage follower (FVF) with push-pull capability and an embedded super source follower (SSF) and high-pass network. This structure cleverly integrates a super source follower (SSF) with a high-pass network, embedded within a flip-voltage follower (FVF), resulting in a significant improvement in transient response.

[0051] This design not only eliminates the traditional LDO's reliance on large external output capacitors, thereby reducing the overall circuit size and cost, but also ensures rapid stabilization and precise control of the output voltage even with rapid changes in load current through the application of a high-pass network.

[0052] The present invention balances efficiency and performance, providing a more efficient, compact, and responsive option for power management in modern electronic devices. This design is particularly advantageous in applications where power stability is crucial.

[0053] This OCL-LDO regulator can be integrated on-chip, supports a wide load current range, provides high-precision output voltage, has fast transient response capability, efficiently utilizes the power tube area, achieves a high power supply rejection ratio, maintains high stability and low output ripple. These features make it an ideal choice for electronic products that pursue high performance and miniaturization. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 Schematic diagram of the structure of a flipped voltage follower (FVF) with an embedded super source follower (SSF) and a high-pass network (HPN) according to an embodiment of the present invention;

[0055] Figure 2 Schematic diagram of the structure of an OCL-LDO circuit with an embedded SSF based on FVF and Qualcomm network integration and enhanced transient response with a push-pull structure according to an embodiment of the present invention;

[0056] Figure 3 Schematic diagram of the circuit structure of an improved super source follower (SSF) in an embodiment of the present invention;

[0057] Figure 4 Graph showing frequency response of various loads in an embodiment of the present invention;

[0058] Figure 5 Schematic diagram of the transient response process of an embodiment of the present invention. DETAILED DESCRIPTION

[0059] The present invention will be further described below with reference to the following examples, but it should not be understood that the scope of the present invention is limited to the following examples. Without departing from the above technical ideas of the present invention, various substitutions and modifications can be made according to common technical knowledge and customary means in the art, and all should be included in the scope of protection of the present invention.

[0060] Example 1:

[0061] See also Figures 1 to 5 , an OCL-LDO circuit, including a bandgap reference unit, a super source follower, a bias circuit, a power transistor M P , error amplifier, flip voltage follower, frequency compensation unit and high-pass network;

[0062] The bandgap reference unit (generating a reference voltage and a reference current through an ideal voltage source and a current source) generates a reference voltage and a reference current;

[0063] The bandgap reference unit outputs a reference voltage to the flip voltage follower and the inverting input terminal of the error amplifier, and outputs a reference current to the bias circuit;

[0064] The super source follower and the power transistor M P The gate connection pushes the parasitic capacitance of the gate to high frequency, ensuring the stability of the output voltage of the power transistor MP;

[0065] The bias circuit provides a bias voltage for the current source in the OCL-LDO circuit; the current source here includes the tail current source of the error amplifier and other current sources (transistors M13, M14, M16, and M21 serve as current sources).

[0066] The power transistor M P Perform charge and discharge operations; when the power transistor is discharging, the power transistor M P The drain of the LDO circuit serves as the output terminal, outputting voltage to the outside.

[0067] The error amplifier is used to generate a first-order gain voltage for the input reference voltage and feedback voltage; the feedback voltage is generated at the gate of the error amplifier transistor M1 and comes from M5, M12, and M14. The current mirror composed of the transistor M11 in the flipped voltage follower and the transistor M12 in the error amplifier accurately replicates the first-order gain voltage, generates an output voltage of the same magnitude as the reference voltage VREF, and outputs it to the outside (outputting a precise 1.2V voltage V OUT , providing energy for other chip modules);

[0068] The flip-flop voltage follower forms a local loop, detecting changes in the LDO circuit's output voltage. By adjusting the gate voltages of each transistor, the output currents vary, thereby suppressing undershoot and overshoot at the output. When the flip-flop voltage follower is operating, all transistors are turned on. For example, during an undershoot, the gate voltage of M23 increases, increasing the leakage current and creating a current difference with transistor M21. This discharges the gate capacitance of transistor MP, thus suppressing undershoot.

[0069] The frequency compensation unit is connected across the output end of the LDO circuit and the input end of the super source follower to optimize the stability of the system. Specifically, Miller compensation is used to increase the distance between the main pole at the gate of the transistor M22 and the parasitic pole at the output end, thereby increasing the phase margin and achieving high stability of the system.

[0070] The high-pass network is used to detect the voltage change at the output end of the LDO circuit and feed it back to the super source follower.

[0071] Also includes power supply V IN ;

[0072] The power supply V IN It powers the super source follower, error amplifier, flip voltage follower, and bias circuit.

[0073] The super source follower includes a transistor M 21 , transistor M 22 , transistor M 23 and resistor R2;

[0074] One end of the resistor R2 is connected to the transistor M 23 The gate of the resistor R2 is grounded;

[0075] Transistor M 21 The drain of transistor M 23 The drain of transistor M 22 The source of the power transistor M P Gate connection;

[0076] Transistor M 21 The source is connected to the power supply V IN , transistor M 21 The gate of the transistor M in the bias circuit is connected B3 The gate;

[0077] Transistor M 22 The gates of the transistors M of the flip voltage follower are connected to 15 and transistor M 16 The drain of transistor M 22 The drain of transistor M 23 The gate of transistor M23 The source is grounded.

[0078] The error amplifier includes a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M 12 , transistor M 14 ;

[0079] The sources of transistors M3 and M4 are connected to the power supply voltage V IN , the gates of transistors M3 and M4 are short-circuited with the drain of M3 and then connected to the drain of transistor M1;

[0080] The drain of the transistor M4 is connected to the drain of the transistor M2 and the gate of the transistor M5, and outputs a first-level gain voltage;

[0081] The gate of transistor M1 is connected to the drain of transistor M5 and the drain of transistor M 12 The source connection;

[0082] The gate of the transistor M2 is connected to the bandgap reference unit for receiving a reference voltage;

[0083] The source of transistors M1 and M2 is connected to the drain of transistor M6, the source of transistor M6 is grounded, and the gate of transistor M6 is connected to the bias circuit of transistor M1. B1 The gate;

[0084] The source of transistor M5 is connected to the power supply V IN ;

[0085] Transistor M 12 After the drain and gate are shorted, connect the transistor M 14 The drain;

[0086] Transistor M 14 The gate of the transistor M in the bias circuit is connected B1 The gate of transistor M 14 The source is grounded.

[0087] The flip voltage follower includes a transistor M 11 , transistor M 13 , transistor M 15 , transistor M 16 ;

[0088] Transistor M 11 , transistor M 13 The drain of transistor M is connected 15 The source of

[0089] Transistor M 11 The source of the power transistor M is connected P The drain of transistor M11 The gate of the error amplifier transistor M is connected 12 The gate;

[0090] Transistor M 13 The gate of the transistor M in the bias circuit is connected B1 The gate of transistor M 13 The source is grounded;

[0091] Transistor M 15 The gate of transistor M is connected to the bandgap reference unit for receiving the reference voltage; 15 The drain of transistor M is connected 16 The drain;

[0092] Transistor M 16 The gate of the bias circuit is connected to the transistor M B3 The gate of transistor M 16 The source terminal is connected to the power supply.

[0093] The bias circuit includes a transistor M B1 , transistor M B2 , transistor M B3 ;

[0094] Transistor M B1 , transistor M B2 The source of transistor M is grounded. B1 The drain of the bandgap reference unit is connected to receive the reference current I bias ;

[0095] Transistor M B1 The gate and drain of the device are short-circuited and connected to one end of the resistor R1 in the high-pass network;

[0096] Transistor M B2 The gate is connected to the other end of the resistor R1;

[0097] Transistor M B3 The gate and drain of the transistor M are short-circuited. B2 The drain of transistor M B3 The source terminal is connected to the power supply.

[0098] Transistor M B1 , transistor M B2 Form a current mirror.

[0099] The frequency compensation unit includes a capacitor C m ;

[0100] Capacitor C m One end is connected to the input of the super source follower, and the other end is connected to the output of the LDO circuit;

[0101] The input of the super source follower is transistor M 22 of the gate.

[0102] The high-pass network includes a resistor R1 and a capacitor C1;

[0103] One end of resistor R1 is connected to transistor M in the bias circuit B1 The other end of resistor R1 is connected to the gate of transistor M in the bias circuit. B2 The gate;

[0104] One end of capacitor C1 is connected to the output end of the LDO circuit, and the other end of capacitor C1 is connected to the transistor M in the bias circuit. B2 of the gate.

[0105] Example 2:

[0106] An OCL-LDO circuit includes a bandgap reference unit, a super source follower, a bias circuit, a power transistor M P , error amplifier, flip voltage follower, frequency compensation unit and high-pass network;

[0107] The bandgap reference unit generates a reference voltage and a reference current;

[0108] The bandgap reference unit outputs a reference voltage to the flip voltage follower and the inverting input terminal of the error amplifier, and outputs a reference current to the bias circuit;

[0109] The super source follower and the power transistor M P The gate connection pushes the parasitic capacitance of the gate to high frequency, ensuring the stability of the output voltage of the power transistor MP;

[0110] The bias circuit provides a bias voltage for the tail current source of the error amplifier and other current sources;

[0111] The power transistor M P Perform charge and discharge operations; when the power transistor is discharging, the power transistor M P The drain of the LDO circuit serves as the output terminal, outputting voltage to the outside.

[0112] The error amplifier is used to generate a first-order gain voltage for the input reference voltage and feedback voltage; the feedback voltage is generated at the gate of the error amplifier transistor M1 and comes from M5, M12, and M14.

[0113] The flip voltage follower forms a local loop for detecting changes in the voltage at the output end of the LDO circuit and suppressing undershoot and overshoot phenomena at the output end;

[0114] The frequency compensation unit is connected across the output end of the LDO circuit and the input end of the super source follower to optimize the stability of the system. Specifically, Miller compensation is used to increase the distance between the main pole at the gate of the transistor M22 and the parasitic pole at the output end, thereby increasing the phase margin and achieving high stability of the system.

[0115] The high-pass network is used to detect the voltage change at the output end of the LDO circuit and feed it back to the super source follower.

[0116] Example 3:

[0117] An OCL-LDO circuit, the technical content is the same as that of embodiment 2, further comprising a power supply V IN ;

[0118] The power supply V IN It powers the super source follower, error amplifier, flip voltage follower, and bias circuit.

[0119] Example 4:

[0120] An OCL-LDO circuit, the technical content is the same as any one of embodiments 2-3, further, the super source follower includes a transistor M 21 , transistor M 22 , transistor M 23 and resistor R2;

[0121] One end of the resistor R2 is connected to the transistor M 23 The gate of the resistor R2 is grounded;

[0122] Transistor M 21 The drain of transistor M 23 The drain of transistor M 22 The source of the power transistor M P Gate connection;

[0123] Transistor M 21 The source is connected to the power supply V IN , transistor M 21 The gate of the transistor M in the bias circuit is connected B3 The gate;

[0124] Transistor M 22 The gates of the transistors M of the flip voltage follower are connected to 15 and transistor M 16 The drain of transistor M 22 The drain of transistor M 23 The gate of transistor M 23 The source is grounded.

[0125] Example 5:

[0126] An OCL-LDO circuit, the technical content is the same as any one of embodiments 2-4, further, the error amplifier includes a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M 12 , transistor M 14 ;

[0127] The sources of transistors M3 and M4 are connected to the power supply voltage V IN , the gates of transistors M3 and M4 are short-circuited with the drain of M3 and then connected to the drain of transistor M1;

[0128] The drain of the transistor M4 is connected to the drain of the transistor M2 and the gate of the transistor M5, and outputs a first-level gain voltage;

[0129] The gate of transistor M1 is connected to the drain of transistor M5 and the drain of transistor M 12 The source connection;

[0130] The gate of the transistor M2 is connected to the bandgap reference unit for receiving a reference voltage;

[0131] The source of transistors M1 and M2 is connected to the drain of transistor M6, the source of transistor M6 is grounded, and the gate of transistor M6 is connected to the bias circuit of transistor M1. B1 The gate;

[0132] The source of transistor M5 is connected to the power supply V IN ;

[0133] Transistor M 12 After the drain and gate are shorted, connect the transistor M 14 The drain;

[0134] Transistor M 14 The gate of the transistor M in the bias circuit is connected B1 The gate of transistor M 14 The source is grounded.

[0135] Example 6:

[0136] An OCL-LDO circuit, the technical content of which is the same as any one of embodiments 2-5, further, the flip voltage follower includes a transistor M 11 , transistor M 13 , transistor M 15 , transistor M 16 ;

[0137] Transistor M 11 , transistor M 13 The drain of transistor M is connected 15 The source of

[0138] Transistor M 11 The source of the power transistor M is connected P The drain of transistor M 11 The gate of the error amplifier transistor M is connected 12 The gate;

[0139] Transistor M 13 The gate of the transistor M in the bias circuit is connected B1 The gate of transistor M 13 The source is grounded;

[0140] Transistor M 15 The gate of transistor M is connected to the bandgap reference unit for receiving the reference voltage; 15 The drain of transistor M is connected 16 The drain;

[0141] Transistor M 16 The gate of the bias circuit is connected to the transistor M B3 The gate of transistor M 16 The source terminal is connected to the power supply.

[0142] Example 7:

[0143] An OCL-LDO circuit, the technical content of which is the same as any one of embodiments 2-6, further, the bias circuit includes a transistor M B1 , transistor M B2 , transistor M B3 ;

[0144] Transistor M B1 , transistor M B2 The source of transistor M is grounded. B1 The drain of the bandgap reference unit is connected to receive the reference current I bias ;

[0145] Transistor M B1 The gate and drain of the device are short-circuited and connected to one end of the resistor R1 in the high-pass network;

[0146] Transistor M B2 The gate is connected to the other end of the resistor R1;

[0147] Transistor M B3 The gate and drain of the transistor M are short-circuited. B2 The drain of transistor M B3 The source terminal is connected to the power supply.

[0148] Example 8:

[0149] An OCL-LDO circuit, the technical content is the same as any one of embodiments 2-7, further, the transistor MB1 , transistor M B2 Form a current mirror.

[0150] Example 9:

[0151] An OCL-LDO circuit, the technical content of which is the same as any one of embodiments 2-8, further, the frequency compensation unit includes a capacitor C m ;

[0152] Capacitor C m One end is connected to the input of the super source follower, and the other end is connected to the output of the LDO circuit;

[0153] The input of the super source follower is transistor M 22 of the gate.

[0154] Example 10:

[0155] An OCL-LDO circuit, having the same technical content as any one of Embodiments 2-9, wherein the high-pass network further comprises a resistor R1 and a capacitor C1;

[0156] One end of resistor R1 is connected to transistor M in the bias circuit B1 The other end of resistor R1 is connected to the gate of transistor M in the bias circuit. B2 The gate;

[0157] One end of capacitor C1 is connected to the output end of the LDO circuit, and the other end of capacitor C1 is connected to the transistor M in the bias circuit. B2 of the gate.

[0158] Example 11:

[0159] An OCL-LDO circuit, comprising:

[0160] a bandgap reference unit, for generating a reference voltage and outputting the reference voltage to an inverting input terminal of the error amplifier;

[0161] Super source follower (SSF), connected to the power transistor M P The gate pushes the parasitic capacitance at the gate to high frequency to ensure system stability;

[0162] a bias circuit that provides a fixed bias voltage for the tail current source of the error amplifier (EA) and other current sources;

[0163] a power transistor for performing intelligent charge and discharge operations based on an input super source follower (SSF) output voltage and outputting the voltage as an output terminal;

[0164] The error amplifier is used to generate a first-level gain voltage for the input reference voltage and feedback voltage;

[0165] The flip voltage follower (FVF) forms a local loop, which can quickly detect the sharp change of the output voltage and quickly suppress the undershoot and overshoot phenomena at the output.

[0166] The frequency compensation unit is connected across the output of the LDO circuit and the input of the super source follower (SSF) to optimize the frequency response of the output voltage control loop and achieve high system stability.

[0167] High-pass network, used to detect output voltage changes and provide timely feedback to the super source follower (SSF);

[0168] The super source follower (SSF) includes a transistor M 21 、M 22 、M 23 and resistor R2, one end of which is connected to transistor M 23 The gate of the transistor M 21 and M 23 The drain of transistor M 22 The source of the power transistor M P The gate of transistor M 21 The source is connected to the power supply voltage V IN , transistor M 21 The gate of transistor M B3 The gate of transistor M 22 The gate of transistor M 15 and M 16 The drain of transistor M 22 The drain of transistor M 23 The gate of transistor M 23 The source is grounded.

[0169] The error amplifier includes transistors M1, M2, M3, M4, M5, M6, M 12 、M 14 , the sources of transistors M3 and M4 are connected to the power supply voltage V IN , the gates of M3 and M4 are short-circuited with the drain of M3 and then connected to the drain of M1. The drain of M4 is connected to the drain of M2 and the gate of M5 and outputs a first-level gain voltage. The gate of M1 is connected to the drain of M5 and M 12 The source of M1 and M2 is connected to the drain of M6, the source of M6 is grounded, and the gate of M6 is connected to the reference voltage. B1 The gate of M5 is connected to the power supply voltage V IN , M 12 After the drain and gate are shorted, connect M 14 The drain, M 14 The gate connection M B1Gate, M 14 The source is grounded.

[0170] The flip voltage follower (FVF) includes a transistor M 11 、M 13 、M 15 、M 16 , where M 11 、M 13 The drain connection M 15 The source, M 11 The source connection M P The drain, M 11 The gate connection M 12 Gate, M 13 The gate connection M B1 Gate, M 13 The source is grounded, M 15 The gate is connected to the reference voltage V REF , M 15 The drain connection M 16 The drain, M 16 The gate is connected to M B3 Gate, M 16 The source is connected to the power supply voltage V IN .

[0171] The bias circuit includes a transistor M B1 、M B2 、M B3 , M B1 、M B2 Forming a current mirror, M B1 、M B2 The source is grounded, M B1 The drain connection reference current I bias , M B1 The gate and drain of the M are short-circuited and connected to one end of the resistor R1. B2 The gate is connected to the other end of the resistor R1, M B3 The gate and drain of the M B2 The drain, M B3 The source is connected to the power supply voltage V IN .

[0172] The frequency compensation unit includes a capacitor C m , capacitor C m One end is connected to the input of the super source follower (SSF), that is, the transistor M 22 The gate of the transistor M is connected to the output of the LDO circuit. P of the drain.

[0173] The high-pass network includes a resistor R1 and a capacitor C1. One end of the resistor R1 is connected to MB1 The other end of resistor R1 is connected to M B2 The gate of the capacitor C1 is connected to the output end of the LDO circuit, that is, the transistor M P The other end of capacitor C1 is connected to the drain of M B2 of the gate.

[0174] Example 12:

[0175] An OCL-LDO circuit, the contents are as follows:

[0176] Figure 1 FIG. 1 is a schematic structural diagram of a flip voltage follower (FVF) with an embedded super source follower (SSF) and a high-pass network (HPN) according to an embodiment of the present invention. Figure 1 As shown, the LDO circuit includes:

[0177] 1) Super source follower, connected to power transistor M P The gate pushes the parasitic capacitance at the gate to high frequency to ensure system stability, including transistor M 21 、M 22 、M 23 and resistor R2, one end of which is connected to transistor M 23 The gate of the transistor M 21 and M 23 The drain of transistor M 22 The source of the power transistor M P The gate of transistor M 21 The source is connected to the power supply voltage V IN , transistor M 21 The gate of transistor M B3 The gate of transistor M 22 The gate of transistor M 15 and M 16 The drain of transistor M 22 The drain of transistor M 23 The gate of transistor M 23 The source is grounded.

[0178] Supply voltage V IN Generally, it is 1.5V to 1.8V, and its typical value is 1.5V, which is used as the power supply for the entire OCL-LDO. By setting the load capacitance C L For 1pF, the corresponding load driving current can be 0.1~50mA, so the stable output voltage V of OCL-LDO can be obtained. OUT , its typical value is 1.2V.

[0179] 2) Flip the voltage follower to form a local loop, which can quickly detect the sharp change of the output voltage and quickly suppress the undershoot and overshoot of the output, including the transistor M 11 、M 13 、M 15 、M 16 , where M 11 、M 13 The drain connection M 15 The source, M 11 The source connection M P The drain, M 11 The gate connection M 12 Gate, M 13 The gate connection M B1 Gate, M 13 The source is grounded, M 15 The gate is connected to the reference voltage V REF , M 15 The drain connection M 16 The drain, M 16 The gate is connected to M B3 Gate, M 16 The source is connected to the power supply voltage V IN .

[0180] 3) A power transistor, the power transistor MP is used to perform intelligent charging and discharging operations based on the input super source follower output voltage and output voltage as an output terminal;

[0181] 4) High-pass network, used to detect the output voltage change and timely feedback to the super source follower (SSF), including resistor R1 and capacitor C1, one end of resistor R1 is connected to M B1 The other end of resistor R1 is connected to M B2 The gate of the capacitor C1 is connected to the output end of the LDO circuit, that is, the transistor M P The other end of capacitor C1 is connected to the drain of M B2 of the gate.

[0182] 5) Bias circuit, which provides a fixed bias voltage for the tail current source of the error amplifier (EA) and other current sources, including transistor M B1 、M B2 、M B3 , M B1 、M B2 Forming a current mirror, M B1 、M B2 The source is grounded, M B1 The drain connection reference current I bias , M B1 The gate and drain of the M are short-circuited and connected to one end of the resistor R1. B2The gate is connected to the other end of the resistor R1, M B3 The gate and drain of the M B2 The drain, M B3 The source is connected to the power supply voltage V IN .

[0183] like Figure 2 As shown in the red path, when the output voltage V OUT When the output voltage overshoots, the output voltage change is fed back in time through the high-pass network, and finally the transistor M in the super source follower (SSF) is realized. 21 The change of leakage current has an impact on the power transistor M P The gate of the MOSFET is quickly charged to suppress the overshoot of the output voltage. Figure 2 As shown in the blue path, when the output voltage undershoot occurs, the output voltage change is fed back in time through a fast local loop, and finally the transistor M in the super source follower (SSF) is realized. 23 The change of leakage current has an impact on the power transistor M P The gate of the transistor is quickly discharged to suppress the undershoot of the output voltage. Therefore, a push-pull structure of the circuit is formed.

[0184] 6) Error amplifier, used to generate a first-level gain voltage for the input reference voltage and feedback voltage, including transistors M1, M2, M3, M4, M5, M6, M 12 、M 14 , the sources of transistors M3 and M4 are connected to the power supply voltage V IN , the gates of M3 and M4 are short-circuited with the drain of M3 and then connected to the drain of M1. The drain of M4 is connected to the drain of M2 and the gate of M5 and outputs a first-level gain voltage. The gate of M1 is connected to the drain of M5 and M 12 The source of M1 and M2 is connected to the drain of M6, the source of M6 is grounded, and the gate of M6 is connected to the reference voltage. B1 The gate of M5 is connected to the power supply voltage V IN , M 12 After the drain and gate are shorted, connect M 14 The drain, M 14 The gate connection M B1 Gate, M 14 The source is grounded.

[0185] 7) A frequency compensation unit is connected across the output of the LDO circuit and the input of the super source follower (SSF) to optimize the frequency response of the output voltage control loop and achieve high system stability. The unit includes a capacitor Cm. One end of the capacitor Cm is connected to the input of the super source follower (SSF), i.e., the gate of the transistor M22, and the other end is connected to the output of the LDO circuit, i.e., the drain of the transistor MP.

[0186] The super source follower (SSF) receives the output signal from the high-pass network and the voltage flip follower, and P The gate performs intelligent charging and discharging operations. This process ensures that the M P The transistor leakage current is quickly adjusted, thus significantly improving the transient response performance of the system. This innovative flip voltage follower (FVF) structure with embedded super source follower (SSF) and high pass network (HPN) is used to ensure the stability of the system. 24 Replace it with a resistor R2 with a smaller resistance, such as Figure 3 As shown, the transistor M 23 The gate parasitic pole is pushed toward high frequencies.

[0187] like Figure 2 As shown in Figure 2, when the output load transitions from full load to no load, the high-pass network and super source follower (SSF) work together to reduce M 21 The gate voltage increases the M 21 This mechanism effectively reduces the voltage overshoot at the output.

[0188] On the contrary, when the output load switches from no-load to full-load, the flip voltage follower (FVF) and super source follower (SSF) work together to improve M 23 The gate voltage increases the M 23 This action promotes the rapid discharge of the power transistor gate and effectively suppresses the voltage undershoot at the output. 21 and M 23 It forms a push-pull structure with fast charging and discharging capabilities.

[0189] like Figure 4 Figure 2 illustrates the amplitude-frequency and phase-frequency characteristics of the entire FVF-based OCL-LDO regulator with embedded SSF and Qualcomm network integration for enhanced transient response under different current load conditions. The phase margin exceeds 110° from a light load of 100μA to a full load of 50mA. This circuit system achieves highly stable performance over a wide load range.

[0190] like Figure 5 As shown in Figure 2, the transient response process of the proposed OCL-LDO is illustrated.

[0191] The introduced high-pass network is denoted as a slew rate enhancement circuit (SRE). Under conditions of an edge time of 300ns and a load capacitance of only 1pF, when the load current jumps from 100μA to 50mA, the undershoot voltage drops from 96.3mV to 68.2mV, with a recovery time of only approximately 1μs. When the load current jumps from 50mA to 100μA, the overshoot voltage drops from 188.2mV to 79.9mV, with a recovery time of less than 2μs, effectively suppressing both overshoot and undershoot. These results demonstrate the effective verification of the proposed FVF-based OCL-LDO regulator with an embedded SSF and high-pass network integrated to enhance transient response.

Claims

1. An OCL-LDO circuit, characterized in that: Including bandgap reference unit, super source follower, bias circuit, power transistor M P , error amplifier, flip voltage follower, frequency compensation unit and high-pass network; The bandgap reference unit generates a reference voltage and a reference current; The bandgap reference unit outputs a reference voltage to the flip voltage follower and the inverting input terminal of the error amplifier, and outputs a reference current to the bias circuit; The super source follower and the power transistor M P The gate connection pushes the parasitic capacitance of the gate to high frequency, ensuring that the power transistor M P Output voltage stability; The bias circuit provides a bias voltage for the current source in the OCL-LDO circuit; The power transistor M P Perform charge and discharge operations; when the power transistor is discharging, the power transistor M P The drain of the LDO circuit serves as the output terminal, outputting voltage to the outside. The error amplifier is used to generate a first-order gain voltage based on the input reference voltage and feedback voltage; the feedback voltage is generated at the gate of the error amplifier transistor M1; a current mirror composed of the transistor M11 in the flipped voltage follower and the transistor M12 in the error amplifier replicates the first-order gain voltage to generate an output voltage of the same magnitude as the reference voltage VREF, and outputs it externally; The flip voltage follower forms a local loop for detecting changes in the voltage at the output end of the LDO circuit and suppressing undershoot and overshoot phenomena at the output end; The frequency compensation unit is connected across the output end of the LDO circuit and the input end of the super source follower to optimize the stability of the system; The high-pass network is used to detect the voltage change at the output end of the LDO circuit and feed it back to the super source follower.

2. An OCL-LDO circuit according to claim 1, characterized in that: Also includes power supply V IN ; The power supply V IN It powers the super source follower, error amplifier, flip voltage follower, and bias circuit.

3. An OCL-LDO circuit according to claim 1, characterized in that: The super source follower includes a transistor M 21 , transistor M 22 , transistor M 23 and resistor R2; One end of the resistor R2 is connected to the transistor M 23 The gate of the resistor R2 is grounded; Transistor M 21 The drain of transistor M 23 The drain of transistor M 22 The source of the power transistor M P Gate connection; Transistor M 21 The source is connected to the power supply V IN , transistor M 21 The gate of the transistor M in the bias circuit is connected B3 The gate; Transistor M 22 The gates of the transistors M of the flip voltage follower are connected to 15 and transistor M 16 The drain of transistor M 22 The drain of transistor M 23 The gate; Transistor M 23 The source is grounded.

4. The OCL-LDO circuit according to claim 1, wherein: The error amplifier includes a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M 12 , transistor M 14 ; The sources of transistors M3 and M4 are connected to the power supply voltage V IN , the gates of transistors M3 and M4 are short-circuited with the drain of M3 and then connected to the drain of transistor M1; The drain of the transistor M4 is connected to the drain of the transistor M2 and the gate of the transistor M5, and outputs a first-level gain voltage; The gate of transistor M1 is connected to the drain of transistor M5 and the drain of transistor M 12 The source connection; The gate of the transistor M2 is connected to the bandgap reference unit for receiving a reference voltage; The source of transistors M1 and M2 is connected to the drain of transistor M6, the source of transistor M6 is grounded, and the gate of transistor M6 is connected to the bias circuit of transistor M1. B1 The gate; The source of transistor M5 is connected to the power supply V IN ; Transistor M 12 After the drain and gate are shorted, connect the transistor M 14 The drain; Transistor M 14 The gate of the transistor M in the bias circuit is connected B1 The gate of transistor M 14 The source is grounded.

5. The OCL-LDO circuit according to claim 1, wherein: The flip voltage follower includes a transistor M 11 , transistor M 13 , transistor M 15 , transistor M 16 ; Transistor M 11 , transistor M 13 The drain of transistor M is connected 15 The source of Transistor M 11 The source of the power transistor M is connected P The drain of transistor M 11 The gate of the error amplifier transistor M is connected 12 The gate; Transistor M 13 The gate of the transistor M in the bias circuit is connected B1 The gate of transistor M 13 The source is grounded; Transistor M 15 The gate is connected to a bandgap reference unit for receiving a reference voltage; Transistor M 15 The drain of transistor M is connected 16 The drain; Transistor M 16 The gate of the bias circuit is connected to the transistor M B3 The gate of transistor M 16 The source terminal is connected to the power supply.

6. The OCL-LDO circuit according to claim 1, wherein: The bias circuit includes a transistor M B1 , transistor M B2 , transistor M B3 ; Transistor M B1 , transistor M B2 The source of transistor M is grounded. B1 The drain of the bandgap reference unit is connected to receive the reference current I bias ; Transistor M B1 The gate and drain of the device are short-circuited and connected to one end of the resistor R1 in the high-pass network; Transistor M B2 The gate is connected to the other end of the resistor R1; Transistor M B3 The gate and drain of the transistor M are short-circuited. B2 The drain of transistor M B3 The source terminal is connected to the power supply.

7. The OCL-LDO circuit according to claim 6, wherein: Transistor M B1 , transistor M B2 Form a current mirror.

8. The OCL-LDO circuit according to claim 1, wherein: The frequency compensation unit includes a capacitor C m ; Capacitor C m One end is connected to the input of the super source follower, and the other end is connected to the output of the LDO circuit; The input of the super source follower is transistor M 22 of the gate.

9. The OCL-LDO circuit according to claim 1, wherein: The high-pass network includes a resistor R1 and a capacitor C1; One end of resistor R1 is connected to transistor M in the bias circuit B1 The other end of resistor R1 is connected to the gate of transistor M in the bias circuit. B2 The gate; One end of capacitor C1 is connected to the output end of the LDO circuit, and the other end of capacitor C1 is connected to the transistor M in the bias circuit. B2 of the gate.

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