PE compilation method and system of an AI chip

Abstract

The application discloses a PE compiling method of an AI chip, comprising the following steps: obtaining source code, preprocessing the obtained source code to obtain preprocessed source code, performing lexical analysis and syntax analysis on the preprocessed source code in sequence to obtain a syntax tree corresponding to the source code, processing the syntax tree by using a semantic analyzer to generate a symbol table, generating an intermediate representation corresponding to the preprocessed source code according to the syntax tree and the symbol table and using a code conversion module inside a low-level virtual machine (LLVM) compiler, converting each of all operations and all data structures in the intermediate representation corresponding to the preprocessed source code into a corresponding PE instruction according to a PE instruction set specification of the AI chip, and performing parallel optimization on each PE instruction by multiple PEs to obtain an execution result of the optimized PE instruction. The application can solve the technical problem that a traditional compiler cannot fully exert performance because PE optimization is not performed for the AI chip.

Description

Technical Field

[0001] The present invention belongs to the field of computer technology, and more specifically, relates to a processing element (PE) compilation method and system for an artificial intelligence (AI) chip. Background Art

[0002] With the rapid development of artificial intelligence (AI) technology, AI computing is placing increasing demands on hardware performance. This has necessitated the emergence of AI chips, of which the processing unit (PE) is a key component. Compilation is performed by executing PE instructions. By dynamically adjusting the internal structure and configuration of the PE array, AI chips can further optimize computing performance, reduce energy consumption, and reduce hardware costs.

[0003] Existing PE compilers mainly include traditional compilers and specialized compilers developed for specific architectures.

[0004] However, both of the above-mentioned PE compilers have some defects that cannot be ignored: First, since traditional compilers are not PE-optimized for AI chips, they cannot fully exert their performance; second, dedicated compilers have poor versatility and high cost, and cannot adapt to various algorithm models; third, the computing resources of the above-mentioned two PE compilers are not allocated reasonably, so they cannot fully utilize the hardware resources of the PE array. Summary of the Invention

[0005] In response to the above-mentioned defects or improvement needs in the prior art, the present invention provides a PE compilation method and system for an AI chip. Its purpose is to convert code written in a high-level programming language into a PE instruction set optimized for self-reconfigurable and self-evolving AI chips by preprocessing the source code, generating an intermediate representation, mapping it to a PE instruction set, and optimizing the steps. This method solves the technical problem that traditional compilers cannot fully exert their performance because they are not PE optimized for AI chips, the technical problem that dedicated compilers have poor versatility, high cost, and cannot adapt to multiple algorithm models, and the technical problem that the two existing PE compilers cannot fully utilize the hardware resources of the PE array due to unreasonable allocation of computing resources.

[0006] To achieve the above objectives, according to one aspect of the present invention, a PE compilation method for an AI chip is provided, comprising the following steps:

[0007] (1) Obtain source code;

[0008] (2) preprocessing the source code obtained in step (1) to obtain preprocessed source code;

[0009] (3) performing lexical analysis and grammatical analysis on the source code preprocessed in step (2) to obtain a syntax tree corresponding to the source code, and processing the syntax tree using a semantic analyzer to generate a symbol table;

[0010] (4) generating an intermediate representation corresponding to the preprocessed source code based on the syntax tree and symbol table obtained in step (3) and using a code conversion module within the low-level virtual machine LLVM compiler;

[0011] (5) converting all operations and all data structures in the intermediate representation corresponding to the preprocessed source code obtained in step (4) into corresponding PE instructions according to the PE instruction set specification of the AI ​​chip;

[0012] (6) Each PE instruction obtained in step (5) is optimized in parallel by multiple PEs to obtain the execution result of the optimized PE instruction.

[0013] Preferably, step (1) is to obtain the source code by reading a code file.

[0014] Step (2) is to use the preprocessor provided by the compiler to process the macro definition and conditional compilation in the source code, thereby obtaining the preprocessed source code.

[0015] Preferably, step (3) is specifically as follows: first, the preprocessed source code is processed using a lexical analyzer Flex, specifically, the source code is decomposed into multiple lexical units, such as identifiers, keywords, operators, etc.; then, the lexical units are combined into a syntax tree according to the grammatical rules of the programming language using a syntax analyzer Bison to represent the structure of the preprocessed source code; finally, the semantic analyzer is used to check the semantic errors in the syntax tree and generate a symbol table.

[0016] Step (4) is to generate an intermediate representation using the code conversion module inside the LLVM compiler.

[0017] Preferably, step (5) is based on the PE instruction set specification of the AI ​​chip, and uses the instruction mapping module of the LLVM compiler to map all operations and each of all data structures in the intermediate representation into PE instructions that can be understood by the PE instruction set.

[0018] Preferably, step (6) includes the following sub-steps:

[0019] (6-1) creating a first instruction group list and a second instruction group list for storing a plurality of instruction groups;

[0020] (6-2) Set counter cnt1 = 1;

[0021] (6-3) Determine whether cnt1 is greater than the total number of PE instructions obtained in step (5). If so, proceed to step (6-6); otherwise, proceed to step (6-4).

[0022] (6-4) Determine whether there is no dependency between the cnt1th PE instruction among all the PE instructions obtained in step (5) and any PE instruction in any instruction group in the instruction group list. If so, add the instruction to a new instruction group, add the instruction group to the first instruction group list, set cnt1 = cnt1 + 1, and return to step (6-3); otherwise, go to step (6-5);

[0023] (6-5) adding the cnt1th PE instruction among all PE instructions obtained in step (5) to each instruction group in the first instruction group list that has a dependency relationship with the PE instruction;

[0024] (6-6) obtaining computing resource information required by each instruction group in the first instruction group list, and prioritizing all instruction groups according to the computing resources required by each instruction group in the first instruction group list, thereby obtaining an updated first instruction group list;

[0025] (6-7) Setting counter i = the number of instruction groups in the updated first instruction group list obtained in step (6-6);

[0026] (6-8) Determine the load and available resources of each PE;

[0027] (6-9) Determine whether i is greater than 0. If so, proceed to step (6-10), otherwise proceed to step (6-15);

[0028] (6-10) Set counter cnt2 = the number of idle PEs and PE positions obtained in step (6-8);

[0029] (6-11) Determine whether cnt2 is greater than 0. If so, proceed to step (6-12), otherwise proceed to step (6-14);

[0030] (6-12) obtaining an instruction group with the highest priority in the first instruction group list in step (6-5), deleting it from the first instruction group list, and adding it to the second instruction group list;

[0031] (6-13) Determine multiple idle PEs based on the parallelism of all PE instructions in the instruction group obtained in step (6-12), select multiple idle PEs with suitable PE positions from all the idle PEs, set cnt2 = cnt2 - the number of all determined idle PEs, and return to step (6-11);

[0032] (6-14) using the multiple idle PEs with suitable PE positions selected in step (6-13) to execute all PE instructions in the instruction group at their PE positions to obtain the execution results of all PE instructions, and updating the status information of all PEs, setting i = the number of remaining instruction groups in the first instruction group list, and returning to step (6-8);

[0033] (6-15) Output the execution results of all PE instructions and the process ends.

[0034] Preferably, in step (6-13), a plurality of idle PEs are determined based on the parallelism of all PE instructions in the instruction group obtained in step (6-12), and a plurality of idle PEs with suitable PE positions are selected from all the idle PEs. This process includes the following sub-steps:

[0035] (6-13-1) constructing a dependency graph based on all PE instructions in the instruction group obtained in (6-12) to represent the dependency relationship between each PE instruction;

[0036] (6-13-2) parsing the dependency graph obtained in step (6-13-1) using a topological sorting algorithm to determine a plurality of idle PEs by analyzing the parallelism of all PE instructions in the instruction group obtained in step (6-12);

[0037] (6-13-3) Determine whether there is an instruction group in the second instruction group list that has the same computing resources as the instruction group obtained in step (6-12). If so, obtain the PE position and number of PEs allocated to the instruction group, and then proceed to step (6-13-4). Otherwise, proceed to step (6-13-5).

[0038] (6-13-4) Allocate a PE position for each idle PE obtained in step (6-13-2), and the PE position allocated to each idle PE is physically close to the PE position of the PE allocated to the instruction group obtained in step (6-13-3), and the process ends;

[0039] (6-13-5) Randomly assign a PE position to each idle PE obtained in step (6-13-2), and the process ends.

[0040] Preferably, step (6-13-1) is specifically as follows: first, the dependency relationship between each pair of PE instructions in the instruction group is obtained, and then a dependency graph is constructed based on all the dependencies and using a directed graph tool.

[0041] According to another aspect of the present invention, a PE compilation system for an AI chip is provided, comprising:

[0042] The first module is used to obtain source code;

[0043] The second module is used to preprocess the source code obtained by the first module to obtain preprocessed source code;

[0044] The third module is used to perform lexical analysis and grammatical analysis on the source code preprocessed by the second module to obtain a syntax tree corresponding to the source code, and process the syntax tree using a semantic analyzer to generate a symbol table;

[0045] The fourth module is used to generate an intermediate representation corresponding to the preprocessed source code based on the syntax tree and symbol table obtained in the third module and using the code conversion module inside the low-level virtual machine LLVM compiler;

[0046] The fifth module is used to convert all operations and all data structures in the intermediate representation corresponding to the preprocessed source code obtained by the fourth module into corresponding PE instructions according to the PE instruction set specification of the AI ​​chip;

[0047] The sixth module is used to perform parallel optimization on each PE instruction obtained by the fifth module through multiple PEs to obtain the execution result of the optimized PE instruction.

[0048] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects compared with the prior art:

[0049] 1. In step (6), the present invention uses multiple PEs to perform parallel optimization on each PE instruction obtained in step (5), thereby solving the problem that traditional compilers are not optimized for AI chip PEs and cannot fully utilize their performance;

[0050] 2. The method of allocating PE positions adopted in step (6) of the present invention can support dynamic reconfiguration of the PE array, enabling the chip to adjust computing resources and connection structures in real time according to different application scenarios, thereby improving the chip's adaptability to multiple algorithm models. Therefore, it can solve the technical problems of existing dedicated compilers, such as poor versatility, high cost, and inability to adapt to multiple algorithm models.

[0051] 3. The present invention adopts step (6) and adopts a method of allocating PE positions to make PEs with duplicate computing resources close in physical location, thereby optimizing computing resource allocation. At the same time, all PEs perform compilation work, ensuring that the hardware resources of the PE array are fully utilized and reducing computing resource waste;

[0052] 4. The present invention has a wide range of applications. Through compiler optimization, various algorithm models (such as YOLOv5, LSTM, GRU, etc.) can be mapped to the PE array, enhancing the versatility and flexibility of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1It is a flow chart of the PE compilation method of the AI ​​chip of the present invention. DETAILED DESCRIPTION

[0054] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

[0055] like Figure 1 As shown, the present invention provides a PE compilation method for an AI chip, comprising the following steps:

[0056] (1) Obtain source code;

[0057] Specifically, this step is to obtain the source code by reading the code file.

[0058] (2) preprocessing the source code obtained in step (1) to obtain preprocessed source code;

[0059] Specifically, this step uses the preprocessor provided by the compiler to process macro definitions and conditional compilation in the source code, thereby obtaining preprocessed source code.

[0060] (3) performing lexical analysis and grammatical analysis on the preprocessed source code to obtain a syntax tree corresponding to the source code, and processing the syntax tree using a semantic analyzer to generate a symbol table;

[0061] Specifically, this step first uses a lexical analyzer (Flex) to process the preprocessed source code, specifically decomposing the source code into multiple lexical units, such as identifiers, keywords, operators, etc.; then, using a syntax analyzer (Bison), according to the grammatical rules of the programming language, the lexical units are combined into a syntax tree to represent the structure of the preprocessed source code. Finally, a semantic analyzer is used to check for semantic errors in the syntax tree and generate a symbol table for the subsequent compilation process.

[0062] (4) generating an intermediate representation corresponding to the preprocessed source code based on the syntax tree and symbol table obtained in step (3) and using a code conversion module within a Low Level Virtual Machine (LLVM) compiler;

[0063] Specifically, this step uses the code conversion module inside the LLVM compiler to generate an intermediate representation, which can concisely represent the semantic information of the source code and facilitate subsequent optimization and code generation.

[0064] (5) converting all operations and all data structures in the intermediate representation corresponding to the preprocessed source code obtained in step (4) into corresponding PE instructions according to the PE instruction set specification of the AI ​​chip;

[0065] Specifically, this step uses the LLVM compiler's instruction mapping module to map all operations and data structures in the intermediate representation into PE instructions that the PE instruction set understands, based on the AI ​​chip's PE instruction set specification. By analyzing and optimizing the intermediate representation, the number and complexity of instructions are minimized, improving execution efficiency.

[0066] (6) performing parallel optimization on each PE instruction obtained in step (5) through multiple PEs to obtain an execution result of the optimized PE instruction;

[0067] Specifically, this step uses the optimization module in the LLVM compiler to perform instruction reordering operations on PE instructions to improve parallelism and utilize hardware characteristics, thereby obtaining optimized PE instructions.

[0068] This step (6) includes the following sub-steps:

[0069] (6-1) creating a first instruction group list and a second instruction group list for storing a plurality of instruction groups;

[0070] (6-2) Set counter cnt1 = 1;

[0071] (6-3) Determine whether cnt1 is greater than the total number of PE instructions obtained in step (5). If so, proceed to step (6-6); otherwise, proceed to step (6-4).

[0072] (6-4) Determine whether there is no dependency between the cnt1th PE instruction among all the PE instructions obtained in step (5) and any PE instruction in any instruction group in the instruction group list. If so, add the instruction to a new instruction group, add the instruction group to the first instruction group list, set cnt1 = cnt1 + 1, and return to step (6-3); otherwise, go to step (6-5);

[0073] The advantage of this step is that a parallel instruction group can be obtained, so that multiple PEs can execute PE instructions in parallel.

[0074] (6-5) adding the cnt1th PE instruction among all PE instructions obtained in step (5) to each instruction group in the first instruction group list that has a dependency relationship with the PE instruction;

[0075] (6-6) obtaining computing resource information required for each instruction group in the first instruction group list, and prioritizing all instruction groups according to the computing resources (such as memory resources, communication resources, etc.) required by each instruction group in the first instruction group list (i.e., the instruction group requiring the most computing resources has the highest priority), thereby obtaining an updated first instruction group list;

[0076] (6-7) Setting counter i = the number of instruction groups in the updated first instruction group list obtained in step (6-6);

[0077] (6-8) Determine the load and available resources of each PE;

[0078] (6-9) Determine whether i is greater than 0. If so, proceed to step (6-10), otherwise proceed to step (6-15);

[0079] (6-10) Set counter cnt2 = the number of idle PEs and PE positions obtained in step (6-8);

[0080] (6-11) Determine whether cnt2 is greater than 0. If so, proceed to step (6-12), otherwise proceed to step (6-14);

[0081] (6-12) obtaining an instruction group with the highest priority in the first instruction group list in step (6-5), deleting it from the first instruction group list, and adding it to the second instruction group list;

[0082] (6-13) Determine multiple idle PEs based on the parallelism of all PE instructions in the instruction group obtained in step (6-12), select multiple idle PEs with suitable PE positions from all the idle PEs, set cnt2 = cnt2 - the number of all determined idle PEs, and return to step (6-11);

[0083] In this step, multiple idle PEs are determined based on the parallelism of all PE instructions in the instruction group obtained in steps (6-12), and multiple idle PEs with suitable PE positions are selected from all the idle PEs. This process includes the following sub-steps:

[0084] (6-13-1) constructing a dependency graph based on all PE instructions in the instruction group obtained in (6-12) to represent the dependency relationship between each PE instruction;

[0085] Specifically, this step first obtains the dependency relationship between each pair of PE instructions in the instruction group, and then constructs a dependency graph based on all the dependencies using a directed graph tool.

[0086] (6-13-2) parsing the dependency graph obtained in step (6-13-1) using a topological sorting algorithm to determine a plurality of idle PEs by analyzing the parallelism of all PE instructions in the instruction group obtained in step (6-12);

[0087] (6-13-3) Determine whether there is an instruction group in the second instruction group list that has the same computing resources as the instruction group obtained in step (6-12). If so, obtain the PE position and number of PEs allocated to the instruction group, and then proceed to step (6-13-4). Otherwise, proceed to step (6-13-5).

[0088] (6-13-4) Allocate a PE position for each idle PE obtained in step (6-13-2), and the PE position allocated to each idle PE is physically close to the PE position of the PE allocated to the instruction group obtained in step (6-13-3), and the process ends;

[0089] The advantage of this step is that it makes the PEs with duplicate computing resources close to each other in physical locations, thereby optimizing the allocation of computing resources.

[0090] (6-13-5) Randomly assign a PE position to each idle PE obtained in step (6-13-2), and the process ends;

[0091] The advantages of step (6-13-4) and step (6-13-5) are that the PE instructions of various algorithm models can be mapped to the PE, and the PE position of the PE can be allocated, thereby enhancing the versatility and flexibility of the chip.

[0092] (6-14) using the multiple idle PEs with suitable PE positions selected in step (6-13) to execute all PE instructions in the instruction group at their PE positions to obtain the execution results of all PE instructions, and updating the status information of all PEs, setting i = the number of remaining instruction groups in the first instruction group list, and returning to step (6-8);

[0093] The advantage of this step is that all PEs perform compilation work, ensuring that the hardware resources of the PE array are fully utilized and reducing the waste of computing resources.

[0094] (6-15) Output the execution results of all PE instructions and the process ends.

[0095] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A PE compilation method for an AI chip, characterized in that: The following steps are involved: (1) Obtain source code; (2) preprocessing the source code obtained in step (1) to obtain preprocessed source code; (3) Performing lexical analysis and grammatical analysis on the source code preprocessed in step (2) to obtain a syntax tree corresponding to the source code, and processing the syntax tree using a semantic analyzer to generate a symbol table; (4) Based on the syntax tree and symbol table obtained in step (3), the intermediate representation corresponding to the preprocessed source code is generated using the code conversion module inside the low-level virtual machine LLVM compiler; (5) According to the PE instruction set specification of the AI ​​chip, all operations and all data structures in the intermediate representation corresponding to the preprocessed source code obtained in step (4) are converted into corresponding PE instructions; (6) Optimizing each PE instruction obtained in step (5) in parallel through multiple PEs to obtain the execution result of the optimized PE instruction; step (6) includes the following sub-steps: (6-1) Creating a first instruction group list and a second instruction group list for storing a plurality of instruction groups; (6-2) Set counter cnt1=1; (6-3) Determine whether cnt1 is greater than the total number of PE instructions obtained in step (5). If so, proceed to step (6-6), otherwise proceed to step (6-4). (6-4) Determine whether there is no dependency between the cnt1th PE instruction among all the PE instructions obtained in step (5) and any PE instruction in any instruction group in the instruction group list. If so, add the instruction to a new instruction group, add the instruction group to the first instruction group list, set cnt1=cnt1+1, and return to step (6-3); otherwise, go to step (6-5); (6-5) adding the cnt1th PE instruction among all the PE instructions obtained in step (5) to each instruction group in the first instruction group list that has a dependency relationship with the PE instruction; (6-6) Obtaining computing resource information required by each instruction group in the first instruction group list, and prioritizing all instruction groups according to the computing resources required by each instruction group in the first instruction group list, thereby obtaining an updated first instruction group list; (6-7) Setting a counter i = the number of instruction groups in the updated first instruction group list obtained in step (6-6); (6-8) Determine the load and available resources of each PE; (6-9) Determine whether i is greater than 0. If so, proceed to step (6-10), otherwise proceed to step (6-15); (6-10) Set counter cnt2 = the number of idle PEs and PE positions obtained in step (6-8); (6-11) Determine whether cnt2 is greater than 0. If so, proceed to step (6-12), otherwise proceed to step (6-14); (6-12) Obtaining an instruction group with the highest priority in the first instruction group list in step (6-5), deleting it from the first instruction group list, and adding it to the second instruction group list; (6-13) Determine multiple idle PEs based on the parallelism of all PE instructions in the instruction group obtained in step (6-12), select multiple idle PEs with suitable PE positions from all the idle PEs, set cnt2 = cnt2 - the number of all determined idle PEs, and return to step (6-11); (6-14) using the multiple idle PEs with suitable PE positions selected in step (6-13) to execute all PE instructions in the instruction group at their PE positions to obtain the execution results of all PE instructions, and updating the status information of all PEs, setting i = the number of remaining instruction groups in the first instruction group list, and returning to step (6-8); (6-15) Output the execution results of all PE instructions and the process ends.

2. The PE compilation method for an AI chip according to claim 1, characterized in that: Step (1) is to obtain the source code by reading the code file; Step (2) is to use the compiler's built-in preprocessor to process the macro definitions and conditional compilation in the source code, thereby obtaining the preprocessed source code.

3. The PE compilation method for an AI chip according to claim 1 or 2, characterized in that: Step (3) is as follows: first, the lexical analyzer Flex is used to process the preprocessed source code, specifically, the source code is decomposed into multiple lexical units; then, the grammatical analyzer Bison is used to combine the lexical units into a syntax tree according to the grammatical rules of the programming language to represent the structure of the preprocessed source code; finally, the semantic analyzer is used to check the semantic errors in the syntax tree and generate a symbol table; Step (4) is to generate an intermediate representation using the code transformation module inside the LLVM compiler.

4. The PE compilation method for an AI chip according to claim 3, characterized in that: Step (5) is to map all operations and all data structures in the intermediate representation into PE instructions that can be understood by the PE instruction set according to the PE instruction set specification of the AI ​​chip and using the instruction mapping module of the LLVM compiler.

5. The PE compilation method for an AI chip according to claim 1, characterized in that: In step (6-13), a plurality of idle PEs are determined based on the parallelism of all PE instructions in the instruction group obtained in step (6-12), and a plurality of idle PEs with suitable PE positions are selected from all the idle PEs. This process includes the following sub-steps: (6-13-1) constructing a dependency graph based on all PE instructions in the instruction group obtained in (6-12) to represent the dependency relationship between each PE instruction; (6-13-2) parsing the dependency graph obtained in step (6-13-1) using a topological sorting algorithm to determine multiple idle PEs by analyzing the parallelism of all PE instructions in the instruction group obtained in step (6-12); (6-13-3) Determine whether there is an instruction group in the second instruction group list that has the same computing resources as the instruction group obtained in step (6-12). If so, obtain the PE position and number of PEs allocated to the instruction group, and then proceed to step (6-13-4). Otherwise, proceed to step (6-13-5). (6-13-4) Allocate a PE position for each idle PE obtained in step (6-13-2), and the PE position allocated to each idle PE is physically close to the PE position of the PE allocated to the instruction group obtained in step (6-13-3). The process ends; (6-13-5) Randomly assign a PE position to each idle PE obtained in step (6-13-2), and the process ends.

6. The PE compilation method for an AI chip according to claim 5, characterized in that: Specifically, step (6-13-1) is to first obtain the dependency relationship between each pair of PE instructions in the instruction group, and then construct a dependency graph based on all the dependencies using a directed graph tool.

7. A PE compilation system for an AI chip, characterized in that: include: The first module is used to obtain source code; The second module is used to preprocess the source code obtained by the first module to obtain preprocessed source code; The third module is used to perform lexical analysis and grammatical analysis on the source code preprocessed by the second module to obtain a syntax tree corresponding to the source code, and process the syntax tree using a semantic analyzer to generate a symbol table; The fourth module is used to generate an intermediate representation corresponding to the preprocessed source code based on the syntax tree and symbol table obtained in the third module and using the code conversion module inside the low-level virtual machine LLVM compiler; The fifth module is used to convert all operations and all data structures in the intermediate representation corresponding to the preprocessed source code obtained by the fourth module into corresponding PE instructions according to the PE instruction set specification of the AI ​​chip; a sixth module, configured to perform parallel optimization on each PE instruction obtained by the fifth module through multiple PEs to obtain an execution result of the optimized PE instruction; The sixth module includes the following sub-steps: (6-1) Creating a first instruction group list and a second instruction group list for storing a plurality of instruction groups; (6-2) Set counter cnt1=1; (6-3) Determine whether cnt1 is greater than the total number of PE instructions obtained by the fifth module. If so, proceed to step (6-6); otherwise, proceed to step (6-4). (6-4) Determine whether there is no dependency between the cnt1th PE instruction among all PE instructions obtained by the fifth module and any PE instruction in any instruction group in the instruction group list. If so, add the instruction to a new instruction group, add the instruction group to the first instruction group list, set cnt1=cnt1+1, and return to step (6-3); otherwise, go to step (6-5); (6-5) Add the cnt1th PE instruction from all PE instructions obtained by the fifth module to each instruction group in the first instruction group list that has a dependency relationship with the PE instruction; (6-6) Obtaining computing resource information required by each instruction group in the first instruction group list, and prioritizing all instruction groups according to the computing resources required by each instruction group in the first instruction group list, thereby obtaining an updated first instruction group list; (6-7) Setting a counter i = the number of instruction groups in the updated first instruction group list obtained in step (6-6); (6-8) Determine the load and available resources of each PE; (6-9) Determine whether i is greater than 0. If so, proceed to step (6-10), otherwise proceed to step (6-15); (6-10) Set counter cnt2 = the number of idle PEs and PE positions obtained in step (6-8); (6-11) Determine whether cnt2 is greater than 0. If so, proceed to step (6-12), otherwise proceed to step (6-14); (6-12) Obtaining an instruction group with the highest priority in the first instruction group list in step (6-5), deleting it from the first instruction group list, and adding it to the second instruction group list; (6-13) Determine multiple idle PEs based on the parallelism of all PE instructions in the instruction group obtained in step (6-12), select multiple idle PEs with suitable PE positions from all the idle PEs, set cnt2 = cnt2 - the number of all determined idle PEs, and return to step (6-11); (6-14) using the multiple idle PEs with suitable PE positions selected in step (6-13) to execute all PE instructions in the instruction group at their PE positions to obtain the execution results of all PE instructions, and updating the status information of all PEs, setting i = the number of remaining instruction groups in the first instruction group list, and returning to step (6-8); (6-15) Output the execution results of all PE instructions and the process ends.

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