Processor structure, chip and electronic device based on odd-even scheduling and allocation

Abstract

The present invention relates to the field of processor technology, and provides a processor structure, chip and electronic device based on odd-even scheduling and allocation. The processor structure based on odd-even scheduling and allocation provided by the present invention divides an idle physical register stack into an odd part and an even part in a renaming stage, and determines whether an odd physical register or an even physical register is allocated for a current renaming according to the instruction type. The embodiment provided by the present invention can reduce the write port of the register stack by half, cooperate with a register allocation balancing algorithm, and effectively perform physical register allocation and instruction scheduling.

Description

Technical Field

[0001] The present invention relates to the field of processor technology, and in particular to a processor structure, chip and electronic equipment based on odd-even scheduling and allocation. Background Art

[0002] In a superscalar processor, an important stage is register renaming, which solves the Read after Write (RAW) correlation by allocating physical registers in the free physical register list freeList to achieve the purpose of out-of-order execution. Therefore, a key component is the physical register file, which is usually divided into different register files according to type, such as integer register file, floating point register file, and vector register file. However, how to allocate physical registers and schedule instructions is a problem that the industry urgently needs to solve. Summary of the invention

[0003] In view of the problems existing in the prior art, the present invention provides a processor structure, chip and electronic device based on parity scheduling and allocation.

[0004] A first aspect of the present invention provides a processor structure based on odd-even scheduling and allocation, comprising a front-end instruction fetch unit, an instruction decoding unit, a renaming unit, a dispatch unit, a plurality of reservation stations, a plurality of execution units and two register stacks which are sequentially coupled and connected; wherein the instruction decoding unit is used to generate a control signal for instruction diversion based on the type of instructions to be processed; the number of the reservation stations and the execution units is the same as the number of the types of instructions to be processed;

[0005] The dispatch unit is used to dispatch and divert the instructions to be processed according to the control signal;

[0006] Each of the execution units includes an odd execution unit and an even execution unit, the two register files include an odd register file and an even register file, the odd execution unit in the execution unit is coupled to the odd register file, and the even execution unit in the execution unit is coupled to the even register file;

[0007] The renaming unit is used to rename the registers of the pending instructions; the renaming unit stores an odd register list OddFreeList and an even register list EvenFreeList, and the table entries of the OddFreeList and the EvenFreeList store the numbers of free physical registers; the renaming unit determines whether to allocate free physical registers according to the type of the pending instructions and determines whether to allocate registers in the OddFreeList or in the EvenFreeList based on the state of the ping-pong signal corresponding to each type; wherein the ping-pong signal flips its state according to whether the previous instruction allocates odd or even.

[0008] Optionally, the dispatch unit includes a misc dispatch queue and a load / store dispatch queue. It is known that the dispatch unit can be divided into more detailed categories according to requirements, for example, the misc dispatch queue can be divided into alu, mul, etc.

[0009] Optionally, the reservation station includes an arithmetic reservation station ALU Reservation, a mixed reservation station MiscReservation, a write reservation station Load Reservation and a store reservation station Store Reservation; wherein the ALUReservation and the Misc Reservation are coupled to the misc dispatch queue, and the LoadReservation and the Store Reservation are coupled to the load / store dispatch queue.

[0010] Optionally, the execution unit includes an arithmetic ALU execution unit, a mixed Misc execution unit, a write Load execution unit and a store Store execution unit; wherein:

[0011] The ALU execution unit is coupled to the ALU Reservation, the Misc execution unit is coupled to the Misc Reservation, the Load execution unit is coupled to the Load Reservation, and the Store execution unit is coupled to the Store Reservation.

[0012] Optionally, the structures of the OddFreeList and the EvenFreeList are first-in-first-out queues FIFO read and written by pointers.

[0013] Optionally, the renaming unit is further configured to determine whether to preferentially allocate physical registers from the odd register file or from the even register file in the current renaming stage based on the number of odd / even instructions of each type in the previous renaming stage.

[0014] Optionally, the status array statusArray in the reservation station includes an odd status array odd statusArray and an even status array even statusArray, and when the pending instruction is queued for update, the two oddstatusArray and even statusArray are updated simultaneously.

[0015] Optionally, the renaming unit is further used to update a corresponding counter according to whether an odd or even number is allocated when a physical register is allocated for the instruction to be processed, and the counter is used to update corresponding queue pointers respectively.

[0016] A second aspect of the present invention provides a chip, comprising the processor structure based on parity scheduling and allocation as described in the first aspect.

[0017] A third aspect of the present invention provides an electronic device, comprising the chip described in the second aspect.

[0018] The processor structure, chip and electronic device based on odd-even scheduling and allocation provided by the present invention divide the idle physical register stack into odd and even parts in the renaming stage, and determine whether the current renaming is to allocate an odd physical register or an even physical register according to the instruction type. The embodiment provided by the present invention can reduce the write port of the register stack by half, and cooperate with the register allocation balancing algorithm to effectively perform physical register allocation and instruction scheduling. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 A schematic diagram of a processor structure based on odd-even scheduling and allocation provided in an embodiment of the present invention.

[0021] Figure 2 A schematic diagram of the structure of a register list freeList provided in an embodiment of the present invention.

[0022] Figure 3A schematic diagram of allocating physical registers in the renaming stage provided by an embodiment of the present invention.

[0023] Figure 4 A schematic diagram of register allocation balance in the renaming phase provided by an embodiment of the present invention.

[0024] Figure 5 A schematic diagram of the generation logic of various types of ping-pong signals for the first instruction in the renaming phase provided by an embodiment of the present invention.

[0025] Figure 6 A schematic diagram of allocBalance logic determining allocation pointer update in the renaming phase provided by an embodiment of the present invention.

[0026] Figure 7 A schematic diagram of the release and update process of allocBalance provided in an embodiment of the present invention.

[0027] Figure 8 A schematic diagram of a source operand wake-up logic in a dataArray in a reservation station provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] For each additional write port in the register file, the increase in standard cells, area, and critical path is as follows:

[0030] 1. Increase in standard units:

[0031] Each additional write port requires an N-bit write address decoder, with a complexity of O(log2N). Each register requires an N-input multiplexer, also with a complexity of O(log2N). Therefore, the total increase in standard cells is O(M log2 N), where M is the number of register bits. For example, for a 32-bit, 32-register register file, each additional write port will increase the number of standard cells by approximately 32. log2 32 = 160 standard cells.

[0032] 2. Area increase:

[0033] The increase in area is mainly reflected in the increase in the area of ​​the write address decoder and the multiplexer circuit. The area complexity of these two parts of the circuit is proportional to log2 N, so the total area increase is also approximately O(M log2 N). For the above example, the area increase is also about 160 standard cells.

[0034] 3. Increase of critical path:

[0035] Each additional write port requires the addition of a corresponding write address decoder and multiplexer circuit. These circuits increase the critical path delay of the register stack by approximately O(log2 N). For the example of 32 registers, the critical path delay increases by approximately log2 32 = 5 standard cell delays.

[0036] In summary, each additional write port in the register file increases the number of standard cells by approximately O(M log2 N), the area increase is about O(M log2 N), and the critical path delay increases by about O(log2 N). Therefore, the number of read and write ports of the register stack directly affects the area and read and write timing of the register. The embodiments of the present invention provide a solution, and divide the free physical register stack into odd and even parts during the renaming stage. Each renaming even_freeList provides a renaming width renameWidth free registers, and odd_freeList provides renameWidth free registers. The instruction determines whether the current renaming is to allocate an odd physical register or an even physical register according to the instruction type and the balance logic of odd and even allocation. Through the embodiments of the present invention, the write ports of the register stack can be reduced by half, the write timing of the register stack is optimized, and physical register allocation and instruction scheduling are effectively performed.

[0037] Figure 1 A schematic diagram of a processor structure based on parity scheduling and allocation provided by an embodiment of the present invention, such as Figure 1 As shown, the processor includes a front-end instruction fetch unit 112, an instruction decoding unit 113, a renaming unit 114, a dispatch unit 115, reservation stations 122A, 122B, 122C, 122D, execution units 124, 125, 126, and 127, and two register files.

[0038] As will be appreciated by those skilled in the art, the number of reservation stations and execution units is the same as the number of types of instructions to be processed. Figure 1In the embodiment shown, the types of instructions to be processed may include four types (arithmetic ALU type, mixed Misc type, write Load type and store Store type), so there are also four reservation stations and execution units, which are respectively set corresponding to each type. In actual design, it can be designed according to needs and is not limited to this.

[0039] The instruction decoding unit 113 is used to generate a control signal for instruction diversion based on the type of the instruction to be processed. The instruction to be processed will obtain a control signal of the execution unit type fuType after passing through the Decode Unit 113. This signal is usually used as a control signal for instruction diversion. For example, in this example, the instructions are divided into alu type, misc type (other arithmetic instructions except alu instructions, usually with a long or non-fixed execution cycle, such as multiplication and division instructions, etc.), and load / store memory access instruction type.

[0040] Each execution unit includes two execution components (even / odd), namely the odd execution component and the even execution component. Figure 1 ExeUnit 124 in contains Even-ExeUnit 124A and Odd_ExeUnit 124B.

[0041] like Figure 1 As shown, in this embodiment, the front-end instruction fetch unit 112 is coupled to the instruction decoding unit 113, the instruction decoding unit 113 is coupled to the renaming unit 114, and the renaming unit 114 is coupled to the dispatch unit 115. The dispatch unit 115 includes two dispatch queues, namely, a misc dispatch queue 120A and a load / store dispatch queue 120B.

[0042] In this example, the register file includes two register files, namely an odd register file 130B and an even register file 130A. The odd execution unit in each execution unit is coupled to the odd register file 130B, and the even execution unit in each execution unit is coupled to the even register file 130A.

[0043] In this example, the dispatch unit 115 is used to dispatch and divert the pending instructions according to the control signal, that is, the pending instructions are diverted according to whether they are memory access types during the dispatch stage, and are coupled to the misc dispatch queue 120A and the load / store dispatch queue 120B respectively.

[0044] Based on the above-mentioned four categories of pending instructions, in this example, the reservation stations may include an arithmetic reservation station ALU Reservation 122A, a mixed reservation station Misc Reservation 122B, a write reservation station Load Reservation 122C, and a store reservation station Store Reservation 122D. The ALU Reservation and the Misc Reservation are coupled to the misc dispatch queue, and the Load Reservation and the Store Reservation are coupled to the load / store dispatch queue. Figure 1 As shown, the miscdispatch queue 120A couples the Alu Reservation 122A and the Misc Reservation 122B, and the load / store dispatch queue 120B couples the load Reservation 122C and the store Reservation 122D.

[0045] In this example, the execution unit includes an arithmetic ALU execution unit, a mixed Misc execution unit, a write Load execution unit, and a store Store execution unit; wherein: the ALU execution unit is coupled to the ALU Reservation, the Misc execution unit is coupled to the Misc Reservation, the Load execution unit is coupled to the LoadReservation, and the Store execution unit is coupled to the Store Reservation. Specifically, Figure 1 As shown, Alu Reservation 122A is coupled to ExuUnit 124, Misc Reservation 122B is coupled to ExuUnit 125, load Reservation 122C is coupled to ExuUnit 126, and store reservation 122D is coupled to ExuUnit 127. Even-ExeUnit 124A, EvenExeUnit 125A, and Even-ExeUnit 126A are coupled to EvenRegFile 130A, and Oven-ExeUnit 124B, Odd-ExeUnit 125B, and Odd-ExeUnit 126B are coupled to OddRegFile 130B. It should be noted that this implementation may include Figure 1Other combinations and interfaces not shown.

[0046] The renaming unit 114 is used to rename registers for instructions to be processed. The register renaming technology is to allocate temporary physical registers to instructions instead of directly using the logical registers referenced in the instructions. Through register renaming, a temporary physical register can be allocated to each instruction, thereby avoiding conflicts such as read-after-write (WAR) and write-after-write (WAW), and improving execution efficiency.

[0047] Figure 2 Schematic diagram of the structure of the register list freeList provided in an embodiment of the present invention. In this embodiment, freeList is split into two, namely, the odd register list OddFreeList and the even register list EvenFreeList. Figure 2 As shown, the evenOddFreeList 160 is composed of two submodules, the even register list EvenFreeList 160A and the odd register list OddFreeList 160B. The structures of the OddFreeList and the EvenFreeList can be pointer read-write first-in-first-out queue FIFO, and the table entries store the numbers of free physical registers.

[0048] The renaming unit 114 determines whether to allocate free physical registers according to the type of the pending instruction and determines whether to allocate registers in the OddFreeList or the EvenFreeList based on the state of the ping-pong signal corresponding to each type; wherein the state of the ping-pong signal is flipped according to whether the previous instruction allocated an odd or even state. Specifically, the renaming unit 114 also maintains a plurality of ping-pong signals, and each ping-pong signal corresponds to the type of the pending instruction, for example, an ALU type pending instruction corresponds to a ping-pong signal, etc. The state of the ping-pong signal switches between "0" and "1", for example, "0" represents "true", corresponding to allocating registers from the even register stack 130A; "1" represents "false", corresponding to allocating registers from the odd register stack 130A. For example, when the register allocated for the previous ALU type instruction comes from the even register stack 130A, it will trigger a state change of the ping-pong signal, for example, from "0" to "1", and the next ALU type instruction needs to allocate a register from the odd register stack 130A.

[0049] In an embodiment of the present invention, the emission selection algorithm in the default reservation station can be an emission algorithm based on the age matrix, which distinguishes even / odd from the masks of the source operands in the reservation station that are ready for emission and the last bit of the physical destination register, and selects the relatively oldest one from the even / odd.

[0050] Figure 3 A schematic diagram of allocating physical registers in the renaming phase provided by an embodiment of the present invention. In each cycle, even physical registers with a renaming width of (e.g., 10) are given from EvenFreeList 160A, and odd physical registers with a renaming width of (e.g., 10) are given from OddFreeList 160B. The process of determining the destination physical register number of each instruction is as follows: Figure 3 As shown:

[0051] Determine the instruction type. In this embodiment, instructions are divided into the following categories: alu, misc, load / store (not limited to this in actual implementation, but the execution unit type connected to the reservation station must be coupled). Determine whether the destination register is really needed (there are many conditions for this, such as store instructions, which naturally have no destination register, and direct jump instructions jump also have no register rd. In this embodiment, arithmetic instructions without destination registers are classified into the alu category). If register rd is really needed, then decide whether to allocate from the odd free physical register stack or the even free physical register stack based on whether this type of ping-pong signal (in this implementation, it is divided into 4 categories, alu_pingpong, misc_pingpong, load_pingpong, store_pingpong, where store_pingpong is a false ping-pong, do not use allocBalance logic) is true or false. For example, ping-pong is true, indicating allocation from the even free physical register, and vice versa, allocation from the odd free physical register. The register renaming width instructions implement this logic serially, and the ping-pong logic of each instruction needs to be flipped based on whether the previous instruction was assigned odd or even.

[0052] When the last instruction completes the above process, the mask allocated by the even channel is accumulated to update EvenFreeList160A even_enqPtr, and the mask allocated by the odd channel is accumulated to update OddFreeList 160B odd_enqPtr. The update logic of EvenFreeList 160A even_deqPtr: when the instruction is committed, the old even physical register is written back (based on the lowest bit of the physical register number being 0); when rolling back (walk), only the number of rolled back even physical registers needs to be calculated to roll back even_deqPtr, and there is no need to update the table entry content.

[0053] Furthermore, in implementation, the unbalanced register parity allocation may easily cause the parallelism of the execution unit to change from the actual 2 to 1. For example, consider a situation where Figure 1 Therefore, ExuUnit 124, if two instructions have all operands ready at the same time, but the destination physical registers are all even or all odd, the two instructions can only be issued serially from the reservation station, while the other execution unit is idle. Therefore, the embodiment of the present invention also provides register allocation balancing logic. For example, the renaming unit 114 is also used to determine whether to allocate physical registers from the odd register stack or from the even register stack in the current renaming stage based on the number of odd / even instructions of each type in the previous renaming stage, that is, considering the number of odd and even instructions of each type from the entire processing core to determine which type of idle physical register stack to allocate physical registers from in the current renaming stage.

[0054] Figure 4 A schematic diagram of register allocation balance in the renaming phase provided by an embodiment of the present invention, Figure 5 A schematic diagram of the logic for generating various types of ping-pong signals for the first instruction of the renaming phase provided by an embodiment of the present invention, in an organizational structure such as Figure 4 As shown in fuType evenOddBalance 180, fuType in this embodiment refers to alu, misc and load. The structure is a fifo maintained by the queue entry and the queue exit pointer. The distance between the head and tail pointers (actually calculated is the occupied table entry) is used to determine which of the odd and even items is emptier. This signal is used to actually control the ping-pong of the first instruction. For example, if even>= odd, ping-pong is set to true, such as Figure 5 shown.

[0055] Figure 6The allocBalance logic determines the allocation pointer update schematic diagram of the renaming stage provided by the embodiment of the present invention. The renaming unit 114 is also used to update the corresponding counter counter according to whether the allocation is odd or even when a physical register is allocated to the pending instruction, and the counter counter is used to update the corresponding queue pointer respectively. Specifically, the allocBalance allocation update process is as follows Figure 6 As shown, all valid instructions entering the Rename Unit 114 stage execute this logic serially. Taking the load instruction as an example, a single instruction determines in parallel whether there is a destination register. If so, the state of the ping-pong signal is determined; if the state of the ping-pong signal is true, "load evenalloc mask is set to 1", and if the state of the ping-pong signal is false, "load odd alloc mask is set to 1". It is similar to the instruction and will not be repeated.

[0056] The destination register is really needed to update the corresponding counter according to whether the allocation is odd or even, and the final counter is used to update the corresponding queue pointer respectively.

[0057] Figure 7 The release update flow diagram of allocBalance provided in the embodiment of the present invention, the release logic of allocBalance is as follows Figure 7 As shown in the figure, this diagram only uses the alu type as an example. The instruction is updated during the commit or rollback (walk) phase:

[0058] 1. commit:

[0059] a. even: Determine the write enable according to isAlu_even&&!old_pdest.lsb (the lowest bit of the old physical register) given by the instruction in the renaming stage.

[0060] b. odd: Determine the write enable according to isAlu_odd&&old_pdest.lsb assigned by the instruction in the renaming stage.

[0061] 2. walk:

[0062] a. even: The step size of the dequeue pointer back off is determined by isAlu_even&&!pdest.lsb given by the instruction in the renaming stage.

[0063] b. odd: The step size of the dequeue pointer retreat is further determined according to the isAlu_odd&&pdest.lsb assigned by the instruction in the renaming stage.

[0064] Figure 8 A source operand wake-up logic diagram in dataArray in a reservation station provided in an embodiment of the present invention, wherein a status array statusArray in the reservation station includes an odd status array odd statusArray and an even status array evenstatusArray. When the pending instruction is queued and updated, the two odd statusArray and evenstatusArray are updated simultaneously.

[0065] Specifically, the reservation station wake-up logic is that part of the organization structure in the statusArray in the reservation station is as follows: Figure 8 As shown, the example here assumes that the alu type instruction has two source operands, psrc_0 and psrc_1. When the instruction is updated in the queue, two blocks (even / odd) are updated at the same time. The even execution unit or the even reservation station fast wakeup port is directly hardwired to even_dataArray 170A, and the odd execution unit or the odd reservation station fast wakeup port is directly hardwired to odd_dataArray170B. In this design, when a copy of the psrc array is made, although the circuit level of determining the destination register is log2N, where N is the number of reservation station wakeup ports, the wakeup ports are directly hardwired into two groups, and the fan-out of each wakeup port is reduced by half, which reduces the insertion of the drive buffer and is beneficial to the timing.

[0066] The processor structure based on odd-even scheduling and allocation provided by the present invention divides the idle physical register stack into odd and even parts in the renaming stage, and determines whether to allocate an odd physical register or an even physical register according to the instruction type. The embodiment provided by the present invention can reduce the write ports of the register stack by half, and cooperate with the physical register allocation balancing algorithm and the scheduling algorithm to effectively reduce the number of write ports of the register stack while ensuring performance, and effectively perform physical register allocation and instruction scheduling.

[0067] An embodiment of the present invention also provides a chip, which is applied to an electronic device. The chip includes one or more processors and a communication interface. The communication interface is coupled to the processor. The processor can adopt the processor structure based on parity scheduling and allocation provided in the above-mentioned embodiments, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0068] It should be understood that the chip mentioned in the embodiment of the present invention may also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0069] An embodiment of the present invention further provides an electronic device, the electronic device comprising a chip. The chip is a processor provided in the above embodiments. The processor can adopt the processor structure based on parity scheduling and allocation provided in the above embodiments, and can achieve the same technical effect, so it will not be repeated here to avoid repetition.

[0070] The electronic device provided by the embodiment of the present invention may include a handheld device, a vehicle-mounted device, etc. having an image processing function. For example, some electronic devices are: mobile phones, tablet computers, PDAs, laptop computers, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDAs), handheld devices with wireless communication capabilities, computing devices or other processing devices connected to wireless modems, vehicle-mounted devices, wearable devices, terminal devices in 5G networks or future evolved public land mobile communication networks (publicland mobile The embodiment of the present invention does not limit this.

[0071] As an example but not limitation, in an embodiment of the present invention, the electronic device may also be a wearable device. Wearable devices may also be referred to as wearable smart devices, which are a general term for wearable devices that are intelligently designed and developed using wearable technology for daily wear, such as glasses, gloves, watches, clothing, and shoes. A wearable device is a portable device that is worn directly on the body or integrated into the user's clothes or accessories. Wearable devices are not only hardware devices, but also powerful functions achieved through software support, data interaction, and cloud interaction. Broadly speaking, wearable smart devices include devices that are fully functional, large in size, and can achieve complete or partial functions without relying on smartphones, such as smart watches or smart glasses, as well as devices that only focus on a certain type of application function and need to be used in conjunction with other devices such as smartphones, such as various types of smart bracelets and smart jewelry for vital sign monitoring.

[0072] In addition, in the embodiments of the present invention, the electronic device may also be a terminal device in the Internet of Things (IoT) system. IoT is an important part of the future development of information technology. Its main technical feature is to connect objects to the network through communication technology, thereby realizing an intelligent network that interconnects people and machines and things.

[0073] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A processor structure based on odd-even scheduling and allocation, characterized in that: The invention comprises a front-end instruction fetch unit, an instruction decoding unit, a renaming unit, a dispatch unit, a plurality of reservation stations, a plurality of execution units and two register stacks which are sequentially coupled and connected; wherein the instruction decoding unit is used to generate a control signal for instruction diversion based on the type of the instruction to be processed; the number of the reservation stations and the execution units is the same as the number of the types of the instruction to be processed; The dispatch unit is used to dispatch and divert the instructions to be processed according to the control signal; Each of the execution units includes an odd execution unit and an even execution unit, the two register files include an odd register file and an even register file, the odd execution unit in the execution unit is coupled to the odd register file, and the even execution unit in the execution unit is coupled to the even register file; The renaming unit is used to rename registers of the pending instructions; the renaming unit stores an odd register list OddFreeList and an even register list EvenFreeList, and the table entries of the OddFreeList and the EvenFreeList store numbers of free physical registers; the renaming unit determines whether to allocate free physical registers according to the type of the pending instructions and determines whether to allocate registers in the OddFreeList or in the EvenFreeList based on the state of the ping-pong signal corresponding to each type; wherein the ping-pong signal flips state according to whether the last instruction allocates odd or even; The dispatch unit includes a mixed dispatch queue misc dispatch queue and a write / store dispatch queue load / store dispatch queue; The reservation stations include an arithmetic reservation station ALU Reservation, a mixed reservation station Misc Reservation, a write reservation station Load Reservation, and a store reservation station Store Reservation; wherein the ALU Reservation and the Misc Reservation are coupled and connected with the misc dispatch queue, and the Load Reservation and the Store Reservation are coupled and connected with the load / store dispatch queue; The execution unit includes an arithmetic ALU execution unit, a mixed Misc execution unit, a write Load execution unit and a store Store execution unit; wherein: The ALU execution unit is coupled to the ALU Reservation, the Misc execution unit is coupled to the Misc Reservation, the Load execution unit is coupled to the Load Reservation, and the Store execution unit is coupled to the Store Reservation.

2. The processor structure based on parity scheduling and allocation according to claim 1, characterized in that: The structures of the OddFreeList and the EvenFreeList are first-in-first-out queues FIFO read and written by pointers.

3. The processor structure based on parity scheduling and allocation according to claim 1, characterized in that: The renaming unit is further configured to determine whether to allocate physical registers from the odd register file or the even register file preferentially in the current renaming stage based on the number of odd / even instructions of each type in the previous renaming stage.

4. The processor structure based on parity scheduling and allocation according to claim 1, characterized in that: The status array statusArray in the reservation station includes an odd status array odd statusArray and an even status array evenstatusArray. When the pending instruction is queued for update, the two odd statusArray and evenstatusArray are updated simultaneously.

5. The processor structure based on parity scheduling and allocation according to claim 1, characterized in that: The renaming unit is also used to update the corresponding counter according to whether the allocated physical register is odd or even when a physical register is allocated for the pending instruction, and the counter is used to update the corresponding queue pointer respectively.

6. A chip, characterized in that: The invention comprises a processor structure based on odd-even scheduling and allocation as described in any one of claims 1 to 5.

7. An electronic device, characterized in that: Comprising the chip as claimed in claim 6.

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