Key protection circuit and method and memory
By designing a key protection circuit and using multiple sub-sequence circuits to output sequence signals, the complexity of key sequence input before HPPR/SPPR repair in DDR5 memory is solved, and the memory performance is improved and the stability of the repair process is achieved.
Patent Information
- Application Number
- CN202310782891.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-28
- Publication Date
- 2025-01-07
AI Technical Summary
Before performing hard post-package repair (HPPR) or temporary post-package repair (SPPR) of DDR5 memory, the key sequence needs to be protected by mode register write (MRW) to prevent PPR from being accidentally programmed, resulting in complex and error-prone repair.
A key protection circuit is designed, including a signal input circuit and a protection sequence circuit. The sequence signals are output in sequence through multiple sub-sequence circuits, and the HPPR/SPPR repair of the wrong row address is determined based on the final obtained target sequence signal to ensure the sequence signal. Output in sequence to avoid interrupts.
Simplifies the repair process, improves memory performance, ensures the accuracy and stability of HPPR/SPPR repair, and avoids repair failures caused by key sequence errors.
Smart Images
Figure CN119272350A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of memory technology, and relates to but is not limited to a key protection circuit, method and memory. Background Art
[0002] The fifth generation of Double Data Rate Five (DDR5) supports repairing some wrong row addresses. Among them, Post Package Repair (PPR) is a simple and easy repair method that can be used in the system; for example, Hard Post Package Repair (HPPR) for permanent row repair and Soft Post Package Repair (SPPR) for temporary row repair.
[0003] Before performing HPPR or SPPR, a Mode Register Write (MRW) protection key sequence is currently required to prevent the PPR from being accidentally programmed and to avoid affecting the repair of the erroneous row address. Summary of the invention
[0004] In view of this, embodiments of the present disclosure provide a key protection circuit, method, and memory.
[0005] In a first aspect, an embodiment of the present disclosure provides a key protection circuit, the key protection circuit comprising a signal input circuit and a protection sequence circuit, wherein:
[0006] The signal input circuit is used to receive a first enable signal and a target sequence signal, and perform a logic operation according to the first enable signal and the target sequence signal to obtain a second enable signal;
[0007] The protection sequence circuit includes multiple sub-sequence circuits, and the input end of each sub-sequence circuit is used to receive a mode control signal, the set end of each sub-sequence circuit is used to receive a mode write signal, the key end of the first sub-sequence circuit is used to receive the second enable signal, the output end of the i-th sub-sequence circuit is connected to the key end of the i+1-th sub-sequence circuit, and the output end of the last sub-sequence circuit is used to output the target sequence signal, and i is an integer greater than 0.
[0008] In some embodiments, the signal input circuit includes a first NOT gate and a first NOR gate, wherein:
[0009] The first NOT gate is used to perform a NOT logic operation on the first enable signal to obtain a third enable signal;
[0010] The first NOR gate is used to perform a NOR logic operation on the third enable signal and the target sequence signal to obtain the second enable signal.
[0011] In some embodiments, the key protection circuit further includes a reset circuit, wherein:
[0012] The reset circuit is used to generate a reset signal when the working state of the key protection circuit meets a preset condition, and the reset signal is connected to the reset end of each of the sub-sequence circuits.
[0013] In some embodiments, the protection sequence circuit includes four sub-sequence circuits, and the four sub-sequence circuits include a first sub-sequence circuit, a second sub-sequence circuit, a third sub-sequence circuit, and a fourth sub-sequence circuit, wherein:
[0014] The first subsequence circuit is used to receive the mode control signal, the mode write signal, the second enable signal and the reset signal, and perform a logic operation according to the mode control signal, the mode write signal, the second enable signal and the reset signal to obtain a first sequence signal;
[0015] The second subsequence circuit is used to receive the mode control signal, the mode write signal, the first sequence signal and the reset signal, and perform a logic operation according to the mode control signal, the mode write signal, the first sequence signal and the reset signal to obtain a second sequence signal;
[0016] The third subsequence circuit is used to receive the mode control signal, the mode write signal, the second sequence signal and the reset signal, and perform a logic operation according to the mode control signal, the mode write signal, the second sequence signal and the reset signal to obtain a third sequence signal;
[0017] The fourth subsequence circuit is used to receive the mode control signal, the mode write signal, the third sequence signal and the reset signal, and perform logic operations according to the mode control signal, the mode write signal, the third sequence signal and the reset signal to obtain the target sequence signal.
[0018] In some embodiments, the first sub-sequence circuit includes a first signal processing circuit, a second signal processing circuit and a third signal processing circuit, wherein:
[0019] The first signal processing circuit is used to perform logic processing on the mode control signal and the power supply signal to obtain a first target mode signal;
[0020] The second signal processing circuit is used to perform logic processing on the first target mode signal, the mode write signal and the second enable signal to obtain a first intermediate sequence signal;
[0021] The third signal processing circuit is used to perform logic processing on the first intermediate sequence signal and the reset signal to obtain the first sequence signal.
[0022] In some embodiments, the mode control signal includes a first mode signal, a second mode signal, a third mode signal, a fourth mode signal, a fifth mode signal, a sixth mode signal, a seventh mode signal, and an eighth mode signal;
[0023] The first signal processing circuit includes a first NAND gate, a second NAND gate, a third NAND gate, and a second NOR gate, wherein:
[0024] The first input end of the first NAND gate is used to receive the power signal, the second input end of the first NAND gate is used to receive the first mode signal, the third input end of the first NAND gate is used to receive the second mode signal, and the output end of the first NAND gate is connected to the first input end of the second NOR gate;
[0025] The first input end of the second NAND gate is used to receive the third mode signal, the second input end of the second NAND gate is used to receive the fourth mode signal, the third input end of the second NAND gate is used to receive the fifth mode signal, and the output end of the second NAND gate is connected to the second input end of the second NOR gate;
[0026] The first input end of the third NAND gate is used to receive the sixth mode signal, the second input end of the third NAND gate is used to receive the seventh mode signal, the third input end of the third NAND gate is used to receive the eighth mode signal, and the output end of the third NAND gate is connected to the third input end of the second NOR gate;
[0027] The output terminal of the second NOR gate is used to output the first target mode signal.
[0028] In some embodiments, the second signal processing circuit includes a fourth NAND gate, a second NOT gate and a fifth NAND gate, wherein:
[0029] The first input end of the fourth NAND gate is used as the set end of the first sub-sequence circuit to receive the mode write signal, the second input end of the fourth NAND gate is used to receive the first target mode signal, and the output end of the fourth NAND gate is connected to the input end of the second NAND gate;
[0030] The first input end of the fifth NAND gate is connected to the output end of the second NAND gate, the second input end of the fifth NAND gate is used as the key end of the first subsequence circuit to receive the second enable signal, and the output end of the fifth NAND gate is used to output the first intermediate sequence signal.
[0031] In some embodiments, the third signal processing circuit includes a third NOT gate and an SR latch, and the SR latch includes a sixth NAND gate and a seventh NAND gate, wherein:
[0032] The input end of the third NOT gate is used as the reset end of the first sub-sequence circuit to receive the reset signal, and the output end of the third NOT gate is connected to the first input end of the seventh NAND gate;
[0033] The second input end of the seventh NAND gate is connected to the output end of the sixth NAND gate, the output end of the seventh NAND gate is connected to the first input end of the sixth NAND gate, the second input end of the sixth NAND gate is used to receive the first intermediate sequence signal, and the output end of the sixth NAND gate is used as the output end of the first sub-sequence circuit to output the first sequence signal.
[0034] In some embodiments, the values of the mode control signals in the first sub-sequence circuit, the second sub-sequence circuit, the third sub-sequence circuit, and the fourth sub-sequence circuit are different, wherein:
[0035] In the first subsequence circuit, the first mode signal, the second mode signal, the third mode signal, the fourth mode signal, the seventh mode signal and the eighth mode signal are all true values output by the first mode register, and the fifth mode signal and the sixth mode signal are both inverted values output by the first mode register;
[0036] In the second subsequence circuit, the first mode signal, the second mode signal, the fifth mode signal, the sixth mode signal and the seventh mode signal are all true values output by the first mode register, and the third mode signal, the fourth mode signal and the eighth mode signal are all inverted values output by the first mode register;
[0037] In the third subsequence circuit, the first mode signal, the second mode signal, the fourth mode signal, the fifth mode signal, the sixth mode signal and the eighth mode signal are all true values output by the first mode register, and the third mode signal and the seventh mode signal are both inverted values output by the first mode register;
[0038] In the fourth sub-sequence circuit, the first mode signal, the second mode signal, the fourth mode signal, the fifth mode signal and the sixth mode signal are all true values output by the first mode register, and the third mode signal, the seventh mode signal and the eighth mode signal are all inverted values output by the first mode register.
[0039] In some embodiments, the structures of the second sub-sequence circuit, the third sub-sequence circuit and the fourth sub-sequence circuit are the same as the structure of the first sub-sequence circuit.
[0040] In a second aspect, an embodiment of the present disclosure provides a key protection method, which is applied to a key protection circuit, and the key protection circuit includes a signal input circuit and a protection sequence circuit, and the method includes:
[0041] Performing a logic operation on the first enable signal and the target sequence signal through the signal input circuit to obtain a second enable signal;
[0042] When the protection sequence circuit includes multiple sub-sequence circuits, the first sub-sequence circuit performs a logical operation on the mode control signal, the mode write signal and the second enable signal to obtain a first sequence signal; the i+1th sub-sequence circuit performs a logical operation on the mode control signal, the mode write signal and the i-th sequence signal output by the i-th sub-sequence circuit to obtain an i+1th sequence signal, until the last sub-sequence circuit outputs the target sequence signal, where i is an integer greater than 0.
[0043] In some embodiments, the signal input circuit includes a first NOT gate and a first NOR gate; performing a logic operation on the first enable signal and the target sequence signal through the signal input circuit to obtain the second enable signal includes:
[0044] Performing a NOT logic operation on the first enable signal through the first NOT gate to obtain a third enable signal;
[0045] The second enable signal is obtained by performing a NOR logic operation on the third enable signal and the target sequence signal through the first NOR gate.
[0046] In some embodiments, the protection sequence circuit includes four sub-sequence circuits, the four sub-sequence circuits include a first sub-sequence circuit, a second sub-sequence circuit, a third sub-sequence circuit, and a fourth sub-sequence circuit; outputting the target sequence signal through the protection sequence circuit includes:
[0047] Performing a logic operation on the mode control signal, the mode write signal, the second enable signal and the reset signal through the first subsequence circuit to obtain a first sequence signal;
[0048] Performing a logic operation on the mode control signal, the mode write signal, the first sequence signal and the reset signal through the second subsequence circuit to obtain a second sequence signal;
[0049] Performing a logic operation on the mode control signal, the mode write signal, the second sequence signal and the reset signal through the third subsequence circuit to obtain a third sequence signal;
[0050] The target sequence signal is obtained by performing a logic operation on the mode control signal, the mode write signal, the third sequence signal and the reset signal through the fourth subsequence circuit.
[0051] In some embodiments, the method further includes: when the first sequence signal, the second sequence signal, the third sequence signal and the target sequence signal meet a preset sequence condition, determining that key protection is successful to support a row address post-packaging repair (PPR) function.
[0052] In a third aspect, an embodiment of the present disclosure provides a memory, comprising a key protection circuit as described in any one of the first aspects.
[0053] The disclosed embodiment provides a key protection circuit, method and memory, wherein the key protection circuit includes a signal input circuit and a protection sequence circuit. The signal input circuit is used to receive a first enable signal and a target sequence signal, and perform a logic operation according to the first enable signal and the target sequence signal to obtain a second enable signal; the protection sequence circuit includes multiple subsequence circuits, and the input end of each subsequence circuit is used to receive a mode control signal, the set end of each subsequence circuit is used to receive a mode write signal, the key end of the first subsequence circuit is used to receive the second enable signal, the output end of the i-th subsequence circuit is connected to the key end of the i+1-th subsequence circuit, and the output end of the last subsequence circuit is used to output a target sequence signal, where i is an integer greater than 0. In this way, for multiple subsequence circuits in the protection sequence circuit, different sequence signals can be output in sequence, and it is determined whether to perform HPPR / SPPR repair of the error row address according to the target sequence signal finally obtained; if these sequence signals are output in sequence and without interruption, HPPR / SPPR repair can be performed at this time, thereby improving the memory performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0054] Figure 1 A signal timing diagram of a key protection circuit;
[0055] Figure 2 A schematic diagram of the structure of a key protection circuit provided in an embodiment of the present disclosure Figure 1 ;
[0056] Figure 3 A schematic diagram of the structure of a key protection circuit provided in an embodiment of the present disclosure Figure 2 ;
[0057] Figure 4 A schematic diagram of the structure of a key protection circuit provided in an embodiment of the present disclosure Figure 3 ;
[0058] Figure 5 A schematic diagram of the structure of a key protection circuit provided in an embodiment of the present disclosure Figure 4 ;
[0059] Figure 6 A schematic diagram of the structure of a key protection circuit provided in an embodiment of the present disclosure Figure 5 ;
[0060] Figure 7 A schematic diagram of the structure of a key protection circuit provided in an embodiment of the present disclosure Figure 6 ;
[0061] Figure 8 A schematic diagram of the structure of a key protection circuit provided in an embodiment of the present disclosure Figure 7 ;
[0062] Fig. 9 A schematic diagram of a key protection method provided in the embodiment of the present disclosure Figure 1 ;
[0063] Fig.10 A schematic diagram of a key protection method provided in the embodiment of the present disclosure Figure 2 ;
[0064] Fig.11 A schematic diagram of a key protection method provided in the embodiment of the present disclosure Figure 3 ;
[0065] Fig.12 A signal timing diagram of a key protection circuit provided by an embodiment of the present disclosure;
[0066] Fig.13 A schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION
[0067] The present disclosure is further described in detail below in conjunction with the accompanying drawings and embodiments.
[0068] It should be understood that the embodiments provided herein are only used to explain the present disclosure and are not intended to limit the present disclosure. In addition, the embodiments provided below are partial embodiments for implementing the present disclosure, rather than providing all embodiments for implementing the present disclosure. In the absence of conflict, the technical solutions recorded in the embodiments of the present disclosure can be implemented in any combination.
[0069] In the following description, the terms "first\second\..." are merely used to distinguish different objects, and do not imply that the objects are identical or related.
[0070] It should be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element. The term "connected" includes both direct and indirect connections unless otherwise specified.
[0071] For example, Figure 1 Figure 1 is a signal timing diagram of a key protection circuit. Figure 1 As shown, CK_t and CK_c are a pair of input complementary clock signals; CMD is a command signal, including an enable signal and a command sequence, wherein MR23 OP[0] or OP[1] is an enable signal (i.e., PPR Enable) for determining whether PPR performs HPPR / SPPR repair. HPPR / SPPR protection keys (Guard Keys) need to issue 4 MRW command sequences immediately after entering HPPR / SPPR, namely, MR24 Seq1, MR24 Seq2, MR24 Seq3, and MR24 Seq4. The protection key sequence needs to be input in the order specified in the technical specifications and Table 1. After executing the 4 MRW command sequences, PPR (PPR Available) can be performed.
[0072] Table 1
[0073] Guard Keys OP[7] OP[6] OP[5] OP[4] OP[3] OP[2] OP[1] OP[0] MR24 Seq1 1 1 0 0 1 1 1 1 MR24Seq2 0 1 1 1 0 0 1 1 MR24Seq3 1 0 1 1 1 0 1 1 MR24Seq4 0 0 1 1 1 0 1 1
[0074] Furthermore, the protection key sequence does not allow interruptions by other MRW / R commands or non-MR commands (such as ACT, WR, RD, etc.). In addition, if the protection key sequence is not entered in the specified order or is interrupted by other commands, the HPPR / SPPR repair will not be executed and the offending command will be terminated. The HPPR / SPPR entry may or may not be executed correctly, but the offending command will not cause the DRAM to lock. Among them, the offending command that interrupts the HPPR / SPPR may include:
[0075] 1) Other MRW / R commands or non-MR command protection key sequence interruption;
[0076] 2) The control word (CW) of the MRW command is high level;
[0077] 3) 2 cycle instructions, and the CS_n signal is low in the second cycle.
[0078] In addition, when the protection key sequence of the HPPR input is interrupted, the subsequent ACT and WR commands will be executed as normal DRAM commands. If the HPPR operation is interrupted and / or terminated prematurely, MR23OP[1] and OP[0] must be reset to "0" before executing another HPPR / SPPR operation; if an incorrect HPPR / SPPR protection key sequence is entered, the DRAM does not provide an error indication.
[0079] That is, before performing HPPR / SPPR, a continuous MRW protection key sequence is required to prevent PPR from being accidentally programmed and to avoid affecting the repair of the erroneous row address.
[0080] Based on this, the embodiment of the present disclosure provides a key protection circuit, which includes a signal input circuit and a protection sequence circuit, wherein: the signal input circuit is used to receive a first enable signal and a target sequence signal, and perform a logic operation according to the first enable signal and the target sequence signal to obtain a second enable signal; the protection sequence circuit includes multiple subsequence circuits, and the input end of each subsequence circuit is used to receive a mode control signal, the set end of each subsequence circuit is used to receive a mode write signal, the key end of the first subsequence circuit is used to receive the second enable signal, the output end of the i-th subsequence circuit is connected to the key end of the i+1-th subsequence circuit, and the output end of the last subsequence circuit is used to output the target sequence signal, i is an integer greater than 0. In this way, for multiple subsequence circuits in the protection sequence circuit, different sequence signals can be output in sequence, and it is determined whether to perform HPPR / SPPR repair of the error row address according to the target sequence signal finally obtained; if these sequence signals are output in sequence and without interruption, HPPR / SPPR repair can be performed at this time, thereby improving the memory performance.
[0081] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.
[0082] In one embodiment of the present disclosure, see Figure 2 , which shows a schematic diagram of the composition structure of a key protection circuit 10. Figure 2 As shown, the key protection circuit 10 may include a signal input circuit 11 and a protection sequence circuit 12, wherein:
[0083] The signal input circuit 11 is used to receive a first enable signal and a target sequence signal, and perform a logic operation according to the first enable signal and the target sequence signal to obtain a second enable signal;
[0084] The protection sequence circuit 12 includes a plurality of subsequence circuits (A 1 , A 2 , …, A n , n is a positive integer), and the input end of each subsequence circuit is used to receive the mode control signal, and the set end of each subsequence circuit is used to receive the mode write signal. The first subsequence circuit A 1 The key terminal is used to receive the second enable signal, and the i-th subsequence circuit A i The output end of the i+1th subsequence circuit A i+1 The key end of the last subsequence circuit A n The output terminal is used to output the target sequence signal, i is an integer greater than 0 and less than or equal to n, and n represents the number of sub-sequence circuits in the protection sequence circuit 12.
[0085] It should be noted that, in the disclosed embodiment, the first enable signal is a PPR enable signal from the mode register 23 (MR23), which can be determined by OP[0] or OP[1]; the first enable signal can be represented by PPRENT. The value of the PPRENT signal can be logic 1, or it can be logic 0, which is not specifically limited here. Exemplarily, if the key protection circuit 10 allows the execution of the repair function, the value of the PPRENT signal can be logic 1; otherwise, if the key protection circuit 10 does not allow the execution of the repair function, the value of the PPRENT signal can be logic 0.
[0086] It should also be noted that in the embodiment of the present disclosure, the mode write signal is the MRW24 command, which can be represented by MRW24T. The second enable signal can be represented by PPRENT1. In addition, the mode control signal can be generated by the mode register 24 (MR24). Among them, for the mode control signal, it can be the actual value output by the mode register 24, or it can be the inverted value output by the mode register 24, which is not specifically limited here. Exemplarily, the actual value output by the mode register 24 can be represented by MROPT[7:0], and the inverted value output by the mode register 24 can be represented by MROPB[7:0]. It should be noted that MROPT[7:0] is not a signal, but represents a group of signals, namely MROP7T~MROP0T; similarly, MROPB[7:0] is not a signal, but represents a group of signals, namely MROP7B~MROP0B.
[0087] It is worth noting that the mode control signals corresponding to different subsequence circuits are different. Although the mode control signals are all composed of MROPT[7:0] and MROPB[7:0], in actual scenarios, the mode control signals can be composed of MROP0T, MROP1T, MROP2T, MROP3T, MROP4B, MROP5B, MROP6T and MROP7T; or they can also be composed of MROP0T, MROP1T, MROP2B, MROP3B, MROP4T, MROP5T, MROP6T and MROP7B, which are not specifically limited here.
[0088] In addition, the mode control signals received by different sub-sequence circuits can be selected according to actual needs. For example, the mode control signal received by the first sub-sequence circuit can be composed of MROP0T, MROP1T, MROP2T, MROP3T, MROP4B, MROP5B, MROP6T and MROP7T; the mode control signal received by the second sub-sequence circuit can be composed of MROP0T, MROP1T, MROP2B, MROP3B, MROP4T, MROP5T, MROP6T and MROP7B; and so on.
[0089] In this way, for multiple sub-sequence circuits in the protection sequence circuit, different sequence signals can be output in sequence, and whether to perform HPPR / SPPR repair of the error row address can be determined based on the target sequence signal finally obtained; if these sequence signals are output in sequence and without interruption, HPPR / SPPR repair can be performed at this time, thereby improving memory performance.
[0090] In some embodiments, Figure 2 As shown in the signal input circuit 11, Figure 3As shown, the signal input circuit 11 may include a first NOT gate 111 and a first NOR gate 112, wherein:
[0091] A first NOT gate 111, used for performing a NOT logic operation on the first enable signal to obtain a third enable signal;
[0092] The first NOR gate 112 is used for performing a NOR logic operation on the third enable signal and the target sequence signal to obtain a second enable signal.
[0093] It should be noted that, in the embodiment of the present disclosure, the input end of the first NOT gate 111 is used to receive the first enable signal, the first input end of the first NOR gate 112 is connected to the output end of the first NOR gate 111, the second input end of the first NOR gate 112 is used to receive the target sequence signal, and the output end of the first NOR gate 112 is used to output the second enable signal.
[0094] It should also be noted that in the embodiment of the present disclosure, for the signal input circuit 11, the logic device here may include a first NOT gate 111 and a first NOR gate 112, but as long as the level logic of the second enable signal is met, the logic device here is not limited to this and can be adaptively adjusted according to actual conditions.
[0095] In some embodiments, Figure 2 The key protection circuit 10 shown is based on Figure 4 As shown, the key protection circuit 10 may further include a reset circuit 13, wherein:
[0096] The reset circuit 13 is used to generate a reset signal when the working state of the key protection circuit 10 meets a preset condition, and the reset signal is connected to the reset terminal of each sub-sequence circuit.
[0097] Here, the reset signal can be represented by Reset. When the working state of the key protection circuit 10 meets the preset conditions, the level value of the reset signal is logic 1, that is, the reset signal is valid, and the key protection circuit 10 can be reset at this time.
[0098] In a specific implementation, the preset conditions include the following three situations:
[0099] 1) Other MRW / R commands or non-MR command protection key sequence interruption;
[0100] 2) The control word (CW) of the MRW command is high level;
[0101] 3) 2 cycle instructions, and the CS_n signal is low in the second cycle.
[0102] That is to say, when the working state of the key protection circuit 10 satisfies one of the above three conditions, the repair operation of HPPR or SPPR will not be performed at this time, and the reset signal is valid at this time, and the key protection circuit 10 can be reset.
[0103] It should also be noted that when the working state of the key protection circuit 10 does not meet the preset conditions, the level value of the reset signal is logic 0, that is, the reset signal does not work, so there is no need to reset the key protection circuit 10. Specifically, when all the above three conditions are not met, it means that the protection key sequence is input in the prescribed order and is not interrupted by other commands. At this time, the reset signal is invalid, that is, there is no need to reset the key protection circuit 10.
[0104] In some embodiments, Figure 4 The protection sequence circuit 12 shown is based on Figure 5 As shown, the protection sequence circuit 12 may include four sub-sequence circuits, and the four sub-sequence circuits may include a first sub-sequence circuit A 1 , the second subsequence circuit A 2 , the third subsequence circuit A 3 and the fourth subsequence circuit A 4 ,in:
[0105] First subsequence circuit A 1 , used for receiving a mode control signal, a mode write signal, a second enable signal and a reset signal, performing a logic operation according to the mode control signal, the mode write signal, the second enable signal and the reset signal to obtain a first sequence signal;
[0106] Second subsequence circuit A 2 , used for receiving a mode control signal, a mode write signal, a first sequence signal and a reset signal, performing a logic operation according to the mode control signal, the mode write signal, the first sequence signal and the reset signal to obtain a second sequence signal;
[0107] The third subsequence circuit A 3 , used for receiving a mode control signal, a mode write signal, a second sequence signal and a reset signal, performing a logic operation according to the mode control signal, the mode write signal, the second sequence signal and the reset signal to obtain a third sequence signal;
[0108] Fourth subsequence circuit A 4 , used to receive a mode control signal, a mode write signal, a third sequence signal and a reset signal, and perform logic operations according to the mode control signal, the mode write signal, the third sequence signal and the reset signal to obtain a target sequence signal.
[0109] It should be noted that the first sequence signal is represented by pprseq1, the second sequence signal is represented by pprseq2, the third sequence signal is represented by pprseq3, and the target sequence signal is represented by pprseq4. Among them, the first sequence signal, the second sequence signal, the third sequence signal and the fourth sequence signal can be called protection key sequences. In actual scenarios, only when these four sequence signals all meet the aforementioned Table 1, it means that the protection key sequence is correct, and the HPPR or SPPR repair operation can be performed later.
[0110] It should also be noted that the mode control signal is not a signal, but a group of signals. Specifically, the mode control signal may include a first mode signal, a second mode signal, a third mode signal, a fourth mode signal, a fifth mode signal, a sixth mode signal, a seventh mode signal and an eighth mode signal.
[0111] In the embodiment of the present disclosure, Figure 5 The protection sequence circuit 12 shown is based on Figure 6 As shown, the input end of each subsequence circuit can be represented by MROP0-MROP7, the set end of each subsequence circuit can be represented by TDFTSET, the key end of each subsequence circuit can be represented by KEY, the output end of each subsequence circuit can be represented by OUT, and the reset end of each subsequence circuit can be represented by RST.
[0112] Among them, the input end (MROP0-MROP7) of each subsequence circuit is used to receive the mode control signal, the set end TDFTSET of each subsequence circuit is used to receive the mode write signal MRW24T, the key end KEY of the first subsequence circuit is used to receive the second enable signal PPRENT1, the key end KEY of the second subsequence circuit is used to receive the first sequence signal pprseq1, the key end KEY of the third subsequence circuit is used to receive the second sequence signal pprseq2, the key end KEY of the fourth subsequence circuit is used to receive the third sequence signal pprseq3, and the output end OUT of the fourth subsequence circuit is used to output the target sequence signal pprseq4. In addition, the reset end RST of each subsequence circuit is used to receive the reset signal Reset.
[0113] In some embodiments, please refer to Figure 6 , the first subsequence circuit A 1 , the second subsequence circuit A 2 , the third subsequence circuit A 3 and the fourth subsequence circuit A 4 There are different values of the mode control signal in , among which:
[0114] In the first subsequence circuit A 1, the first mode signal, the second mode signal, the third mode signal, the fourth mode signal, the seventh mode signal and the eighth mode signal are all true values output by the first mode register, and the fifth mode signal and the sixth mode signal are all inverted values output by the first mode register;
[0115] In the second subsequence circuit A 2 , the first mode signal, the second mode signal, the fifth mode signal, the sixth mode signal and the seventh mode signal are all true values output by the first mode register, and the third mode signal, the fourth mode signal and the eighth mode signal are all inverted values output by the first mode register;
[0116] In the third subsequence circuit A 3 , the first mode signal, the second mode signal, the fourth mode signal, the fifth mode signal, the sixth mode signal and the eighth mode signal are all true values output by the first mode register, and the third mode signal and the seventh mode signal are all inverted values output by the first mode register;
[0117] In the fourth subsequence circuit A 4 In the embodiment, the first mode signal, the second mode signal, the fourth mode signal, the fifth mode signal and the sixth mode signal are all true values output by the first mode register, and the third mode signal, the seventh mode signal and the eighth mode signal are all inverted values output by the first mode register.
[0118] Specifically, in the first subsequence circuit A 1 The mode control signals in the circuit A may be MROP0T, MROP1T, MROP2T, MROP3T, MROP4B, MROP5B, MROP6T and MROP7T in sequence; in the second subsequence circuit A 2 The mode control signals in the circuit A can be MROP0T, MROP1T, MROP2B, MROP3B, MROP4T, MROP5T, MROP6T and MROP7B in sequence; 3 The mode control signals in the fourth subsequence circuit A may be MROP0T, MROP1T, MROP2B, MROP3T, MROP4T, MROP5T, MROP6B and MROP7T in sequence; 4 The mode control signals in may be MROP0T, MROP1T, MROP2B, MROP3T, MROP4T, MROP5T, MROP6B and MROP7B respectively.
[0119] In short, the mode control signals of the four sub-sequence circuits are not exactly the same. Although their mode control signals are all composed of MROPT[7:0] and MROPB[7:0], in actual scenarios, different sub-sequence circuits have different mode control signals to achieve the generation of the four sequence signals pprseq1, pprseq2, pprseq3, and pprseq4.
[0120] In some embodiments, for four sub-sequence circuits, the following takes the first sub-sequence circuit A as an example. 1 For detailed explanation, refer to Figure 7 , the first subsequence circuit A 1 The system comprises a first signal processing circuit 121a, a second signal processing circuit 121b and a third signal processing circuit 121c, wherein:
[0121] The first signal processing circuit 121a is used to perform logic processing on the mode control signal and the power supply signal to obtain a first target mode signal;
[0122] The second signal processing circuit 121b is used to perform logic processing on the first target mode signal, the mode write signal and the second enable signal to obtain a first intermediate sequence signal;
[0123] The third signal processing circuit 121c is used to perform logic processing on the first intermediate sequence signal and the reset signal to obtain a first sequence signal.
[0124] Here, the power supply signal may be represented by VDD.
[0125] In a specific embodiment, Figure 7 The first subsequence circuit A shown 1 On the basis of Figure 8 As shown, the first signal processing circuit 121a includes a first NAND gate 1211, a second NAND gate 1212, a third NAND gate 1213 and a second NOR gate 1214, wherein:
[0126] The first input terminal of the first NAND gate 1211 is used to receive the power supply signal VDD, the second input terminal of the first NAND gate 1211 is used to receive the first mode signal MROP0T, the third input terminal of the first NAND gate 1211 is used to receive the second mode signal MROP1T, and the output terminal of the first NAND gate 1211 is connected to the first input terminal of the second NOR gate 1214; the first input terminal of the second NAND gate 1212 is used to receive the third mode signal MROP2T, the second input terminal of the second NAND gate 1212 is used to receive the fourth mode signal MROP3T, and the third input terminal of the second NAND gate 1212 is used to receive the fourth mode signal MROP4T. Used to receive the fifth mode signal MROP4B, the output end of the second NAND gate 1212 is connected to the second input end of the second NOR gate 1214; the first input end of the third NAND gate 1213 is used to receive the sixth mode signal MROP5B, the second input end of the third NAND gate 1213 is used to receive the seventh mode signal MROP6T, the third input end of the third NAND gate 1213 is used to receive the eighth mode signal MROP7T, the output end of the third NAND gate 1213 is connected to the third input end of the second NOR gate 1214; the output end of the second NOR gate 1214 is used to output the first target mode signal.
[0127] Further, in some embodiments, please continue to refer to Figure 8 , the second signal processing circuit 121b includes a fourth NAND gate 1215, a second NOT gate 1216 and a fifth NAND gate 1217, wherein:
[0128] The first input terminal of the fourth NAND gate 1215 serves as the first subsequence circuit A. 1 The set end TDFTSET of the fourth NAND gate 1215 is used to receive the mode write signal MRW24T, the second input end of the fourth NAND gate 1215 is used to receive the first target mode signal, the output end of the fourth NAND gate 1215 is connected to the input end of the second NAND gate 1216; the first input end of the fifth NAND gate 1217 is connected to the output end of the second NAND gate 1216, and the second input end of the fifth NAND gate 1217 is used as the first sub-sequence circuit A 1 The key terminal KEY of the gate 1217 is used to receive the second enable signal PPRENT1, and the output terminal of the fifth NAND gate 1217 is used to output the first intermediate sequence signal.
[0129] Further, in some embodiments, please continue to refer to Figure 8 , the third signal processing circuit 121c includes a third NOT gate 1218 and an SR latch, and the SR latch includes a sixth NAND gate 1219 and a seventh NAND gate 1220, wherein:
[0130] The input terminal of the third NOT gate 1218 serves as the first subsequence circuit A 1The reset terminal RST of the third inverter 1218 is used to receive the reset signal Reset, the output terminal of the third inverter 1218 is connected to the first input terminal of the seventh NAND gate 1220; the second input terminal of the seventh NAND gate 1220 is connected to the output terminal of the sixth NAND gate 1219, the output terminal of the seventh NAND gate 1220 is connected to the first input terminal of the sixth NAND gate 1219, the second input terminal of the sixth NAND gate 1219 is used to receive the first intermediate sequence signal, and the output terminal of the sixth NAND gate 1219 is used as the first subsequence circuit A. 1 The output end is used to output the first sequence signal pprseq1.
[0131] It should be noted that, in the embodiment of the present disclosure, the second input terminal of the first NAND gate 1211 is used as the first sub-sequence circuit A. 1 The input terminal MROP0 of the first NAND gate 1211 is used to receive the first mode signal MROP0T; the third input terminal of the first NAND gate 1211 is used as the first sub-sequence circuit A 1 The input terminal MROP1 of the second NAND gate 1212 is used to receive the second mode signal MROP1T; the first input terminal of the second NAND gate 1212 is used as the first sub-sequence circuit A 1 The input terminal MROP2 of the second NAND gate 1212 is used to receive the third mode signal MROP2T; the second input terminal of the second NAND gate 1212 is used as the first sub-sequence circuit A 1 The input terminal MROP3 of the second NAND gate 1212 is used to receive the fourth mode signal MROP3T; the third input terminal of the second NAND gate 1212 is used as the first sub-sequence circuit A 1 The input terminal MROP4 of the third NAND gate 1213 is used to receive the fifth mode signal MROP4B; the first input terminal of the third NAND gate 1213 is used as the first sub-sequence circuit A 1 The input terminal MROP5 of the third NAND gate 1213 is used to receive the sixth mode signal MROP5B; the second input terminal of the third NAND gate 1213 is used as the first sub-sequence circuit A 1 The input terminal MROP6 of the third NAND gate 1213 is used to receive the seventh mode signal MROP6T; the third input terminal of the third NAND gate 1213 is used as the first sub-sequence circuit A 1 The input terminal MROP7 is used to receive the eighth mode signal MROP7T.
[0132] In some embodiments, the second subsequence circuit A 2 , the third subsequence circuit A 3 and the fourth subsequence circuit A 4 The structures of the first subsequence circuit A are the same 1 The structure is the same.
[0133] Here, the same structure means: the second subsequence circuit A 2 , the third subsequence circuit A 3 and the fourth subsequence circuit A 4The components and connections in the first subsequence circuit A are the same as those in the first subsequence circuit A. 1 That is, the second subsequence circuit A 2 , the third subsequence circuit A 3 and the fourth subsequence circuit A 4 The structure is like Figure 8 As shown. For the second subsequence circuit A 2 , the third subsequence circuit A 3 and the fourth subsequence circuit A 4 For technical features not disclosed in detail, please refer to the first subsequence circuit A 1 The structure of is understood and will not be elaborated here.
[0134] In addition, the second subsequence circuit A 2 , the third subsequence circuit A 3 and the fourth subsequence circuit A 4 With the first subsequence circuit A 1 The difference is that: the second subsequence circuit A 2 , the third subsequence circuit A 3 and the fourth subsequence circuit A 4 The mode control signal received at the input end and the signal received at the key end KEY are connected to the first subsequence circuit A 1 For example, the second subsequence circuit A 2 In the example, the mode control signals received by the input terminals MROP0 to MROP7 are MROP0T, MROP1T, MROP2B, MROP3B, MROP4T, MROP5T, MROP6T and MROP7B, and the signal received by the key terminal KEY is the first sequence signal pprseq1. 3 In the example, the mode control signals received by the input terminals MROP0 to MROP7 are MROP0T, MROP1T, MROP2B, MROP3T, MROP4T, MROP5T, MROP6B and MROP7T, and the signal received by the key terminal KEY is the second sequence signal pprseq2. 4 In the embodiment, the mode control signals received by the input terminals MROP0 to MROP7 are MROP0T, MROP1T, MROP2B, MROP3T, MROP4T, MROP5T, MROP6B and MROP7B, and the signal received by the key terminal KEY is the third sequence signal pprseq3.
[0135] An embodiment of the present disclosure provides a key protection circuit. Taking the protection sequence circuit including four sub-sequence circuits as an example, these four sub-sequence circuits can output a first sequence signal, a second sequence signal, a third sequence signal and a target sequence signal in sequence, and determine whether to perform HPPR / SPPR repair of the error row address according to the target sequence signal finally obtained; if these sequence signals are output in sequence and without interruption, HPPR / SPPR repair can be performed at this time, thereby improving memory performance.
[0136] In another embodiment of the present disclosure, a key protection method is provided, which is applied to a key protection circuit 10, and the key protection circuit 10 includes a signal input circuit 11 and a protection sequence circuit 12. Figure 2 and Fig. 9 For reference, the key protection method may include step S110 and step S120.
[0137] Step S110, performing a logic operation on the first enable signal and the target sequence signal through the signal input circuit 11 to obtain a second enable signal;
[0138] Step S120: the protection sequence circuit 12 includes a plurality of sub-sequence circuits (A 1 , A 2 , …, A n , n is a positive integer), through the first subsequence circuit A 1 Perform logic operation on the mode control signal, the mode write signal and the second enable signal to obtain a first sequence signal; and pass the i+1th subsequence circuit A i+1 The mode control signal, the mode write signal and the i-th subsequence circuit A i The output i-th sequence signal is subjected to logic operation to obtain the i+1-th sequence signal until the last subsequence circuit A n Output target sequence signal.
[0139] Here, i is an integer greater than 0 and less than or equal to n, and n represents the number of subsequence circuits in the protection sequence circuit 12 .
[0140] In some embodiments, please combine Figure 3 and Fig.10 For reference, the signal input circuit 11 includes a first NOT gate 111 and a first NOR gate 112 ; step S110 includes step S111 and step S112 .
[0141] Step S111, performing a NOT logic operation on the first enable signal through the first NOT gate 111 to obtain a third enable signal;
[0142] Step S112: Perform a NOR logic operation on the third enable signal and the target sequence signal through the first NOR gate 112 to obtain a second enable signal.
[0143] It should be noted that in the embodiment of the present disclosure, for step S110, logical operations can be performed through the first NOT gate 111 and the first NOR gate 112 of the logic devices, but as long as the level logic of the second enable signal is met, the logic devices here are not limited to this and can be adaptively adjusted according to actual conditions.
[0144] In some embodiments, the key protection circuit 10 further includes a reset circuit 13, and the key protection method further includes: inputting a reset signal Reset to the reset end of each subsequence circuit through the reset circuit 13 when the working state of the key protection circuit 10 meets a preset condition.
[0145] Here, when the working state of the key protection circuit 10 meets the preset conditions, the level value of the reset signal is logic 1, that is, the reset signal is valid, and the key protection circuit 10 can be reset at this time.
[0146] In a specific implementation, the preset conditions include the following three situations:
[0147] 1) Other MRW / R commands or non-MR command protection key sequence interruption;
[0148] 2) The control word (CW) of the MRW command is high level;
[0149] 3) 2 cycle instructions, and the CS_n signal is low in the second cycle.
[0150] That is to say, when the working state of the key protection circuit 10 satisfies one of the above three conditions, the repair operation of HPPR or SPPR will not be performed at this time, and the reset signal is valid at this time, and the key protection circuit 10 can be reset.
[0151] It should also be noted that when the working state of the key protection circuit 10 does not meet the preset conditions, the level value of the reset signal is logic 0, that is, the reset signal does not work, so there is no need to reset the key protection circuit 10. Specifically, when all the above three conditions are not met, it means that the protection key sequence is input in the prescribed order and is not interrupted by other commands. At this time, the reset signal is invalid, that is, there is no need to reset the key protection circuit 10.
[0152] In some embodiments, please combine Figure 5 and Fig.11 For reference, the protection sequence circuit 12 may include four sub-sequence circuits, and the four sub-sequence circuits may include a first sub-sequence circuit A1 , the second subsequence circuit A 2 , the third subsequence circuit A 3 and the fourth subsequence circuit A 4 ; Step S120 includes steps S121 to S124.
[0153] Step S121: using the first subsequence circuit A 1 Performing a logic operation on the mode control signal, the mode write signal, the second enable signal and the reset signal to obtain a first sequence signal;
[0154] Step S122: using the second subsequence circuit A 2 Performing a logic operation on the mode control signal, the mode write signal, the first sequence signal and the reset signal to obtain a second sequence signal;
[0155] Step S123: through the third subsequence circuit A 3 Performing logic operation on the mode control signal, the mode write signal, the second sequence signal and the reset signal to obtain a third sequence signal;
[0156] Step S124: through the fourth subsequence circuit A 4 A logic operation is performed on the mode control signal, the mode write signal, the third sequence signal and the reset signal to obtain a target sequence signal.
[0157] Among them, the first sequence signal, the second sequence signal, the third sequence signal and the fourth sequence signal can be called the protection key sequence. In the actual scenario, only when these four sequence signals all meet the aforementioned Table 1, it means that the protection key sequence is correct, and the HPPR or SPPR repair operation can be performed later.
[0158] In the embodiment of the present disclosure, the first subsequence circuit A 1 The first signal processing circuit 121a, the second signal processing circuit 121b and the third signal processing circuit 121c (see Figure 8 ), the following is a detailed description taking step S121 as an example. Step S121 includes steps 1 to 3.
[0159] Step 1: The first signal processing circuit 121a performs logic processing on the mode control signal and the power signal to obtain a first target mode signal;
[0160] Step 2: Performing logic processing on the first target mode signal, the mode write signal and the second enable signal through the second signal processing circuit 121b to obtain a first intermediate sequence signal;
[0161] Step three: the third signal processing circuit 121c performs logic processing on the first intermediate sequence signal and the reset signal to obtain a first sequence signal.
[0162] In a specific embodiment, the first signal processing circuit 121a includes a first NAND gate 1211, a second NAND gate 1212, a third NAND gate 1213 and a second NOR gate 1214, and step 1 includes: performing a NAND logic operation on the power supply signal VDD, the first mode signal MROP0T and the second mode signal MROP1T through the first NAND gate 1211, and inputting the operation result into a first end of the second NOR gate 1214; performing a NAND logic operation on the third mode signal MROP2T, the fourth mode signal MROP3T and the fifth mode signal MROP4T through the second NAND gate 1212. The sixth mode signal MROP4B is subjected to a NAND logic operation, and the operation result is input to the second end of the second NOR gate 1214; the sixth mode signal MROP5B, the seventh mode signal MROP6T and the eighth mode signal MROP7T are subjected to a NAND logic operation through the third NAND gate 1213, and the operation result is input to the third end of the second NOR gate 1214; the operation results output by the first NAND gate 1211, the second NAND gate 1212 and the third NAND gate 1213 are subjected to a NOR logic operation through the second NOR gate 1214 to obtain the first target mode signal.
[0163] Further, the second signal processing circuit 121b includes a fourth NAND gate 1215, a second NOT gate 1216 and a fifth NAND gate 1217, and step two includes: performing a NAND logic operation on the first target mode signal and the mode write signal MRW24T through the fourth NAND gate 1215, and then performing an inversion operation on them through the second NOT gate 1216; performing a NAND operation on the inverted signal and the second enable signal PPRENT1 through the fifth NAND gate 1217 to obtain a first intermediate sequence signal.
[0164] Further, the third signal processing circuit 121c includes a third NOT gate 1218 and an SR latch, and the SR latch includes a sixth NAND gate 1219 and a seventh NAND gate 1220, and step three includes: inverting the reset signal Reset through the third NOT gate 1218 to obtain the inverted reset signal Reset; latching the inverted reset signal Reset and the first intermediate sequence signal through the sixth NAND gate 1219 and the seventh NAND gate 1220 to obtain the first sequence signal pprseq1.
[0165] It should be noted that, since the second subsequence circuit A provided in the embodiment of the present disclosure 2 , the third subsequence circuit A 3 and the fourth subsequence circuit A 4 The components and connections in the first subsequence circuit A are the same as those in the first subsequence circuit A. 1The same, so step S122 to step S124 are similar to step S121. For the technical features not fully disclosed in step S121 to step S124, please refer to the above embodiment for understanding, and will not be repeated here.
[0166] In some embodiments, the key protection method further includes: when the first sequence signal, the second sequence signal, the third sequence signal and the target sequence signal meet a preset sequence condition, determining that the key protection is successful to support the row address to perform a post-packaging repair (PPR) function.
[0167] Through the key protection method provided by the present invention, the first sequence signal, the second sequence signal, the third sequence signal and the target sequence signal can be output in sequence through the four sub-sequence circuits in the protection sequence circuit, and it can be determined whether to perform HPPR / SPPR repair of the error row address based on the target sequence signal finally obtained; if these sequence signals are output in sequence and without interruption, HPPR / SPPR repair can be performed at this time, thereby improving the memory performance.
[0168] In yet another embodiment of the present disclosure, Fig.12 Schematic diagram of signal timing of a key protection circuit 10 provided in an embodiment of the present disclosure. Fig.12 As shown in the dotted box in FIG, the level value of the first enable signal PPRENT is logic 1, and the repair function is allowed to be executed at this time. After the key protection circuit 10 performs a logic operation on the mode control signal and the mode write signal MRW24T, the first sequence signal pprseq1, the second sequence signal pprseq2, the third sequence signal pprseq3 and the target sequence signal pprseq4 are output in sequence.
[0169] exist Fig.12 In the input key protection circuit 10 based on the aforementioned embodiment, for the protection key (Guard Key) of the mode register MR24, corresponding to OP[7]~OP[0] of MR24, the value of the first sequence signal pprseq1 is 11001111, the value of the second sequence signal pprseq2 is 01110011, the value of the third sequence signal pprseq4 is 10111011, and the value of the fourth sequence signal pprseq4 is 001111011.
[0170] So, because Fig.12 The protection key sequence in is output in order and without interruption, therefore, the target sequence signal pprseq4 is the same as the level state of the determination key protection signal pmrpprent, meaning that the protection key sequence is successful, so that the repair operation of HPPR / SPPR can be performed.
[0171] In another embodiment of the present disclosure, see Fig.13 , which shows a schematic diagram of the composition structure of a memory 20 provided by an embodiment of the present disclosure. Fig.13 As shown, the memory 20 may include the key protection circuit 10 described in any one of the aforementioned embodiments.
[0172] In some embodiments, the memory 20 may include a DRAM chip. The DRAM chip may not only comply with memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, and DDR6, but may also comply with memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, and LPDDR6, which are not specifically limited here.
[0173] In the embodiment of the present disclosure, for the memory 20, since it includes the key protection circuit 10 described in the above embodiment, it can implement a key sequence protection operation on the memory to repair the error row address in the memory, thereby improving the memory performance.
[0174] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.
[0175] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative.
[0176] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in several method or device embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.
[0177] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.
Claims
1. A key protection circuit, characterized in that: The key protection circuit comprises a signal input circuit and a protection sequence circuit, wherein: The signal input circuit is used to receive a first enable signal and a target sequence signal, and perform a logic operation according to the first enable signal and the target sequence signal to obtain a second enable signal; The protection sequence circuit includes multiple sub-sequence circuits, and the input end of each sub-sequence circuit is used to receive a mode control signal, the set end of each sub-sequence circuit is used to receive a mode write signal, the key end of the first sub-sequence circuit is used to receive the second enable signal, the output end of the i-th sub-sequence circuit is connected to the key end of the i+1-th sub-sequence circuit, and the output end of the last sub-sequence circuit is used to output the target sequence signal, and i is an integer greater than 0.
2. The key protection circuit according to claim 1, characterized in that: The signal input circuit includes a first NOT gate and a first NOR gate, wherein: The first NOT gate is used to perform a NOT logic operation on the first enable signal to obtain a third enable signal; The first NOR gate is used to perform a NOR logic operation on the third enable signal and the target sequence signal to obtain the second enable signal.
3. The key protection circuit according to claim 1 or 2, characterized in that: The key protection circuit also includes a reset circuit, wherein: The reset circuit is used to generate a reset signal when the working state of the key protection circuit meets a preset condition, and the reset signal is connected to the reset end of each of the sub-sequence circuits.
4. The key protection circuit according to claim 3, characterized in that: The protection sequence circuit includes four sub-sequence circuits, and the four sub-sequence circuits include a first sub-sequence circuit, a second sub-sequence circuit, a third sub-sequence circuit and a fourth sub-sequence circuit, wherein: The first subsequence circuit is used to receive the mode control signal, the mode write signal, the second enable signal and the reset signal, and perform a logic operation according to the mode control signal, the mode write signal, the second enable signal and the reset signal to obtain a first sequence signal; The second subsequence circuit is used to receive the mode control signal, the mode write signal, the first sequence signal and the reset signal, and perform a logic operation according to the mode control signal, the mode write signal, the first sequence signal and the reset signal to obtain a second sequence signal; The third subsequence circuit is used to receive the mode control signal, the mode write signal, the second sequence signal and the reset signal, and perform a logic operation according to the mode control signal, the mode write signal, the second sequence signal and the reset signal to obtain a third sequence signal; The fourth subsequence circuit is used to receive the mode control signal, the mode write signal, the third sequence signal and the reset signal, and perform logic operations according to the mode control signal, the mode write signal, the third sequence signal and the reset signal to obtain the target sequence signal.
5. The key protection circuit according to claim 4, characterized in that: The first subsequence circuit includes a first signal processing circuit, a second signal processing circuit and a third signal processing circuit, wherein: The first signal processing circuit is used to perform logic processing on the mode control signal and the power supply signal to obtain a first target mode signal; The second signal processing circuit is used to perform logic processing on the first target mode signal, the mode write signal and the second enable signal to obtain a first intermediate sequence signal; The third signal processing circuit is used to perform logic processing on the first intermediate sequence signal and the reset signal to obtain the first sequence signal.
6. The key protection circuit according to claim 5, characterized in that: The mode control signal includes a first mode signal, a second mode signal, a third mode signal, a fourth mode signal, a fifth mode signal, a sixth mode signal, a seventh mode signal and an eighth mode signal; The first signal processing circuit includes a first NAND gate, a second NAND gate, a third NAND gate, and a second NOR gate, wherein: The first input end of the first NAND gate is used to receive the power signal, the second input end of the first NAND gate is used to receive the first mode signal, the third input end of the first NAND gate is used to receive the second mode signal, and the output end of the first NAND gate is connected to the first input end of the second NOR gate; The first input end of the second NAND gate is used to receive the third mode signal, the second input end of the second NAND gate is used to receive the fourth mode signal, the third input end of the second NAND gate is used to receive the fifth mode signal, and the output end of the second NAND gate is connected to the second input end of the second NOR gate; The first input end of the third NAND gate is used to receive the sixth mode signal, the second input end of the third NAND gate is used to receive the seventh mode signal, the third input end of the third NAND gate is used to receive the eighth mode signal, and the output end of the third NAND gate is connected to the third input end of the second NOR gate; The output terminal of the second NOR gate is used to output the first target mode signal.
7. The key protection circuit according to claim 5, characterized in that: The second signal processing circuit includes a fourth NAND gate, a second NOT gate and a fifth NAND gate, wherein: The first input end of the fourth NAND gate is used as the set end of the first sub-sequence circuit to receive the mode write signal, the second input end of the fourth NAND gate is used to receive the first target mode signal, and the output end of the fourth NAND gate is connected to the input end of the second NAND gate; The first input end of the fifth NAND gate is connected to the output end of the second NAND gate, the second input end of the fifth NAND gate is used as the key end of the first subsequence circuit to receive the second enable signal, and the output end of the fifth NAND gate is used to output the first intermediate sequence signal.
8. The key protection circuit according to claim 5, characterized in that: The third signal processing circuit includes a third NOT gate and an SR latch, and the SR latch includes a sixth NAND gate and a seventh NAND gate, wherein: The input end of the third NOT gate is used as the reset end of the first sub-sequence circuit to receive the reset signal, and the output end of the third NOT gate is connected to the first input end of the seventh NAND gate; The second input end of the seventh NAND gate is connected to the output end of the sixth NAND gate, the output end of the seventh NAND gate is connected to the first input end of the sixth NAND gate, the second input end of the sixth NAND gate is used to receive the first intermediate sequence signal, and the output end of the sixth NAND gate is used as the output end of the first sub-sequence circuit to output the first sequence signal.
9. The key protection circuit according to claim 6, characterized in that: The values of the mode control signals in the first subsequence circuit, the second subsequence circuit, the third subsequence circuit and the fourth subsequence circuit are different, wherein: In the first subsequence circuit, the first mode signal, the second mode signal, the third mode signal, the fourth mode signal, the seventh mode signal and the eighth mode signal are all true values output by the first mode register, and the fifth mode signal and the sixth mode signal are both inverted values output by the first mode register; In the second subsequence circuit, the first mode signal, the second mode signal, the fifth mode signal, the sixth mode signal and the seventh mode signal are all true values output by the first mode register, and the third mode signal, the fourth mode signal and the eighth mode signal are all inverted values output by the first mode register; In the third subsequence circuit, the first mode signal, the second mode signal, the fourth mode signal, the fifth mode signal, the sixth mode signal and the eighth mode signal are all true values output by the first mode register, and the third mode signal and the seventh mode signal are both inverted values output by the first mode register; In the fourth sub-sequence circuit, the first mode signal, the second mode signal, the fourth mode signal, the fifth mode signal and the sixth mode signal are all true values output by the first mode register, and the third mode signal, the seventh mode signal and the eighth mode signal are all inverted values output by the first mode register.
10. The key protection circuit according to any one of claims 4 to 9, characterized in that: The structures of the second sub-sequence circuit, the third sub-sequence circuit and the fourth sub-sequence circuit are the same as the structure of the first sub-sequence circuit.
11. A key protection method, characterized in that: Applied to a key protection circuit, wherein the key protection circuit includes a signal input circuit and a protection sequence circuit, and the method includes: Performing a logic operation on the first enable signal and the target sequence signal through the signal input circuit to obtain a second enable signal; When the protection sequence circuit includes multiple sub-sequence circuits, the first sub-sequence circuit performs a logical operation on the mode control signal, the mode write signal and the second enable signal to obtain a first sequence signal; the i+1th sub-sequence circuit performs a logical operation on the mode control signal, the mode write signal and the i-th sequence signal output by the i-th sub-sequence circuit to obtain an i+1th sequence signal, until the last sub-sequence circuit outputs the target sequence signal, where i is an integer greater than 0.
12. The method according to claim 11, characterized in that The signal input circuit includes a first NOT gate and a first NOR gate; the signal input circuit performs a logic operation on the first enable signal and the target sequence signal to obtain a second enable signal, including: Performing a NOT logic operation on the first enable signal through the first NOT gate to obtain a third enable signal; The second enable signal is obtained by performing a NOR logic operation on the third enable signal and the target sequence signal through the first NOR gate.
13. The method according to claim 11, characterized in that The protection sequence circuit includes four sub-sequence circuits, and the four sub-sequence circuits include a first sub-sequence circuit, a second sub-sequence circuit, a third sub-sequence circuit and a fourth sub-sequence circuit; Outputting the target sequence signal through the protection sequence circuit includes: Performing a logic operation on the mode control signal, the mode write signal, the second enable signal and the reset signal through the first subsequence circuit to obtain a first sequence signal; Performing a logic operation on the mode control signal, the mode write signal, the first sequence signal and the reset signal through the second subsequence circuit to obtain a second sequence signal; Performing a logic operation on the mode control signal, the mode write signal, the second sequence signal and the reset signal through the third subsequence circuit to obtain a third sequence signal; The target sequence signal is obtained by performing a logic operation on the mode control signal, the mode write signal, the third sequence signal and the reset signal through the fourth subsequence circuit.
14. The method according to claim 13, characterized in that The method further comprises: When the first sequence signal, the second sequence signal, the third sequence signal and the target sequence signal meet a preset sequence condition, it is determined that the key protection is successful to support the row address to perform a post-packaging repair (PPR) function.
15. A memory, characterized in that: The memory comprises a key protection circuit as claimed in any one of claims 1 to 10.