A circuit level optimization method based on NAND and XOR majority logic

Abstract

The present invention discloses a circuit level optimization method based on NAND and XOR majority logic, including the steps of: parsing target design circuit information to obtain NAND graph AIG; performing logic optimization on AIG with the goal of optimizing the number of nodes; converting the AIG logic after the number of nodes is optimized into XOR majority logic graph XMG; performing logic optimization on XMG obtained by logic conversion with the goal of optimizing the logic level; converting the XMG logic after the logic level is optimized into AIG; performing logic optimization on AIG obtained by logic conversion with the goal of optimizing the logic level; performing delay-oriented process mapping on AIG after the logic level is optimized, generating and outputting a process gate-level netlist. The method effectively combines the logic optimization process of AIG and XMG, improves the local optimal problem in optimization, enhances the adaptability to specific design goals, improves the optimization efficiency and effect of large-scale circuit design, and obtains a better circuit after logic optimization.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design automation, and in particular to a circuit level optimization method based on NAND and XOR majority logic. Background Art

[0002] With the rapid development of integrated circuits, chip design cannot be separated from the support of electronic design automation (EDA) tools. EDA refers to the design method that uses computer-aided design software to complete the functional design, logic synthesis, verification, physical design and other processes of the chip. Logic synthesis is a key step in the EDA workflow. It is the process of converting the circuit design using hardware description language to the circuit netlist at the logic gate level after optimizing the Boolean function under the process library input and design constraints. Among them, logic optimization is the core part of logic synthesis.

[0003] Logic synthesis mainly includes three stages: translation, optimization, and mapping. Among them, logic optimization is to optimize the power consumption, delay, and area of ​​the target design while satisfying the design constraints and logical functional equivalence. Existing logic optimization methods generally have problems such as insufficient optimization methods, limited adaptability to specific optimization targets, and low efficiency in handling large-scale designs when facing complex designs. The effect of logic optimization directly affects the quality of the mapped netlist, which in turn has an important impact on the subsequent steps of EDA work. Therefore, the existing problems in logic optimization need to be further studied and solved. Summary of the invention

[0004] The purpose of the present invention is to provide a circuit level optimization method based on NAND and XOR majority logic. The method combines the characteristics of different logic representations and utilizes optimization methods of multiple logic representations to achieve efficient circuit logic level optimization with adaptive judgment, and makes targeted improvements to the problems of insufficient optimization methods in logic optimization, limited adaptability to specific optimization targets, and low efficiency in handling large-scale designs.

[0005] The technical solution adopted by the present invention to solve the above technical problems is: a circuit level optimization method based on NAND and XOR majority logic, comprising the following steps:

[0006] Step 1, read the aig file or Verilog file containing the target design circuit information, parse the target design circuit information, and obtain an AND-Inverter Graph (AIG) representing the target design circuit, where the AIG is a directed acyclic graph that stores the logic function of the target design circuit;

[0007] Step 2, performing logic optimization with the goal of optimizing the number of nodes on the AIG representing the target design circuit, and obtaining the AIG with optimized number of nodes;

[0008] Step 3: The AIG with optimized node quantity is logically converted into XOR-Majority Graph (XMG) while maintaining the equivalent of logical functions;

[0009] Step 4: Execute logic optimization with the goal of optimizing the logic level on the XMG obtained by the logic conversion to obtain an XMG after the logic level is optimized;

[0010] Step 5: logically convert the XMG after logic level optimization into AIG while maintaining the equivalent of logical functions;

[0011] Step 6: Execute logic optimization with the goal of optimizing the logic level on the AIG obtained by the logic conversion to obtain the AIG after the logic level optimization;

[0012] Step 7: Perform delay-oriented process mapping on the AIG after logic-level optimization to generate and output a process gate-level netlist.

[0013] The circuit level optimization method based on NAND and XOR majority logic proposed in the present invention is a new adaptive logic optimization method applicable to the logic synthesis stage. The logic representations of the target design circuit in the logic synthesis stage include: NAND graph (AND-Inverter graph, AIG), majority logic graph (Majority-Inverter graph, MIG), XOR-AND graph (XAG), XOR majority logic graph (XOR-Majority graph, XMG), etc. Different logic representations have their own advantages. The present invention combines the characteristics of different logic representations and uses optimization methods of multiple logic representations to achieve efficient circuit logic level optimization with adaptive judgment, and makes targeted improvements to the problems of insufficient optimization methods in logic optimization, limited adaptability to specific optimization targets, and low efficiency in handling large-scale designs.

[0014] Preferably, the specific process of step 2 is: define the AIG with the best number of global nodes as the AIG with the least number of nodes in the logic optimization process; cyclically use the comprehensive flow of optimizing the number of AIG nodes until convergence, update and save the AIG with the best number of global nodes, and the specific operation is as follows: cyclically use different optimization operators to reduce the number of nodes of AIG, and judge whether the convergence condition is met, wherein the convergence condition is: (number of AIG nodes before optimization - number of AIG nodes after optimization) / whether the number of AIG nodes before optimization is greater than or equal to the optimization convergence rate r1; if the convergence condition is met, stop the optimization and output the AIG with the best number of global nodes as the AIG with optimized number of nodes; if the convergence condition is not met, continue the cyclic optimization, update and save the AIG with the best number of global nodes until the convergence condition is met or the number of AIG nodes no longer decreases, and output the AIG with the best number of global nodes as the AIG with optimized number of nodes.

[0015] Preferably, the specific process of step 4 is: define the XMG with the best number of levels globally as the XMG with the least number of levels in the logic optimization process; cyclically use the comprehensive flow of optimizing the number of XMG levels until convergence, update and save the XMG with the best number of levels globally, and the specific operation is as follows: cyclically use different optimization operators to reduce the number of levels of XMG, and determine whether the convergence condition is met, wherein the convergence condition is: (the number of XMG levels before optimization - the number of XMG levels after optimization) / whether the number of XMG levels before optimization is greater than or equal to the optimization convergence rate r2; if the convergence condition is met, stop the optimization and output the XMG with the best number of levels globally as the XMG after logic level optimization; if the convergence condition is not met, continue the cyclic optimization, update and save the XMG with the best number of levels globally, until the convergence condition is met or the number of XMG levels no longer decreases, and output the XMG with the best number of levels globally as the XMG after logic level optimization.

[0016] Preferably, the specific process of step 6 is: define the AIG with the best number of global levels as the AIG with the least number of levels in the logic optimization process; cyclically use the comprehensive flow of optimizing the number of AIG levels until convergence, update and save the AIG with the best number of global levels, and the specific operation is as follows: cyclically use different optimization operators to reduce the number of levels of AIG, and judge whether the convergence condition is met, wherein the convergence condition is: (the number of AIG levels before optimization - the number of AIG levels after optimization) / whether the number of AIG levels before optimization is greater than or equal to the optimization convergence rate r3; if the convergence condition is met, stop the optimization and output the AIG with the best number of global levels as the AIG after the logic level optimization; if the convergence condition is not met, continue the cyclic optimization, update and save the AIG with the best number of global levels until the convergence condition is met or the number of AIG levels no longer decreases, and output the AIG with the best number of global levels as the AIG after the logic level optimization.

[0017] Compared with the prior art, the present invention has the following advantages:

[0018] (1) The circuit level optimization method based on NAND and XOR majority logic proposed in the present invention is a new type of adaptive logic optimization method applicable to the logic synthesis stage. It can combine the characteristics of different logic representations and use optimization methods of multiple logic representations to achieve efficient circuit logic level optimization with adaptive judgment. The method of the present invention combines the logic expression characteristics of AIG and XMG, and can break through the limitations of traditional logic optimization methods with single logic representation to achieve better logic optimization effects. AIG has a good effect on control circuit representation and optimization, and XMG has a good effect on arithmetic circuit representation and optimization. The method of the present invention can improve the local optimal problem in logic optimization by effectively combining the logic optimization processes of AIG and XMG, enhance the adaptability to specific design goals, improve the optimization efficiency and effect of large-scale circuit design, and obtain better logic-optimized circuits.

[0019] (2) The circuit level optimization method based on NAND and XOR majority logic proposed in the present invention realizes the automatic judgment of the logic optimization effect in the logic synthesis stage and maintains the global optimal circuit, avoiding resource waste and improving the logic optimization efficiency; the adaptive logic optimization of the method of the present invention effectively improves the logic optimization effect, prevents resource waste caused by redundant logic optimization, improves the logic optimization efficiency, and improves the adaptability to different design circuits;

[0020] (3) The method of the present invention has shown good experimental results. The method of the present invention has achieved an optimization effect of 9.69% of the average number of optimized nodes and 73.73% of the average optimized logic level of the original circuit. In the process mapping experiment, compared with the traditional logic optimization method, the test results based on the ASAP7.genlib process library show that the method of the present invention effectively improves the result quality of process mapping. Compared with the mapping results of the traditional method based on single logic representation optimization, the mapping area is reduced by an average of 9.8%, and the mapping delay is reduced by an average of 15.89%. Therefore, the method of the present invention provides a new research idea for the logic level optimization of NAND logic and XOR majority logic circuits, and at the same time shows good experimental results, which has strong engineering practice significance and application value. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a flow chart of a circuit level optimization method based on NAND and XOR majority logic in an embodiment;

[0022] Figure 2 A Verilog file containing target design circuit information;

[0023] Figure 3 AIG is a NAND graph to represent the target designed circuit;

[0024] Figure 4 XMG is the XOR majority logic graph converted from AIG logic after optimizing the number of nodes;

[0025] Figure 5 AIG is converted from XMG logic after logic-level optimization;

[0026] Figure 6 A process gate-level netlist obtained by performing delay-oriented process mapping on the AIG after logic-level optimization;

[0027] Figure 2 In , [1:0]a and [1:0]b represent the input of the target design circuit, and res represents the output of the target design circuit;

[0028] Figure 3~Figure 5 In the figure, 1, 2, 3, and 4 represent the input of the target design circuit. Figure 4 In the example, 0 represents the constant node required for the three-input XOR operation, po0 represents the output of the target design circuit, and 1, 2, 3, and 4 correspond to Figure 2 The target design circuit input in po0 corresponds to Figure 2 The output of the target design circuit in ; the solid line represents the connection relationship of the nodes, the dotted line represents the logical negation, the AND node represents the logical AND, the XOR node represents the logical exclusive OR, and the MAJ node represents the majority voter with three inputs;

[0029] Figure 6 In the figure, PI 0, PI 1, PI 2, and PI 3 represent the input of the target design circuit respectively, PO 0 represents the output of the target design circuit, 9 NOR2xp33 represents the NOR unit in the ASAP7.genlib process library, 6 OA211x2 represents the NAND or OR unit in the ASAP7.genlib process library, 7 NAND2xp33 represents the NAND unit in the ASAP7.genlib process library, 8 XNOR2xp5 represents the XNOR unit in the ASAP7.genlib process library, and 10 AOI22xp33 represents the NAND or AND unit in the ASAP7.genlib process library. DETAILED DESCRIPTION

[0030] The present invention is further described in detail below with reference to the accompanying drawings.

[0031] Example: For Figure 2 The target design circuit represented by the Verilog file shown in FIG. 1 is subjected to circuit level optimization by the method of the present invention. The flowchart of the optimization method is shown in FIG. Figure 1 As shown, the steps are as follows:

[0032] Step 1: Read Figure 2 The Verilog file containing the target design circuit information shown in the figure is parsed to obtain the AIG representing the target design circuit, such as Figure 3 As shown, the AIG is a directed acyclic graph that stores the logic functions of the target design circuit;

[0033] Step 2, perform logic optimization with the goal of optimizing the number of nodes on the AIG representing the target design circuit to obtain the AIG with optimized number of nodes. The specific process is as follows: define the AIG with the best number of global nodes as the AIG with the least number of nodes in the logic optimization process; cyclically use the comprehensive flow of optimizing the number of AIG nodes until convergence, update and save the AIG with the best number of global nodes. The specific operation is as follows: cyclically use different optimization operators to reduce the number of nodes of AIG, and judge whether the convergence condition is met, where the convergence condition is: (the number of AIG nodes before optimization - the number of AIG nodes after optimization) / whether the number of AIG nodes before optimization is greater than or equal to the optimization convergence rate r1. If the convergence condition is met, stop the optimization and output the AIG with the best number of global nodes as the AIG with optimized number of nodes. If the convergence condition is not met, continue the cyclic optimization, update and save the AIG with the best number of global nodes until the convergence condition is met or the number of AIG nodes is no longer reduced, and output the AIG with the best number of global nodes as the AIG with optimized number of nodes.

[0034] Step 3: The AIG with optimized node quantity is logically converted into an XOR majority logic graph XMG while maintaining the equivalent logic function, as shown in Figure 4 As shown;

[0035] Step 4: Perform logic optimization with the goal of optimizing the logic level on the XMG obtained by the logic conversion to obtain the XMG after the logic level is optimized. The specific process is as follows: define the XMG with the best number of global levels as the XMG with the least number of levels in the logic optimization process; cyclically use the comprehensive flow of optimizing the number of XMG levels until convergence, update and save the XMG with the best number of global levels. The specific operation is as follows: cyclically use different optimization operators to reduce the number of levels of XMG, and judge whether the convergence condition is met, wherein the convergence condition is: (the number of XMG levels before optimization - the number of XMG levels after optimization) / whether the number of XMG levels before optimization is greater than or equal to the optimization convergence rate r2. If the convergence condition is met, stop the optimization and output the XMG with the best number of global levels as the XMG after the logic level is optimized. If the convergence condition is not met, continue the cyclic optimization, update and save the XMG with the best number of global levels until the convergence condition is met or the number of XMG levels is no longer reduced, and output the XMG with the best number of global levels as the XMG after the logic level is optimized.

[0036] Step 5: After the logic level optimization, the XMG is logically converted to AIG while maintaining the equivalent logic function, such as Figure 5 As shown;

[0037] Step 6. Perform logic optimization with the goal of optimizing the logic level on the AIG obtained by the logic conversion to obtain the AIG after the logic level is optimized. The specific process is as follows: define the AIG with the best number of global levels as the AIG with the least number of levels in the logic optimization process; cyclically use the comprehensive flow of optimizing the number of AIG levels until convergence, update and save the AIG with the best number of global levels. The specific operation is as follows: cyclically use different optimization operators to reduce the number of levels of AIG, and judge whether the convergence condition is met, where the convergence condition is: (the number of AIG levels before optimization - the number of AIG levels after optimization) / whether the number of AIG levels before optimization is greater than or equal to the optimization convergence rate r3. If the convergence condition is met, stop the optimization and output the AIG with the best number of global levels as the AIG after the logic level is optimized. If the convergence condition is not met, continue the cyclic optimization, update and save the AIG with the best number of global levels until the convergence condition is met or the number of AIG levels is no longer reduced, and output the AIG with the best number of global levels as the AIG after the logic level is optimized.

[0038] Step 7: Perform delay-oriented process mapping on the AIG after logic level optimization to generate and output the process gate level netlist, such as Figure 6 shown.

[0039] The optimization operators used in the above steps 2, 4, and 6 adopt existing technologies, such as the operators in the known open source logic synthesis tools ABC (https: / / github.com / berkeley-abc / abc) and Mockturtle (https: / / github.com / lsils / mockturtle). Specifically, optimization operators such as resyn2; resyn2rs; compress2rs; dc2 can be used cyclically to reduce the number of nodes of AIG, optimization operators such as xmgrs and xmgrw can be used cyclically to reduce the number of levels of XMG, and optimization operators such as sop balancing and dsd balancing can be used cyclically to reduce the number of levels of AIG.

[0040] The method of the present invention optimizes multiple indicators such as the number of nodes and logic levels of the circuit while maintaining the logic function of the circuit through multiple iterations of logic optimization and logic conversion, thereby improving the overall performance of the circuit design.

[0041] The method of the present invention has obvious advantages and excellent performance. It effectively improves the problems of poor adaptation effect for different test cases in logic optimization, optimization is easy to fall into local optimum and logic optimization efficiency is low, and improves the quality and efficiency of logic optimization. After experimental testing, compared with the traditional logic optimization method based on single logic representation AIG loop iteration, the method of the present invention is not easy to fall into local optimum, which improves the effect of logic optimization. The results of the logic optimization experiment are shown in Table 1. The results show that the method of the present invention achieves an optimization effect of 9.69% of the average number of optimized nodes for the original circuit and 73.73% of the average logic level of the optimized circuit. In the process mapping experiment, the test results based on the ASAP7.genlib process library show that the method of the present invention effectively improves the result quality of process mapping. The results of the process mapping experiment are shown in Table 2. The results show that the mapping area of ​​the mapping results of the method of the present invention is reduced by an average of 9.8% compared with the traditional method based on single logic representation optimization, and the mapping delay is reduced by an average of 15.89%.

[0042] Table 1. Logic optimization experimental results:

[0043]

[0044] Table 2. Process mapping experimental results:

[0045]

[0046] In summary, compared with traditional methods, the circuit level optimization method based on NAND and XOR majority logic proposed in the present invention effectively improves the quality of logic optimization results, can improve the local optimal problem in logic optimization, enhance the adaptability to specific design goals, improve the optimization efficiency and effect of large-scale circuit design, and obtain better logic optimized circuits. Finally, the method of the present invention shows good results in delay-oriented process mapping, and has strong practical significance and application value.

Claims

1. A circuit level optimization method based on NAND and XOR majority logic, characterized in that: The following steps are involved: Step 1, read the aig file or Verilog file containing the target design circuit information, parse the target design circuit information, and obtain the NAND graph AIG representing the target design circuit, where the AIG is a directed acyclic graph that stores the logic function of the target design circuit; Step 2, performing logic optimization with the goal of optimizing the number of nodes on the AIG representing the target design circuit, and obtaining the AIG with optimized number of nodes; Step 3: The AIG with optimized node quantity is logically converted into an XOR majority logic graph XMG while maintaining the equivalent logic function; Step 4: Execute logic optimization with the goal of optimizing the logic level on the XMG obtained by the logic conversion to obtain an XMG after the logic level is optimized; Step 5: logically convert the XMG after logic level optimization into AIG while maintaining the equivalent of logical functions; Step 6: Execute logic optimization with the goal of optimizing the logic level on the AIG obtained by the logic conversion to obtain the AIG after the logic level optimization; Step 7: Perform delay-oriented process mapping on the AIG after logic-level optimization to generate and output a process gate-level netlist.

2. The circuit level optimization method based on NAND and XOR majority logic according to claim 1, characterized in that: The specific process of step 2 is as follows: define the AIG with the best number of global nodes as the AIG with the least number of nodes in the logic optimization process; cyclically use the comprehensive flow of optimizing the number of AIG nodes until convergence, update and save the AIG with the best number of global nodes. The specific operation is as follows: cyclically use different optimization operators to reduce the number of nodes of AIG, and judge whether the convergence condition is met, wherein the convergence condition is: (the number of AIG nodes before optimization - the number of AIG nodes after optimization) / whether the number of AIG nodes before optimization is greater than or equal to the optimization convergence rate r1. If the convergence condition is met, stop the optimization and output the AIG with the best number of global nodes as the AIG with optimized number of nodes. If the convergence condition is not met, continue the cyclic optimization, update and save the AIG with the best number of global nodes until the convergence condition is met or the number of AIG nodes no longer decreases, and output the AIG with the best number of global nodes as the AIG with optimized number of nodes.

3. The circuit level optimization method based on NAND and XOR majority logic according to claim 1, characterized in that: The specific process of step 4 is as follows: define the XMG with the best number of global levels as the XMG with the least number of levels in the logic optimization process; cyclically use the comprehensive flow of optimizing the number of XMG levels until convergence, update and save the XMG with the best number of global levels. The specific operation is as follows: cyclically use different optimization operators to reduce the number of levels of XMG, and determine whether the convergence condition is met, wherein the convergence condition is: (the number of XMG levels before optimization - the number of XMG levels after optimization) / whether the number of XMG levels before optimization is greater than or equal to the optimization convergence rate r2. If the convergence condition is met, stop the optimization and output the XMG with the best number of global levels as the XMG after logic level optimization. If the convergence condition is not met, continue the cyclic optimization, update and save the XMG with the best number of global levels until the convergence condition is met or the number of XMG levels no longer decreases, and output the XMG with the best number of global levels as the XMG after logic level optimization.

4. The circuit level optimization method based on NAND and XOR majority logic according to claim 1, characterized in that: The specific process of step 6 is as follows: define the AIG with the best number of global levels as the AIG with the least number of levels in the logic optimization process; cyclically use the comprehensive flow of optimizing the number of AIG levels until convergence, update and save the AIG with the best number of global levels. The specific operation is as follows: cyclically use different optimization operators to reduce the number of levels of AIG, and determine whether the convergence condition is met, wherein the convergence condition is: (the number of AIG levels before optimization - the number of AIG levels after optimization) / whether the number of AIG levels before optimization is greater than or equal to the optimization convergence rate r3. If the convergence condition is met, stop the optimization and output the AIG with the best number of global levels as the AIG after the logic level optimization. If the convergence condition is not met, continue the cyclic optimization, update and save the AIG with the best number of global levels until the convergence condition is met or the number of AIG levels no longer decreases, and output the AIG with the best number of global levels as the AIG after the logic level optimization.

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