Universal routability prediction method based on few-shot learning

Abstract

The application relates to a universal routable linear prediction method based on few-shot learning, and belongs to the technical field of integrated circuit computer-aided design. The universal routable linear prediction is converted into a meta-learning scene, and a prediction method based on few-shot learning (FSL) is proposed. The method can be flexibly adapted to new prediction tasks by only providing the features and label pairs of an example set of a query chip, and does not need additional training. In view of the data imbalance problem commonly existing in the field of electronic design automation, a meta-learning strategy based on importance sampling is further introduced, which is used for optimizing the training process of the model. In order to train the proposed method, a FSL data set based on CircuitNet and an ISPD2015 data set is constructed.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit computer-aided design, and in particular relates to a universal routability prediction method based on few-sample learning. Background Art

[0002] The continuous reduction in feature size and increasing complexity of on-chip connectivity in very large-scale integration (VLSI) designs pose challenges to the scalability of electronic design automation (EDA) technology. Routability is one of the most challenging issues in the EDA process. A key goal is to leverage data from the layout phase to assess the difficulty of routing a chip design. Typical metrics include routing congestion and the distribution of design rule check (DRC) violations. Routing has been proven to be an NP-hard problem, resulting in long feedback cycles in the design process. Rapid and accurate prediction of routability in the early design stages is crucial to improve feedback efficiency and accelerate design convergence. Using machine learning (ML) to predict results in the early design stages to facilitate optimization between design steps has become a popular approach in EDA, providing faster convergence and reducing pessimism.

[0003] Key challenges in using ML for routability prediction include missing datasets, data imbalance, and domain shift. These pose significant obstacles to the application of ML for routability prediction. Different application scenarios present diverse design goals for chips, requiring customized adjustments to EDA tools and continuous updates to routability prediction tasks. To address these challenges, chip design engineers need to train models from scratch or fine-tune existing models. However, training neural networks requires not only machine learning knowledge but also computing resources, labeled data, and manual labor. For engineers who lack these resources, this presents a nearly insurmountable obstacle, hindering chip design efficiency.

[0004] FSL aims to quickly learn and adapt to new tasks with a small amount of data annotation, effectively alleviating the problem of data scarcity. In chip design, the same Register Transfer Level (RTL) design is often reused and optimized differently through the EDA process. Summary of the Invention

[0005] The purpose of the present invention is to provide a universal routability prediction method based on few-shot learning, which can flexibly handle different routability metrics, chip types, design scales, manufacturing technologies and unknown tasks, and realize universal routability prediction.

[0006] To achieve the above objectives, the technical solution of the present invention is: a universal routability prediction method based on few-shot learning, which converts universal routability prediction into a meta-learning scenario, proposes a prediction method based on few-shot learning FSL, and realizes query chip routability prediction.

[0007] In one embodiment of the present invention, the method includes:

[0008] The task of predicting the routability of a chip layout divided into arbitrary W×H grids Defined as Where X represents the chip characteristics used. The tasks include different routability metrics (e.g., congestion and DRC violations), technology nodes (e.g., 28nm and 14nm), chip types (e.g., CPU, GPU, and AI chips), and RTL designs (e.g., different scales and design goals).

[0009] Modeling the general routability prediction task as a meta-learning scenario to build a general few-shot learner By leveraging unseen chip designs, q Chip data with the same RTL design is the support set Adaptable to any routability prediction task Generate accurate routability prediction models Leveraging a meta-training dataset encompassing various routability prediction tasks The routability prediction model is trained through meta-learning, so that the routability prediction model can master general knowledge after going through multiple FSL processes.

[0010] In order to fully utilize the spatial correlation information between chip features and labels, the general routability prediction task is modeled as a dense prediction problem. Use 4 features that are widely used in routability prediction tasks;

[0011] For the routability prediction task t of chip design, the routability prediction model is used to query A support set consisting of chip features and their labels for the same RTL design As input; in the support set, each chip feature and its label are cascaded in the channel dimension, and the cross block promotes the information interaction between the support set and the query, thereby achieving routability results accurate predictions.

[0012] In one embodiment of the present invention, the routability prediction model is trained by meta-learning, so that the routability prediction model can master general knowledge during multiple FSL processes. Importance sampling technology is introduced into the meta-learning to optimize the loss of the model on different tasks. The goal is to enable the model to adaptively adjust the loss L of different tasks during the training process. t Dynamic changes in task sampling Each task retains the last 10 historical loss values ​​and updates them dynamically during training.

[0013] In one embodiment of the present invention, before training begins, a batch of tasks B is randomly sampled until 10 samples are collected for each task, and then the meta-learning strategy based on importance sampling is started; in the task sampling stage, in order to introduce randomness and prevent the model from forgetting past knowledge, the probability p of task sampling is calculated. t When adding a constant γ=0.01, the meta-training dataset D train The number of tasks in is n; based on p t Sample a task t of batch B B ; From each task t b∈B Medium sampling query and support set To prevent the model from overfitting on a specific task and improve the diversity of the data, the query and support set Perform data enhancement; finally, train the t Under the condition of the support set, the accuracy of the model's routability prediction for a given query is improved, and the model can master general knowledge about FSL through meta-learning.

[0014] In one embodiment of the present invention, the four features widely used in routability prediction tasks are: rectangular uniform wire density RUDY, RUDY pins, macro area, and cell density.

[0015] In one embodiment of the present invention, for the routability prediction task t of chip design, routability results are achieved. In the accurate prediction process of , UniverSeg is used as the backbone to adapt to support sets of different sizes.

[0016] In one embodiment of the present invention, the meta-training dataset Built on CricuitNet and ISPD2015 datasets.

[0017] In one embodiment of the present invention, the data set corresponding to each chip design routability prediction task is constructed into three disjoint partitions d={ds ,d v ,d t}, containing 60%, 20%, and 20% of the data respectively; the model uses the support partition d in the training set s and test partition d t To train the model, use the validation split d v for model selection and hyperparameter tuning.

[0018] The present invention also provides a general routability prediction system based on few-sample learning, comprising a memory, a processor, and computer program instructions stored in the memory and capable of being executed by the processor. When the processor executes the computer program instructions, the method steps described above can be implemented.

[0019] The present invention also provides a computer-readable storage medium on which computer program instructions that can be executed by a processor are stored. When the processor executes the computer program instructions, the method steps described above can be implemented.

[0020] Compared with the prior art, the present invention has the following beneficial effects: the method of the present invention transforms general routability prediction into a meta-learning scenario, and proposes a prediction method based on Few-Shot Learning (FSL). The method only needs to provide the features of the query chip and a set of label pair examples, and can be flexibly adapted to new prediction tasks without the need for additional training. In response to the data imbalance problem that is prevalent in the field of electronic design automation, the present invention also introduces a meta-learning strategy based on importance sampling to optimize the training process of the model. In order to train the proposed method, an FSL dataset based on CircuitNet and ISPD2015 datasets was constructed. The method of the present invention can flexibly handle different routability metrics, chip types, design scales, manufacturing technologies and unknown tasks to achieve general routability prediction. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a model architecture diagram of the method of the present invention. DETAILED DESCRIPTION

[0022] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings.

[0023] It should be noted that the following detailed descriptions are exemplary and are intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present application belongs.

[0024] It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0025] The application provides a universal routable linear prediction method based on few-shot learning, which converts the universal routable linear prediction into a meta-learning scene, proposes a prediction method based on few-shot learning FSL, and realizes query chip routable linear prediction.

[0026] The universal routable linear prediction task is modeled as a meta-learning scene, and a universal few-shot learner is constructed By utilizing the chip design not seen, i.e., query X q Chip data with the same RTL design, i.e., support set Adapting to any routable linear prediction task Generating an accurate routable linear prediction model Using a meta-training dataset containing multiple routable linear prediction tasks Through meta-learning, the routable linear prediction model is trained to master general knowledge in the process of multiple FSL;

[0027] In order to fully utilize the spatial correlation information between chip features and labels, the universal routable linear prediction task is modeled as a dense prediction problem Four features widely used in routable linear prediction tasks are used

[0028] For the routable linear prediction task t of the chip design, the routable linear prediction model takes the query And the support set composed of chip features and labels of the same RTL design As input; in the support set, each chip feature and its label are concatenated in the channel dimension, and the cross block is used to promote the information interaction between the support set and the query, so as to realize the accurate prediction of the routable linear prediction result. .

[0029] The following is the specific implementation process of the application.

[0030] The embodiment provides a universal routable linear prediction method based on few-shot learning, and the specific implementation is as follows:

[0031] 1. Model the universal routable linear prediction task as a meta-learning scene

[0032] During the iteration process of chip design, the same RTL design is often reused and optimized differently through the EDA flow for different design targets, thereby accumulating rich data annotation. The core of the present application is to build a general few-shot learner By utilizing the chip design (query) X q with the same RTL design (support set) Flexible adaptation to any routability prediction task Thus, accurate routability prediction is generated Utilizing a meta-training dataset containing multiple routability prediction tasks Through meta-learning, the model is trained to acquire general knowledge during multiple FSL processes. The few-shot learner is based on the given support set Flexible adjustment to adapt to different tasks, thereby generating accurate prediction for the query chip.

[0033] 2. Feature extraction

[0034] Since the routability annotation is usually presented in the form of a 2-dimensional array, in order to fully utilize the spatial correlation information between chip features and labels, the general routability prediction task is modeled as a dense prediction problem Four features widely used in routability prediction tasks are used: rectangular uniform wire density (RUDY), RUDY pin, macro region, and cell density.

[0035] 3. Meta-learning strategy based on importance sampling

[0036] In order to deal with the inherent data imbalance problem, such as the interaction of multiple factors such as chip type, design size and technology node, we introduce the importance sampling technique for meta-learning to smoothly optimize the loss of the model on different tasks. The goal is to enable the model to adaptively sample tasks according to the dynamic changes of the loss L t of different tasks during the training process Specifically, each task retains the last 10 historical loss values and updates dynamically during the training process. Before the start of training, a batch B of tasks t is selected by random sampling, and after 10 samples are collected for each task, the meta-learning strategy based on importance sampling is started. In the task sampling stage, in order to introduce randomness and prevent the model from forgetting past knowledge, a constant γ = 0.01 is added when calculating the task sampling probability p t , and n is the number of tasks in the meta-training dataset D train Based on p t , a batch B of tasks t is sampled BFrom each task t b∈B Medium sampling query and support set In order to prevent the model from overfitting on a specific task and improve the diversity of the data, we query and support set Perform data enhancement. Finally, the training is performed with S t Under the condition of the support set, the accuracy of the model's routability prediction for a given query is improved, and the model can master general knowledge about FSL through meta-learning.

[0037] 4. Model and Reasoning

[0038] In order to fully integrate information across spatial scales, UniverSeg is used as the backbone, as shown in Figure 1 As shown. For the routability prediction task t of a specific chip design, the model is based on query A support set consisting of chip features and their labels for the same RTL design As input, the chip features and their labels in the support set are concatenated in the channel dimension, and the cross-block is used to promote the information interaction between the support set and the query, thereby achieving routability results. The amount of annotated chip data in the EDA field is variable and scarce. Using UniverSeg as the backbone can flexibly adapt to support sets of different sizes, thus better meeting the application needs of FSL in the EDA field.

[0039] 5. FSL Dataset

[0040] In order to train the model, a dataset for FSL is constructed based on CricuitNet and ISPD2015 datasets. This dataset covers different routability metrics, technology nodes, chip types, scales, etc. For different optimization goals, the same RTL design is often reused. Therefore, under specific technology nodes and metrics, the chip data annotation with the same RTL design is divided into a task. The datasets corresponding to these tasks contain chip designs with different optimization goals such as performance, power consumption and area. All features and labels are resized to 256×256 pixels, and the labels are normalized to the range [0,1] by maximum and minimum. The dataset corresponding to each task constructs three non-overlapping partitions d={d s ,d v ,d t}, containing 60%, 20%, and 20% of the data respectively. The model uses the support partition d in the training set s and test partition d t To train the model, use the validation split d v for model selection and hyperparameter tuning.

[0041] The application further provides a general-purpose linear prediction system based on few-shot learning, comprising a memory, a processor and computer program instructions stored in the memory and capable of being executed by the processor, and when the processor executes the computer program instructions, the method steps described above can be realized.

[0042] The application further provides a computer readable storage medium, which stores computer program instructions capable of being executed by a processor, and when the processor executes the computer program instructions, the method steps described above can be realized.

[0043] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system or a computer program product. Therefore, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0044] The present application is described with reference to flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing devices to produce a machine, so that the instructions executed by the computer or other programmable data processing devices produce a device implemented in the flowcharts and / or block diagrams. Figure 1 The function specified in one flow or multiple flows and / or blocks Figure 1 The function specified in one flow or multiple flows and / or blocks

[0045] These computer program instructions can also be stored in a computer readable storage medium capable of guiding the computer or other programmable data processing devices to work in a specific way, so that the instructions stored in the computer readable storage medium produce a product comprising instruction devices, which realize the functions specified in the flowcharts and / or block diagrams. Figure 1 The function specified in one flow or multiple flows and / or blocks Figure 1 The function specified in one flow or multiple flows and / or blocks

[0046] These computer program instructions can also be loaded into a computer or other programmable data processing device, so that a series of operation steps are performed on the computer or other programmable device to produce a computer implemented process, and the instructions executed on the computer or other programmable device provide a process for realizing the functions specified in the flowcharts and / or block diagrams. Figure 1one or more processes and / or blocks Figure 1 the steps of a function specified in one or more blocks.

[0047] The above descriptions are only preferred embodiments of the present application, not intended to limit the present application to other forms described. Any person skilled in the art can make changes or modifications to the above disclosed technical contents as equivalent embodiments. However, any simple modification, equivalent change and modification made to the above embodiments without departing from the technical solution of the present application, according to the technical essence of the present application, still belongs to the protection scope of the present application.

Claims

1. A general routability prediction method based on few-shot learning, characterized in that: The general routability prediction is transformed into a meta-learning scenario, and a prediction method based on few-shot learning (FSL) is proposed to achieve query chip routability prediction. The method includes: The task of predicting the routability of a chip layout divided into arbitrary W×H grids Defined as Where X represents the chip characteristics used; the tasks include different routability metrics, technology nodes, chip types, and RTL designs; Modeling the general routability prediction task as a meta-learning scenario to build a general few-shot learner By leveraging unseen chip designs, q Chip data with the same RTL design is the support set Adaptable to any routability prediction task Generate accurate routability prediction models Leveraging a meta-training dataset encompassing various routability prediction tasks The routability prediction model is trained through meta-learning, so that the routability prediction model can master general knowledge after going through multiple FSL processes. In order to fully utilize the spatial correlation information between chip features and labels, the general routability prediction task is modeled as a dense prediction problem. Use 4 features that are widely used in routability prediction tasks; For the routability prediction task t of chip design, the routability prediction model is used to query A support set consisting of chip features and their labels for the same RTL design As input; in the support set, each chip feature and its label are cascaded in the channel dimension, and the cross block promotes the information interaction between the support set and the query, thereby achieving routability results accurate predictions.

2. The general routability prediction method based on few-shot learning according to claim 1, characterized in that The routability prediction model is trained by meta-learning, so that the routability prediction model can master general knowledge during multiple FSL processes. The importance sampling technique is introduced into the meta-learning to optimize the loss of the model on different tasks. The goal is to enable the model to adaptively adjust the loss L of different tasks during the training process. t Dynamic changes in task sampling Each task retains the last 10 historical loss values ​​and updates them dynamically during training.

3. The general routability prediction method based on few-shot learning according to claim 2, characterized in that: Before training begins, a batch of tasks t is selected by random sampling until 10 samples are collected for each task, and then the meta-learning strategy based on importance sampling is started; in the task sampling stage, in order to introduce randomness and prevent the model from forgetting past knowledge, the probability p of task sampling is calculated. t When adding a constant γ=0.01, the meta-training dataset D train The number of tasks in is n; based on p t Sample a task t of batch B B ; From each task t b∈B Medium sampling query and support set To prevent the model from overfitting on a specific task and improve the diversity of the data, the query and support set Perform data enhancement; finally, train the t Under the condition of the support set, the accuracy of the model's routability prediction for a given query is improved, and the model can master general knowledge about FSL through meta-learning.

4. The general routability prediction method based on few-shot learning according to claim 1, characterized in that: The four features widely used in routability prediction tasks are: rectangular uniform wire density RUDY, RUDY pins, macro area, and cell density.

5. The general routability prediction method based on few-shot learning according to claim 1, characterized in that: Targeting the routability prediction task t of chip design, achieving routability results In the accurate prediction process of , UniverSeg is used as the backbone to adapt to support sets of different sizes.

6. The general routability prediction method based on few-shot learning according to claim 1, characterized in that: The meta-training dataset Built on CricuitNet and ISPD2015 datasets.

7. The general routability prediction method based on few-shot learning according to claim 6, characterized in that: The dataset corresponding to each chip design routability prediction task constructs three disjoint partitions d = {d s ,d v ,d t }, containing 60%, 20%, and 20% of the data respectively; the model uses the support partition d in the training set s and test partition d t To train the model, use the validation split d v for model selection and hyperparameter tuning.

8. A general routability prediction system based on few-shot learning, characterized by: The method comprises a memory, a processor, and computer program instructions stored in the memory and capable of being executed by the processor. When the processor executes the computer program instructions, the method steps according to any one of claims 1 to 7 can be implemented.

9. A computer-readable storage medium storing computer program instructions that can be executed by a processor, wherein when the processor executes the computer program instructions, the method steps according to any one of claims 1 to 7 can be implemented.

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