Data processing method, controller, electronic equipment and computer readable medium

Abstract

The invention discloses a data processing method, a controller, an electronic device and a readable storage medium, and belongs to the technical field of data processing.The method comprises the steps that each line corresponding to a schematic diagram is obtained, if at least two lines in a target track are overlapped, a to-be-optimized line is determined from the overlapped lines, and the to-be-optimized line is optimized according to the determined to-be-optimized line; the line where the to-be-optimized routing is located is a first line; adjusting the to-be-optimized routing to obtain a target routing, wherein the target routing is not overlapped with other routing on the track where the target routing is located; determining a second line comprising the target line according to the first line and the target line, wherein the second line is the same as the pin pair connected with the first line; determining a line, which is not overlapped with the first line, in the second line as a variable line; and if each variable trace is not overlapped with other traces in the track where the variable trace is located, replacing the first line with the second line. The number of overlapped wires can be effectively reduced, and the automatic wiring accuracy of the schematic diagram is improved.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and more specifically, to a data processing method, a controller, an electronic device and a computer-readable medium. Background Art

[0002] After the schematic is automatically generated, the schematic automatic generation technology uses the netlist database as input, and generates a schematic through the schematic automatic generation algorithm based on the component information and connection relationship between components in the netlist database. However, in the process of schematic automatic routing, wiring overlap often occurs, resulting in the schematic after routing unable to clearly and correctly represent the connection relationship of the pins, which brings obstacles to subsequent work. Summary of the invention

[0003] The present application proposes a data processing method, a controller, an electronic device and a computer-readable medium to improve the above-mentioned defects.

[0004] In a first aspect, the present application provides a data processing method, which is applied to a controller of a schematic automatic wiring system, including: obtaining each line corresponding to the schematic, a sub-line segment of each line laid out on a single track is a routing, and different lines are used to connect different pin pairs; if there are at least two overlapping routings in the target track, then determining the routing to be optimized from the overlapping routings, and the line where the routing to be optimized is located is the first routing; adjusting the routing to be optimized to obtain the target routing, and the target routing does not overlap with other routings on the track where it is located; determining a second routing including the target routing based on the first routing and the target routing, and the second routing has the same pin pair connected to the first routing; determining the routing in the second routing that does not overlap with the first routing as a variable routing; if each of the variable routing does not overlap with other routings in the track where it is located, replacing the first routing with the second routing.

[0005] Optionally, for a possible implementation, a track scanning sequence is preset, and the track scanning sequence includes the sequence of all tracks corresponding to the schematic diagram. If each of the changed routes does not overlap with other routes in the track where it is located, after replacing the first route with the second route, it also includes: judging whether there are overlapping routes in the target track; if so, returning to execute if there are at least two overlapping routes in the target track, determining the route to be optimized from the overlapping routes and subsequent operations; if not, determining a target track according to the track scanning sequence, returning to execute each route corresponding to the schematic diagram and subsequent steps until the track corresponding to the track scanning sequence is read to be empty.

[0006] Optionally, for a possible implementation, if there are at least two overlapping routes in the target track, determining the route to be optimized from the overlapping routes, including: if there are at least two overlapping routes in the target track, selecting the two overlapping routes as an overlapping route group, the overlapping route group including a first route and a second route; determining the overlapping range according to the wiring range of the first route and the wiring range of the second route; if the overlapping range is equal to the wiring range of the first route or the wiring range of the second route, screening out the route whose wiring range is equal to the overlapping range from the first route and the second route as the route to be optimized.

[0007] Optionally, in a possible implementation manner, adjusting the routing to be optimized to obtain a target routing includes:

[0008] Create a new alternative track parallel to the target track; determine the first inflection point, the second inflection point, the first associated inflection point and the second associated inflection point according to the route to be optimized and the first route, the first associated inflection point being a inflection point on the first route that is adjacent to the first inflection point and is not the second inflection point, and the second associated inflection point being a inflection point on the first route that is adjacent to the second inflection point and is not the first inflection point; synchronously translate the first inflection point and the second inflection point along a direction perpendicular to the route to be optimized to the alternative track to obtain a temporary first inflection point and a temporary second inflection point, respectively; determine the route connecting the temporary first inflection point and the temporary second inflection point at both ends as the target route.

[0009] Optionally, for a possible implementation, the changed routing includes a target routing, a first associated routing and a second associated routing, the first associated routing being a routing connecting the first associated inflection point and the temporary first inflection point at both ends, and the second associated routing being a routing connecting the second associated inflection point and the temporary second inflection point at both ends.

[0010] Optionally, for a possible implementation, if there are at least two overlapping routes in the target track, determining the route to be optimized from the overlapping routes, including: if there are at least two overlapping routes in the target track, selecting the two overlapping routes as an overlapping route group, the overlapping route group including a first route and a second route; determining the overlapping range according to the wiring range of the first route and the wiring range of the second route; if the overlapping range is not equal to the wiring range of the first route and is not equal to the wiring range of the second route, arbitrarily selecting one route from the first route and the second route as the route to be optimized.

[0011] Optionally, for a possible implementation, the adjusting the route to be optimized to obtain the target route includes: determining a third inflection point, a fourth inflection point, a third associated inflection point and a first node according to the route to be optimized and the first line, the third inflection point being one end point of the route to be optimized and being located within the overlapping range, the fourth inflection point being the other end point of the route to be optimized, the third associated inflection point being an inflection point on the first line that is adjacent to the third inflection point and is not the fourth inflection point, and the third associated inflection point overlaps with the first node; synchronously moving the third inflection point and the third associated inflection point along a preset direction by a preset distance to obtain a temporary third inflection point and a temporary third associated inflection point, the preset direction being a direction from the third inflection point to the fourth inflection point, the preset distance being greater than the length of the overlapping route and less than the length of the route to be optimized, the overlapping route being an overlapping line segment in the overlapping route group; and taking the route with the temporary third inflection point and the fourth inflection point connected at both ends as the target route.

[0012] Optionally, for a possible implementation, the change routing includes a third associated routing and a fourth associated routing, the third associated routing is a routing connecting the first node and the temporary third associated inflection point at both ends, and the fourth associated routing is a routing connecting the temporary third inflection point and the temporary third associated inflection point at both ends.

[0013] Optionally, for a possible implementation, after determining the third inflection point, the fourth inflection point, the third associated inflection point and the first node according to the route to be optimized and the first line, it also includes: creating a new alternative track parallel to the target track; creating a second node and a third node that overlap with each other on the route between the third inflection point and the fourth inflection point, the distance between the third inflection point and the second node being greater than the length of the overlapping route and less than the length of the route to be optimized, and the overlapping route is the overlapping line segment in the overlapping route group; synchronously translating the third inflection point and the second node along a direction perpendicular to the route to be optimized to the alternative track, to obtain a temporary third inflection point and a fifth inflection point respectively; and taking the route connecting the temporary third inflection point and the fifth inflection point at both ends as the target route.

[0014] Optionally, for a possible implementation, the changed routing includes a target routing, a third associated routing and a fourth associated routing, the third associated routing being a routing connecting the third associated inflection point and the temporary third inflection point at both ends, and the fourth associated routing being a routing connecting the fifth inflection point and the third node at both ends.

[0015] In a second aspect, the present application also provides a controller, which is applied to a schematic automatic routing system, including: an acquisition unit, used to acquire each line corresponding to the schematic, a sub-segment of each line laid out on a single track is a routing, and different lines are used to connect different pin pairs; a judgment unit, used to determine the routing to be optimized from the overlapping routings if there are at least two overlapping routings in the target track, and the line where the routing to be optimized is located is the first routing; an adjustment unit, used to adjust the routing to be optimized to obtain a target routing, and the target routing does not overlap with other routings on the track where it is located; a determination unit, used to determine a second routing including the target routing based on the first routing and the target routing, and the second routing has the same pin pair connected to the first routing; a comparison unit, used to determine that the routing in the second routing that does not overlap with the first routing is a changed routing; a replacement unit, used to replace the first routing with the second routing if each of the changed routing does not overlap with other routings in the track where it is located.

[0016] In a third aspect, the present application also provides an electronic device, comprising: one or more processors; a memory; one or more applications, wherein the one or more applications are stored in the memory, the one or more applications are configured to be executed by the one or more processors, and the one or more applications are configured to execute the above method.

[0017] In a fourth aspect, the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a program code executable by a processor, and when the program code is executed by the processor, the processor executes the above method.

[0018] The solution provided by the present application is to obtain a target routing by adjusting the routing to be optimized, wherein the target routing does not overlap with other routings on the track where it is located, and to obtain a second circuit including the target routing according to the first circuit and the target routing, wherein the second circuit has the same pin pair as the first circuit, and the routings in the second circuit that do not overlap with the first circuit are variable routings, and when each variable routing does not overlap with other routings in the track where it is located, the first circuit is replaced by the second circuit. The present application can eliminate the overlap between the routing to be optimized and other routings, and ensure that no other overlapping routings are added, thereby effectively reducing the number of overlapping routings and improving the accuracy of automatic wiring of schematic diagrams.

[0019] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained by the structures specifically pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 A flow chart of a method for data processing provided by an embodiment of the present application is shown;

[0022] Figure 2 A method flow chart of a data processing method provided by another embodiment of the present application is shown;

[0023] Figure 3 A method flow chart of a data processing method provided by another embodiment of the present application is shown;

[0024] Figure 4 A method flow chart of a data processing method provided by another embodiment of the present application is shown;

[0025] Figure 5 A method flow chart of a data processing method provided by another embodiment of the present application is shown;

[0026] Figure 6 A method flow chart of a data processing method provided by another embodiment of the present application is shown;

[0027] Figure 7 A partial schematic diagram of the principle diagram provided by the embodiment of the present application is shown;

[0028] Figure 8 A schematic diagram of part of the principle diagram with overlapping routing provided by an embodiment of the present application is shown;

[0029] Fig. 9 Shows the elimination Figure 8 Schematic diagram of part of the schematic after overlapping routing;

[0030] Fig.10 Shows the elimination Figure 8 Another schematic diagram of a partial schematic after overlapping routing in;

[0031] Fig.11 A schematic diagram of a part of a schematic diagram with overlapping routing provided by an embodiment of the present application is shown;

[0032] Fig.12 This shows the elimination Fig.11 Schematic diagram of part of the schematic after overlapping routing;

[0033] Fig.13The structure block diagram of the controller provided by the embodiment of the present application is shown;

[0034] Fig.14 A structural block diagram of an electronic device provided in an embodiment of the present application is shown;

[0035] Fig.15 A structural block diagram of a computer-readable storage medium provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0036] In order to make those skilled in the art better understand the present application scheme, the technical scheme in the present application embodiment will be clearly and completely described below in conjunction with the drawings in the present application embodiment. Obviously, the described embodiment is only a part of the present application embodiment, rather than all the embodiments. The components of the present application embodiment usually described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the present application for protection, but merely represents the selected embodiment of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0037] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0038] After the schematic is automatically generated, the schematic automatic generation technology uses the netlist database as input, and generates a schematic through the schematic automatic generation algorithm based on the component information and the connection relationship between components in the netlist database. However, in the process of schematic automatic routing, wiring overlap often occurs, resulting in the schematic after routing unable to clearly and correctly represent the connection relationship of the pins, which brings obstacles to subsequent work.

[0039] Therefore, in the embodiments of the present application, a data processing method, a controller, an electronic device and a computer-readable medium are provided to solve or partially solve the above-mentioned problems.

[0040] See also Figure 1 , which shows a method flow chart of a data processing method provided by an embodiment of the present application, the method is applied to a controller of a schematic automatic wiring system, and the controller can execute the data processing method. The method specifically includes steps S110 to S160.

[0041] Step S110: Acquire each circuit corresponding to the schematic diagram, wherein a sub-segment of each circuit arranged on a single track is a routing line, and different circuits are used to connect different pin pairs.

[0042] It should be noted that the schematic automatic generation system can automatically generate and output the schematic based on the netlist database, and the automatic wiring system can automatically wire the schematic data output by the schematic automatic generation system to obtain original wiring data, wherein the original wiring data includes the schematic and each circuit corresponding to the schematic, and the circuit includes wiring data between pins, and each sub-segment of the circuit laid out on a single track is a routing, and different circuits are used to connect different pairs of pins. The present application can obtain a circuit connected between two pins from the original wiring data, and the circuit includes at least one routing. The original wiring data may include multiple circuits.

[0043] It should be noted that, when designing the automatic wiring of the schematic diagram, it is designed that a plurality of horizontal tracks and a plurality of vertical tracks are sequentially arranged between the chips, and the horizontal tracks and the vertical tracks are crisscrossed.

[0044] Specifically, the line may include one routing line, or may include multiple routing lines connected end to end.

[0045] For example, see Figure 7 The x1 line includes a horizontal trace, and the pin pair connected to the x1 line includes two pins, namely the m2.b4 pin and the m5.a7 pin. One end of the horizontal trace is connected to the m2.b4 pin, and the other end of the horizontal trace is connected to the m5.a7 pin. The horizontal trace is arranged on the 7th horizontal track.

[0046] For example, see Figure 7 The x2 line includes three lines connected end to end, namely line A, line B and line C. The pin pair connected to the x2 line includes two pins, namely m2.b2 pin and m5.a5 pin. The two ends of the line B are respectively connected to one end of the line A and one end of the line C, the other end of the line A is connected to the m2.b2 pin, and the other end of the line C is connected to the m5.a5 pin. The line A is arranged on the third horizontal track, the line B is arranged on the fourth vertical track, and the line C is arranged on the fifth horizontal track.

[0047] It should be noted that the two pins in the pin pair may be pins on the same chip or pins on different chips, which is not specifically limited here and depends on the original wiring data obtained.

[0048] Step S120: If there are at least two overlapping routes in the target track, determine a route to be optimized from the overlapping routes, and the route where the route to be optimized is located is the first route.

[0049] There may be multiple routing lines in the target track. When the routing ranges of multiple routing lines overlap, the routing displayed by the schematic diagram of the original routing data will overlap. Figure 8 , which shows that the x2 line and the x3 line overlap on the third track. It is difficult for the staff to determine the pin pairs connected to the x2 line and the pin pairs connected to the x3 line, which leads to the suspension of subsequent work and brings great obstacles to the subsequent work.

[0050] To this end, if overlapping routing is detected in the target track, the overlapping routing needs to be adjusted to eliminate the overlap of the routing.

[0051] It should be noted that each routing line in the original routing data has the serial number of its horizontal track and the serial number of its vertical track, and the layout position of each routing line, that is, the routing range of each routing line, can be obtained through the original routing data.

[0052] Continuing with the above-mentioned embodiment, please refer to Figure 8 , the target track is the 3rd horizontal track, the x2 line includes three end-to-end routings, the routing of the x2 line on the target track is the first routing, that is, segment A1B1, spanning the 1st to 5th vertical tracks, and the routing range of the first routing can be expressed as (1.3->5.3). Similarly, the x3 line includes three end-to-end routings, the routing of the x3 line on the target track is the second routing, that is, segment A2B2, spanning the 3rd to 11th vertical tracks, and the routing range of the second routing can be expressed as (3.3->11.3). Based on the routing range of the first routing and the routing range of the second routing, it can be determined whether the two routings overlap.

[0053] Specifically, if there are at least two overlapping routes in the target track, two routes are selected from the overlapping routes as an overlapping route group, and the overlapping route group includes a first route and a second route. The overlapping range is determined according to the wiring range of the first route and the wiring range of the second route. If the overlapping range is the same as the wiring range of the first route or the same as the wiring range of the second route, the route whose wiring range is equal to the overlapping range is selected from the first route and the second route as the route to be optimized. Otherwise, one of the first route and the second route is arbitrarily selected as the route to be optimized. For details, please refer to the subsequent embodiments.

[0054] It should be noted that the original wiring data can indicate the data of each line in the schematic diagram, but when working, it is often necessary to intuitively display the schematic diagram in data form in the form of a diagram, so as to facilitate the subsequent etching of the circuit on the chip or laying it out on the circuit board. For this purpose, it is necessary to ensure the accuracy of the schematic wiring and avoid wiring overlap.

[0055] Step S130: adjusting the routing to be optimized to obtain a target routing, wherein the target routing does not overlap with other routings on the track where the target routing is located.

[0056] Since the routing line to be optimized overlaps with other routing lines in the target track, it is necessary to adjust the position to be optimized, and adjust the routing line to be optimized to obtain the target routing line, and the target routing line does not overlap with other routing lines on the track where it is located.

[0057] Continuing with the above-mentioned embodiment, if the overlapping range is the same as the routing range of the first routing line or the same as the routing range of the second routing line, the routing line to be optimized is translated to the alternative track to obtain the target routing line. If the overlapping range is not equal to the routing range of the first routing line and is not equal to the routing range of the second routing line, the target routing line can be obtained by shortening the routing line to be optimized or moving the routing line to be optimized. For details, please refer to the subsequent embodiments.

[0058] Step S140: determining a second circuit including the target routing line according to the first circuit and the target routing line, wherein the second circuit and the first circuit are connected to the same pair of pins.

[0059] According to the first circuit, the pin pair connected to the first circuit can be determined as the target pin pair, and the target pin pair includes a first pin and a second pin. The second circuit is determined according to the first pin, the second pin and the target routing, so that the two ends of the second circuit are respectively connected to the first pin and the second pin, and the second circuit includes the target routing, so that the position adjustment of the routing to be optimized does not change the pins connected to the circuit.

[0060] Step S150: determining that the routing lines in the second circuit that do not overlap with the first circuit are variable routing lines.

[0061] The routing lines in the first circuit and the second circuit are compared, and the routing lines in the second circuit that do not overlap with the routing lines in the first circuit are used as the changed routing lines.

[0062] Step S160: If each of the changed routing lines does not overlap with other routing lines in the track where it is located, the first routing line is replaced by the second routing line.

[0063] Determine whether each changed route overlaps with other routes in the track where it is located. If there is overlap, it means that when the overlap of the route to be optimized is eliminated, the overlap of other routes will be increased. In this case, the route to be optimized is readjusted or the second route is re-determined. If each of the changed routes does not overlap with other routes in the track where it is located, it means that when the overlap of the route to be optimized is eliminated, the overlap of other routes will not be increased. The first route is replaced by the second route.

[0064] It should be noted that there may be no less than three overlapping routings in the same track in the original wiring data. The method of the present application can be used to first eliminate one of the overlapping routings, and then the method of the present application can be used to eliminate the remaining overlapping routings in turn.

[0065] In addition, there may be overlapping routings in multiple tracks in the original wiring data. The method of the present application can be used to first eliminate the overlapping routings in one track, and then eliminate the overlapping routings in the remaining tracks in turn. For details, please refer to the subsequent embodiments.

[0066] The embodiment of the present application proposes a data processing method. First, each circuit corresponding to the schematic diagram is obtained, and a sub-segment of each circuit arranged on a single track is a routing, and different circuits are used to connect different pin pairs; if there are at least two overlapping routings in the target track, the routing to be optimized is determined from the overlapping routings, and the circuit where the routing to be optimized is located is the first routing; secondly, the routing to be optimized is adjusted to obtain the target routing, and the target routing does not overlap with other routings on the track where it is located; then, a second routing including the target routing is determined according to the first routing and the target routing, and the second routing is connected to the same pin pair as the first routing; finally, the routings in the second routing that do not overlap with the first routing are determined as variable routings; if each of the variable routings does not overlap with other routings in the track where it is located, the first routing is replaced by the second routing.

[0067] The present application obtains the target routing by adjusting the routing to be optimized, and the target routing does not overlap with other routings on the track where it is located. In order to ensure the connectivity between the routing and the pin pair, it is necessary to adjust the routing connected to the routing to be optimized, and obtain a second circuit including the target routing. The second routing has the same pin pair as the first routing, and the routing in the second routing that does not overlap with the first routing is a variable routing. When each variable routing does not overlap with other routings in the track where it is located, the first routing is replaced by the second routing. The present application can eliminate the overlap between the routing to be optimized and other routings, and ensure that no other overlapping routings are added, which can effectively reduce the number of overlapping routings and improve the accuracy of automatic routing of schematic diagrams. The automatic routing overlap processing algorithm of the present application can solve the problem of routing overlap.

[0068] See also Figure 2 , which shows a method flow chart of a data processing method provided by an embodiment of the present application, the method is applied to a controller of a schematic automatic wiring system, and the controller can execute the data processing method. The method specifically includes steps S210 to S2110.

[0069] Step S210: Acquire each circuit corresponding to the schematic diagram, wherein a sub-segment of each circuit arranged on a single track is a routing line, and different circuits are used to connect different pin pairs.

[0070] Among them, step S210 has been introduced in detail in the above embodiment and will not be repeated here.

[0071] Step S220: Determine whether there are at least two overlapping routes in the target track.

[0072] If there are no at least two overlapping routes in the target track, jump to step S280.

[0073] Step S230: If there are at least two overlapping routes in the target track, determine a route to be optimized from the overlapping routes, and the route where the route to be optimized is located is the first route.

[0074] Step S240: adjusting the routing to be optimized to obtain a target routing, wherein the target routing does not overlap with other routings on the track where the target routing is located.

[0075] Step S250: determining a second circuit including the target routing according to the first circuit and the target routing, wherein the second circuit and the first circuit are connected to the same pair of pins.

[0076] Step S260: determining that the routing lines in the second circuit that do not overlap with the first circuit are variable routing lines.

[0077] Step S270: If each of the changed lines does not overlap with other lines in the track where it is located, the first line is replaced by the second line.

[0078] Among them, step S230 and step S270 have been introduced in detail in the above embodiments and will not be repeated here.

[0079] It should be noted that a track scanning sequence is preset, and the track scanning sequence includes the sequence of all tracks corresponding to the schematic diagram. The above method can be performed on each track in turn based on the track scanning sequence.

[0080] Step S280: Determine whether there are overlapping routes in the target track.

[0081] After eliminating an overlapping routing on the target track, there may be overlapping routings on the target track that need to be eliminated. Therefore, it is necessary to determine whether there are overlapping routings in the target track.

[0082] If there are still overlapping routing lines in the target track, return to step S220 to continue eliminating the overlapping routing lines.

[0083] Step S290: If not, determine whether the track corresponding to the track scanning sequence is empty.

[0084] If the track corresponding to the track scanning order is empty, it means that the overlapping routing has been eliminated for all tracks in the schematic diagram. Otherwise, it means that the overlapping routing still needs to be eliminated.

[0085] Step S2100: If the track corresponding to the track scanning sequence is not empty, determine a target track according to the track scanning sequence, and return to execute each line corresponding to the schematic diagram and subsequent steps.

[0086] If the track corresponding to the track scanning sequence is not empty, it means that overlapping routing lines need to be eliminated, and the process returns to step S210.

[0087] Step S2110: If the track corresponding to the track scanning sequence is empty, the target wiring data is obtained.

[0088] If the track corresponding to the track scanning sequence is empty, it means that the overlapping routing of all tracks in the schematic diagram has been eliminated to obtain the target wiring data.

[0089] If there are no overlapping routings in the target track, it means that there are no overlapping routings in the current target track, and a new target track is determined according to the track scanning order, and then returns to step S220 to eliminate the overlapping routings in the target track until there are no overlapping routings in all tracks in the schematic diagram, and a schematic diagram without overlapping routings is obtained. The present application realizes automatic elimination of overlapping routings in the schematic diagram, thereby improving the accuracy of schematic diagram wiring.

[0090] Exemplarily, the schematic diagram corresponds to 54 tracks, including horizontal tracks and vertical tracks. The 54 tracks are set in a sequence, which is the track scanning sequence. The first track is first used as the target track based on the track scanning sequence, and the overlapping routing in the first track is eliminated. When it is detected that there are no overlapping routings in the first track, the second track is used as the target track, and the execution returns to obtain each line corresponding to the schematic diagram and subsequent steps. In this way, the overlapping routing in the 54 tracks can be eliminated. It can be achieved to eliminate all overlapping routings in the schematic diagram and obtain the target wiring data, ensuring that the target wiring data can clearly and correctly represent the connection relationship of the pins, and the staff can quickly and accurately obtain the wiring data of the schematic diagram.

[0091] It should be noted that the method of the present application can be a part of the steps of automatic wiring of a schematic diagram. When the original wiring data is obtained after the schematic diagram is automatically wired, the original wiring data is processed using the method of the present application to obtain target wiring data without wiring overlap. The staff can clearly understand the wiring situation of the schematic diagram through the target wiring data.

[0092] See also Figure 3 , which shows a method flow chart of a data processing method provided by an embodiment of the present application, the method is applied to a controller of a schematic automatic wiring system, and the controller can execute the data processing method. The method specifically includes steps S310 to S380.

[0093] Step S310: Acquire each circuit corresponding to the schematic diagram, wherein a sub-segment of each circuit arranged on a single track is a routing line, and different circuits are used to connect different pin pairs.

[0094] Among them, step S310 has been introduced in detail in the above embodiment and will not be repeated here.

[0095] Step S320: If there are at least two overlapping routing lines in the target track, select the two overlapping routing lines as an overlapping routing line group, where the overlapping routing line group includes a first routing line and a second routing line.

[0096] If at least two overlapping routes exist in the target track, two routes are selected from the overlapping routes as an overlapping route group, the overlapping route group includes a first route and a second route, and one route is selected from the first route and the second route for adjustment to eliminate the overlap of the routes.

[0097] Step S330: determining an overlapping range according to a routing range of the first routing line and a routing range of the second routing line.

[0098] The overlap range can be determined based on the routing range of the two traces. Figure 8 , the target track is the 3rd horizontal track, the x2 line includes three lines connected end to end, the line of the x2 line laid on the target track is the first line, that is, line segment A1B2, spanning the 1st to 11th vertical tracks, and the routing range of the first line can be expressed as (1.3->11.3). Similarly, the x3 line includes three lines connected end to end, the line of the x3 line laid on the target track is the second line, that is, line segment A2B1, spanning the 3rd to 5th vertical tracks, and the routing range of the second line can be expressed as (3.3->5.3). According to the routing range of the first line and the routing range of the second line, the overlapping range can be determined to be (3.3->5.3).

[0099] Step S340: If the overlapping range is equal to the routing range of the first routing line or the routing range of the second routing line, select a routing line having a routing range equal to the overlapping range from the first routing line and the second routing line as a routing line to be optimized.

[0100] Continuing with the above-mentioned embodiment, the routing of the x2 line arranged on the target track is the first routing, and the routing range of the first routing is expressed as (1.3->11.3); the routing of the x3 line arranged on the target track is the second routing, and the routing range of the second routing is expressed as (3.3->5.3), and the overlapping range is (3.3->5.3). It can be known that the overlapping range is equal to the routing range of the second routing, and the second routing is used as the routing to be optimized.

[0101] Further, if the overlapping range is not equal to the routing range of the first routing line and is not equal to the routing range of the second routing line, one of the first routing line and the second routing line is arbitrarily selected as the routing line to be optimized.

[0102] For example, see Figure 8 , the target track is the 3rd horizontal track, the x2 line includes three end-to-end routings, the routing of the x2 line on the target track is the first routing, namely, segment A1B1, spanning the 1st to 5th vertical tracks, and the routing range of the first routing can be expressed as (1.3->5.3). Similarly, the x3 line includes three end-to-end routings, the routing of the x3 line on the target track is the second routing, namely, segment A2B21, spanning the 3rd to 11th vertical tracks, and the routing range of the second routing can be expressed as (3.3->11.3). According to the routing range of the first routing and the routing range of the second routing, the overlapping range can be determined to be (3.3->5.3). It can be seen that the overlapping range is not equal to the routing range of the first routing and is not equal to the routing range of the second routing, so any one of the first routing and the second routing is selected as the routing to be optimized.

[0103] Step S350: adjusting the routing to be optimized to obtain a target routing, wherein the target routing does not overlap with other routings on the track where the target routing is located.

[0104] Step S360: determining a second circuit including the target routing according to the first circuit and the target routing, wherein the second circuit and the first circuit are connected to the same pair of pins.

[0105] Step S370: Determine that a routing line in the second circuit that does not overlap with the first circuit is a variable routing line.

[0106] Step S380: If each of the changed lines does not overlap with other lines in the track where it is located, the first line is replaced by the second line.

[0107] Among them, step S350 and step S380 have been introduced in detail in the above embodiments and will not be repeated here.

[0108] See also Figure 4 , which shows a method flow chart of a data processing method provided by an embodiment of the present application, the method is applied to a controller of a schematic automatic wiring system, and the controller can execute the data processing method. The method specifically includes steps S410 to S4110.

[0109] Step S410: Acquire each circuit corresponding to the schematic diagram, wherein a sub-segment of each circuit arranged on a single track is a routing line, and different circuits are used to connect different pin pairs.

[0110] Step S420: If there are at least two overlapping routing lines in the target track, select the two overlapping routing lines as an overlapping routing line group, where the overlapping routing line group includes a first routing line and a second routing line.

[0111] Step S430: determining an overlapping range according to a routing range of the first routing line and a routing range of the second routing line.

[0112] Step S440: If the overlapping range is equal to the routing range of the first routing line or the routing range of the second routing line, select routing lines whose routing range is equal to the overlapping range from the first routing line and the second routing line as routing lines to be optimized.

[0113] Among them, step S410 and step S440 have been introduced in detail in the above embodiments and will not be repeated here.

[0114] Step S450: creating a new candidate track parallel to the target track.

[0115] It should be noted that the candidate tracks do not overlap with the tracks in the original wiring data.

[0116] Step S460: Determine a first inflection point, a second inflection point, a first associated inflection point and a second associated inflection point based on the route to be optimized and the first route, wherein the first associated inflection point is a inflection point on the first route that is adjacent to the first inflection point and is not the second inflection point, and the second associated inflection point is a inflection point on the first route that is adjacent to the second inflection point and is not the first inflection point.

[0117] The first inflection point, the second inflection point, the first associated inflection point and the second associated inflection point can be determined according to the routing line to be optimized and the first line. The inflection point is the connection point of two vertical routing lines and is also the overlapping point of the two routing lines.

[0118] Step S470: synchronously translate the first inflection point and the second inflection point to the candidate track in a direction perpendicular to the alignment to be optimized, to obtain a temporary first inflection point and a temporary second inflection point respectively.

[0119] The first inflection point and the second inflection point are synchronously translated to the candidate track in a direction perpendicular to the route to be optimized to obtain a temporary first inflection point and a temporary second inflection point. It should be noted that when the position of the inflection point changes, the route connected to the inflection point will also move accordingly.

[0120] Step S480: Determine a routing line whose two ends connect the temporary first inflection point and the temporary second inflection point as a target routing line.

[0121] The route connecting the temporary first turning point and the temporary second turning point at both ends is determined as the target route. Since the alternative track is a newly built track, there is no other route on the alternative track except the target route, which can ensure that the target route does not overlap with other routes on the track where it is located.

[0122] Step S490: determining a second circuit including the target routing according to the first circuit and the target routing, wherein the second circuit and the first circuit are connected to the same pair of pins.

[0123] Step S4100: Determine that a routing line in the second circuit that does not overlap with the first circuit is a variable routing line.

[0124] Step S4110: If each of the changed routing lines does not overlap with other routing lines in the track where it is located, the first routing line is replaced by the second routing line.

[0125] Among them, step S490 and step S4110 have been introduced in detail in the above embodiments and will not be repeated here.

[0126] Furthermore, the change routing includes a temporary optimized routing, a first associated routing and a second associated routing, wherein the first associated routing is a routing connecting the first associated turning point and the temporary first turning point at both ends, and the second associated routing is a routing connecting the second associated turning point and the temporary second turning point at both ends. If each of the change routings does not overlap with other routings in the track where it is located, the first route is replaced by the second route.

[0127] It should be noted that the line where the routing to be optimized is located is the first line, but the routing to be optimized overlaps with other routings on the track where it is located. For this reason, it is necessary to adjust the routing to be optimized to eliminate the overlap. Then, the present application adjusts the routing to be optimized to the alternative track to obtain the target routing. The routing connected to the routing to be optimized also needs to be adjusted accordingly to maintain connectivity with the target routing to obtain the second line. The second line has the same pin pair connected to the first line, but the first line and the second line do not completely overlap. At this time, it is necessary to determine that the routing on the second line that does not overlap with the first line is a variable routing. The variable routing is a routing that has changed relative to the first routing. The variable routing includes the target routing, and also includes the first associated routing and the second associated routing. The routing to be optimized is adjusted to the target routing to eliminate its overlap. The first associated routing overlaps with the second associated routing and other routings on the track where they are located, which means that although the second line eliminates the overlap of the routing to be optimized relative to the first line, it adds additional overlapping routings, which indicates that the second line is unqualified and needs to be re-determined. If the first associated routing and the second associated routing do not overlap with other routings on the track where they are located, it means that the second route not only eliminates the overlap of the routings to be optimized, but also does not add any additional overlapping routings compared to the first route. This indicates that the second route is qualified and the first route is replaced by the second route.

[0128] For example, see Figure 8 , the route of x2 line on the target track is the first route A1B2, the routing range of the first route is expressed as (1.3->11.3), the route of x3 line on the target track is the second route A2B1, the routing range of the second route is expressed as (3.3->5.3), the overlapping range is (3.3->5.3), and the second route A2B1 is used as the route to be optimized. According to the second route A2B1 and the x3 line, the first turning point is determined to be A2, the second turning point is determined to be B1, the first associated turning point is determined to be C1, and the second associated turning point is determined to be C2. The first turning point C1 and the second turning point C2 are simultaneously translated to the alternative track in a direction perpendicular to the route. After moving, please refer to Fig. 9, and obtain the temporary first turning point A22 and the temporary second turning point B11 respectively. The line connecting the temporary first turning point A22 and the temporary second turning point B11 at both ends is determined as the target line, the line connecting the first associated turning point C1 and the temporary first turning point A22 at both ends is used as the first associated line, and the line connecting the second associated turning point C2 and the temporary second turning point B11 at both ends is used as the second associated line, and the second line is obtained as x4, that is, the x3 line is changed into the x4 line. The pin pairs connected to the x3 line and the x4 line are the same, and the changed lines on the x4 line can be determined through the x3 line and the x4 line. The changed lines include the target line, the first associated line and the second associated line. It can be known that each of the changed lines does not overlap with other lines in the track where it is located. Replacing the x3 line with the x4 line can reduce an overlapping line on the third horizontal track.

[0129] See also Figure 5 , which shows a method flow chart of a data processing method provided by an embodiment of the present application, the method is applied to a controller of a schematic automatic wiring system, and the controller can execute the data processing method. The method specifically includes steps S510 to S5100.

[0130] Step S510: Acquire each circuit corresponding to the schematic diagram, wherein a sub-segment of each circuit arranged on a single track is a routing line, and different circuits are used to connect different pin pairs.

[0131] Step S520: If there are at least two overlapping routing lines in the target track, select the two overlapping routing lines as an overlapping routing line group, where the overlapping routing line group includes a first routing line and a second routing line.

[0132] Step S530: adjusting the routing to be optimized to obtain a target routing, wherein the target routing does not overlap with other routings on the track where the target routing is located.

[0133] Step S540: If the overlapping range is not equal to the routing range of the first routing line and is not equal to the routing range of the second routing line, then arbitrarily select one of the first routing line and the second routing line as the routing line to be optimized.

[0134] Among them, step S510 to step S540 have been introduced in detail in the above embodiments and will not be repeated here.

[0135] Step S550: Determine a third inflection point, a fourth inflection point, a third associated inflection point and a first node based on the route to be optimized and the first route, wherein the third inflection point is an end point of the route to be optimized and is located within the overlapping range, the fourth inflection point is the other end point of the route to be optimized, the third associated inflection point is an inflection point on the first route that is adjacent to the third inflection point and is not the fourth inflection point, and the third associated inflection point overlaps with the first node.

[0136] A third inflection point, a fourth inflection point, a third associated inflection point, a fourth associated inflection point and a first node are determined according to the route to be optimized and the first route, wherein the third associated inflection point overlaps with the first node.

[0137] Step S560: Synchronously move the third turning point and the third associated turning point along a preset direction and a preset distance to obtain a temporary third turning point and a temporary third associated turning point, wherein the preset direction is the direction from the third turning point to the fourth turning point, and the preset distance is greater than the length of the overlapping routing and less than the length of the routing to be optimized, and the overlapping routing is the overlapping line segments in the overlapping routing group.

[0138] The third inflection point and the third associated inflection point are synchronously moved along a preset direction by a preset distance to obtain a temporary third inflection point and a temporary third associated inflection point.

[0139] Preferably, the preset distance may be a distance obtained by adding an integral multiple of a standard distance to the length of the overlapping trace, and the standard distance is the minimum distance that can be moved.

[0140] Step S570: taking a routing line whose two ends connect the temporary third inflection point and the fourth inflection point as a target routing line.

[0141] The line connecting the temporary third turning point and the fourth turning point at both ends is used as the target line.

[0142] Step S580: determining a second circuit including the target routing according to the first circuit and the target routing, wherein the second circuit and the first circuit are connected to the same pair of pins.

[0143] Step S590: Determine that a routing line in the second circuit that does not overlap with the first circuit is a variable routing line.

[0144] Step S5100: If each of the changed routing lines does not overlap with other routing lines in the track where it is located, the first routing line is replaced by the second routing line.

[0145] Among them, step S580 and step S5100 have been introduced in detail in the above embodiments and will not be repeated here.

[0146] Furthermore, the change route includes a target route, a third associated route and a fourth associated route, wherein the third associated route is a route connecting the first node and the temporary third associated inflection point at both ends, and the fourth associated route is a route connecting the temporary third inflection point and the temporary third associated inflection point at both ends. If each of the change routes does not overlap with other routes in the track where it is located, the first route is replaced by the second route, otherwise the second route is re-determined.

[0147] For example, see Figure 8 , the route of the x2 line on the target track is the first route A1B1, and the routing range of the first route is expressed as (1.3->5.3), the route of the x3 line on the target track is the second route A2B2, and the routing range of the second route is expressed as (3.3->11.3), and the overlapping range is (3.3->5.3). The second route A2B2 is used as the route to be optimized. According to the second route A2B2 and the x3 line, the third inflection point is determined to be A2, the fourth inflection point is determined to be B2, the third associated inflection point is determined to be C1 and the first node C3, and the third associated inflection point overlaps with the first node, and the third inflection point A2 and the third associated inflection point C1 are simultaneously moved along the preset direction H by a preset distance. After moving, please refer to Fig.10 , respectively obtain the temporary third inflection point and A23 temporary third associated inflection point C12, take the line connecting the temporary third inflection point A23 and the fourth inflection point B2 at both ends as the target line, take the line connecting the first node C3 and the temporary third associated inflection point C12 at both ends as the third associated line, take the line connecting the temporary third inflection point A23 and the temporary third associated inflection point C12 at both ends as the fourth associated line. Get the second line x5, that is, the x3 line is changed to the x5 line, the pin pairs connected to the x3 line and the x5 line are the same, and the changed line on the x5 line can be determined by the x3 line and the x5 line. The changed line includes the target line, the first associated line and the second associated line. It can be known that each of the changed lines does not overlap with other lines in the track where it is located. Replacing the x3 line with the x5 line can reduce an overlapping line on the third horizontal track.

[0148] See also Figure 6 , which shows a method flow chart of a data processing method provided by an embodiment of the present application, the method is applied to a controller of a schematic automatic wiring system, and the controller can execute the data processing method. The method specifically includes steps S610 to S6120.

[0149] Step S610: Acquire each circuit corresponding to the schematic diagram, wherein a sub-segment of each circuit arranged on a single track is a routing line, and different circuits are used to connect different pin pairs.

[0150] Step S620: If there are at least two overlapping routing lines in the target track, select the two overlapping routing lines as an overlapping routing line group, where the overlapping routing line group includes a first routing line and a second routing line.

[0151] Step S630: adjusting the routing to be optimized to obtain a target routing, wherein the target routing does not overlap with other routings on the track where the target routing is located.

[0152] Step S640: If the overlapping range is not equal to the routing range of the first routing line and is not equal to the routing range of the second routing line, then arbitrarily select one of the first routing line and the second routing line as the routing line to be optimized.

[0153] Step S650: Determine a third inflection point, a fourth inflection point, a third associated inflection point and a first node based on the route to be optimized and the first route, wherein the third inflection point is an end point of the route to be optimized and is located within the overlapping range, the fourth inflection point is the other end point of the route to be optimized, the third associated inflection point is an inflection point on the first route that is adjacent to the third inflection point and is not the fourth inflection point, and the third associated inflection point overlaps with the first node.

[0154] Among them, step S610 to step S650 have been introduced in detail in the above embodiments and will not be repeated here.

[0155] Step S660: Create a new candidate track parallel to the target track.

[0156] A new candidate track is created that is parallel to the target track, and the candidate track does not overlap with the track in the original routing data.

[0157] Step S670: Create a second node and a third node that overlap with each other on the routing line between the third inflection point and the fourth inflection point, wherein the distance between the third inflection point and the second node is greater than the length of the overlapping routing line and less than the length of the routing line to be optimized, and the overlapping routing line is an overlapping line segment in the overlapping routing group.

[0158] A second node and a third node that overlap with each other are newly created on the routing line between the third inflection point and the fourth inflection point, and the distance between the third inflection point and the second node is greater than the length of the overlapping routing line and less than the length of the routing line to be optimized. The overlapping routing line is an overlapping line segment in the overlapping routing group.

[0159] Step S680: synchronously translate the third inflection point and the second node to the alternative track in a direction perpendicular to the alignment to be optimized, to obtain a temporary third inflection point and a temporary fifth inflection point respectively.

[0160] The third inflection point and the second node are synchronously translated to the alternative track in a direction perpendicular to the alignment to be optimized to obtain a temporary third inflection point and a fifth inflection point.

[0161] Step S690: taking a route whose two ends connect the temporary third inflection point and the fifth inflection point as a target route.

[0162] It can be known that, since the alternative track is a newly built track, the target route on the alternative track does not overlap with other routes on the track where it is located.

[0163] Step S6100: Determine a second circuit including the target routing according to the first circuit and the target routing, wherein the second circuit and the first circuit are connected to the same pair of pins.

[0164] Step S6110: Determine that a routing line in the second circuit that does not overlap with the first circuit is a variable routing line.

[0165] Step S6120: If each of the changed routes does not overlap with other routes in the track where it is located, the first route is replaced by the second route.

[0166] Among them, step S6100 and step S6120 have been introduced in detail in the above embodiments and will not be repeated here.

[0167] Furthermore, the change route includes a target route, a third associated route and a fourth associated route, wherein the third associated route is a route whose two ends connect the third associated inflection point and the temporary third inflection point, and the fourth associated route is a route whose two ends connect the fifth inflection point and the third node. If each of the change routes does not overlap with other routes in the track where it is located, the first route is replaced by the second route, otherwise the second route is re-determined.

[0168] For example, see Fig.11 , the route of x2 line on the target track is the first route A1B1, the route of x3 line on the target track is the second route A2B2, and the second route A2B2 is used as the route to be optimized. According to the second route A2B2 and the x3 line, the third inflection point is determined to be A2, the fourth inflection point is determined to be B2, and the third associated inflection point is determined to be C1. A new candidate track is created, and a second node C4 and a third node C5 that overlap with each other are created on the route between the third inflection point A2 and the fourth inflection point B2. The third inflection point A2 and the second node C4 are simultaneously translated to the candidate track in a direction perpendicular to the route to be optimized. Please refer to the following after the movement. Fig.12, respectively obtain the temporary third inflection point A24 and the fifth inflection point C41; take the line connecting the third associated inflection point C1 and the temporary third inflection point A24 at both ends as the third associated line, and take the line connecting the fifth inflection point C41 and the third node C5 at both ends as the fourth associated line. Obtain the second line x6, that is, the x3 line is changed into the x6 line. The pin pairs connected to the x3 line and the x6 line are the same. The changed lines on the x6 line can be determined through the x3 line and the x6 line. The changed lines include the target line, the third associated line and the fourth associated line. It can be known that each of the changed lines does not overlap with other lines in the track where it is located. Replacing the x3 line with the x6 line can reduce an overlapping line on the third horizontal track.

[0169] An exemplary automatic routing overlap processing algorithm step in a horizontal channel may be implemented as follows.

[0170] Step 1: Let the horizontal channel wiring width be (w1, w2), the track sequence from low to high in the channel be T[], and the track range of the track Rij(j>=1) with the routing sequence Ri[] in track Ti(i>=1) can be expressed as (Cij_xmin, Cij_xmax). Let i=0, timax be the number of tracks, rimax be the number of routings in the track, and go to step 2.

[0171] Step 2: Set i = i + 1. If i > timax, go to step 8. Otherwise, set j = 0 and go to step 3.

[0172] Step 3: Set j = j + 1. If j > rimax, go to step 2. Otherwise, set k = j and go to step 4.

[0173] Step 4: Let k = k + 1. If k > rimax, go to step 3. Otherwise, go to step 5.

[0174] Step 5: Let the routing range of Rij be (Cij_min, Cij_max), and the routing range of Rik be (Cik_min, Cik_max). Determine whether Rij and Rik overlap, if not, go to step 4. Let the obtained overlapping range be (o_min, o_max), let the current track coordinate be Tic, if (o_min, o_max) == (Cij_min, Cij_max) or (Cik_min, Cik_max), then it is included overlap, go to step 6 for processing. Otherwise, it is cross overlap, go to step 7 for processing.

[0175] Step 6: Include overlapping type processing.

[0176] (1) Create a new track: Let z = i + 1. If Tz exists in T[] and its coordinates are Tzc, then create a new track T with coordinates (Tic + Tzc) / 2, add the track to T[], number it as i + 1, and timax = timax + 1.

[0177] (2) Move the inflection point coordinates: Let the included line be Riz, and its inflection point on track Ti be J1(o_min, Tic), J1(o_max, Tic). Move the inflection point to J1(o_min, (Tic+Tzc) / 2), J1(o_max, (Tic+Tzc) / 2).

[0178] (3) Go to step 4.

[0179] Step 7: Cross-overlapping type processing.

[0180] Let the inflection points be J1(Cij_min, Tic) and J2(Cij_max, Tic) respectively. Let the standard line spacing be Dx.

[0181] (1) Move the inflection point to the right: Determine whether moving the inflection point J1 (Cij_min, Tic) to (Cij_max+Dx, Tic) will cause the line to overlap on another track. If not, move the inflection point J1 (Cij_min, Tic) to (Cij_max+Dx, Tic) and go to step 4.

[0182] (2) Move the inflection point to the left: Determine whether moving the inflection point J2 (Cij_max, Tic) to (Cij_min-Dx, Tic) will cause the line to overlap on another track. If not, move the inflection point J2 (Cij_max, Tic) to (Cij_min-Dx, Tic) and go to step 4.

[0183] (3) Create a new inflection point to resolve the conflict: Taking the left shift as an example, move the inflection point J2 (Cij_max, Tic) to Cij_min-Dx, Tic). Let z = i + 1. If Tz exists in T[] and its coordinates are Tzc, then create a new track T, and its track coordinates are (Tic + Tzc) / 2. Add the track to T[] and number it as i + 1, timax = timax + 1. Create new inflection points J3 (Cij_min-Dx, (Tic + Tzc) / 2) and J4 (Cij_max, (Tic + Tzc) / 2) on the line to which J2 belongs. Go to step 4.

[0184] Step 8: End.

[0185] See also Fig.13, which shows a structural block diagram of a controller 600 provided in an embodiment of the present application. The test device 600 includes: an acquisition unit 610, a judgment unit 620, an adjustment unit 630, a determination unit 640, a comparison unit 650 and a replacement unit 660.

[0186] The acquisition unit 610 is used to acquire each circuit corresponding to the schematic diagram, wherein a sub-segment of each circuit arranged on a single track is a routing line, and different circuits are used to connect different pin pairs.

[0187] The judgment unit 620 is configured to determine a route to be optimized from the overlapping routes if at least two routes overlap in the target track, wherein the route to be optimized is the first route.

[0188] Furthermore, the judgment unit 620 can also be used to select two overlapping routes as an overlapping route group if there are at least two overlapping routes in the target track, and the overlapping route group includes a first route and a second route; determine the overlapping range according to the wiring range of the first route and the wiring range of the second route; if the overlapping range is equal to the wiring range of the first route or the wiring range of the second route, select the route whose wiring range is equal to the overlapping range from the first route and the second route as the route to be optimized.

[0189] Furthermore, the judgment unit 620 can also be used to select two overlapping routes as an overlapping route group if there are at least two overlapping routes in the target track, and the overlapping route group includes a first route and a second route; determine the overlapping range according to the wiring range of the first route and the wiring range of the second route; if the overlapping range is not equal to the wiring range of the first route and is not equal to the wiring range of the second route, then arbitrarily select one route from the first route and the second route as the route to be optimized.

[0190] The adjustment unit 630 is used to adjust the routing to be optimized to obtain a target routing, where the target routing does not overlap with other routings on the track where it is located.

[0191] Furthermore, the adjustment unit 630 can also be used to create a new alternative track parallel to the target track; determine the first inflection point, the second inflection point, the first associated inflection point and the second associated inflection point according to the route to be optimized and the first route, the first associated inflection point being a inflection point on the first route that is adjacent to the first inflection point and is not the second inflection point, and the second associated inflection point being a inflection point on the first route that is adjacent to the second inflection point and is not the first inflection point; synchronously translate the first inflection point and the second inflection point along a direction perpendicular to the route to be optimized to the alternative track to obtain a temporary first inflection point and a temporary second inflection point, respectively; and determine the route connecting the temporary first inflection point and the temporary second inflection point at both ends as the target route.

[0192] Furthermore, the adjustment unit 630 can also be used to determine a third inflection point, a fourth inflection point, a third associated inflection point and a first node based on the route to be optimized and the first line, the third inflection point being one end point of the route to be optimized and being located within the overlapping range, the fourth inflection point being the other end point of the route to be optimized, the third associated inflection point being an inflection point on the first line that is adjacent to the third inflection point and is not the fourth inflection point, and the third associated inflection point overlaps with the first node; synchronously moving the third inflection point and the third associated inflection point along a preset direction by a preset distance to obtain a temporary third inflection point and a temporary third associated inflection point, the preset direction being the direction from the third inflection point to the fourth inflection point, the preset distance being greater than the length of the overlapping route and less than the length of the route to be optimized, and the overlapping route being the overlapping line segments in the overlapping route group; and taking the route connecting the temporary third inflection point and the fourth inflection point at both ends as the target route.

[0193] Furthermore, the adjustment unit 630 can also be used to create a new alternative track parallel to the target track; create a new second node and a third node that overlap with each other on the route between the third inflection point and the fourth inflection point, the distance between the third inflection point and the second node is greater than the length of the overlapping route and less than the length of the route to be optimized, and the overlapping route is the overlapping line segment in the overlapping route group; synchronously translate the third inflection point and the second node along a direction perpendicular to the route to be optimized to the alternative track, and obtain a temporary third inflection point and a fifth inflection point respectively; and use the route connecting the temporary third inflection point and the fifth inflection point at both ends as the target route.

[0194] The determining unit 640 is configured to determine a second circuit including the target routing line according to the first circuit and the target routing line, wherein the second circuit and the first circuit are connected to the same pair of pins.

[0195] The comparison unit 650 is used to determine that the routing lines in the second circuit that do not overlap with the first circuit are variable routing lines.

[0196] Furthermore, the changed routing in the comparison unit 650 includes a target routing, a first associated routing and a second associated routing, the first associated routing being a routing connecting the first associated inflection point and the temporary first inflection point at both ends, and the second associated routing being a routing connecting the second associated inflection point and the temporary second inflection point at both ends.

[0197] Furthermore, the replacement unit 660 may also be configured to determine a target track according to the track scanning sequence, and return to execute each line corresponding to the acquisition schematic and subsequent steps until the track corresponding to the track scanning sequence is read to be empty.

[0198] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and modules can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0199] In several embodiments provided in the present application, the coupling between modules may be electrical, mechanical or other forms of coupling.

[0200] In addition, each functional module in each embodiment of the present application can be integrated into a processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or software functional modules.

[0201] Please refer to Fig.14 , which shows a structural block diagram of an electronic device 700 provided in an embodiment of the present application. The electronic device 700 may be a vehicle system, which may be arranged in a vehicle. The electronic device 700 in the present application may include one or more of the following components: a processor 711, a memory 712, and one or more application programs, wherein the processor 711 is electrically connected to the memory 712, and the one or more program configurations are used to execute the methods described in the various embodiments of the aforementioned test method.

[0202] The processor 711 may include one or more processing cores. The processor 711 uses various interfaces and lines to connect various parts of the entire electronic device 700, and executes various functions and processes data of the electronic device 700 by running or executing instructions, programs, code sets or instruction sets stored in the memory 712, and calling data stored in the memory 712. Optionally, the processor 711 can be implemented in at least one hardware form of digital signal processing (Digital Signal Processing, DSP), field programmable gate array (Field-Programmable Gate Array, FPGA), and programmable logic array (Programmable Logic Array, PLA). The processor 711 can integrate one or more combinations of a central processing unit (Central Processing Unit, CPU), a graphics processing unit (Graphics Processing Unit, GPU) and a modem. Among them, the CPU mainly processes the operating system, user interface and computer programs; the GPU is responsible for rendering and drawing display content; and the modem is used to process wireless communications. It can be understood that the above-mentioned modem may not be integrated into the processor 711, and it can be implemented separately through a communication chip. Specifically, the method described in the above embodiment can be executed by one or more processors 711.

[0203] For some embodiments, the memory 712 may include a random access memory (RAM) or a read-only memory (ROM). The memory 712 may be used to store instructions, programs, codes, code sets, or instruction sets. The memory 712 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for implementing at least one function, instructions for implementing the following various method embodiments, etc. The data storage area may also store data created by the electronic device 700 during use, etc.

[0204] Please refer to Fig.15 , which shows a structural block diagram of a computer-readable medium provided in an embodiment of the present application. The computer-readable medium 800 stores program codes, which can be called by a processor to execute the method described in the above method embodiment.

[0205] The computer readable medium 800 can be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read-only memory), an EPROM, a hard disk, or a ROM. Optionally, the computer readable medium 800 includes a non-transitory computer-readable storage medium. The computer readable medium 800 has storage space for program code 810 that performs any method steps in the above method. These program codes can be read from or written to one or more computer program products. The program code 810 can be compressed, for example, in an appropriate form.

[0206] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A data processing method, characterized in that: The method is applied to a controller of a schematic automatic wiring system, comprising: Obtain each circuit corresponding to the schematic diagram, wherein a sub-segment of each circuit arranged on a single track is a routing line, and different circuits are used to connect different pin pairs; If at least two routes overlap in the target track, determine a route to be optimized from the overlapping routes, where the route to be optimized is the first route; Adjusting the alignment to be optimized to obtain a target alignment, wherein the target alignment does not overlap with other alignments on the track where the target alignment is located; Determine a second circuit including the target routing according to the first circuit and the target routing, wherein the second circuit is connected to the same pair of pins as the first circuit; Determine that a routing line in the second circuit that does not overlap with the first circuit is a variable routing line; If each of the changed routing lines does not overlap with other routing lines in the track where it is located, the first routing line is replaced by the second routing line.

2. The method according to claim 1, characterized in that A track scanning sequence is preset, and the track scanning sequence includes the sequence of all tracks corresponding to the schematic diagram. If each of the changed routing lines does not overlap with other routing lines in the track where it is located, after replacing the first line with the second line, it also includes: Determining whether there are overlapping traces in the target track; If so, return to execute. If there are at least two overlapping routes in the target track, determine the route to be optimized from the overlapping routes and subsequent operations; If it does not exist, a target track is determined according to the track scanning sequence, and the process returns to execute each line corresponding to the acquisition schematic and subsequent steps until the track corresponding to the track scanning sequence is read to be empty.

3. The method according to claim 1, characterized in that If at least two routing lines overlap in the target track, determining a routing line to be optimized from the overlapping routing lines includes: If at least two overlapping routing lines exist in the target track, the two overlapping routing lines are selected as an overlapping routing line group, where the overlapping routing line group includes a first routing line and a second routing line; Determine an overlapping range according to a routing range of the first routing line and a routing range of the second routing line; If the overlapping range is equal to the routing range of the first routing line or the routing range of the second routing line, a routing line having a routing range equal to the overlapping range is selected from the first routing line and the second routing line as the routing line to be optimized.

4. The method according to claim 3, characterized in that The step of adjusting the routing to be optimized to obtain a target routing includes: Creating a new alternative track parallel to the target track; Determine a first inflection point, a second inflection point, a first associated inflection point, and a second associated inflection point according to the route to be optimized and the first route, wherein the first associated inflection point is an inflection point on the first route that is adjacent to the first inflection point and is not the second inflection point, and the second associated inflection point is an inflection point on the first route that is adjacent to the second inflection point and is not the first inflection point; Synchronously translating the first inflection point and the second inflection point to the candidate track in a direction perpendicular to the alignment to be optimized, to obtain a temporary first inflection point and a temporary second inflection point respectively; A routing line having two ends connecting the temporary first inflection point and the temporary second inflection point is determined as a target routing line.

5. The method according to claim 4, characterized in that The changed routing includes a target routing, a first associated routing and a second associated routing, wherein the first associated routing is a routing connecting the first associated inflection point and the temporary first inflection point at both ends, and the second associated routing is a routing connecting the second associated inflection point and the temporary second inflection point at both ends.

6. The method according to claim 1, characterized in that If at least two routing lines overlap in the target track, determining a routing line to be optimized from the overlapping routing lines includes: If at least two overlapping routing lines exist in the target track, the two overlapping routing lines are selected as an overlapping routing line group, where the overlapping routing line group includes a first routing line and a second routing line; Determine an overlapping range according to a routing range of the first routing line and a routing range of the second routing line; If the overlapping range is not equal to the routing range of the first routing line and is not equal to the routing range of the second routing line, one of the first routing line and the second routing line is arbitrarily selected as the routing line to be optimized.

7. The method according to claim 6, characterized in that The step of adjusting the routing to be optimized to obtain a target routing includes: Determine a third inflection point, a fourth inflection point, a third associated inflection point and a first node according to the routing line to be optimized and the first line, wherein the third inflection point is an end point of the routing line to be optimized and is located in the overlapping range, the fourth inflection point is the other end point of the routing line to be optimized, the third associated inflection point is an inflection point on the first line that is adjacent to the third inflection point and is not the fourth inflection point, and the third associated inflection point overlaps with the first node; Synchronously moving the third inflection point and the third associated inflection point by a preset distance in a preset direction to obtain a temporary third inflection point and a temporary third associated inflection point, wherein the preset direction is a direction from the third inflection point to the fourth inflection point, and the preset distance is greater than the length of the overlapping routing and less than the length of the routing to be optimized, and the overlapping routing is an overlapping line segment in the overlapping routing group; The routing line connecting the temporary third inflection point and the fourth inflection point at both ends is used as the target routing line.

8. The method according to claim 7, characterized in that The variable routing includes a third associated routing and a fourth associated routing. The third associated routing is a routing whose two ends connect the first node and the temporary third associated inflection point. The fourth associated routing is a routing whose two ends connect the temporary third inflection point and the temporary third associated inflection point.

9. The method according to claim 7, characterized in that: After determining the third inflection point, the fourth inflection point, the third associated inflection point and the first node according to the route to be optimized and the first route, the method further includes: Creating a new alternative track parallel to the target track; Create a second node and a third node that overlap with each other on the routing line between the third inflection point and the fourth inflection point, wherein the distance between the third inflection point and the second node is greater than the length of the overlapping routing line and less than the length of the routing line to be optimized, and the overlapping routing line is an overlapping line segment in the overlapping routing line group; Synchronously translating the third inflection point and the second node to the alternative track in a direction perpendicular to the alignment to be optimized, to obtain a temporary third inflection point and a temporary fifth inflection point respectively; The routing line connecting the temporary third inflection point and the fifth inflection point at both ends is used as the target routing line.

10. The method according to claim 9, characterized in that The changed routing includes a target routing, a third associated routing and a fourth associated routing, wherein the third associated routing is a routing whose two ends connect the third associated inflection point and the temporary third inflection point, and the fourth associated routing is a routing whose two ends connect the fifth inflection point and the third node.

11. A controller, characterized in that: The controller is applied to a schematic automatic wiring system, comprising: An acquisition unit, used for acquiring each circuit corresponding to the schematic diagram, wherein a sub-segment of each circuit arranged on a single track is a routing line, and different circuits are used for connecting different pin pairs; A judgment unit, configured to determine a to-be-optimized route from the overlapping routes if at least two routes overlap in the target track, wherein the route to be optimized is a first route; An adjustment unit, used for adjusting the alignment to be optimized to obtain a target alignment, wherein the target alignment does not overlap with other alignments on the track where the target alignment is located; A determining unit, configured to determine a second circuit including the target routing line according to the first circuit and the target routing line, wherein the second circuit and the first circuit are connected to the same pair of pins; A comparison unit, configured to determine that a line in the second line that does not overlap with the first line is a variable line; A replacement unit is used to replace the first line with the second line if each of the changed lines does not overlap with other lines in the track where it is located.

12. An electronic device, characterized in that: include: one or more processors; Memory; One or more applications, wherein the one or more applications are stored in the memory, the one or more applications are configured to be executed by the one or more processors, and the one or more applications are configured to execute the method according to any one of claims 1-10.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program codes, which can be called by a processor to execute the method according to any one of claims 1 to 10.

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