Erasure techniques using analog bit scanning in memory devices

Abstract

A memory device includes a plurality of memory cells arranged in a plurality of word lines. The plurality of word lines includes a selected group of word lines to be erased in an erase operation. The memory device also includes circuitry configured to erase the memory cells of the selected set of word lines in at least one erase cycle. The at least one erase cycle includes an erase pulse, an erase-verify operation, and an analog bit scan operation. The circuit is configured to determine an output of an analog bit scan operation, the output being one of at least three options. The circuit is further configured to control at least one erase parameter based on an output of the analog bit scan operation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 524,015, filed on June 29, 2023. The entire disclosure of the above-referenced application is incorporated herein by reference. Background Art 1. Technical Field

[0003] The present disclosure relates generally to the operation of non-volatile memory and, more particularly, to erase techniques to improve performance, reliability and / or endurance.

[0004] 2. Related technologies

[0005] Semiconductor memory is widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, servers, solid-state drives, non-mobile computing devices and other devices. Semiconductor memory can include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery).

[0006] NAND memory devices include a chip having multiple memory blocks, each of which includes an array of memory cells arranged in multiple word lines. Programming the memory cells of a word line to hold data typically occurs in multiple programming cycles, each of which includes applying a programming pulse to the control gate of the word line and optionally including a verification operation for sensing the threshold voltage of the memory cell being programmed. Each programming cycle may also include a precharge operation prior to the programming pulse to precharge multiple channels containing the memory cells to be programmed. Summary of the invention

[0007] One aspect of the present disclosure relates to a method for performing an erase operation in a memory device. The method includes the step of preparing a memory block, the memory block including a plurality of memory cells arranged in a plurality of word lines. The plurality of word lines include a selected group of word lines to be erased. The method proceeds with the step of erasing the memory cells of the selected group of word lines in at least one erase cycle. The at least one erase cycle includes an erase pulse, an erase-verify operation, and an analog bit scan operation. The method proceeds with the step of determining an output of the analog bit scan operation, the output being one of at least three options. The method proceeds with the step of controlling at least one erase parameter based on the output of the analog bit scan operation.

[0008] According to another aspect of the present disclosure, in response to the output of the analog bit scanning operation being the first output option, the method continues with the step of increasing the voltage of the erase pulse with the first step size. In response to the output of the analog bit scanning operation being the second output option, the method continues with the step of increasing the voltage of the erase pulse with a second step size different from the first step size.

[0009] According to yet another aspect of the present disclosure, in response to the output of the analog bit scanning operation being the third output option, the method continues with the step of ending the erase operation.

[0010] According to yet another aspect of the present disclosure, the first output option is strong fail; the second output option is weak fail or weak pass; and the third output option is strong pass.

[0011] According to another aspect of the present disclosure, the second step size is approximately half the first step size.

[0012] According to yet another aspect of the present disclosure, in response to the output of the analog bit scan operation being the first output option, the method continues with the step of increasing the voltage of the erase pulse by the first step size. In response to the output of the analog bit scan operation being the second output option, the method continues with the step of increasing the voltage of the erase pulse by a second step size different from the first step size and applying an additional erase pulse to the word lines of the selected group.

[0013] According to yet another aspect of the present disclosure, in response to the output of the analog bit scanning operation being the third output option, the method continues with the step of ending the erase operation.

[0014] According to another aspect of the present disclosure, the first output option is strong fail, the second output option is weak fail and the third output option is pass.

[0015] Another aspect of the present disclosure relates to a memory device, the memory device including a plurality of memory cells arranged in a plurality of word lines. The plurality of word lines include a selected group of word lines to be erased in an erase operation. The memory device also includes a circuit configured to erase the memory cells of the selected group of word lines in at least one erase cycle. At least one erase cycle includes an erase pulse, an erase-verify operation, and an analog bit scan operation. The circuit is configured to determine an output of the analog bit scan operation, the output being one of at least three options. The circuit is also configured to control at least one erase parameter based on the output of the analog bit scan operation.

[0016] According to another aspect of the present disclosure, in response to the output of the analog bit scanning operation being a first output option, the circuit is further configured to increase the voltage of the erase pulse with a first step size. In response to the output of the analog bit scanning operation being a second output option, the circuit is further configured to increase the voltage of the erase pulse with a second step size different from the first step size.

[0017] According to yet another aspect of the present disclosure, in response to the output of the analog bit scanning operation being a third output option, the circuit is configured to end the erase operation.

[0018] According to yet another aspect of the present disclosure, the first output option is strong fail; the second output option is weak fail or weak pass; and the third output option is strong pass.

[0019] According to another aspect of the present disclosure, the second step size is approximately half the first step size.

[0020] According to yet another aspect of the present disclosure, in response to the output of the analog bit scan operation being a first output option, the circuit is further configured to increase the voltage of the erase pulse by a first step size. In response to the output of the analog bit scan operation being a second output option, the circuit is further configured to increase the voltage of the erase pulse by a second step size different from the first step size and apply an additional erase pulse to the selected group of word lines.

[0021] According to yet another aspect of the present disclosure, in response to the output of the analog bit scanning operation being a third output option, the circuit is further configured to end the erase operation.

[0022] According to another aspect of the present disclosure, the first output option is strong fail, the second output option is weak fail and the third output option is pass.

[0023] Yet another aspect of the present disclosure relates to a device comprising a memory block having a plurality of memory cells arranged in a plurality of word lines. The plurality of word lines comprises a selected group of word lines to be erased in an erase operation. The device further comprises an erase device for erasing the memory cells of the selected group of word lines in at least one erase cycle. At least one erase cycle comprises an erase pulse, an erase-verify operation, and an analog bit scan operation. The erase device is configured to determine an output of the analog bit scan operation, the output being one of at least three options including a strong fail, a weak fail, and a pass. The erase device is further configured to: in response to the output of the analog bit scan operation being a strong fail, increase the voltage of the erase pulse by a first step size, and in response to the output of the analog bit scan operation being a weak fail, increase the voltage of the erase pulse by a second step size, the second step size being different from the first step size.

[0024] According to another aspect of the present disclosure, the at least three options for the output of the analog bit scan operation further include weak pass and strong pass.

[0025] According to yet another aspect of the present disclosure, the erasing device is further configured to: in response to the output of the analog bit scanning operation being a weak pass, increase the voltage of the erase pulse by a second step size, and in response to the output of the analog bit scanning operation being a strong pass, end the erase operation.

[0026] According to yet another aspect of the present disclosure, the erase apparatus is further configured to apply an additional erase pulse to the selected group of word lines in response to the output of the analog bit scan operation being a weak fail. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] A more detailed description is set forth below with reference to the exemplary embodiments depicted in the accompanying drawings. It is understood that these drawings depict only exemplary embodiments of the present disclosure and, therefore, should not be considered to limit the scope thereof. The present disclosure is described and explained with additional specificity and detail through the use of the accompanying drawings, in which:

[0028] Figure 1A is a block diagram of an exemplary memory device;

[0029] Figure 1B is a block diagram of an exemplary control circuit;

[0030] Figure 1C yes Figure 1A A block diagram of an exemplary programming circuit for a memory device of;

[0031] Figure 2 Depicted Figure 1A a block of memory cells in an exemplary two-dimensional configuration of a memory array;

[0032] Figure 3A and Figure 3B depicts a cross-sectional view of an exemplary floating gate memory cell in a NAND string;

[0033] Figure 4A and Figure 4B depicts a cross-sectional view of an exemplary charge trapping memory cell in a NAND string;

[0034] Figure 5 depicts an exemplary block diagram of the sensing block SB1 of FIG. 1 ;

[0035] Fig. 6A is a perspective view of a set of blocks in an exemplary three-dimensional configuration of the memory array of FIG. 1 ;

[0036] Figure 6B Depicted Fig. 6A An exemplary cross-sectional view of a portion of one of the blocks;

[0037] Figure 6C Depicted Figure 6B A graph of memory hole diameters in a stack of;

[0038] Fig.6D Depicted Figure 6B A close up view of region 622 of the stack;

[0039] Fig. 7A Depicted Figure 6B A top view of an exemplary word line layer WL0 of the stack;

[0040] Figure 7B Depicted Figure 6B A top view of an exemplary top dielectric layer DL116 of the stack;

[0041] Figure 8 depicts a threshold voltage distribution for a page of memory cells programmed to one bit per memory cell (SLC);

[0042] Fig. 9 depicts a threshold voltage distribution for a page of memory cells programmed to three bits per memory cell (TLC);

[0043] Fig.10 depicts exemplary voltage waveforms applied to a selected word line during programming of memory cells of the selected word line;

[0044] Fig.11 is a table containing analog bit scan output options and corresponding busy time calculations resulting in different options according to an embodiment of the present disclosure;

[0045] Fig.12 is a graph of busy time, an oscillator, and a corresponding clock counter according to an exemplary embodiment;

[0046] Fig.13 is a table containing analog bit scan output options and corresponding parameters resulting in different options according to an embodiment of the present disclosure;

[0047] Fig.14 is a table containing analog bit scan output options and corresponding parameters resulting in different options according to another embodiment of the present disclosure;

[0048] Fig.15 is a table containing analog bit scan output options and corresponding parameters resulting in different options according to yet another embodiment of the present disclosure;

[0049] Fig.16 is a table containing analog bit scan output options and corresponding parameters resulting in different options according to yet another embodiment of the present disclosure;

[0050] Fig.17 is a flow chart comprising steps for performing an exemplary embodiment of an analog bit scan operation;

[0051] Fig.18 is a flow chart comprising steps for performing another exemplary embodiment of an analog bit scan operation;

[0052] Fig.19 is a flow chart comprising steps for performing yet another exemplary embodiment of an analog bit scan operation;

[0053] Fig. 20 is a graph of erase upper tail versus program and erase cycles during the operating life of a memory block for an example;

[0054] Fig.21 It is for Fig. 20 A graph of erase cycles versus program and erase cycles during the operating life of a memory block for the same example;

[0055] Fig. 22 is a flow chart including steps for performing an erase operation including an analog bit scan operation;

[0056] Fig.23A is a threshold voltage distribution graph showing conditions that will produce a strong fail output of an analog bit scan operation;

[0057] Fig. 23B is a threshold voltage distribution graph showing conditions that will produce a weak fail output of an analog bit scan operation;

[0058] Fig.23C is a threshold voltage distribution diagram showing conditions that will produce a pass output of an analog bit scan operation;

[0059] Fig.24 is a flow chart including steps for performing an erase operation including an analog bit scan operation;

[0060] Fig.25 is a graph of erase upper tail versus program and erase cycles during the operating life of a memory block when utilizing an analog bit scan technique;

[0061] Fig.26 is a graph of threshold voltage distributions of a plurality of memory cells after a plurality of programming pulses according to an example;

[0062] Fig. 27 It shows that according to the Fig.26 Examples of results of which data states are verified in which programming cycles;

[0063] Fig.28 is a flowchart including steps for performing a programming operation including an analog bit scan operation according to an exemplary embodiment of the present disclosure;

[0064] Fig.29 is a graph depicting programming pulses and verify pulses during and immediately after an exemplary smart verify operation;

[0065] Fig.30 is a flow chart including steps for performing a smart verification operation including an analog bit scan operation according to an exemplary embodiment of the present disclosure;

[0066] Fig.31A is a threshold voltage distribution of a plurality of memory cells that will produce weak pass outputs in an exemplary analog bit scan operation;

[0067] Fig.31B is a threshold voltage distribution of a plurality of memory cells that will produce a strong pass output in an exemplary analog bit scan operation;

[0068] Fig.31C is a threshold voltage distribution of a plurality of memory cells that will produce weak fail outputs in an exemplary analog bit scan operation;

[0069] Fig.31D is a threshold voltage distribution of a plurality of memory cells that will produce a strong fail output in an exemplary analog bit scan operation;

[0070] Fig.32 is a flow chart including steps for performing a smart verification operation including an analog bit scan operation according to another exemplary embodiment of the present disclosure;

[0071] Fig.33 is a flow chart including steps for performing a smart verification operation including an analog bit scan operation according to yet another exemplary embodiment of the present disclosure;

[0072] Fig.34 is a flow chart including steps for performing a smart verification operation including an analog bit scan operation according to yet another exemplary embodiment of the present disclosure;

[0073] Fig.35A is a threshold voltage distribution graph of a plurality of memory cells under conditions that would produce a weak fail for a verify low Vvsl analog bit scan operation and a strong pass for a verify high Vvsh analog bit scan operation;

[0074] Fig.35B is a threshold voltage distribution graph of a plurality of memory cells under conditions that would produce a strong fail for a verify low Vvsl analog bit scan operation and a strong pass for a verify high Vvsh analog bit scan operation;

[0075] Fig.35Cis a threshold voltage distribution graph of a plurality of memory cells under conditions that would produce a weak pass for a verify high Vvsh analog bit scan operation;

[0076] Fig.35D is a threshold voltage distribution graph of a plurality of memory cells under conditions that would produce a weak fail for a verify high Vvsh analog bit scan operation;

[0077] Fig.35E is a threshold voltage distribution graph of a plurality of memory cells under conditions that would produce a strong fail for a verify high Vvsh analog bit scan operation;

[0078] Fig.36 is a table identifying which data states to verify in which programming cycles according to an exemplary programming operation;

[0079] Fig.37 is a table containing actions to be taken in response to different analog bit scan outputs according to an exemplary embodiment of the present disclosure;

[0080] Fig.38 is a table identifying which data states to verify in which programming cycles according to an exemplary embodiment of a programming operation;

[0081] Fig.39 is a threshold voltage distribution graph having a plurality of curves identifying strong fail, weak fail, and pass conditions for an exemplary simulated bit scan operation;

[0082] Fig.40 is a table identifying which data states to verify in which programming cycles according to an exemplary embodiment of a programming operation;

[0083] Fig.41 is a table that identifies which data states to verify in which programming cycles according to another exemplary embodiment of a programming operation;

[0084] Fig.42 is a graph of various voltages applied to different components in a memory block before and during a programming pulse according to an exemplary embodiment of the present disclosure;

[0085] Fig.43 is a table that identifies which data states to verify in which programming cycles according to another exemplary embodiment of a programming operation;

[0086] Fig.44 is a flowchart including steps for performing an SLC programming operation including an emulated bit scan operation according to an exemplary embodiment of the present disclosure;

[0087] Fig.45 is a flow chart including steps for performing a smart verification operation including an analog bit scan operation according to another exemplary embodiment of the present disclosure;

[0088] Fig.46 is a flowchart containing steps for performing a STPFINE operation including an analog bit scan operation according to an exemplary embodiment of the present disclosure;

[0089] Fig.47 is a flowchart containing steps for performing a STPFINE operation including an analog bit scan operation according to another exemplary embodiment of the present disclosure;

[0090] Fig.48 is a flowchart including steps for performing a smart verification operation including an analog bit scan operation according to another exemplary embodiment of the present disclosure; and

[0091] Fig.49 is a flow chart including steps for performing a smart verification operation including an analog bit scan operation according to yet another exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0092] Programming and erasing typically occur in multiple cycles, each of which includes a programming or erasing pulse and a verification operation. In the verification operation, the threshold voltage Vt of the memory cell being programmed or erased is checked to determine whether these threshold voltages have completed programming or erasing. After the verification operation, a bit scanning operation can be performed to count how many memory cells have completed or failed the programming or erasing operation. The present disclosure generally relates to so-called "analog bit scanning" operations, whereby the bit scanning operation can generate more than two possible outputs, i.e., more than just "pass" and "fail". By generating additional output options (e.g., strong pass, weak pass, weak fail, and strong fail), certain parameters of the programming or erasing operation can be optimized to improve the performance, reliability, and / or durability of the memory device. These analog bit scanning techniques and corresponding programming and erasing operations using analog bit scanning will be discussed in more detail below.

[0093] Figure 1A1 is a block diagram of an exemplary memory device 100 configured to operate according to the analog bit scanning technique of the present disclosure. The memory die 108 includes a memory structure 126 of memory cells, such as an array of memory cells, a control circuit 110, and a read / write circuit 128. The memory structure 126 is addressable by word lines via a row decoder 124 and is addressable by bit lines via a column decoder 132. The read / write circuit 128 includes a plurality of sense blocks SB1, SB2, ... ..., SBp (sense circuits) and allows pages of memory cells to be read or programmed in parallel. Typically, the controller 122 is included in the same memory device 100 (e.g., a removable memory card) as one or more memory dies 108. Commands and data are transmitted between the host 140 and the controller 122 via a data bus 120, and between the controller and the one or more memory dies 108 via a line 118.

[0094] The memory structure 126 may be two-dimensional or three-dimensional. The memory structure 126 may include an array of one or more memory cells, the array of one or more memory cells comprising a three-dimensional array. The memory structure 126 may include a monolithic three-dimensional memory structure in which multiple memory levels are formed above (but not in) a single substrate such as a wafer, without intervening substrates. The memory structure 126 may include any type of non-volatile memory integrally formed in an array of memory cells having one or more physical levels of active regions disposed above a silicon substrate. The memory structure 126 may be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is above or within the substrate.

[0095] Control circuitry 110 cooperates with read / write circuitry 128 to perform memory operations on memory structure 126, and includes a state machine 112, an on-chip address decoder 114, and a power control module 116. State machine 112 provides chip-level control of memory operations.

[0096] The storage area 113 may, for example, be provided for programming parameters. The programming parameters may include a programming voltage, a programming voltage bias, a location parameter indicating the location of a memory cell, a contact wire connector thickness parameter, a verification voltage, etc. The location parameter may indicate the location of the memory cell within the entire NAND string array, the location of the memory cell within a specific NAND string group, the location of the memory cell on a specific plane, etc. The contact wire connector thickness parameter may indicate the thickness of the contact wire connector, the substrate or material constituting the contact wire connector, etc.

[0097] The on-chip address decoder 114 provides an address interface between the hardware addresses used by the host or memory controller and the hardware addresses used by decoders 124 and 132. The power control module 116 controls the power and voltage supplied to the word lines and bit lines during memory operations. The power control module may include drivers for the word lines, SGS transistors, and SGD transistors and source lines. In one approach, the sense block may include a bit line driver. The SGS transistor is a select gate transistor at the source end of the NAND string, and the SGD transistor is a select gate transistor at the drain end of the NAND string.

[0098] In some embodiments, some of the components may be combined. In various designs, one or more of the components other than the memory structure 126 (alone or in combination) may be considered as at least one control circuit configured to perform the actions described herein. For example, the control circuit may include any one of the control circuit 110, the state machine 112, the decoder 114 / 132, the power control module 116, the sense blocks SBb, SB2, ... ..., SBp, the read / write circuit 128, the controller 122, etc., or a combination thereof.

[0099] The control circuit 150 may include a programming circuit 151 configured to perform programming and verification operations on a group of memory cells, wherein the group of memory cells includes memory cells assigned to represent one data state of multiple data states, and memory cells assigned to represent another data state of multiple data states; the programming and verification operations include multiple programming and verification iterations; and in each programming and verification iteration, the programming circuit performs programming on a selected word line, after which the programming circuit applies a verification signal to the selected word line. The control circuit 150 may also include a counting circuit 152, which is configured to obtain a count of memory cells that pass the verification test for one data state. The control circuit 150 may also include a determination circuit 153, which is configured to determine whether the programming operation is completed based on the amount by which the count exceeds a threshold.

[0100] For example, Figure 1B is a block diagram of an exemplary control circuit 150 including a programming circuit 151 , a counting circuit 152 , and a determination circuit 153 .

[0101] The off-chip controller 122 may include a processor 122c, a storage device (memory) such as a ROM 122a and a RAM 122b, and an error correction code (ECC) engine 245. The ECC engine can correct multiple read errors caused when the upper tail of the Vth distribution becomes too high. However, uncorrectable errors may exist in some cases. The technology provided herein reduces the possibility of uncorrectable errors.

[0102] The memory devices 122a, 122b include code, such as a set of instructions, and the processor 122c is operable to execute the set of instructions to provide the functions described herein. Alternatively or additionally, the processor 122c can access code from the storage device 126a of the memory structure 126, such as a reserved area of ​​the memory cell in one or more word lines. For example, the controller 122 can use the code to access the memory structure 126, such as for programming operations, read operations and erase operations. The code may include boot code and control code (e.g., a set of instructions). The boot code is software that initializes the controller 122 and enables the controller 122 to access the memory structure 126 during the boot or startup process. The controller 122 can use the code to control one or more memory structures 126. At power-on, the processor 122c takes out the boot code from the ROM 122a or the storage device 126a for execution, and the boot code initializes the system components and loads the control code into the RAM 122b. Once the control code is loaded into the RAM 122b, it is executed by the processor 122c. The control code includes drivers that perform basic tasks such as controlling and allocating memory, prioritizing the processing of instructions, and controlling input and output ports.

[0103] In general, the control code may include instructions for performing the functions described herein, including the steps of the flowcharts discussed further below, and providing voltage waveforms, including those discussed further below. Figure 1C As shown in , the control circuit 110, the controller 122 and / or the control circuit 150 are configured to program and / or erase the memory cells of the selected word line WLn according to the unique techniques including the analog bit scanning operation discussed herein. At step 160, the circuit starts the programming or erasing operation. At step 161, the circuit performs the analog bit scanning operation that produces one of more than two possible outputs. At step 162, the circuit adjusts at least one parameter of the programming or erasing operation based on the output of the analog bit scanning operation. At step 163, the circuit continues the programming or erasing operation using at least one adjusted parameter.

[0104] In one embodiment, the host is a computing device (e.g., a laptop computer, a desktop computer, a smart phone, a tablet computer, a digital camera) that includes one or more processors, one or more processor-readable storage devices (RAM, ROM, flash memory, hard drive, solid-state memory), and the one or more processor-readable storage devices store processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices that communicate with the one or more processors.

[0105] In addition to NAND flash memory, other types of non-volatile memory may be used.

[0106] Semiconductor memory devices include volatile memory devices, such as dynamic random access memory ("DRAM") or static random access memory ("SRAM") devices, non-volatile memory devices, such as resistive random access memory ("ReRAM"), electrically erasable programmable read-only memory ("EEPROM"), flash memory (which may also be considered a subset of EEPROM), ferroelectric random access memory ("FRAM"), and magnetoresistive random access memory ("MRAM"), as well as other semiconductor elements capable of storing information. Each type of memory device may have a different configuration. For example, a flash memory device may be configured in a NAND configuration or a NOR configuration.

[0107] The memory device may be formed of passive components and / or active components in any combination. By way of non-limiting example, passive semiconductor memory components include ReRAM device components, which in some embodiments include resistivity switching storage elements, such as antifuses or phase change materials, and optional steering elements, such as diodes or transistors. In addition, by way of non-limiting example, active semiconductor memory components include EEPROM and flash memory device components, which in some embodiments include components containing charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0108] Multiple memory elements may be configured so that they are connected in series or so that each element may be accessed individually. By way of non-limiting example, a flash memory device (NAND memory) in a NAND configuration typically includes memory elements connected in series. A NAND string is an example of a group of transistors connected in series that includes a memory cell and a SG transistor.

[0109] A NAND memory array can be configured so that the array consists of multiple memory strings, where the string consists of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, the memory elements can be configured so that each element can be accessed individually, such as a NOR memory array. NAND memory configurations and NOR memory configurations are examples, and memory elements can be configured in other ways. Semiconductor memory elements located in and / or above a substrate can be arranged in two or three dimensions, such as a two-dimensional memory structure or a three-dimensional memory structure.

[0110] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane (e.g., in an xy-direction plane) that extends substantially parallel to the major surface of a substrate supporting the memory elements. The substrate may be a wafer on or in which the layers of the memory elements are formed, or it may be a carrier substrate to which the memory elements are attached after they are formed. As a non-limiting example, the substrate may include a semiconductor, such as silicon.

[0111] The memory elements may be arranged in a single memory device level in an ordered array, such as in multiple rows and / or columns. However, the memory elements may be arranged in an unconventional configuration or a non-orthogonal configuration. The memory elements may each have two or more electrodes or contact lines, such as a bit line and a word line.

[0112] The three-dimensional memory array is arranged so that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., in x, y and z directions, where the z direction is substantially vertical and the x and y directions are substantially parallel to the major surface of the substrate).

[0113] As a non-limiting example, a three-dimensional memory structure may be arranged vertically as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array may be arranged as a plurality of vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y-direction), each column having a plurality of memory cells. The columns may be arranged in a two-dimensional configuration, such as in an xy plane, resulting in a three-dimensional arrangement of memory elements, wherein the elements are located in a plurality of vertically stacked memory planes. Other configurations of three-dimensional memory elements may also constitute a three-dimensional memory array.

[0114] By way of non-limiting example, in a three-dimensional array of NAND strings, memory elements may be coupled together to form a NAND string within a single horizontal (e.g., xy) memory device level. Alternatively, memory elements may be coupled together to form a vertical NAND string that spans multiple horizontal memory device levels. Other three-dimensional configurations are contemplated, with some NAND strings containing memory elements in a single memory level and other strings containing memory elements that span multiple memory levels. Three-dimensional memory arrays may also be designed in NOR configurations as well as ReRAM configurations.

[0115] Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed over a single substrate. Optionally, a monolithic three-dimensional memory array may also have one or more memory layers at least partially within a single substrate. As a non-limiting example, the substrate may include a semiconductor, such as silicon. In a monolithic three-dimensional array, the layers of each memory device level that make up the array are typically formed on the layers of the underlying memory device level of the array. However, the layers of adjacent memory device levels of a monolithic three-dimensional memory array may be shared or have intervening layers between the memory device levels.

[0116] The two-dimensional arrays may then be formed separately and then packaged together to form a non-monolithic memory device having multiple memory layers. For example, a non-monolithic stacked memory may be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of each other. The substrate may be thinned or removed from the memory device levels before stacking, but since the memory device levels are initially formed over separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. In addition, multiple two-dimensional memory arrays or three-dimensional memory arrays (monolithic or non-monolithic) may be formed on separate chips and then packaged together to form a stacked chip memory device.

[0117] Figure 2 Memory blocks 200, 210 of memory cells in an exemplary two-dimensional configuration of the memory array 126 of FIG. 1 are shown. The memory array 126 may include many such memory blocks 200, 210. Each exemplary block 200, 210 includes a plurality of NAND strings and corresponding bit lines, such as BL0, BL1, ... shared between blocks. Each NAND string is connected to a drain side select gate (SGD) at one end, and the control gate of the drain select gate is connected via a common SGD line. The NAND string is connected to a source side select gate (SGS) at its other end, which is in turn connected to a common source line 220. One hundred and twelve word lines (e.g., WL0 to WL111) extend between SGS and SGD. In some embodiments, a memory block may include more or less than one hundred and twelve word lines. For example, in some embodiments, a memory block includes one hundred and sixty-four word lines. In some cases, dummy word lines that do not contain user data may also be used in a memory array adjacent to a select gate transistor or between certain data word lines. Such dummy word lines can shield edge data word lines from certain edge effects.

[0118] One type of nonvolatile memory that may be provided in a memory array is a floating gate memory, such as Figure 3A and Figure 3B However, other types of non-volatile memory may also be used. As discussed in further detail below, Figure 4A and Figure 4B In another example shown, a charge trap memory cell uses a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner. A three-layer dielectric formed of silicon oxide, silicon nitride, and silicon oxide ("ONO") is sandwiched between a conductive control gate and the surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where the electrons are trapped and stored in a limited area. This stored charge then changes the threshold voltage of a portion of the cell's channel in a detectable manner. The cell is erased by injecting hot holes into the nitride. A similar cell can be provided in a split gate configuration, where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor.

[0119] In another approach, an NROM cell is used. For example, two bits are stored in each NROM cell, where an ONO dielectric layer extends over the channel between source and drain diffusions. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit is localized in the dielectric layer adjacent to the source. Multi-state data storage is obtained by separately reading the binary states of spatially separated charge storage regions within the dielectric. Other types of non-volatile memory are also known.

[0120] Figure 3A A cross-sectional view of an exemplary floating gate memory cell 300, 310, 320 in a NAND string is shown. In this figure, the bit line or NAND string direction is into the page, and the word line direction is from left to right. For example, word line 324 extends across the NAND string, which includes corresponding channel regions 306, 316 and 326. Memory cell 300 includes control gate 302, floating gate 304, tunnel oxide layer 305 and channel region 306. Memory cell 310 includes control gate 312, floating gate 314, tunnel oxide layer 315 and channel region 316. Memory cell 320 includes control gate 322, floating gate 321, tunnel oxide layer 325 and channel region 326. Each of memory cells 300, 310 and 320 is in a different corresponding NAND string. An inter-polysilicon dielectric (IPD) layer 328 is also shown. The control gates 302, 312, 322 are part of a word line. Figure 3B A cross-sectional view along the contact line connector 329 is provided in FIG.

[0121] The control gate 302, 312, 322 is wrapped around the floating gate 304, 314, 321, thereby increasing the surface contact area between the control gate 302, 312, 322 and the floating gate 304, 314, 321. This results in a higher IPD capacitance, which results in a higher coupling ratio, which makes programming and erasing easier. However, when the NAND memory device is scaled down, the spacing between adjacent cells 300, 310, 320 becomes smaller, so there is almost no space for the control gate 302, 312, 322 and the IPD layer 328 between two adjacent floating gates 302, 312, 322.

[0122] As an alternative, Figure 4A and Figure 4B As shown, a flat or planar memory cell 400, 410, 420 has been developed in which the control gate 402, 412, 422 is flat or planar; that is, the control gate is not wrapped around the floating gate, and the only contact of the control gate with the charge storage layer 428 is from above it. In this case, there is no advantage to having a tall floating gate. Instead, the floating gate is made thinner. In addition, the floating gate can be used to store charge, or a thin charge trapping layer can be used to trap charge. This approach can avoid the problem of ballistic electron transport, in which electrons can travel through the floating gate after tunneling through the tunnel oxide during programming.

[0123] Figure 4A A cross-sectional view of an exemplary charge trapping memory cell 400, 410, 420 in a NAND string is depicted. The view is in the word line direction of the memory cell 400, 410, 420 including a planar control gate and a charge trapping region as a two-dimensional example of a memory cell 400, 410, 420 in the memory cell array 126 of FIG. 1 . Charge trapping memory can be used in NOR and NAND flash memory devices. Compared to floating gate MOSFET technology that uses conductors such as doped polysilicon to store electrons, this technology uses insulators such as SiN films to store electrons. For example, a word line 424 extends across a NAND string that includes corresponding channel regions 406, 416, 426. Portions of the word line provide control gates 402, 412, 422. An IPD layer 428, a charge trapping layer 404, 414, 421, a polysilicon layer 405, 415, 425, and a tunnel layer 409, 407, 408 are below the word line. Each charge trapping layer 404, 414, 421 extends continuously in a corresponding NAND string. The planar configuration of the control gate can be made thinner than the floating gate. In addition, the memory cells can be placed closer together.

[0124] Figure 4B Shows Figure 4A435, and SGD transistor 436. The passage in IPD layer 428 in SGS transistor 431 and SGD transistor 436 allows control gate layer 402 and floating gate layer to communicate. For example, control gate layer 402 and floating gate layer can be polysilicon, and tunnel oxide layer can be silicon oxide. IPD layer 428 can be a stack of nitride (N) and oxide (O), such as in NONON configuration.

[0125] The NAND string may be formed on a substrate including a p-type substrate region 455, an n-type well 456, and a p-type well 457. N-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 are formed in the p-type well. A channel voltage Vch may be directly applied to the channel region of the substrate.

[0126] Figure 5 An exemplary block diagram of the sense block SB1 of FIG. 1 is shown. In one approach, the sense block includes a plurality of sense circuits. Each sense circuit is associated with a data latch. For example, exemplary sense circuits 550a, 551a, 552a, and 553a are associated with data latches 550b, 551b, 552b, and 553b, respectively. In one approach, different corresponding sense blocks can be used to sense different bit line subsets. This allows the processing load associated with the sense circuit to be divided and processed by the corresponding processor in each sense block. For example, the sense circuit controller 560 in SB1 can communicate with the group of sense circuits and latches. The sense circuit controller 560 may include a precharge circuit 561 that provides a voltage to each sense circuit for setting a precharge voltage. In one possible approach, the voltage may be independently provided to each sense circuit, for example, via a data bus and a local bus. In another possible approach, a common voltage may be provided to each sense circuit simultaneously. The sense circuit controller 560 may also include a precharge circuit 561, a memory 562, and a processor 563. The memory 562 may store code that can be executed by the processor to perform the functions described herein. These functions may include reading latches 550b, 551b, 552b, 553b associated with the sensing circuits 550a, 551a, 552a, 553a, setting bit values ​​in the latches, and providing a voltage for setting a precharge level in a sensing node of the sensing circuits 550a, 551a, 552a, 553a. Further exemplary details of the sensing circuit controller 560 and the sensing circuits 550a, 551a, 552a, 553a are provided below.

[0127] In some embodiments, the memory cell may include a tag register including a set of latches storing a tag bit. In some embodiments, the number of tag registers may correspond to the number of data states. In some embodiments, one or more tag registers may be used to control the type of verification technique used when verifying the memory cell. In some embodiments, the output of the tag bit may modify the associated logic of the device, such as an address decoding circuit, so that a specified cell block is selected. Body operations (e.g., erase operations, etc.) may be performed using a tag set in a tag register, or a combination of a tag register and an address register, as in implicit addressing, or alternatively performed by direct addressing using only an address register.

[0128] Fig. 6A 1 is a perspective view of a set of blocks 600 in an exemplary three-dimensional configuration of the memory array 126 of FIG. On the substrate are exemplary blocks BLK0, BLK1, BLK2, BLK3 of memory cells (storage elements), and a peripheral region 604 having circuits for use by the blocks BLK0, BLK1, BLK2, BLK3. For example, the circuits may include a voltage driver 605 that may be connected to the control gate layers of the blocks BLK0, BLK1, BLK2, BLK3. In one approach, the control gate layers at a common height in the blocks BLK0, BLK1, BLK2, BLK3 are driven together. The substrate 601 may also carry the circuits below the blocks BLK0, BLK1, BLK2, BLK3, together with one or more lower metal layers that are patterned in conductive paths to carry the signals of the circuits. The blocks BLK0, BLK1, BLK2, BLK3 are formed in the middle region 602 of the memory device. In the upper region 603 of the memory device, one or more upper metal layers are patterned in a conductive path to carry the signals of the circuit. Each block BLK0, BLK1, BLK2, BLK3 includes a stacked region of memory cells, wherein alternating levels of the stack represent word lines. In one possible approach, each block BLK0, BLK1, BLK2, BLK3 has an opposing layered side from which vertical contacts extend upward to the upper metal layer to form a connection with the conductive path. Although four blocks BLK0, BLK1, BLK2, BLK3 are shown as examples, two or more blocks extending in the x-direction and / or the y-direction may be used.

[0129] In one possible approach, the length of the plane in the x-direction represents the direction in which the signal path to the word line extends in one or more upper metal layers (the word line or SGD line direction), and the width of the plane in the y-direction represents the direction in which the signal path to the bit line extends in one or more upper metal layers (the bit line direction). The z-direction represents the height of the memory device.

[0130] Figure 6B Shows Fig. 6A 1 is an exemplary cross-sectional view of a portion of one of the blocks BLK0, BLK1, BLK2, BLK3. The block includes a stack 610 of alternating conductive layers and dielectric layers. In this example, in addition to data word line layers (word lines) WL0 to WL111, the conductive layers include two SGD layers, two SGS layers, and four dummy word line layers DWLD0, DWLD1, DWLS0, and DWLS1. The dielectric layers are labeled DL0 to DL116. In addition, a region of the stack 610 including NAND strings NS1 and NS2 is shown. Each NAND string contains memory holes 618, 619 that are filled with material that forms memory cells adjacent to the word lines. Region 622 of the stack 610 is Fig.6D The dielectric layer may have a variable thickness, such that some of the conductive layers may be closer or farther away from adjacent conductive layers. The thickness of the dielectric layer affects the "ON spacing," which is a factor in memory density. Specifically, a smaller ON spacing allows more memory cells in a given area, but may compromise reliability.

[0131] The stack 610 includes a substrate 611, an insulating film 612 located on the substrate 611, and a portion of a source line SL. NS1 has a source terminal 613 at the bottom 614 of the stack and a drain terminal 615 at the top 616 of the stack 610. Contact line connectors (e.g., slits, such as metal-filled slits) 617, 620 can be provided periodically across the stack 610 as interconnectors extending through the stack 610, such as to connect the source line to a specific contact line above the stack 610. The contact line connectors 617, 620 can be used during the formation of the word lines and subsequently filled with metal. A portion of the bit line BL0 is also shown. A conductive via 621 connects the drain terminal 615 to BL0.

[0132] Figure 6C Shows Figure 6B The vertical axis is plotted against the diameter of the memory holes in the stack. Figure 6B The stack is aligned and the width (wMH), eg, diameter, of memory hole 618 and memory hole 619 are shown. Fig. 6AThe word line layers WL0 to WL111 of are repeated as examples and are at corresponding heights z0 to z111 in the stack. In such memory devices, the memory hole etched through the stack has a very high aspect ratio. For example, a depth to diameter ratio of about 25 to 30 is common. The memory hole may have a circular cross-section. Due to the etching process, the width of the memory hole may vary along the length of the hole. Typically, the diameter of the memory hole tapers from its top to its bottom. That is, the memory hole is tapered and narrows at the bottom of the stack. In some cases, a slight narrowing occurs at the top of the hole near the select gate, so that the diameter of the memory hole widens slightly before taper from its top to its bottom.

[0133] Due to the non-uniformity of the memory hole width, the programming speed including the programming slope and the erase speed of the memory cell may vary based on the location of the memory cell along the memory hole (e.g., based on the height of the memory cell in the stack). For smaller diameter memory holes, the electric field across the tunnel oxide is relatively strong, so that the programming and erase speeds are relatively high. One approach is to define a group of adjacent word lines with a similar diameter to the memory hole (e.g., within a defined diameter range), and apply an optimized verification scheme for each word line in the group. Different groups may have different optimized verification schemes.

[0134] Fig.6D Shows Figure 6B 622 of the stack 610 of FIG. Memory cells are formed at different levels of the stack at the intersection of the word line layer and the memory hole. In this example, SGD transistors 680, 681 are disposed above dummy memory cells 682, 683 and data memory cells MC. Multiple layers may be deposited along the sidewalls (SW) of the memory hole 630 and / or within each word line layer, for example, using atomic layer deposition. For example, each column (e.g., a column formed by the material within the memory hole 630) may include a charge trapping layer or film 663 (such as SiN or other nitride), a tunnel layer 664, a polysilicon body or channel 665, and a dielectric core 666. The word line layer may include a blocking oxide / block high-k material 660, a metal barrier layer 661, and a conductive metal 662 (such as tungsten) as a control gate. For example, control gates 690, 691, 692, 693, and 694 are provided. In this example, all layers except the metal are provided in the memory hole 630. In other approaches, some of the layers may be in the control gate layer. Additional pillars are similarly formed in different memory holes. The pillars may form a pillar-shaped active area (AA) of the NAND string.

[0135] When programming a memory cell, electrons are stored in a portion of the charge trapping layer associated with the memory cell. These electrons are attracted from the channel into the charge trapping layer and travel through the tunnel layer. The Vth of the memory cell increases in proportion to the amount of charge stored. During an erase operation, the electrons return to the channel.

[0136] Each of the memory holes 630 may be filled with a plurality of annular layers including a blocking oxide layer, a charge trapping layer 663, a tunnel layer 664, and a channel layer. A core region of each of the memory holes 630 is filled with a body material, and the plurality of annular layers are located between the core region and the word line in each of the memory holes 630.

[0137] The NAND string can be considered to have a floating body channel because the length of the channel is not formed on the substrate.In addition, the NAND string is provided by multiple word line layers stacked on top of each other and separated from each other by dielectric layers.

[0138] Fig. 7A Shows Figure 6B 610. As mentioned, a three-dimensional memory device may include a stack of alternating conductive layers and dielectric layers. The conductive layers provide control gates for SG transistors and memory cells. The layers for SG transistors are SG layers, and the layers for memory cells are word line layers. In addition, memory holes are formed in the stack and filled with charge trapping material and channel material. Thus, vertical NAND strings are formed. Source lines are connected to the NAND strings below the stack and bit lines are connected to the NAND strings above the stack.

[0139] The block BLK in the three-dimensional memory device can be divided into sub-blocks, wherein each sub-block includes a NAND string group with a common SGD control line. For example, refer to the SGD line / control gate SGD0, SGD1, SGD2 and SGD3 in the sub-blocks SBa, SBb, SBc and SBd, respectively. In addition, the word line layer in the block can be divided into regions. Each region is in a corresponding sub-block and can extend between contact line connectors (e.g., slits), which are periodically formed in the stack to process the word line layer during the manufacturing process of the memory device. The treatment may include replacing the sacrificial material of the word line layer with metal. Generally speaking, the distance between the contact line connectors should be relatively small to consider the limitation of the distance that the etchant can travel laterally to remove the sacrificial material, and the metal can travel to fill the gap created by removing the sacrificial material. For example, the distance between the contact line connectors can allow several rows of memory holes to exist between adjacent contact line connectors. The layout of the memory holes and contact line connectors should also consider the limitation of the number of bit lines that can extend across the region when each bit line is connected to a different memory cell. After processing the wordline layer, contact line connectors may optionally be filled with metal to provide interconnection through the stack.

[0140] In this example, there are four rows of memory holes between adjacent contact line connectors. A row here is a group of memory holes aligned in the x-direction. In addition, the rows of memory holes are arranged in a staggered pattern to increase the density of the memory holes. The word line layer or word line is divided into regions WL0a, WL0b, WL0c, and WL0d, which are each connected by contact lines 713. In one approach, the last region of the word line layer in a block can be connected to the first region of the word line layer in the next block. Contact line 713 is in turn connected to a voltage driver for the word line layer. Region WL0a has exemplary memory holes 710, 711 along contact line 712. Region WL0b has exemplary memory holes 714, 715. Region WL0c has exemplary memory holes 716, 717. Region WL0d has exemplary memory holes 718, 719. Memory holes are also Figure 7B Each memory hole can be part of a corresponding NAND string. For example, memory holes 710, 714, 716, and 718 can be part of NAND strings NS0_SBa, NS1_SBb, NS2_SBc, NS3_SBd, and NS4_SBe, respectively.

[0141] Each circle represents a cross section of a memory hole at a word line layer or SG layer. The exemplary circles shown with dashed lines represent memory cells provided by the material in the memory hole and the adjacent word line layer. For example, memory cells 720, 721 are in WL0a, memory cells 724, 725 are in WL0b, memory cells 726, 727 are in WL0c, and memory cells 728, 729 are in WL0d. These memory cells are at a common height in the stack.

[0142] Contact line connectors (e.g., slots, such as metal-filled slots) 701, 702, 703, 704 may be located between and adjacent to the edges of regions WL0a to WL0d. The contact line connectors 701, 702, 703, 704 provide a conductive path from the bottom of the stack to the top of the stack. For example, a source line at the bottom of the stack may be connected to a conductive line above the stack, where the conductive line is connected to a voltage driver in a peripheral region of the memory device.

[0143] Figure 7B Shows Figure 6B 1. A top view of an exemplary top dielectric layer DL116 of a stack of . The dielectric layer is divided into regions DL116a, DL116b, DL116c, and DL116d. Each region can be connected to a corresponding voltage driver. This allows a group of memory cells in one region of the word line layer to be programmed simultaneously, where each memory cell is in a corresponding NAND string connected to a corresponding bit line. A voltage can be set on each bit line to allow or prohibit programming during each programming voltage.

[0144] Region DL116a has exemplary memory holes 710, 711 along contact line 712 that coincides with bit line BL0. Many bit lines extend over and connect to the memory holes, as indicated by the "X" symbol. BL0 connects to a group of memory holes that includes memory holes 711, 715, 717, 719. Another exemplary bit line BL1 connects to a group of memory holes that includes memory holes 710, 714, 716, 718. Also shown are bits from Fig. 7A The contact line connectors (eg, slots, such as metal filled slots) 701, 702, 703, 704 are shown as they extend vertically through the stack. The bit lines may be numbered in the order BL0 to BL23 across the DL116 layer in the x-direction.

[0145] Different subsets of the bit lines are connected to memory cells in different rows. For example, BL0, BL4, BL8, BL12, BL16, BL20 are connected to memory cells in the first row of cells at the right hand edge of each region. BL2, BL6, BL10, BL14, BL18, BL22 are connected to memory cells in the adjacent row of cells adjacent to the first row at the right hand edge. BL3, BL7, BL11, BL15, BL19, BL23 are connected to memory cells in the first row of cells at the left hand edge of each region. BL1, BL5, BL9, BL13, BL17, BL21 are connected to memory cells in the adjacent row of memory cells adjacent to the first row at the left hand edge.

[0146] The memory cells of a memory block may be programmed to store one or more bits of data in a plurality of data states, each of which is associated with a corresponding threshold voltage Vt. For example, Figure 8 Depicted are threshold voltage Vt distributions for a group of memory cells programmed according to a one-bit per memory cell (SLC) storage scheme. In the SLC storage scheme, there are a total of two data states, including an erased state (Er) and a single programmed data state (S1). Fig. 9 Threshold voltage Vt distributions are shown for a three-bit per cell (TLC) storage scheme that includes a total of eight data states, an erased state (Er) and seven programmed data states (S1, S2, S3, S4, S5, S6, and S7). Each programmed data state (S1 to S7) is associated with a corresponding verification voltage (Vv1 to Vv7) that is employed during the verification portion of a programming operation. Other storage schemes are also available, such as two bits per cell (MLC) with four data states, four bits per cell (QLC) with sixteen data states, or five bits per cell (PLC) with thirty-two data states.

[0147] Programming of the memory cells of a memory block occurs on a word-by-word basis from one side of the memory block toward the opposite side. The programming direction may start from the drain side of the memory block (or in some cases a sub-block) and occur toward the source side, or vice versa. For example, referring to Figure 6B , in the normal order programming (NOP) direction, the first word line to be programmed may be WL0. The next word line to be programmed may be WL1 and then WL2, and so on. In a reverse order programming (ROP) operation, the first word line to be programmed may be physical WLN (where N is the highest data word line in the memory block or sub-block, e.g., WL111), and then programming proceeds to physical WLN-1 (e.g., WL110), followed by physical WLN-2 (e.g., WL109), and so on.

[0148] Programming the memory cells of one of the word lines to multiple bits per memory cell (eg, MLC, TLC, or QLC) typically begins with the memory cells in an erased state and includes multiple programming cycles. Fig.10 Depicted is a waveform 1000 of a voltage applied to a selected word line during an exemplary memory cell programming operation for programming the memory cells of the selected word line to a larger number of bits per memory cell (e.g., TLC). As depicted, each programming loop includes a programming pulse VPGM and one or more verify pulses, depending on which data states are being programmed in a particular programming loop. For simplicity, a square waveform is depicted for each pulse; however, other shapes are possible, such as a multi-level shape or a ramp shape.

[0149] Incremental step pulse programming (ISPP) is used in this example, which means that the VPGM pulse amplitude is raised or increased in each consecutive programming cycle. In other words, the pulse train includes VPGM pulses that increase in amplitude stepwise with each consecutive programming cycle at a fixed step size (dVPGM). A new pulse train starts at an initial VPGM pulse level VPGMU and ends at a final VPGM pulse level that does not exceed the maximum allowed level. The exemplary pulse train 1000 includes a series of VPGM pulses 1001 to 1009 applied to a selected word line including a group of nonvolatile memory cells. As an example, one or more verification voltage pulses 1010 to 1019 are provided after each VPGM pulse based on the target memory state being verified in the programming cycle. The verification voltages correspond to voltages Vv1 to Vv7, as shown in FIG. Fig. 9 As shown. While applying the verification voltage, the sensing operation can determine whether a particular memory cell in the selected word line has a threshold voltage Vt higher than the verification voltage associated with the expected data state of the particular memory cell by sensing the current passing through the memory cell. If the current is relatively high, this indicates that the memory cell is in a conductive state, so that the threshold voltage Vt of the memory cell is less than the verification voltage. If the current is relatively low, this indicates that the memory cell is in a non-conductive state, so that the threshold voltage Vt of the memory cell is higher than the verification voltage. If the memory cell passes verification, programming of the memory cell is completed, and further programming of the memory cell is prohibited for all remaining programming cycles by applying a prohibition voltage to the bit line coupled to the memory cell simultaneously with the VPGM pulse. Programming continues until all memory cells pass verification for their expected data states (in which case, programming passes), or until a predetermined maximum number of programming cycles is exceeded (in which case, programming fails). In some embodiments, the memory cells of a word line can be divided into a series of string groups that can be programmed independently of each other or simply divided into strings, and programming can start from one string to another across word lines before proceeding to the next word line in the memory block.

[0150] In addition to the verification operations described above, a bit scan operation may be performed to determine when programming of a group of memory cells (e.g., a plurality of memory cells in a selected word line that are being programmed to a given data state or being erased) is complete. As used herein, a "bit scan" is a count of the number of memory cells whose programming characteristics have not yet shifted to a particular verification voltage level above or below a particular data state, or have shifted to a level above the verification voltage, depending on the particular application. In some embodiments, a bit scan may include a bit count operation that counts the number of memory cells whose threshold voltage Vt has not yet shifted to a particular verification voltage Vv level above a particular data state. For example, a data state Sn bit scan is a count of the number of data state Sn memory cells whose threshold voltage Vt has not yet shifted to a verification voltage level Vvn above data state Sn. Similarly, a state Sn+1 bit scan is a count of the number of state n+1 memory cells whose threshold voltage Vt has not yet shifted to a verification voltage level Vvn+1 above data state Sn+1, and so on. In some other implementations, the bit scan may be a count of the number of memory cells that pass verification (ie, whose threshold voltage Vt has shifted above the verify voltage level Vvn).

[0151] If the bit scan count for a particular state is less than a predetermined bit scan pass fail (BSPF) threshold, then programming of the memory cells of a particular memory state Sn may be considered complete. In some embodiments, the BSPF threshold is less than the number of read errors that can be corrected by the ECC engine of the memory device. In other words, programming of the memory cells of the particular memory state Sn may be considered complete even if all of the memory cells to be programmed to the particular memory state Sn do not have a threshold voltage that has shifted to a verification voltage level Vvn that is higher than the data state Wn, as long as the number of "failed" memory cells is less than the number of read errors that can be corrected by the ECC engine.

[0152] The bit scan operation is typically performed based on the results of the verify operation of a particular program-verify iteration. In particular, the results of the verify operation can be used to calculate a bit scan for a particular memory state.

[0153] A bit scan may also be performed after erase-verify in an erase operation to count the number of memory cells having a threshold voltage Vt greater than the erase verify voltage, as discussed in further detail below.

[0154] Traditionally, the result of a bit scan operation is binary. That is, the bit scan passes (e.g., if the number of failed memory cells is less than the BSPF threshold) or fails (e.g., if the number of failed memory cells is greater than the BSPF threshold). The present disclosure improves these techniques by allowing the bit scan operation to produce additional (non-binary) results. A bit scan operation that produces a non-binary result (greater than two possible options) is referred to as a "simulated bit scan" hereinafter. For example, if the bit scan operation passes, some simulated bit scan operations may determine whether the pass is a strong pass (where the number of failed memory cells is significantly less than the BSPF threshold) or a weak pass (where the number of failed memory cells is equal to or slightly below the BSPF threshold). Similarly, if the bit scan operation fails, some simulated bit scan operations may determine whether the failure is a strong failure (where the number of failed memory cells is significantly higher than the BSPF threshold) or a weak failure (where the number of failed bits is slightly higher than the BSPF threshold).

[0155] In some embodiments discussed below, the analog bit scan operation can produce even more than four possible outputs or bins. By extending the bit scan results to provide additional information beyond the binary pass / fail of the conventional bit scan operation, the programming and erasure algorithms and modes can be optimized with dynamic control for improving performance, reliability and / or durability. For example, in some embodiments, programming verification can be skipped in certain programming cycles to improve performance. In some other embodiments, different dVPGM or dVERA voltages can be dynamically applied to improve performance and / or durability. In yet other embodiments, additional verification operations can be triggered to improve reliability. These and other features and advantages will be discussed further below.

[0156] A first example of a simulated bit scan operation utilizes a busy time detector to determine an output (e.g., "strong fail," "weak fail," "weak pass," or "strong pass"). When a bit scan operation fails, the bit scan operation stops immediately after the number of failed bits exceeds the BSPF threshold. Therefore, a word line with a failed bit scan with a large number of failed bits (strong fail) will be failed bit scanned faster than a word line with a failed bit scan with a relatively small number of failed bits (weak fail). Similarly, counting failed bits takes some time during the bit scan operation. Therefore, a word line with a relatively low number of failed bits (strong pass) will be passed through the bit scan faster than a word line with a relatively high (but still passed) number of failed bits (weak pass). In this exemplary embodiment, the magnitude of a bit scan pass (strong pass / weak pass) or a bit scan failure (strong fail / weak fail) is determined substantially based on the time or busy time of the bit scan operation.

[0157] The simulated bit scan operation begins by comparing the number of failed bits (memory cells) to the BSPF threshold to determine whether the bit scan passed or failed. The busy time detector then determines whether the bit scan passed or failed was a strong pass or a weak pass. The amount of time to complete the bit scan operation is proportional to the busy time, which can be determined using a mathematical formula such as:

[0158] Busy time=1+(DBUS_Precharge_Cycle+1)+(DBUS_Discharge_Cycle+1)+(Detection_Time_1_Tier_No_Error)*(#_of_Tiers_Executed)+(#_of_Fail_Bits) / 8

[0159] DBUS is the internal bus that connects the user cache to the internal data latches. Therefore, DBUS_Precharge_Cycle is a count of the clock cycles required to precharge the DBUS, and DBUS_Discharge_Cycle is a count of the clock cycles required to discharge the DBUS. Therefore, DBUS_Precharge_Cycle and DBUS_Discharge_Cycle are both preset parameters. In the exemplary embodiment, both are set to five (5) cycles. Detection_Time_for_1_Tier_No_Error is also a parameter, and is set to thirty-one (31) cycles in the exemplary embodiment, but may be set to different levels in other embodiments. The variable #_of_Tier_Executed includes the number of tiers in the page. In the exemplary embodiment, the number of tiers is sixteen (16). The variable #_of_Fail_Bits increases the busy time with each failed bit (memory cell) detected.

[0160] Fig.11 An exemplary table is provided that illustrates an example of how busy time may be used to determine the magnitude of a bit scan pass or bit scan fail. In this example, the BSPF threshold is set to one hundred twenty (120) bits, and the bit scan is a four-layer bit scan. There are four possible outputs for this exemplary simulated bit scan operation: strong fail, weak fail, weak pass, and strong pass. In some embodiments, more bins may be added, such as medium fail and medium pass. The pass / fail bit scan status is first determined by comparing the number of failed bits to the BSPF threshold.

[0161] Once the bit scan state is determined, a formula (such as the one given above) can be used to calculate the busy time. If the busy time is less than a busy time threshold (e.g., one hundred fifty

[150] cycles), then if the bit scan state is a pass, then the output is a strong pass, and if the bit scan state is a fail, then the output is a strong fail. On the other hand, if the busy time is greater than or equal to the busy time threshold, then if the bit scan state is a pass, then the output is a weak pass, and if the bit scan state is a fail, then the output is a weak fail.

[0162] For example, if the simulated bit scan operation fails when scanning the first layer (the failed bit exceeds the BSPF threshold), the busy time will naturally be below the busy time threshold and the output is a strong failure. On the other hand, if the bit scan operation fails when scanning the last layer, the busy time will be equal to or above the busy time threshold and the output is a weak failure. In other words, if the bit scan operation is completed relatively quickly, the output is a strong failure, and if the bit scan operation is completed relatively slowly, the output is a weak failure.

[0163] In the case where the bit scan state is PASS, according to the above formula, if there are very few failed bits, the busy time will be lower than if there are many failed bits because the variable (#_of_Fail_Bits) will be low. Therefore, if the bit scan state is PASS and the busy time is less than the busy time threshold, the output is a strong PASS. In other words, if the bit scan operation is completed relatively quickly, the output is a strong PASS, and if the bit scan operation is completed relatively slowly, the output is a weak PASS. The busy time threshold for PASS may be the same or different from the busy time threshold for FAIL.

[0164] Now go to Fig.18 , a flowchart 1800 is provided depicting an exemplary embodiment of the present disclosure. These steps may be performed by a controller, processor or processing device or any other circuitry executing instructions stored in a memory and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0165] At step 1802, an analog bit scan operation is performed to count failed bits and the number of failed bits is compared to a BSPF threshold. At step 1804, a busy time is determined, for example, by using the busy time formula described above.

[0166] At decision step 1806, it is determined whether the analog bit scan operation passed. If the answer at decision step 1806 is "yes", then at decision step 1808, it is determined whether the busy time is less than the busy time threshold. If the answer at decision step 1808 is "no", then at step 1810, the output of the analog bit scan operation is a weak pass. If the answer at decision step 1808 is "yes", then at step 1812, the output of the analog bit scan operation is a strong pass.

[0167] If the answer at decision step 1806 is "no", then at decision step 1814, it is determined whether the busy time is less than the busy time threshold. If the answer at decision step 1814 is "no", the output of the simulated bit scan operation is a weak failure. If the answer at decision step 1814 is "yes", the output of the simulated bit scan operation is a strong failure.

[0168] exist Fig.11 , Fig.12 and Fig.18 In the example depicted in , the bit scan operation scans four layers of the page. In some embodiments, as few as a single layer may be scanned during the bit scan operation. In some embodiments that scan multiple layers, whether a bit scan failure is a strong failure or a weak failure may be determined based on which layer is being scanned when the bit scan operation is completed. For example, if four layers are scanned and the bit scan operation fails during scanning of any of the first three layers, the failed layer information will be substituted into the busy time formula, which will increase the busy time and may result in a strong failure output. However, if the bit scan operation fails during scanning of the fourth layer, the output may be a weak failure. If only one layer is scanned, a count of clock cycles may be used to determine whether the output is a strong failure or a weak failure.

[0169] Now go to Fig.12 and Fig.13 , which depicts a busy control signal YBUSYn that remains active during a bit scan operation, an oscillator TMOSC_SMB, and a clock CLK counter that counts cycles of the oscillator during a bit scan operation. Based on the clock count, a parameter is set that determines whether a bit scan failure is a strong failure or a weak failure and whether a bit scan pass is a strong pass or a weak pass during a simulated bit scan operation that includes only a single layer scan.

[0170] Specifically, the CLK counter is compared to a counter threshold. If the CLK counter is less than the counter threshold at the end of the scan, the output is a strong failure, and if the CLK counter is equal to or greater than the counter threshold, the output is a weak failure. The counter threshold can be set to any suitable level to separate strong failure conditions from weak failures.

[0171] For determining whether the pass is a strong pass or a weak pass, separate parameters BSPF_ABSCAN_WP and BSPF_ABSCAN_SP are provided to change the busy time that separates the strong pass from the weak pass. Specifically, when determining whether the pass is a weak pass, instead of (#_of_Fail_Bits / 8), the difference (BSPF-BSPF_ABSCAN_WP) between BSPF and BSPF_ABSCAN_WP is input into the above-mentioned busy time formula to establish a busy time weak pass threshold. The number of clock cycles during the bit scan operation is then compared with the busy time threshold. If the number of clock cycles is greater than the busy time weak pass threshold, the output is a weak pass. Similarly, the difference between BSPF and BSPF_ABSCAN_SP can be calculated, and it is substituted into the above-mentioned formula to establish a busy time strong pass threshold. Then, the number of clock cycles to complete the bit scan operation is compared with the busy time strong pass threshold. If the number of clock signals is less than the busy time strong pass threshold, the output is a strong pass. On the contrary, if the number of clock cycles to complete the bit scan operation is greater than the busy time strong pass threshold, the output is a weak pass.

[0172] According to another exemplary embodiment, the determination of whether a bit scan failure is strong or weak is based on which layer was being scanned at the time of the bit scan failure. As discussed above, in an exemplary embodiment, the page may be divided into multiple layers, such as sixteen (16) layers (layers 0 to 15). The bit scan operation may scan all sixteen layers or only some of those layers, such as every other layer, every fourth layer, or only two layers. Fig.14 is a table depicting different layer scan options, layer scan order, and output based on which layer is being scanned when an in-place scan fails. For example, in a sixteen layer scan, if a failure occurs during the scan of layers 0 to 3, the output is a strong fail. If a failure occurs during the scan of layers 12 to 15, the output is a weak fail. If a failure occurs during any other layer, the output is a regular fail or "medium fail". There may be additional bins, depending on how many layers are scanned. Moreover, the barriers between these bins can be set appropriately for a given memory device or operation. In a two layer scan, only two fail bins (strong fail, weak fail) are possible according to the techniques of this embodiment.

[0173] Fig.19 A flowchart 1900 is provided depicting an exemplary embodiment of the present disclosure. These steps may be performed by a controller, processor or processing device or any other circuitry executing instructions stored in a memory and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0174] At step 1902, a multi-layer analog bit scan operation is performed on the page (e.g., the selected word line being programmed). At decision step 1904, it is determined whether the analog bit scan operation has completed scanning all layers and the number of failed bits is also less than or equal to the BSPF threshold. If the answer at decision step 1904 is "yes", then at step 1906, the output of the analog bit scan operation is "pass".

[0175] If the answer at decision step 1904 is "no", the process proceeds to decision step 1908. At decision step 1908, it is determined whether the analog bit scan operation failed during an early layer scan (e.g., one of the first four layers scanned in a sixteen-layer scan). If the answer at decision step 1908 is "yes", then at step 1910, the output of the analog bit scan operation is a strong failure.

[0176] If the answer at decision step 1908 is "no", the process proceeds to decision step 1912. At decision step 1912, it is determined whether the analog bit scan operation fails during a late layer scan (e.g., one of the last four layers scanned in a sixteen-layer scan). If the answer at decision step 1912 is "yes", then at step 1914, the output of the analog bit scan operation is a weak failure. If the answer at decision step 1912 is "no", then at step 1916, the output of the analog bit scan operation is a "moderate failure".

[0177] exist Fig.14 In the exemplary embodiment of , the layers are scanned sequentially in the order from layer 0 to layer 15. However, in some embodiments, other orders may be used. The output will be adjusted accordingly, so that if a failure occurs during scanning of one of the first layers (regardless of its layer #), the output is a strong failure, and if a failure occurs during scanning of one of the last layers (regardless of its layer #), the output is a weak failure.

[0178] Fig.14 One disadvantage of the exemplary embodiment of is that the embodiment does not allow the analog bit scan operation to distinguish between weak passes and strong passes, i.e., any completed output of the bit scan operation is only a pass. Fig.15According to another exemplary embodiment, a weak pass may be detected by adjusting (reducing) the BSPF threshold downward from the baseline so that BSPF_adj is at a lower amount than the ECC engine can easily correct. Specifically, the BSPF threshold is set to the adjusted (reduced) level BSPF_adj before the bit scan. Then, if the bit scan operation fails during the scan of the last layer or one of the following layers, the output is a weak pass, and if the bit scan passes even at a higher BSPF_adj level, the output is a strong pass because the number of failed bits must actually be less than the baseline BSPF threshold. In other words, in this embodiment, the layers are binned and the failure during each bin can be a strong fail, a weak fail, or a weak pass, and any pass at the adjusted BSPF is a strong pass.

[0179] In some embodiments, the layers are selected to cover the memory hole variations so that each layer is associated with a memory hole from a particular row (e.g., see Figure 7B Selecting the layers in this way ensures that each layer includes memory cells that will have a range of different behaviors (program fast and program slow), and therefore each layer represents a cross section of similar cell behavior.

[0180] According to another embodiment, multiple BSPF windows or ranges are established, and which option (e.g., strong fail, weak fail, weak pass, or strong pass) is outputted depends on which BSPF window the fail bit count (FBC) falls within. The BSPF windows are defined by a predetermined BSPF standard. For example, in Fig.16 In the embodiment depicted in the table of , the baseline BSPF is one criterion. Other exemplary criteria are BSPF_ABSCAN_F greater than BSPF and BSPF_ABSCAN_P less than BSPF. These three criteria define a total of four windows: a first window that includes FBC greater than BSPF_ABSCAN_F; a second window that includes FBC between BSPF_ABSCAN_F and BSPF; a third window that includes FBC between BSPF and BSPF_ABSCAN_P; and a fourth window that includes FBC less than BSPCF_ABSCAN_P.

[0181] In this example, a simulated bit scan operation is performed to determine the FBC. If the FBC in the first window (FBC > BSPF_ABSCAN_F), the output is a strong failure. If the FBC is in the second window (BSPF < FBC ≤ BSPF_ABSCAN_F), the output is a weak failure. If the FBC is in the third window (BSPF_ABSCAN_P < FBC ≤ BSPF), the output is a weak pass. If the FBC is less than the fourth window (FBC ≤ BSPF_ABSCAN_P), the output is a strong pass.

[0182] Turning now to Fig.17 , FIG. 1700 is a flow chart depicting steps including performing a simulated bit scan operation in accordance with one embodiment of the present disclosure. These steps may be performed by a controller, a processor, or a processing device, or any other circuitry that executes instructions stored in a memory and / or other circuitry specifically configured / programmed to perform the following steps described herein.

[0183] At step 1702, the variable n is set to zero such that the first layer to be scanned is layer 0. This numbering format is intended to be exemplary in nature, and in some embodiments, the numbering may be different and the first layer to be scanned may be some layer other than layer 0.

[0184] At step 1704, a bit scan operation is performed on Tier_n, and the failed bits are counted and included in the FBC. At decision step 1706, it is determined whether Tier_n is the last layer to be scanned. If the answer at decision step 1706 is "no", then at step 1708, the next layer to be scanned is incrementally advanced. In an exemplary embodiment, this involves incrementally advancing the variable n, i.e., n = n + 1. In some embodiments, every other layer or every fourth layer may be scanned, in which case n may be incremented by two or four. In some other embodiments, the layers may be scanned in a very different order, and in those embodiments, the layer being scanned may be advanced in a different manner. The process then returns to step 1704.

[0185] If the answer at decision step 1706 is "yes", then at decision step 1710, it is determined whether the FBC is greater than BSPF_ABSCAN_F. If the answer at decision step 1710 is "yes", then at step 1712, the output is a strong failure and the process ends.

[0186] If the answer at decision step 1710 is "no", then at decision step 1714, it is determined whether the FBC is between BSPF_ABSCAN_F and BSPF. If the answer at decision step 1714 is "yes", then at step 1716, the output is a weak failure and the process ends.

[0187] If the answer at decision step 1714 is "no", then at decision step 1718, it is determined whether the FBC is between the BSPF and BSPF_ABSCAN_P. If the answer at decision step 1718 is "yes", then at step 1720, the output is a weak pass and the process ends. If the answer at decision step 1718 is "no", then at step 1722, the output is a strong pass and the process ends.

[0188] According to this embodiment, the scan must be completed for all layers to be scanned, that is, the failed bits must be counted to the last layer. In other words, if the FBC exceeds the BSPF threshold, the bit scanning operation cannot be stopped, as is the case in the embodiment described above. However, in an alternative embodiment, between steps 1704 and 1706, an additional decision step may be introduced to determine whether the FBC is greater than BSPF_ABSCAN_F. This additional decision step determines whether a strong fail condition has been reached. If the answer at this additional decision step is "yes", the process proceeds directly to step 1712 and the process ends with a strong fail output.

[0189] A fail bit count detector that performs or facilitates the performance of these steps may be incorporated into a range of different circuits within a memory device.

[0190] Another aspect of the disclosure relates to using analog bit scan operations, such as any of the techniques and implementations discussed above, to improve erase performance and improve the operating life or endurance of a memory device.

[0191] An erase operation involves changing a memory cell from its corresponding programmed data state (e.g., Fig. 9 The erase operation is performed by erasing the memory cells to change the data states S1 to S7 in the memory cells to the erased state Er so that the memory cells can be reprogrammed to contain new data. During the erase operation, it is desirable to reduce the threshold voltage Vt of the memory cells to an upper limit below the erase-verify level representing the erased data state Er. The erase operation typically includes multiple erase cycles, each erase cycle including an erase portion followed by an erase-verify operation. The erase operation is typically performed at the memory block or sub-block level rather than the word line level. In other words, one memory block or sub-block including many word lines is erased at one time.

[0192] In the erase portion of the erase cycle, circuits in the memory device apply an erase voltage VERA to the strings of the memory block via the bit lines and / or source lines, while applying a very low voltage (e.g., zero volts) to the word lines of the memory block to provide a positive channel-to-gate voltage difference for the memory cells of the memory block to tunnel holes from the channel to the charge storage material of the memory cell, thereby reducing the threshold voltage Vt of the memory cell. In the verify portion, a verify voltage is applied to the word line, and a sensing circuit is used to sense the current in the NAND string to determine whether the memory cell has been sufficiently erased. If an insufficient number of memory cells have been sufficiently erased, the process is repeated in one or more subsequent erase cycles until the erase-verify operation passes. Between erase cycles, the erase voltage can be increased by a step size dVERA, similar to how the programming voltage VPGM is increased by dVPGM between programming cycles.

[0193] Unnecessary deep erase in which the threshold voltage Vt of a memory cell is significantly below the erase-verify voltage can reduce the endurance of the memory device and / or cause degradation of data retention capabilities. It is also known that as programming and erase cycles increase, the erasure of memory cells becomes slower than when the memory device is at the beginning of its operating life, and additional erase pulses may be required to bring its threshold voltage Vt below the erase-verify voltage. Each time the number of erase cycles that pass erase-verify increases with program-erase cycles, the erase depth is reduced by approximately the same voltage magnitude as the step size dVERA. For example, Fig. 20 is a graph of erase upper tail versus program-erase (PE) cycles in an exemplary memory device, and Fig.21 is a graph of erase cycles to complete erase versus program-erase cycles. The erase-verify levels are shown, and the "over-erase" voltage range is highlighted. As shown, due to the slow erase speed of the memory cell, the erase upper tail increases with the program-erase cycle until the upper tail reaches the erase-verify level, at which point an additional erase cycle is triggered and added to each subsequent erase operation. When this occurs, the erase upper tail falls into the "over-erase" region at approximately the step size dVERA, thereby increasing degradation in the memory cell. One way to avoid over-erase is to use a small step size dVERA, but this may come at the expense of erase time (performance) because the method will require additional erase cycles to complete the erase operation.

[0194] According to aspects of the present disclosure, an analog bit scan operation is utilized in each erase cycle to achieve a more finely controlled erase depth with minimal performance loss. According to these techniques, the erase voltage step size dVERA that the erase voltage VERA increases between erase cycles is set according to the output of the analog bit scan operation. In some embodiments, if the output of the analog bit scan operation is a weak failure (i.e., the threshold voltage Vt of the memory cell is slightly higher than the erase-verify voltage), the erase voltage VERA can be increased by a reduced step size (e.g., dVERA / 2) and the erase-verify operation can be skipped in the final erase cycle. This allows for improved erase accuracy and a reduction in the threshold voltage Vt of memory cells reaching an over-erased region.

[0195] Fig. 22 2200 is a flowchart depicting the steps of erasing a memory block or sub-block according to one embodiment of these techniques. These steps may be performed by a controller, processor or processing device or any other circuitry executing instructions stored in a memory and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0196] At step 2202, an erase pulse at an erase voltage VERA is applied to a NAND string of a memory block that is itself to be completely erased or that contains a sub-block to be erased. The VERA voltage may be applied to: the drain side of the NAND string; the source side of the NAND string; or both the source side and the drain side. At step 2204, an erase-verify operation is performed on the memory block or sub-block to determine whether a sufficient number of memory cells in the memory block or sub-block have a threshold voltage Vt below the erase-verify voltage. Also, at this step, an analog bit scan operation is performed to determine whether the erase-verify is a strong fail, a weak fail, or a pass.

[0197] At decision step 2206, it is determined whether the analog bit scan operation passed. If the answer or output at decision step 2206 is strong fail, the process proceeds to step 2208. Fig.23A An exemplary threshold voltage distribution is shown that will produce a strong fail result because a larger number of memory cells have a threshold voltage Vt that is higher than the erase-verify voltage. At step 2208, the erase voltage VERA is increased by a first step size dVERA. The process then returns to step 2202 to begin another erase cycle.

[0198] If the output at decision step 2206 is a weak fail, the process proceeds to step 2210 . Fig. 23BAn exemplary threshold voltage distribution Vt is shown that will produce a weak fail output because a moderate number of memory cells have a threshold voltage Vt that is higher than the erase-verify voltage. At step 2210, the erase voltage VERA is increased by a second step size (e.g., dVERA / 2) that is smaller than the first step size. In other embodiments, the second step size can be any suitable voltage that is smaller than the first step size dVERA. At step 2212, an erase pulse at the erase voltage VERA is applied to the memory block without a subsequent erase-verify operation. The erase operation then ends.

[0199] If the output at decision step 2206 is a pass (strong pass or weak pass), then the erase operation ends there without any more erase cycles. Fig.23C An exemplary threshold voltage Vt distribution is shown that will produce a pass output because a large number of memory cells have a threshold voltage Vt below the erase-verify voltage, ie, very few memory cells have failed erase-verify.

[0200] Now go to Fig.24 In the flowchart 2400 of the embodiment of the present invention, the steps of erasing the memory cells of a memory block or sub-block are depicted with similar numbers, separated by the prefix "24" instead of "22", so as to identify the steps corresponding to the steps of erasing the memory cells of a memory block or sub-block. Fig. 22 The implementation scheme corresponds to the steps of Fig. 22 The difference of the embodiment of is that: in the case where the output at 2406 is a weak pass, the process proceeds to step 2410 instead of ending. Moreover, after the erase pulse at step 2412, at step 2414, an erase-verify operation is performed, followed by an analog bit scan operation. At step 2416, it is determined whether the analog bit scan passes. The process ends only if the output at step 2416 is a strong pass. If the output at step 2416 is a fail or a weak pass, the process returns to step 2410 to start another erase-verify cycle with a reduced erase voltage step size (dVERA / 2). In this embodiment, the applied erase pulse is always verified with an erase verify VERA pulse before the process ends. In some alternative embodiments, if the output at step 2406 is determined to be a strong pass or a weak pass, the process ends and only a weak fail output causes the process to proceed to step 2410.

[0201] In some alternative embodiments, more than two step size voltages dVERA may be used, where the step size is selected based on how strongly the bit scan operation passes or fails. In other embodiments, the erase intensity may be adjusted by changing the erase duration or bias of the BL, source voltage, or other nodes.

[0202] like Fig.25As shown, over-erasure is avoided by reducing the step size voltage when the bit scan is almost failed, thereby protecting the memory cell from damage. Therefore, the overall endurance and performance of the memory device are improved. Fig.25 Similar to Fig. 20 , but the techniques of these exemplary embodiments have been applied. As shown, over-erasure is substantially eliminated.

[0203] Another aspect of the present disclosure relates to a specific implementation of smart PCV during programming operations using analog bit scanning. When programming to many data bits per memory cell (e.g., TLC or QLC), not all data states are verified in each programming cycle. Instead, in early programming cycles, only early data states (e.g., S1 or S2) are verified, and in later programming cycles, only later data states (e.g., S6 or S7) are verified. "Smart PCV" is a programming technique in which a memory device dynamically decides when to begin verifying each of the data states being programmed during a programming operation, i.e., in which programming cycle to start verification. For example, in some specific implementations, smart PCV indicates that verification should begin for the S2 data state in a programming cycle after some memory cells have passed verification in the S1 data state.

[0204] Now turn to Fig.26 , threshold voltage Vt distributions of multiple memory cells are shown after a first programming loop 2600, a second programming loop 2602, a third programming loop 2604, a fourth programming loop 2606, and a fifth programming loop 2608. According to a smart PCV implementation in which verification of data state Sn is started when some memory cells begin to pass verification at data state Sn-1, verification of data state S2 will begin after the second programming loop 2602, and verification of data state S3 will begin after the third programming loop 2604. However, in this exemplary smart PCV technique, some over-programming of memory cells being programmed to the S3 data state may occur in the fourth programming loop 2606. In other words, some memory cells intended for the S3 data state are unintentionally programmed into the voltage range associated with the S4 data state. This is also Fig. 27 , which shows that some over-programming occurs in the fourth pulse. One solution to this is to perform additional verification operations, for example, automatically starting verification for each data state more quickly. However, this more cautious approach reduces performance by requiring unnecessary verification pulses when over-programming does not occur.

[0205] According to some embodiments of the present disclosure, a smart PCV technique is provided that more effectively prevents over-programming while avoiding unnecessary verification operations. Specifically, after each verification operation, an analog bit scan operation is performed to determine whether the verification is a strong pass (zero or very few memory cells pass verification), a weak pass (many memory cells pass verification, but less than a threshold), a weak fail (the number of memory cells that pass verification is slightly higher than a threshold), or a strong fail (the number of memory cells that pass verification is significantly higher than a threshold). The output of the analog bit scan operation indicates which data states are verified during subsequent programming cycles. In this embodiment, the number of memory cells that pass verification (rather than fail) is the number compared to the threshold.

[0206] Fig.28 2800 is a flowchart including steps for programming memory cells of a selected word line WLn according to an exemplary embodiment of the present disclosure, wherein an analog bit scan operation is utilized to establish when to begin verification for certain data states. These steps may be performed by a controller, processor or processing device or any other circuitry executing instructions stored in a memory and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0207] At step 2802, the program voltage VPGM is set to an initial level VPGMU, and verification is set to start for the first programmed data state S1. At step 2804, a VPGM pulse is applied to the selected word line WLn. At step 2806, a verification operation is performed for all data states currently being verified. In the first case, only data state S1 is verified. However, in later instances, additional data states will be verified, and some data states that have completed programming will not be verified, for example, when programming of data state S1 is completed, then verification of data state S1 will not be performed at step 2806.

[0208] Furthermore, at step 2806, an analog bit scan operation is performed to determine how many memory cells of the highest data state SN being verified in this programming loop have passed verification. For this analog bit scan, a "pass" occurs when fewer memory cells than a threshold pass verification, and a "fail" occurs if more memory cells than a threshold pass verification. The more memory cells that pass verification, the weaker the pass or the stronger the fail. Conversely, the fewer memory cells that pass verification, the stronger the pass or the weaker the fail. Furthermore, an analog bit scan is performed only for the highest data state being verified in a given programming loop, i.e., an analog bit scan operation is not performed for data state SN-1.

[0209] At decision step 2808, it is determined whether the analog bit scan operation has passed the highest data state being verified (i.e., SN). If the output at decision step 2808 is a strong pass, then at step 2814, the programming voltage VPGM is incrementally increased (i.e., VPGM=VPGM+dVPGM). The process then returns to step 2804 to begin the next programming cycle without adding any new data states to be verified.

[0210] If the output at decision step 2808 is a weak fail or a weak pass, then at step 2812, the highest data state SN being verified is incremented by one (i.e., SN=SN+1). The process then proceeds to step 2814 to incrementally increase the programming voltage VPGM, and then proceeds to step 2804 to start the next programming cycle.

[0211] If the output at decision step 2808 is a strong fail, then at step 2810, the highest data state SN being verified is incremented by two (i.e., SN=SN+2). Thus, verification of two additional data states is initiated under this condition. The process then proceeds to step 2814 to incrementally increase the programming voltage VPGM, and then proceeds to step 2804 to begin the next programming cycle.

[0212] These steps are followed until verification of the last data state (eg, S7 in the case of TLC or S15 in the case of QLC) begins.

[0213] In some programming operations, a smart verify operation is performed during the first pair of programming loops to improve programming performance (i.e., reduce verification time). During a smart verify programming loop, only a portion of a selected word line (e.g., one string) is selected to obtain a suitable SV_VPGM voltage, which is then used as the initial programming voltage SV_VPGM during programming of other word lines or strings within the same memory block. Smart verify improves performance by optimizing the initial VPGM voltage during programming of those other word lines, rather than setting the initial VPGM voltage to an overly conservative level that requires unnecessary programming cycles or an overly aggressive level that may result in over-programming. During smart verify, the programming voltage VPGM is started at a pre-trimmed and conservative initial voltage VPGMU, and verification is started with a smart verify voltage Vsv that is equal to or lower than the verification voltage for the first programmed data state (e.g., S1). Reference Fig.29 During an exemplary three-level cell (TLC) programming operation, a smart verification operation is performed on a selected word line WLn until a predetermined threshold of a memory cell has a V exceeding that determined by a bit scan operation. SVThe programming voltage in the programming loop is saved to the latch as SV_VPGM when the predetermined threshold is exceeded for later use as the initial programming voltage VPGM for other programming operations on other strings and / or word lines in the storage block. In all subsequent programming loops, the verification voltage applied during the verification portion is the verification voltage Vv1 to Vv7 associated with the programmed data state (or Vv2 to Vv7 if the smart verification voltage is Vv1) and the verification ends at Vsv. In this example, the smart verification fails after three programming loops, and in the fourth programming loop, the appropriate verification voltage Vvn is used to verify the next data state Sn (e.g., S1 or S2). When programming the next string or word line begins, the programming voltage applied during the first programming loop is SV_VPGM. In some cases, two smart verification voltages (smart verification low Vsvl and smart verification high Vsvh) may be implemented to more accurately set SV_VPGM. However, this may increase the time of the process by requiring two verify pulses (one for Vsvl and one for Vsvh) instead of just one. Therefore, the improved resolution of SV_VPGM may come with a performance loss.

[0214] Aspects of the present disclosure are directed to a smart verify technique that allows a smart verify programming voltage SV_VPGM to be more accurately set using analog bit scan without the performance penalty of verifying at both a smart verify low Vsvl and a smart verify high Vsvh. Fig.30 3000 is a flowchart depicting steps for programming a memory block or sub-block according to one embodiment of these smart verification techniques. These steps may be performed by a controller, processor or processing device or any other circuitry executing instructions stored in a memory and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0215] At step 3002, a smart verification operation is started by setting the programming voltage VPGM to a predetermined initial voltage VPGMU. At step 3004, a programming loop is performed on the selected word line, the programming loop including a programming pulse followed by a verification pulse at a low smart verification voltage Vsvl. Then, the number of bits that pass the verification is counted in an analog bit scan operation and compared to a predetermined threshold. In some embodiments, a loop counter loop may be kept to count the number of programming loops to complete the analog bit scan operation. At decision step 3006, it is determined whether the analog bit scan operation passes, that is, whether the number of memory cells that pass the verification is less than a predetermined threshold?

[0216] If the answer at decision step 3006 is "yes" (pass), then the output of the analog bit scan operation may be a strong pass or a weak pass. Fig.31A An exemplary threshold voltage distribution for a weak pass condition where a small number of bits pass verification but the number is less than a predetermined threshold is depicted. If the output of the analog bit scan operation is a weak pass, then at step 3008, the program voltage VPGM is incrementally increased by the first step size dVPGM_SV1 (VPGM=VPGM+dVPGM_SV1), and then the process returns to step 3004 to start another programming cycle.

[0217] Fig.31B An exemplary threshold voltage distribution for a strong pass condition in which no or very few memory cells pass verification is depicted. If the output of the analog bit scan operation is a strong pass, then at step 3007, the program voltage VPGM is incrementally increased by a second step size dVPGM_SV2 greater than the first step size dVPGM_SV1 (VPGM=VPGM+dVPGM_SV2). The process then returns to step 3004 to begin another programming cycle. Thus, the selected word line WLn receives a next VPGM pulse that is stronger than a weak pass in response to the strong pass.

[0218] If the answer at decision step 3006 is "no" (failure), the output of the analog bit scan operation may be a weak fail or a strong fail. Fig.31C The threshold distribution of a weak fail condition where the number of passed bits slightly exceeds a predetermined threshold is depicted.If the failure of the analog bit scan operation is a weak fail, then at step 3010, the smart verification voltage SV_VPGM is set to the program voltage VPGM.

[0219] Fig.31D Depicted is a threshold voltage distribution for a strong fail condition in which the number of passed bits greatly exceeds a predetermined threshold. If the output of the analog bit scan operation is a strong fail, then at step 3012, the smart verification voltage SV_VPGM is set to a level less than VPGM to avoid over-programming in other word lines. Specifically, the smart verification voltage SV_VPGM is set to VPGM-(1 / 2)*dVPGM. Because the step size dVPGM is dynamically adjusted based on the output of the analog bit scan operation, in some embodiments, SV_VPGM can be increased by the result of dVPGM_SV*(cycle-1). In the example, if the operation results in a strong pass for one programming cycle and a weak pass for two programming cycles, followed by a strong fail, SV_VPGM is set to VPGMU+1*dVPGM_SV2+2*dVPGM_SV1-(1 / 2)*dVPGM_SV1.

[0220] After step 3010 or 3012, programming is performed in the selected word line WLn to completion at step 3014. Then, programming can continue for the remaining strings of the selected word line WLn and / or additional word lines in the memory block while using SV_VPGM as the programming voltage in the first programming loop.

[0221] like FIG. 31A to FIG. 31D As shown, according to these techniques, the smart verification programming voltage SV_VPGM is more accurately established, where there is only a single verification pulse at the low smart verification voltage Vsvl, that is, only one verification pulse is required for each smart verification cycle in the smart verification cycle. This improves performance by reducing programming time compared to using two verification pulses (one at the low smart verification voltage Vsvl and one at the high smart verification voltage Vsvh).

[0222] In addition, by increasing the program voltage VPGM with a larger step size dVPGM_SV2 in response to a strong pass output, the smart verification voltage SV_VPGM can be obtained in fewer programming cycles. In other words, the magnitude of the step size dVPGM is dynamically set based on the output of the analog bit scan operation. However, in some embodiments, step 3007 can be skipped, and any pass (strong or weak) at decision step 3006 can proceed to step 3008.

[0223] Fig.32 3200 is a flowchart depicting steps for programming a memory block or sub-block according to another embodiment of these smart verification techniques, thereby utilizing analog bit scanning and two smart verification voltages Vsvl, Vsvh to greatly improve SV_VPGM accuracy. These steps may be performed by a controller, processor or processing device or any other circuitry executing instructions stored in a memory and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0224] At step 3202, a smart verification operation is started by setting the program voltage VPGM to a predetermined initial voltage VPGMU. At step 3204, a program loop is performed on the selected word line WLn, the program loop including a programming pulse followed by a verification operation at a low smart verification voltage Vsvl. Then, the number of bits that pass the verification is counted in the analog bit scanning operation and compared with a predetermined threshold. Moreover, at step 3204, the loop counter loop is kept. At decision step 3206, it is determined whether the analog bit scanning operation passes, that is, whether the number of passed bits is less than a predetermined threshold.

[0225] If the answer is "yes" (pass) at decision step 3206, the output of the analog bit scan operation can be a strong pass or a weak pass. If the output of the analog bit scan operation is a weak pass, then at step 3208, the program voltage VPGM is incrementally increased by the first step size dVPGM_SV1 (VPGM=VPGM+dVPGM_SV1), and then the process returns to step 3204 to start another programming cycle.

[0226] If the output of the analog bit scan operation is a strong pass, then at step 3207, the program voltage VPGM is incrementally increased by a second step size dVPGM_SV2 greater than the first step size dVPGM_SV1 (VPGM=VPGM+dVPGM_SV2). The process then returns to step 3204 to begin another programming loop.

[0227] If the answer at decision step 3206 is "No" (failure), then at step 3210, another program-verify cycle is performed, but in this cycle, the verify voltage is the high smart verify voltage Vsvh.

[0228] At decision step 3212, it is determined whether the analog bit scan operation passes, i.e., whether the number of passed bits is less than a predetermined threshold. The output of the bit scan operation can be either pass or fail. If the output is pass, then at step 3214, the smart verification voltage SV_VPGM is set to VPGM plus dVPGM_SV times the cycle minus 1 (i.e., SV_VPGM=VPGM+dVPGM_SV*(cycle-1)). Therefore, with Fig.30 Compared with the implementation scheme, Fig.32 In the embodiment of the present invention, SV_VPGM is based on (cycle-1). If the output is "fail", then at step 3216, the smart verification voltage SV_VPGM is set to the same value, but further reduced by half the step size (i.e., SV_VPGM=VPGM+dVPGM_SV*(cycle-1)-(1 / 2)*dVPGM_SV). This minimizes the risk of over-programming in other strings and word lines of the memory block.

[0229] After step 3214 or step 3216, programming of the memory cells of the selected word line WLn may be performed at step 3218. Programming of memory cells of other strings and / or word lines in the same memory block may use SV_VPGM as the programming voltage in the first programming loop. In this embodiment, SV_VPGM is set based on the number of weak pass and strong pass outputs at decision step 3206 and whether the output at decision step 3212 is pass or fail.

[0230] This embodiment allows for improved accuracy and improved performance in setting SV_VPGM by reducing the number of programming cycles necessary to complete an analog bit scan for a low smart verify voltage Vsvl, compared to other techniques with two smart verify voltages.

[0231] according to Fig.33 In another embodiment depicted in flowchart 3300 of , the smart verification operation includes verifying to a low smart verification voltage Vsvl by binary bit scanning (the only output options are pass and fail), and then, an analog bit scanning operation may be applied to verify at a high smart verification voltage Vsvh. These steps may be performed by a controller, processor or processing device or any other circuitry executing instructions stored in a memory and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0232] At step 3302, the program voltage VPGM is set to a predetermined initial program voltage VPGMU. At step 3304, a program loop is performed on the selected word line WLn. During the verify portion of the program loop, the verify voltage is a low smart verify voltage Vsvl. At decision step 3306, it is determined whether the binary bit scan operation passes, i.e., is the number of memory cells that pass verification less than a predetermined threshold?

[0233] If the output at decision step 3306 is "pass", then at step 3308, the program voltage VPGM is incrementally increased (i.e., VPGM=VPGM+dVPGM_SV). The process then returns to step 3304 to start the next programming cycle. If the output at decision step 3306 is "fail", then at step 3310, another program-verify operation is performed, but this time, verification at Vsvl is skipped and the verification voltage is the high smart verification voltage Vsvh.

[0234] At decision step 3312, determine whether the analog bit scan operation passes. Four outputs are possible: strong pass, weak pass, weak fail, and strong fail. The output determines what voltage the smart verification programming voltage SV_VPGM is set to. If the output at decision step 3312 is a strong pass, then at step 3314, the smart verification programming voltage SV_VPGM is set to the programming voltage VPGM. If the output at decision step 3314 is a weak pass, then at step 3316, the smart verification voltage SV_VPGM is set to VPGM minus one quarter of the step size dVPGM_SV (i.e., SV_VPGM=VPGM-(1 / 4)*dVPGM_SV). If the answer at decision step 3312 is a weak fail, then at step 3318, the smart verification voltage SV_VPGM is set to VPGM minus half of the step size dVPGM_SV (i.e., SV_VPGM=VPGM-(1 / 2)*dVPGM_SV). If the answer at decision step 3312 is strong fail, then at step 3320, the smart verification voltage SV_VPGM is set to VPGM minus three quarters of the step size dVPGM_SV (i.e., SV_VPGM=VPGM-(3 / 4)*dVPGM_SV). In other embodiments, the specific voltage options may differ from those of the exemplary embodiment, where the magnitude decreases as the number of memory cells passing verification increases.

[0235] After step 3314, step 3316, step 3318, or step 3320, programming of memory cells of the selected word line WLn may proceed at step 3322. Programming memory cells of other strings and / or word lines in the same memory block may use SV_VPGM as the programming voltage in the first programming loop.

[0236] according to Fig.34 In another embodiment depicted in flowchart 3400 of , the resolution of the smart verification programming voltage SV_VPGM is further improved by performing analog bit scan operations for both the low smart verification voltage Vsvl and the high smart verification voltage Vsvh. These steps may be performed by a controller, processor or processing device or any other circuitry executing instructions stored in a memory and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0237] exist Fig.34 In the embodiment of the present invention, steps 3402 to 3410 are respectively the same as steps 3302 to 3310, except that the analog bit scan operation for the smart verification low voltage Vvsl is now an analog bit scan operation instead of a binary bit scan operation.

[0238] At decision step 3412, the analog bit scan operation has five possible outputs, allowing for improved resolution of the smart verification voltage SV_VPGM. If the Vsvh analog bit scan operation of step 3412 produces a strong pass output and the output of the Vsvl bit scan operation at step 3406 is a weak fail, then at step 3414, the smart verification programming voltage SV_VPGM is set to VPGM. Fig.35A Threshold voltage Vt distributions are depicted for exemplary conditions with a strong pass output for Vsvh and a weak fail output for Vsvl.

[0239] If the Vsvh analog bit scan operation at step 3412 produces a strong pass output and the output of the Vsvl bit scan operation at step 3406 is a strong fail, then at step 3416, the smart verification programming voltage SV_VPGM is set to VPGM minus one quarter of the step size dVPGM_SV (i.e., SV_VPGM=VPGM-1 / 4*dVPGM_SV). Fig.35B Exemplary threshold voltage Vt distributions that can produce this result are depicted.

[0240] If the Vsvh analog bit scan operation of step 3412 produces a weak pass output, then at step 3418, the smart verification programming voltage SV_VPGM is set to VPGM minus three eighths of the step size dVPGM_SV (ie, SV_VPGM=VPGM-(3 / 8)*dVPGM_SV). Fig.35C Exemplary threshold voltage Vt distributions that can produce this result are depicted.

[0241] If the analog bit scan operation of step 3412 produces a weak fail output, then at step 3420, the smart verification programming voltage SV_VPGM is set to VPGM minus half of the step size dVPGM_SV (ie, SV_VPGM=VPGM-1 / 2*dVPGM_SV). Fig.35D Exemplary threshold voltage Vt distributions that can produce this result are depicted.

[0242] If the analog bit scan operation of step 3412 produces a strong fail output, then at step 3422, the smart verification programming voltage SV_VPGM is set to VPGM minus three quarters of the step size dVPGM_SV (ie, SV_VPGM=VPGM-3 / 4*dVPGM_SV). Fig.35E Exemplary threshold voltage Vt distributions that can produce this result are depicted.

[0243] In some embodiments, Fig.30 , Fig.32 , Fig.33 and Fig.34Certain aspects of the embodiments of can be combined into one process. For example, in Fig.30 and Fig.32 The dynamic step size dVPGM found in the implementation scheme can be incorporated into Fig.33 Implementation plan or Fig.34 In the implementation plan.

[0244] Fig.48 4800 is a flowchart depicting steps for programming a memory block or sub-block according to another embodiment of these smart verification techniques, thereby utilizing analog bit scanning and two smart verification voltages Vsvl, Vsvh to prevent over-programming during smart verification operations. These steps may be performed by a controller, processor or processing device or any other circuitry executing instructions stored in a memory and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0245] At step 4802, a programming operation is started by setting the program voltage VPGM to an initial level VPGMU to start the step of a smart verification operation. At step 4804, a program loop including both a VPGM pulse and a verification operation is performed on the selected word line WLn, and the number of memory cells that pass the verification operation is counted and compared with a predetermined threshold in an analog bit scan operation. In this step, a verification operation is performed using a smart verification low voltage Vvsl. Also, at step 4804, the number of programming loops is counted.

[0246] At decision step 4806, it is determined whether the analog bit scan operation has passed (is the number of memory cells passed less than a predetermined threshold?). If the output at decision step 4806 is passed, then at step 4808, the program voltage VPGM is incrementally increased by a step size dVPGM_SV (i.e., VPGM=VPGM+dVPGM_SV), and then the process returns to step 4804 to become the next programming cycle.

[0247] If the output at decision step 4806 is "FAIL", then at decision step 4810, it is determined whether a failure of the analog bit scan operation occurred during the first programming loop. If the answer at decision step 4810 is "YES" and the output of the analog bit scan operation is a strong fail, then the selected word line WLn is at risk of over-programming some of the memory cells intended for the first programmed data state (e.g., S1). At step 4812, the memory device records the programming operation as being at risk of over-programming. The remaining programming operations for the selected word line WLn are aborted, and programming proceeds to the next word line to be programmed.

[0248] If the answer at decision step 4810 is no or yes and the output of the analog bit scan operation is a weak fail, then the selected word line is at a relatively low risk of over programming and the process proceeds to step 4814. At step 4814, a verify operation is performed using the smart verify high voltage Vvsh.

[0249] At decision step 4816, it is determined whether the bit scan operation for the verification operation at the smart verification high voltage Vvsh passes (the number of passed memory cells is less than a predetermined threshold). If the output at decision step 4816 is pass (the number of passed memory cells is less than a predetermined threshold), then at step 4818, the smart verification programming voltage SV_VPGM is set to VPGM. If the output at decision step 4816 is fail, then the smart verification programming voltage SV_VPGM is set to VPGM minus half of the step size dVPGM_SV (i.e., SV_VPGM=VGPM-(1 / 2)*dVPGM_SV).

[0250] After step 4818 or step 4820, at step 4822, the loop counter may be reset and programming may then continue programming the memory cells of the selected word line WLn to their respective intended data states. The smart verification programming voltage SV_VPGM may then be used as an initial programming voltage when programming other strings of the selected word line WLn and / or when programming other word lines in the selected memory block.

[0251] This implementation allows over-programming to be detected during programming so that data intended for a selected word line WLn can be correctly programmed to a different word line instead of incorrectly programmed to the selected word line WLn.

[0252] Fig.49 4900 is a flowchart of steps for programming a memory block or sub-block according to yet another embodiment of these smart verification techniques, thereby utilizing analog bit scanning and two smart verification voltages Vsvl, Vsvh to prevent over-programming during smart verification operations. These steps may be performed by a controller, processor or processing device or any other circuitry executing instructions stored in a memory and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0253] Steps 4902 to 4906 are similar to steps 4802 to 4808 of the embodiment described above. However, if the output at decision step 4906 is a fail, the process proceeds to step 4910. At step 4910, a verification operation is performed using the smart verification high voltage Vsvh, and the number of memory cells that pass the verification is counted in the analog bit scan operation. Also, at step 4910, the programming loop is counted.

[0254] At decision step 4912, it is determined whether the analog bit scan operation passes, that is, whether the number of memory cells that pass verification is less than a predetermined threshold? If the output at decision step 4912 is pass (strong pass or weak pass), then at step 4814, the smart verification voltage programming voltage SV_VPGM is set to VPGM.

[0255] If the output at decision step 4912 is a fail (strong fail or weak fail), then at decision step 4916, it is determined whether the fail at decision step 4906 occurred in the first loop. If the answer at decision step 4916 is "no" or "yes" and the analog bit scan operation output at decision step 4912 is a weak fail, the risk of over-programming is low and the process proceeds to step 4918. At step 4918, the smart verification programming voltage SV_VPGM is set to VPGM-(1 / 2)*dVPGM_SV.

[0256] If the output at decision step 4916 is "yes" and the output of the analog bit scan operation at decision step 4912 is also a strong fail, then the risk of over-programming is high. At step 4920, the smart verification programming voltage SV_VPGM is set to VPGM-dVPGM_SV_OP. dVPGM_SV_OP may be different from the step size dVPGM_SV. Also, at step 4920, the over-programming status may be recorded so that the memory device may take additional precautions before checking for over-programming before completing a programming operation.

[0257] After steps 4914, 4918, or 4920, at step 4922, the loop counter is reset and the programming operation continues to program all memory cells of the selected word line WLn to their respective intended data states.

[0258] As discussed above, in many program-verify operations, verification of each data state begins based on a fixed programming loop count or based on an intelligent PCV determination, where a fast programming bit of one data state SN is detected to determine when to begin verification of the next data state or two data states (e.g., SN+1 and SN+2). Similarly, verification of each data state may end when the number of slow bits is within the bit scan criteria. The end of one data state is detected each time. In other words, once verification for data state SN is completed, detection for data state SN+1 may begin, and so on. Fig.36A table for an exemplary TLC programming operation is included and identifies which data states (S1 to S7) are verified in which programming loops (Loops 1 to 12). In the table, a "0" indicates that verification is not performed for a given combination of programming loop and data state, and a "1" indicates that verification is performed for a given combination of programming loop and data state. In this example, a total of twenty-two (22) verify pulses are applied to complete programming.

[0259] According to another aspect of the present disclosure, an analog bit scan operation is utilized to allow early termination of verification for each data state, while still controlling the slow bits to ensure that they receive sufficient programming so that their threshold voltages Vt are above the corresponding verification voltages Vv. In other words, early program-verify termination parameters are established based on the output of the analog bit scan operation. By reducing the number of verification pulses performed, programming performance is improved with little or no reliability loss.

[0260] The analog bit scan operation is performed after each verify pulse for one of the data states being verified in the cycle. Depending on the results of the analog bit scan operation, programming to that particular data state may continue without change, programming to that data state may stop, or programming to that data state may continue in one or more programming cycles without verification. For example, Fig.37 The table shows four options for a given data state SN based on the output of the simulated bit scan operation. In this example, if the output of the simulated bit scan operation for data state SN is a strong fail (the fail bit greatly exceeds the BSPF threshold), then programming continues unchanged in subsequent programming cycles, i.e., verification of data state SN and any other data states being verified is performed. Fig.39 , curve 3900 shows the threshold voltage Vt distribution of multiple memory cells under a strong fail condition. If the output of the analog bit scan operation for data state SN is a weak fail (the fail bit slightly exceeds the BSPF threshold), the verification of data state SN stops. In the next two programming cycles, the non-inhibited memory cells being programmed to data state SN are programmed, but there are no verification pulses for data state SN after those programming pulses. These programming cycles with programming pulses and no verification are referred to as "blind pulses" hereinafter. Fig.39 In FIG. 3 , curve 3902 shows the threshold voltage Vt distribution of multiple memory cells under weak fail conditions. If the output of the analog bit scan operation for data state SN is a weak pass or a strong pass (fail bit is less than the BSPF threshold), the verification of data state SN stops. In a subsequent programming cycle, the non-inhibited memory cells being programmed to data state SN are programmed with blind pulses. Fig.39 In FIG. 3 , curve 3904 shows the threshold voltage Vt distribution of multiple memory cells under the pass condition. Fig.38 As shown in the table of , by utilizing an analog bit scan operation, in this example, one verify pulse is eliminated for each of the seven (7) data states and a total of fifteen (15) verify pulses are performed. Fig.36 The performance is significantly improved compared to the twenty-two (22) verification pulses in the example of .

[0261] In some embodiments, the BSPF threshold may be adjusted to allow for additional resolution (more possible outputs) for a pass condition or a fail condition. For example, if the BSPF threshold is reduced to BSPF_Low, which is less than the baseline BSPF threshold, then in addition to a single pass option, three possible fail options are available (weak fail, medium fail, and strong fail). For example, Fig.40 A table of possible outputs for simulating a bit scan operation is depicted, wherein the BSPF threshold is set to the BSPF_Low level and associated actions are taken for each output option. In this example, in response to a strong fail output, programming then continues without change in subsequent programming cycles. In response to a medium fail output, three blind pulses are then programmed in the subsequent three programming cycles to further program the slow bit, but the programming amount is less than the strong fail output. In response to a weak fail output, two blind pulses are then programmed in the subsequent two programming cycles to further program the slow bit, but the programming amount is less than the weak fail output. In response to a pass output, one blind pulse is then programmed in the subsequent programming cycles to further program the slow bit, but the programming amount is less than the weak fail output. In some embodiments, additional output options are possible. The lower BSPF threshold of this embodiment also allows improved performance by reducing the bit scan operation time.

[0262] exist Fig.41 In an embodiment of the present invention, the BSPF threshold is set to BSPF_High, which is greater than the baseline BSPF threshold. In this embodiment, in addition to the single fail option, three possible pass options are available (weak pass, medium pass, and strong pass). In this example, in response to a fail output, programming then continues unchanged in subsequent programming cycles. In response to a weak pass output, programming is then performed with three blind pulses in the subsequent three programming cycles to further program the slow bits. In response to a medium pass output, programming is then performed with two blind pulses in the subsequent two programming cycles to further program the slow bits, but the programming amount is less than the weak pass output. In response to a strong pass output, programming is then performed with one blind pulse in the subsequent programming cycles to further program the slow bits, but the programming amount is less than the medium pass output. In some embodiments, additional output options are possible.

[0263] The blind pulses of the exemplary embodiments described above may result in "Vt widening," or a condition in which the threshold voltage Vt distribution of one or more of the data states is widened. The threshold voltage Vt distribution may be tightened by verifying at two levels: verifying low VL and verifying high VH. If the threshold voltage Vt of a memory cell is sensed to be between VL and VH, then programming of that memory cell is nearly complete. Therefore, on a subsequent programming pulse, a quick pass write (QPW) voltage is applied to the bit line coupled to that memory cell to slow down programming of that memory cell so that the voltage may be more accurately programmed to a threshold voltage Vt slightly above the verifying high VH voltage, while allowing other memory cells in the selected word line WLn to be programmed at high speed. Fig.42 Depicted are voltages applied to various components of a memory block during a programming pulse, where some of the memory cells have a threshold voltage Vt between VL and VH and receive a QPW bias voltage applied to their respective bit lines. Bit lines coupled to memory cells having a threshold voltage Vt lower than VL receive a low VSS voltage.

[0264] According to additional aspects of the present disclosure, after verifying the low VL voltage and / or verifying the high VH voltage, an analog bit scan operation is performed. The result of the one or more analog bit scan operations indicates whether programming in a subsequent programming cycle is to be performed at full speed (without QPW bias voltage) or at a reduced speed (with QPW bias voltage), and how many blind pulses will also follow.

[0265] exist Fig.43 In the embodiment depicted in the table of , if the threshold voltage Vt of the memory cell is between the verify low VL and the verify high VH, the result of the analog bit scan operation determines how many blind programming pulses with QPW bias will follow. For example, "Option 1" can be used for memory cells with a threshold voltage Vt that is closer to the verify low VL voltage than the verify high VH voltage, and requires four programming pulses at a reduced speed to complete programming. "Option 4" can be used for memory cells with a threshold voltage Vt that is closer to the verify high VH voltage than the verify low VL voltage, and requires only a single programming pulse at a reduced speed to complete programming. Options 2 and 3 can be between Options 1 and 4.

[0266] Similarly, if the threshold voltage Vt of the memory cell is lower than the verify low VL, the memory cell receives four blind programming pulses with an appropriate programming speed. For example, "Option 1" with four fast (VSS) blind programming pulses may be used for memory cells with a threshold voltage Vt significantly lower than the verify low VL voltage, and "Option 2" with one fast (VSS) and three slow (QPW) blind pulses may be used for memory cells with a threshold voltage Vt very close to the verify low VL voltage.

[0267] Fig.43 Options 1 to 4 in the table of may correspond to the four possible options for the analog bit scan operation discussed above. For example, option 1 may correspond to a strong fail output, option 2 may correspond to a weak fail output, option 3 may correspond to a weak pass output, and option 4 may correspond to a strong pass output. In some embodiments, there may be more or less than four options to go along with more or fewer outputs for the analog bit scan operation.

[0268] According to some additional embodiments, the output of the analog bit scan operation can be used to trigger the end of verification at the verification low VL voltage. If the output of the analog bit scan operation for the verification high VH is a medium failure or a weak failure, performance gains can be achieved by terminating verification at the verification low VL voltage (i.e., skipping the verification low VL in subsequent programming cycles). If the output is a medium failure, the verification at the verification low voltage VL is ended for the memory cell with a threshold voltage Vt between the verification low voltage VL and the verification high voltage VH. For memory cells with a threshold voltage lower than the verification low voltage VL, then during a later VPGM pulse, a low VSS voltage is applied to the bit lines coupled to those corresponding memory cells. Slow memory cells with a threshold voltage Vt lower than the verification low voltage VL will still be programmed in one or more subsequent programming cycles. The weak failure output can produce the same output as the medium failure output, or verification can be stopped for both the verification low voltage VL and the verification high voltage VH.

[0269] Another aspect of the present disclosure relates to an SLC programming technique in which an analog bit scan operation is implemented to improve performance. SLC programming is generally similar to TLC or QLC programming as described above, in that programming occurs in one or more programming cycles that typically include a VPGM pulse and a verify operation. In terms of timing, the analog bit scan operation may occur as an independent operation; it may be partially or completely hidden at the end of the verify operation during the discharge period; or it may be partially or completely hidden at the beginning of the subsequent VPGM pulse setup.

[0270] Fig.44 Included is a flowchart 4400 showing steps for programming memory cells of a selected word line WLn to SLC according to an exemplary embodiment of the present disclosure. These steps may be performed by a controller, processor or processing device or any other circuitry executing instructions stored in a memory and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0271] At step 4402, the program voltage VPGM is set to an initial voltage VPGMU. At step 4404, a VPGM pulse is applied to the selected word line WLn to program the non-inhibited memory cells of the selected word line WLn. After the VPGM pulse, a verify operation is performed to compare each memory cell being programmed with a verify voltage (there is only one verify voltage in SLC programming). At step 4406, an analog bit scan operation is performed to compare the number of fail bits (memory cells that failed verification) with a BSPF threshold.

[0272] At decision step 4408, it is determined whether the analog bit scan operation passes. If the output at decision step 4408 is a strong fail (the number of failed bits is significantly greater than the BSPF threshold), then at step 4410, the program voltage VPGM is incrementally increased by a step size dVPGM (i.e., VPGM=VPGM+dVPGM). The process then returns to step 4404 to begin another programming cycle.

[0273] If the answer at decision step 4408 is weak fail (the number of fail bits is slightly greater than the BSPF threshold), then programming is nearly complete. At step 4412, the program voltage VPGM is incrementally increased (VPGM=VPGM+dVPGM) and a single VPGM pulse is applied to the selected word line WLn to further program the non-inhibited memory cells without subsequent verify pulses.

[0274]

[00106] At step 4412, or following a pass output at decision step 4408, the programming operation is completed at step 4414. Programming may now move to the next word line in the memory block.

[0275] Fig.45 Included is a flowchart 4500 showing steps for programming memory cells of a selected word line WLn to SLC according to another exemplary embodiment of the present disclosure. These steps may be performed by a controller, processor or processing device or any other circuitry executing instructions stored in a memory and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0276] At step 4502, the program voltage VPGM is set to an initial voltage VPGMU. At step 4504, a VPGM pulse is applied to the selected word line WLn to program the non-inhibited memory cells of the selected word line WLn. After the VPGM pulse, a verify operation is performed to compare each memory cell being programmed with the verify voltage. At step 4506, an analog bit scan operation is performed to compare the number of fail bits (memory cells that failed verification) with the BSPF threshold.

[0277] At decision step 4508, it is determined whether the analog bit scan operation passes. If the output at decision step 4508 is a strong fail (the number of failed bits is significantly greater than the BSPF threshold), then at step 4510, the programming voltage is increased by the first step size dVPGM_1 (i.e., VPGM=VPGM+dVPGM_1). If the output at decision step 4508 is a weak fail (the number of failed bits is slightly greater than the BSPF threshold), then at step 4512, the programming voltage is increased by the second step size dVPGM_2 (i.e., VPGM=VPGM+dVPGM_2). The second step size dVPGM_2 is smaller than the first step size dVPGM_1, so that the amount by which the programming voltage VPGM increases in response to a weak fail output of the analog bit scan operation is smaller than the amount by which it increases in response to a strong fail output.

[0278] After step 4510 or 4512, the process proceeds to step 4514 and a VPGM pulse is applied to the selected word line without a subsequent verify operation.

[0279]

[00106] At step 4514, or following a pass output at decision step 4508, at step 4516, programming of the selected word line WLn is completed.

[0280] In some embodiments, rather than the step size dVPGM being dependent on the output of the analog bit scan operation, another aspect of programming may be adjusted. For example, in some embodiments, the programming clock (the time the VPGM pulse is held on the selected word line WLn) may be lengthened in response to a strong fail analog bit scan output, and may be shortened in response to a weak fail analog bit scan output. In some other embodiments, the bit line voltage VBLC may also be adjusted based on the output of the analog bit scan operation to control programming speed (e.g., see the discussion above regarding QPW).

[0281] These SLC programming techniques may allow for improvements in performance compared to conventional nPnV SLC programming operations where each programming loop includes both a VPGM pulse and a verify operation.

[0282] Another aspect of the present disclosure relates to the use of analog bit scanning in a programming technique sometimes referred to as STPFINE. Generally speaking, STPFINE involves automatically completing a final data state (e.g., data state S6) after a predetermined number of programming cycles have been completed after a previous data state (e.g., data state S6). Fig. 9, if it has not passed verification before that point. That is, programming is completed even if data state S7 has not passed verification. As discussed in further detail below, the use of analog bit scanning allows dynamic optimization of certain variables, such as the number of programming cycles to be performed after completing the second data state to the last data state and / or the programming voltage in those additional programming cycles. Dynamic optimization of these variables improves performance and / or reliability.

[0283] Fig.46 A flowchart 4600 is included showing the steps for programming memory cells of a selected word line WLn using analog bit scanning in an STPFINE operation. These steps may be performed by a controller, processor or processing device or any other circuitry executing instructions stored in a memory and / or other circuitry described herein that is specifically configured / programmed to perform the following steps.

[0284] At step 4602, the memory cells of the selected word line WLn are programmed to data states S1 to SN-2 (where SN is the last data state to be programmed) in multiple programming loops using the ISPP technique. In an exemplary embodiment where the memory cells of the selected word line are programmed to TLC, at step 4602, the memory cells may be programmed to data states S1 to S5. Similarly, if the memory cells of the selected word line WLn are being programmed to QLC, then at step 4602, the memory cells are programmed to data states S1 to S13. In other words, the process moves to step 4604 only after verification passes for data state S5. At step 4604, another programming loop is performed on the selected word line. The programming loop includes a VPGM pulse, a verification operation; and an analog bit scan operation for data state SN-1 (e.g., S6 or S14) to compare the number of memory cells that failed verification to a BSPF threshold.

[0285] At decision step 4606, it is determined whether the analog bit scanning operation passes. If the output at decision step 4606 is a fail, then at step 4608, the program voltage VPGM is incrementally increased by a step size dVPGM (i.e., VPGM=VPGM+dVPGM). The process then returns to step 4604 to begin another programming cycle. If the output at decision step 4606 is a weak pass (the number of memory cells that failed verification is slightly below the BSPF threshold), then at step 4610, up to three additional programming cycles are performed on the selected word line WLn to further program the memory cells to the final data state SN (e.g., S7 or S15). If the output at decision step 4606 is a strong pass (the number of memory cells that failed verification is much lower than the BSPF threshold), then at step 4612, up to two additional programming cycles are performed on the selected word line WLn to further program the memory cells to the final data state SN (e.g., S7 or S15). The specific number of additional programming cycles for each of these outputs can be set at any suitable level.

[0286] At step 4610 or 4612, each programming loop includes a VPGM pulse, a verification operation, and a bit scan operation for data state SN. If verification passes before the end of three programming loops (in the case of step 4610) or two programming loops (in the case of step 4612), programming is completed in advance. However, after those additional programming loops, programming is considered completed even if verification does not pass for data state SN.

[0287] This embodiment allows the number of additional programming loops to be performed after a program-verify pass for state SN-1 to be dynamically determined based on the strength of the pass. If the output of the analog bit scan operation is a weak pass, the memory cells being programmed to data state SN may receive more additional programming loops to further program those memory cells than in the case of a strong pass.

[0288] In some implementations, additional outputs or bins may be provided for the analog bit scan operation, where different operations are generated by different outputs. For example, in response to a strong pass output from the analog bit scan operation for data state SN-1, up to two additional programming loops may be performed on the selected word line WLn; in response to a medium pass output, up to three additional programming loops may be performed; and in response to a weak pass output, up to four additional programming loops may be performed. One way to add bins to the analog bit scan operation is to tighten (or reduce) the BSPF threshold to add additional failure scenarios, as discussed above.

[0289] Now turn to Fig.47, a flowchart 4700 is provided showing the steps of programming the memory cells of the selected word line WLn using analog bit scanning in the STPFINE operation according to another embodiment of the present disclosure. These steps can be performed by a controller, a processor or a processing device or any other circuit that executes instructions stored in a memory and / or other circuits described herein that are specifically configured / programmed to perform the following steps.

[0290] In this embodiment, steps 4702 to 4708 are the same as 4602 to 4608 of the embodiment described above, but the analog bit scan operation is configured to provide four different output options (fail, weak pass, medium pass, and strong pass) instead of the three output options described above.

[0291] In response to the strong pass output at decision step 4706, then at step 4710, programming continues for up to a predetermined number of programming loops (e.g., up to three additional programming loops) and wherein the programming voltage VPGM increases by a first step size dVPGM_1 between the additional programming loops. In response to the moderate pass output at decision step 4706, then at step 4712, programming continues for up to a predetermined number of programming loops and wherein the programming voltage VPGM increases by a second step size dVPGM_2 between the additional programming loops. In response to the weak pass output at decision step 4706, then at step 4714, programming continues for up to a predetermined number of programming loops and wherein the programming voltage VPGM increases by a third step size dVPGM_3 between the additional programming loops.

[0292] In this embodiment, the third step size dVPGM_3 is larger than the second step size dVPGM_2, which is larger than the first step size dVPGM_1. Therefore, the programming voltage VPGM increases more slowly for a strong pass because less additional programming is required, and increases more quickly for a weak pass because more additional programming is required. In other words, the step size dVPGM during the additional programming cycle is dynamically optimized based on the results of the simulated bit scan operation for data state SN-1.

[0293] In some implementations, after verification passes for data state SN-1, the step size dVPGM can be dynamically adjusted for only one or less than all additional programming loops, but not all additional programming loops.

[0294] In some other embodiments, certain aspects of two embodiments in these embodiments can be combined together. For example, the number and step size dVPGM of additional programming loops performed after the verification of data state SN-1 can be dynamically determined based on the result of the last bit scan operation for data state SN-1. In some embodiments, different programming parameters can be adjusted based on the results of the analog bit scan operation. For example, the programming clock timing can be increased during the weak pass output in response to the analog bit scan operation to further program the memory cell in the subsequent additional programming loop. In some other embodiments, the bias voltage applied to the unselected word line can be adjusted to increase or decrease the programming occurring in the additional programming loop as needed. In some other embodiments, the bit line voltage VBLC can also be adjusted based on the output of the analog bit scan operation to speed up or slow down the programming of the memory cell coupled thereto.

[0295] Various terms are used herein to refer to specific system components. Different companies may refer to the same or similar components by different names, and this document is not intended to distinguish components that are different in name but not in function. Insofar as the various functional units described in the following disclosure are referred to as "modules", this characterization is intended to not overly limit the scope of possible implementation mechanisms. For example, a "module" may be implemented as a hardware circuit including a custom very large scale integration (VLSI) circuit or gate array, or a ready-made semiconductor including a logic chip, a transistor or other discrete components. In another example, a module may also be implemented in a programmable hardware device such as a field programmable gate array (FPGA), a programmable array logic unit, a programmable logic device, etc. In addition, a module may also be implemented at least in part by software executed by various types of processors. For example, a module may include an executable code segment that constitutes one or more physical or logical blocks of computer instructions that are converted into an object, process or function. In addition, the executable portions of such modules are not required to be physically located together, but may include different instructions that are stored in different locations and, when executed together, constitute the identified module and achieve the purpose of the module. Executable code may include only a single instruction or a set of multiple instructions, and may be distributed across different code segments, or between different programs, or across several memory devices, etc. In the specific implementation of software or a portion of a software module, the software portion may be stored on one or more computer-readable and / or executable storage media, including but not limited to electronic, magnetic, optical, electromagnetic, infrared or semiconductor-based systems, devices or equipment, or any suitable combination thereof. In general, for the purposes of this disclosure, a computer-readable and / or executable storage medium may include any tangible and / or non-transitory medium capable of containing and / or storing a program for use by or in conjunction with an instruction execution system, device, processor or device.

[0296] Similarly, for the purposes of this disclosure, the term "component" may be composed of any tangible, physical, and non-transient device. For example, a component may be in the form of a hardware logic circuit composed of a custom VLSI circuit, a gate array, or other integrated circuit, or composed of an off-the-shelf semiconductor including a logic chip, a transistor, or other discrete component, or any other suitable mechanical and / or electronic device. In addition, a component may also be implemented in a programmable hardware device such as a field programmable gate array (FPGA), a programmable array logic component, a programmable logic device, or the like. In addition, a component may be composed of one or more silicon-based integrated circuit devices (such as chips, dies, die planes, and packages) or other discrete electrical devices, which are in an electrically connected configuration with one or more other components via electrical conductors such as a printed circuit board (PCB). Therefore, a module as defined above may be embodied or implemented as a component in certain embodiments, and in some cases, the terms module and component may be used interchangeably.

[0297] Where the term "circuit" is used herein, it includes one or more electrical and / or electronic components that constitute one or more conductive paths that allow current to flow. The circuit may be in the form of a closed loop configuration or an open loop configuration. In a closed loop configuration, the circuit components may provide a return path for the current. In contrast, in an open loop configuration, the circuit components therein may be considered to form a circuit, although the return path of the current is not included. For example, whether or not the integrated circuit is grounded (as a return path for the current), the integrated circuit is referred to as a circuit. In certain exemplary embodiments, the circuit may include a group of integrated circuits, a unique integrated circuit, or a portion of an integrated circuit. For example, the circuit may include a custom VLSI circuit, a gate array, a logic circuit, and / or other forms of integrated circuits, and may include off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices. In another example, the circuit may include one or more silicon-based integrated circuit devices (such as chips, dies, die planes, and packages) or other discrete electrical devices, which are in an electrically connected configuration with one or more other components via electrical conductors such as a printed circuit board (PCB). The circuit may also be implemented as a composite circuit relative to a programmable hardware device such as a field programmable gate array (FPGA), a programmable array logic component, and / or a programmable logic device. In other exemplary embodiments, the circuit may include a network of non-integrated electrical and / or electronic components (with or without integrated circuit devices).Thus, in certain embodiments, the modules as defined above may be embodied or implemented as circuits.

[0298] It should be understood that the exemplary embodiments disclosed herein may include one or more microprocessors and specifically stored computer program instructions, which control one or more microprocessors to implement some, most or all of the functions disclosed herein in combination with certain non-processor circuits and other elements. Alternatively, some or all of the functions may be implemented by a state machine without stored program instructions or in one or more application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs), where each function or some combination of certain functions is implemented as custom logic. Combinations of these methods may also be used. In addition, references to "controller" hereinafter should be defined as including separate circuit components, application specific integrated circuits (ASICs), microcontrollers with control software, digital signal processors (DSPs), field programmable gate arrays (FPGAs) and / or processors with control software, or combinations thereof.

[0299] Additionally, the terms "couple," "couple," or "connect" as used herein are intended to represent either a direct or indirect connection. Thus, if a first device couples or is coupled to a second device, that connection may be through a direct connection or through an indirect connection via other devices (or components) and connections.

[0300] With regard to the use of terms such as "embodiment", "one embodiment", "exemplary embodiments", "specific embodiments" or other similar terms in this article, these terms are intended to indicate that the specific features, structures, functions, operations or characteristics described in conjunction with the embodiment are present in at least one embodiment of the present disclosure. Therefore, the appearance of phrases such as "in one embodiment", "in embodiments", "in exemplary embodiments", etc. may but do not necessarily all refer to the same embodiment, but to "one or more but not all embodiments", unless otherwise explicitly stated. In addition, the terms "comprising", "having", "including" and variations thereof are used in an open manner, and therefore should be interpreted as meaning "including but not limited to ...", unless otherwise explicitly stated. In addition, the elements preceded by "including ..." do not exclude the presence of additional identical elements in the subject process, method, system, article or device including the element without more restrictions.

[0301] The terms "a", "an", and "the" also refer to "one or more" unless expressly stated otherwise. For example, a "processor" programmed to perform various functions refers to one processor programmed to perform each function or more than one processor programmed together to perform each of the various functions. In addition, the phrase "at least one of A and B" (whereby A and B are variables indicating specific objects or attributes) that may be used herein and / or in the appended claims indicates a selection of either A or B, or a selection of both A and B, similar to the phrase "and / or". In the event that there are more than two variables in such a phrase, the phrase is hereby defined to include only one of the variables, any of the variables, any combination (or subcombination) of any of the variables, and all of the variables.

[0302] In addition, in the case of use in this article, the term "about" or "approximately" applies to all numerical values, whether or not explicitly indicated. These terms generally refer to numerical ranges that are considered by those skilled in the art to be equivalent to the quoted value (e.g., having the same function or result). In some cases, these terms may include numerical values ​​rounded to the nearest significant figure.

[0303] Furthermore, any enumerated list of items presented herein does not imply that any or all of the listed items are mutually exclusive and / or mutually inclusive, unless expressly stated otherwise. In addition, as used herein, the term "group" should be interpreted as meaning "one or more" according to the set theory, and in the case of "multiple groups", it should be interpreted as meaning the plural (multiple) of "one or more" and / or "a plurality or more", unless expressly stated otherwise.

[0304] The above detailed description has been provided for the purpose of illustration and description. It is not intended to be exhaustive or to be limited to the precise form disclosed by the invention. Based on the above description, many modifications and variations are possible. The described embodiments are selected to best illustrate the principles of the present technology and its practical application, so as to enable other technical personnel in the field to best use the technology in various embodiments and with various modifications suitable for the specific purpose contemplated. The scope of the present technology is defined by the appended claims.

Claims

1. A method for performing an erase operation in a memory device, the method comprising the following steps: preparing a memory block including a plurality of memory cells arranged in a plurality of word lines including a selected group of word lines to be erased; erasing the memory cells of the selected group of word lines in at least one erase cycle, the at least one erase cycle comprising an erase pulse, an erase-verify operation, and an analog bit scan operation; determining an output of the analog bit scanning operation, the output being one of at least three options; and At least one erase parameter is set based on the output of the analog bit scanning operation.

2. The method of claim 1 , wherein the step of setting the at least one erase parameter based on the output of the analog bit scan operation comprises: In response to the output of the analog bit scanning operation being a first output option, increasing the voltage of the erase pulse by a first step size; as well as In response to the output of the analog bit scan operation being a second output option, the voltage of the erase pulse is increased by a second step size different from the first step size.

3. The method of claim 2, wherein the step of setting the at least one erase parameter based on the output of the analog bit scan operation further comprises: In response to the output of the analog bit scanning operation being a third output option, the erase operation is ended. 4 . The method of claim 3 , wherein the first output option is a strong fail; the second output option is a weak fail or a weak pass; and the third output option is a strong pass. The method of claim 4 , wherein the second step size is approximately half of the first step size.

6. The method of claim 1 , wherein the step of setting the at least one erase parameter based on the output of the analog bit scan operation comprises: In response to the output of the analog bit scanning operation being a first output option, increasing the voltage of the erase pulse by a first step size; as well as In response to the output of the analog bit scan operation being a second output option, the voltage of the erase pulse is increased by a second step size different from the first step size and an additional erase pulse is applied to the selected set of word lines.

7. The method of claim 6, wherein the step of setting the at least one erase parameter based on the output of the analog bit scan operation further comprises: In response to the output of the analog bit scanning operation being a third output option, the erase operation is ended.

8. The method of claim 6, wherein the first output option is strong fail, the second output option is weak fail and the third output option is pass.

9. A memory device, the memory device comprising: a memory block including a plurality of memory cells arranged in a plurality of word lines including a selected group of word lines to be erased in an erase operation; circuitry configured to erase the memory cells of the selected group of word lines in at least one erase cycle, the at least one erase cycle comprising an erase pulse, an erase-verify operation, and an analog bit scan operation, the circuitry configured to: determining an output of the analog bit scanning operation, the output being one of at least three options, and At least one erase parameter is set based on the output of the analog bit scanning operation.

10. The memory device of claim 9, wherein the circuit is further configured to: In response to the output of the analog bit scanning operation being a first output option, increasing the voltage of the erase pulse by a first step size; and In response to the output of the analog bit scan operation being a second output option, the voltage of the erase pulse is increased by a second step size different from the first step size.

11. The memory device of claim 10, wherein the circuit is further configured to: In response to the output of the analog bit scanning operation being a third output option, the erase operation is ended.

12. The memory device of claim 11, wherein the first output option is a strong fail; the second output option is a weak fail or a weak pass; and the third output option is a strong pass.

13. The memory device of claim 12, wherein the second step size is approximately half of the first step size.

14. The memory device of claim 9, wherein the circuit is further configured to: In response to the output of the analog bit scanning operation being a first output option, increasing the voltage of the erase pulse by a first step size; and In response to the output of the analog bit scan operation being a second output option, the voltage of the erase pulse is increased by a second step size different from the first step size and an additional erase pulse is applied to the selected set of word lines.

15. The memory device of claim 14, wherein the circuit is further configured to: In response to the output of the analog bit scanning operation being a third output option, the erase operation is ended.

16. The memory device of claim 14, wherein the first output option is strong fail, the second output option is weak fail and the third output option is pass.

17. A device, comprising: a memory block including a plurality of memory cells arranged in a plurality of word lines including a selected group of word lines to be erased in an erase operation; an erasing device for erasing the memory cells of the word lines of the selected group in at least one erase cycle, the at least one erase cycle comprising an erase pulse, an erase-verify operation, and an analog bit scan operation, the erasing device being configured to: determining an output of the analog bit scanning operation, the output being one of at least three options including a strong fail, a weak fail, and a pass, In response to the output of the analog bit scan operation being a strong fail, increasing the voltage of the erase pulse by a first step size, and In response to the output of the analog bit scan operation being a weak fail, the voltage of the erase pulse is increased by a second step size, the second step size being different from the first step size.

18. The apparatus of claim 17, wherein the at least three options for the output of the analog bit scan operation further include weak pass and strong pass.

19. The device according to claim 18, wherein the erasing device is further configured to: in response to the output of the analog bit scanning operation being a weak pass, increase the voltage of the erase pulse by the second step size, and in response to the output of the analog bit scanning operation being a strong pass, end the erase operation.

20. The apparatus of claim 17, wherein the erase apparatus is further configured to apply an additional erase pulse to the selected set of word lines in response to the output of the analog bit scan operation being a weak fail.

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