Semiconductor packaging structure and forming method thereof

Abstract

An embodiment is a method of forming a semiconductor package structure, the method including forming a first die, the forming the first die including forming a through-via in a first substrate. The method further includes forming a first redistribution structure over the through-via and the first substrate, the first redistribution structure electrically coupled to the through-via. The method further includes forming a first set of die connectors over the first redistribution structure, the first set of die connectors being electrically coupled to the first redistribution structure, the first set of die connectors being on the first side of the first substrate. The method further includes bonding the first die to the second die. The method further includes encapsulating the first die with a first encapsulant. The method further includes forming a second set of die connectors over the first set of die connectors and electrically coupled to the first set of die connectors, the first set of die connectors and the second set of die connectors forming a stacked die connector. The embodiment of the invention also provides a semiconductor packaging structure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor package structures and methods of forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the increase in integration density is due to the iterative reduction of the minimum component size, which allows more components to be integrated into a given area. With the growth of the demand for shrinking electronic devices, there has emerged a need for smaller and more creative semiconductor die packaging technology. An example of such a packaging system is package-on-package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration density and component density. PoP technology is generally capable of producing semiconductor devices with enhanced functionality and a small footprint on a printed circuit board (PCB). Summary of the invention

[0003] Some embodiments of the present disclosure provide a method for forming a semiconductor packaging structure, the method comprising: forming a first tube core, the forming of the first tube core comprising: forming a through hole in a first substrate; forming a first redistribution structure above the through hole and the first substrate, the first redistribution structure being electrically coupled to the through hole; forming a first group of tube core connectors above the first redistribution structure, and the first group of tube core connectors are electrically coupled to the first redistribution structure, the first group of tube core connectors are located on a first side of the first substrate; thinning the second side of the first substrate, the thinning exposing the through hole; bonding the first tube core to the second tube core; sealing the first tube core with a first sealant; and forming a second group of tube core connectors above the first group of tube core connectors, and the second group of tube core connectors are electrically coupled to the first group of tube core connectors, the first group of tube core connectors and the second group of tube core connectors form stacked tube core connectors.

[0004] Some other embodiments of the present disclosure provide a method for forming a semiconductor packaging structure, the method also includes: sealing a first integrated circuit die in a first sealant, the first integrated circuit die including a first substrate and active devices; forming a first redistribution structure above the first integrated circuit die and the first sealant; forming a second integrated circuit die, the second integrated circuit die including a second substrate and active devices, the forming of the second integrated circuit die including: forming a through hole in the second substrate; forming a second redistribution structure above the through hole and the second substrate, the second redistribution structure electrically coupled to the through hole; forming a first group of conductive vias above the second redistribution structure, and the first group of conductive vias are electrically coupled to the second redistribution structure, the first group of conductive vias are located on a first side of the second substrate; thinning the second side of the second substrate, the thinning exposing the through holes; bonding the first integrated circuit die to the second integrated circuit die; sealing the second integrated circuit die with a second sealant; and forming a second group of conductive vias above the first group of conductive vias, and the second group of conductive vias are electrically coupled to the first group of conductive vias, the first group of conductive vias and the second group of conductive vias form stacked conductive vias.

[0005] Another embodiment of the present disclosure provides a semiconductor packaging structure, which includes: a first integrated circuit die, bonded to a second integrated circuit die, the first integrated circuit die being located in a first sealant, the first integrated circuit die including: a first substrate; an active device; a through-hole located in the first substrate; a first redistribution structure located above the through-hole and the first substrate, the first redistribution structure being electrically coupled to the through-hole; a first group of conductive vias located above the first redistribution structure and electrically coupled to the first redistribution structure, the first group of conductive vias being located on a first side of the first substrate; and a second group of conductive vias located above the first group of conductive vias and electrically coupled to the first group of conductive vias, the first group of conductive vias and the second group of conductive vias forming stacked conductive vias. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 and Figure 2 A cross-sectional view of an integrated circuit die is shown in accordance with some embodiments.

[0008] Figures 3 to 12B Cross-sectional views are shown of intermediate steps in forming a package assembly in accordance with some embodiments.

[0009] Figures 13 to 26 Cross-sectional views are shown of intermediate steps in forming a package structure in accordance with some embodiments.

[0010] Fig. 27 and Fig.28 The formation and implementation of a device stack according to some embodiments is shown. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing the different components of the present application. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the individual embodiments and / or configurations discussed.

[0012] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0013] The embodiments discussed herein may be discussed in a specific context, namely, a via or connector structure that may be integrated into a device (e.g., a chip or die) or a package (e.g., an integrated fan-out (InFO) packaging structure). The via or connector structure includes stacked vias and multiple passivation layers to permit the ability to test the die and chip of the package structure while also permitting reduced chip-package interaction (CPI) risk of the package structure. For example, the stacked vias and multiple polymer layers permit testing of each chip of the core structure with the chip as a known good die (KGD) while providing protection for the chip during and after testing.

[0014] Furthermore, the teachings of the present disclosure apply to any stacked vias or connectors and multiple passivation layers where these structures can allow for the desired testing and probing while maintaining a low risk of CPI. Other embodiments contemplate other applications, such as different package types or different configurations, which will be readily apparent to one of ordinary skill in the art after reading this disclosure. It should be noted that the embodiments discussed herein may not require description of every component or part that may be present in the structure. For example, multiple components may be omitted from a figure, such as when a discussion of one of the components may be sufficient to convey aspects of the embodiment. Furthermore, the method embodiments discussed herein may be discussed as being performed in a particular order; however, other method embodiments may be performed in any logical order.

[0015] Figure 1 A cross-sectional view of an integrated circuit die 50 according to some embodiments is shown. The integrated circuit die 50 will be packaged in a subsequent process to form an integrated circuit package. The integrated circuit die 50 can be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system on a chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc., or a combination thereof.

[0016] The integrated circuit die 50 can be formed in a wafer, which may include different device regions that are singulated in subsequent steps to form multiple integrated circuit dies. The integrated circuit die 50 can be processed according to an applicable manufacturing process to form an integrated circuit. For example, the integrated circuit die 50 includes a semiconductor substrate 52, such as doped or undoped silicon, or an active layer of a semiconductor on insulator (SOI) substrate. The semiconductor substrate 52 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer substrates or gradient substrates, may also be used. The semiconductor substrate 52 has an active surface (e.g., Figure 1 upward-facing surfaces) and inactive surfaces (e.g. Figure 1 The active surface is sometimes referred to as the front side, and the inactive surface is sometimes referred to as the back side.

[0017] Device 54 (represented by a transistor) may be formed at the front surface of semiconductor substrate 52. Device 54 may be an active device (e.g., a transistor, a diode, etc.), a capacitor, a resistor, etc. An interlayer dielectric (ILD) 56 is located over the front surface of semiconductor substrate 52. ILD 56 surrounds device 54 and may cover device 54. ILD 56 may include one or more dielectric layers formed of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0018] Conductive plug 58 extends through ILD 56 to electrically and physically couple to device 54. For example, when device 54 is a transistor, conductive plug 58 can couple the gate of the transistor with the source / drain region. Depending on the context, the source / drain region can refer to the source or drain individually or collectively. Conductive plug 58 can be formed by tungsten, cobalt, nickel, copper, silver, gold, aluminum, etc., or a combination thereof. Interconnect structure 60 is located above ILD 56 and conductive plug 58. Interconnect structure 60 interconnects device 54 to form an integrated circuit. For example, interconnect structure 60 can be formed by a metallization pattern in a dielectric layer on ILD 56. The metallization pattern includes metal lines and vias formed in one or more low-k dielectric layers. The metallization pattern of interconnect structure 60 is electrically coupled to device 54 through conductive plug 58.

[0019] The integrated circuit die 50 also includes a pad 62, such as an aluminum pad, for making external connections. The pad 62 is located on the active side of the integrated circuit die 50, such as in and / or on the interconnect structure 60. One or more passivation films 64 are located on the integrated circuit die 50, such as on portions of the interconnect structure 60 and the pad 62. An opening extends through the passivation film 64 to the pad 62. A die connector 66, such as a conductive column (e.g., formed of a metal such as copper), extends through the opening in the passivation film 64 and is physically and electrically coupled to a corresponding pad of the pad 62. The die connector 66 can be formed by, for example, plating. The die connector 66 electrically couples a corresponding integrated circuit of the integrated circuit die 50.

[0020] A chip probe test can be performed on the integrated circuit die 50. Optionally, a solder area (e.g., a solder ball or a solder bump) can be provided on the die connector 66. The solder ball can be used to perform a chip probe (CP) test on the integrated circuit die 50. In some embodiments, a CP test is performed on the die connector 66 where no solder area is present. A CP test can be performed on the integrated circuit die 50 to determine whether the integrated circuit die 50 is a known good die (KGD). Therefore, only the integrated circuit die 50 that is a KGD is subsequently processed and packaged, while the die that fails the CP test is not packaged. After the test, if a solder area is present, the solder area can be removed in a subsequent processing step.

[0021] exist Figure 2 In the embodiment of the present invention, a dielectric layer 68 is formed on the active side of the integrated circuit die 50, such as on the passivation film 64 and the die connector 66. The dielectric layer 68 laterally seals the die connector 66, and the dielectric layer 68 is laterally co-boundary with the integrated circuit die 50. Initially, the dielectric layer 68 can bury the die connector 66 so that the topmost surface of the dielectric layer 68 is located above the topmost surface of the die connector 66. In some embodiments where the solder region is disposed on the die connector 66, the dielectric layer 68 can also bury the solder region. Alternatively, the solder region can be removed before the dielectric layer 68 is formed.

[0022] The dielectric layer 68 may be a polymer (such as PBO, polyimide, BCB, etc.), a nitride (such as silicon nitride, etc.), an oxide (such as silicon oxide, PSG, BSG, BPSG, etc.), etc., or a combination thereof. For example, the dielectric layer 68 may be formed by spin coating, lamination, chemical vapor deposition (CVD), etc. In some embodiments, the die connector 66 is exposed through the dielectric layer 68 during the formation of the integrated circuit die 50. In some embodiments, the die connector 66 remains buried and is exposed during a subsequent process of packaging the integrated circuit die 50. Exposing the die connector 66 may remove any solder area that may be present on the die connector 66.

[0023] In some embodiments, the integrated circuit die 50 is a stacked device including multiple semiconductor substrates 52. For example, the integrated circuit die 50 may be a memory device including multiple memory dies, such as a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, etc. In such an embodiment, the integrated circuit die 50 includes multiple semiconductor substrates 52 interconnected by through substrate vias (TSVs). Each semiconductor substrate 52 may have (or may not have) an interconnect structure 60.

[0024] Figures 3 to 12BA cross-sectional view of an intermediate step during a process of forming a package assembly 200 according to some embodiments is shown. Specifically, package assembly 200 is formed by bonding an integrated circuit die to integrated circuit die 150. In an embodiment, package assembly 200 is a stacked chip package (sometimes referred to as a die package), but it is understood that embodiments may be applied to other three-dimensional integrated circuit (3DIC) packages.

[0025] exist Figure 3 In the embodiment of the present invention, the integrated circuit die 50 is attached to the carrier substrate 70. In some embodiments, the integrated circuit die 50 is attached to the carrier substrate 70 using a release layer (not shown). The carrier substrate 70 can be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 70 can be a wafer so that multiple integrated circuit dies 50 can be attached to the carrier substrate 70 at the same time.

[0026] The release layer can be formed of a polymer-based material that can be removed from the upper structure to be formed in a subsequent step together with the carrier substrate 70. In some embodiments, the release layer is a thermal release material based on epoxy resin that loses its adhesive properties when heated, such as a light-to-heat conversion (LTHC) release coating. In other embodiments, the release layer can be an ultraviolet (UV) glue that loses its adhesive properties when exposed to UV light. The release layer can be dispensed in liquid form and cured, and the release layer can be a laminated film laminated to the carrier substrate 70, etc. The top surface of the release layer can be horizontal and can have a high degree of flatness.

[0027] exist Figure 4 In the embodiment of the present invention, an encapsulant 72 is formed on and around the integrated circuit die 50. After being formed, the encapsulant 72 seals the integrated circuit die 50. The encapsulant 72 may be a molding compound, an epoxy resin, or the like. The encapsulant 72 may be applied by compression molding, transfer molding, or the like, and the encapsulant 72 may be formed over the carrier substrate 70 so that the integrated circuit die 50 is buried or covered. The encapsulant 72 is also formed in the gap area between adjacent integrated circuit dies 50. The encapsulant 72 may be applied in a liquid or semi-liquid form, and then subsequently cured.

[0028] exist Figure 5 In the process, a planarization process is performed on the encapsulant 72 to expose the die connector 66 and form the redistribution structure 74 and the under bump metallization (UBM) 76. The planarization process may also remove the material of the dielectric layer 68 and / or the die connector 66 until the die connector 66 is exposed. After the planarization process, the top surfaces of the die connector 66, the dielectric layer 68, and the encapsulant 72 are substantially coplanar within process variations. The planarization process may be, for example, a chemical mechanical polishing (CMP), a grinding process, etc. In some embodiments, for example, if the die connector 66 has been exposed, the planarization may be omitted.

[0029] Further in Figure 5 In the embodiment of the present invention, a redistribution structure 74 is formed over the encapsulant 72 and the integrated circuit die 50. The redistribution structure 74 includes a dielectric layer and a metallization pattern. The metallization pattern may also be referred to as a redistribution layer or a redistribution line. The redistribution structure 74 is described below as an example having a single layer of metallization pattern. More dielectric layers and metallization patterns may be formed in the redistribution structure 74. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed below may be repeated.

[0030] As an example, a first dielectric layer is deposited over the encapsulant 72 and the die connector 66. In some embodiments, the dielectric layer is formed of a photosensitive material that can be patterned using a photolithographic mask, such as PBO, polyimide, BCB, etc. The first dielectric layer can be formed by spin coating, lamination, CVD, etc., or a combination thereof. The first dielectric layer is then patterned. The patterning forms an opening to expose a portion of the die connector 66. The patterning can be performed by an acceptable process, such as by exposing the first dielectric layer to light and developing it when the dielectric layer is a photosensitive material, or by etching using, for example, anisotropic etching.

[0031] Then form a metallization pattern. The metallization pattern includes a conductive element that extends along the main surface of the first dielectric layer and extends through the first dielectric layer to be physically coupled and electrically coupled to the integrated circuit die 50. As an example of forming a metallization pattern, a seed layer is formed above the dielectric layer and in an opening extending through the first dielectric layer. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed by different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer located above the titanium layer. For example, PVD, etc. can be used to form the seed layer. Then a photoresist is formed on the seed layer and the photoresist is patterned. The photoresist can be formed by spin coating, etc., and the photoresist can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern. Patterning forms an opening through the photoresist to expose the seed layer. Then a conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating, such as electroplating or chemical plating, etc. The conductive material may include a metal, such as copper, titanium, tungsten, aluminum, etc. The combination of the conductive material and the portion of the underlying seed layer forms a metallization pattern. The photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet etching or dry etching.

[0032] Next, a second dielectric layer is deposited on the metallization pattern and the first dielectric layer. The second dielectric layer may be formed in a similar manner as the first dielectric layer, and may be formed of a similar material as the first dielectric layer.

[0033] Further in Figure 5 In the embodiment of the present invention, UBM 76 is formed for external connection with redistribution structure 74. UBM 76 has a bump portion located on and extending along the main surface of the second dielectric layer, and has a through hole portion extending through the second dielectric layer to physically and electrically couple the metallization pattern. As a result, UBM 76 is electrically coupled to integrated circuit die 50. UBM 76 can be formed of the same material as the metallization pattern. In some embodiments, UBM 76 has a different size from the metallization pattern.

[0034] According to some embodiments, Figures 6 to 9 1 is a cross-sectional view of an intermediate stage in forming an integrated circuit die 150. The integrated circuit die 150 will be formed from a wafer 100. The wafer 100 has a die region 100A, and the die region 100A includes devices formed therein, such as the integrated circuit die 150. The integrated circuit die 50 will be bonded to the wafer 100 (e.g., there are one or more dies 50 in each die region 100A). The die regions 100A will be singulated in subsequent processing to form a package assembly 200, which includes a singulated portion of the wafer 100 (e.g., the integrated circuit die 150) and one or more dies 50. The package assembly 200 can then be packaged in a fan-out package 300 and mounted on a package substrate 500 (see, e.g., Fig.28 ). In an embodiment, the resulting package is an integrated fan-out (InFO) package, including a system-on-integrated chip (SoIC) structure, but it should be appreciated that embodiments may be applied to other 3DIC packages.

[0035] Processing of one die region 100A of the wafer 100 is shown. It should be appreciated that any number of die regions 100A of the wafer 100 may be processed and singulated simultaneously to form a plurality of integrated circuit dies 150 from singulated portions of the wafer 100.

[0036] exist Figure 6 In the process, a wafer 100 is obtained or formed. The wafer 100 includes devices located in a die area 100A, and the die area 100A will be singulated in subsequent processing to be included in an integrated circuit die 150. The devices in the wafer 100 can be integrated circuit dies, etc. In some embodiments, the integrated circuit die 150 is formed in the wafer 100, which includes a substrate 102, an interconnect structure 106, a conductive via 104, a pad 108, a passivation film 110, and a die connector 112.

[0037] The substrate 102 may be a bulk semiconductor substrate, a semiconductor on insulator (SOI) substrate, a multi-layer semiconductor substrate, or the like. The substrate 102 may include semiconductor materials such as silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates may also be used, such as multi-layer substrates or gradient substrates. The substrate 102 may be doped or undoped. In embodiments in which an interposer is formed in the wafer 100, active devices are typically not included in the substrate 102, but the interposer may include a front surface (e.g., Figure 6 In embodiments where integrated circuit devices are formed in wafer 100, active devices such as transistors, capacitors, resistors, diodes, etc. may be formed in and / or on the front surface of substrate 102.

[0038] The interconnect structure 106 is located above the front surface of the substrate 102 and is used to electrically connect the devices (if any) of the substrate 102. The interconnect structure 106 may include one or more dielectric layers and corresponding metallization layers located in the dielectric layers. Acceptable dielectric materials for the dielectric layers include oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; and the like; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbon oxynitride, and the like. Other dielectric materials may also be used, such as polymers, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB)-based polymers, and the like. The metallization layer may include conductive vias and / or wires to interconnect any devices together and / or to external devices. The metallization layer may be formed of a conductive material, such as a metal, such as copper, cobalt, aluminum, gold, combinations thereof, and the like. The interconnect structure 106 may be formed by a damascene process, such as a single damascene process, a dual damascene process, and the like.

[0039] Conductive via 104 extends into interconnect structure 106 and / or substrate 102. Conductive via 104 is electrically connected to the metallization layer of interconnect structure 106. Conductive via 104 is sometimes also referred to as TSV. As an example of forming conductive via 104, a groove can be formed in interconnect structure 106 and / or substrate 102 by, for example, etching, grinding, laser technology, combinations thereof, etc. A thin dielectric material can be formed in the groove, such as by using an oxidation technique. A thin barrier layer can be conformally deposited in the opening, such as by CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, combinations thereof, etc. The barrier layer can be formed of oxide, nitride, carbide, combinations thereof, etc. A conductive material can be deposited over the barrier layer and in the opening. The conductive material can be formed by an electrochemical plating process, CVD, ALD, PVD, combinations thereof, etc. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, combinations thereof, etc. Excess conductive material and barrier layer are removed from the surface of interconnect structure 106 or substrate 102 by, for example, CMP. The remaining portion of the barrier layer and the conductive material form a conductive via 104 .

[0040] The pad 108, the passivation film 110, and the die connector 112 are formed over the interconnect structure 106. The die connector 112 may also be referred to as a conductive via 112. The pad 108, the passivation film 110, and the die connector 112 may be formed by similar processes and similar materials as the pad 62, the passivation film 64, and the die connector 66 described above. In some embodiments, the die connector 112 extends through the passivation film 110 to physically contact the pad 108 and extends along the top surface of the passivation film 110.

[0041] A chip probe test can be performed on the die area 100A of the wafer 100. Optionally, a solder area (e.g., a solder ball or a solder bump) can be set on the connector 112. The solder ball can be used to perform a chip probe (CP) test on the die area 100A. In some embodiments, a CP test is performed on the die connector 112 where no solder area exists. A CP test can be performed on the die area 100A to determine whether the die area 100A (the integrated circuit die 150 after singulation) is a known good die (KGD). Therefore, only the integrated circuit die 150 that is a KGD is subsequently processed and packaged, while the die that fails the CP test is not packaged. After the test, if a solder area exists, the solder area can be removed in a subsequent processing step.

[0042] exist Figure 7In the embodiment, a dielectric layer 114 is formed on the front side 100F of the wafer 100, such as on the passivation film 110 and the die connector 112. The dielectric layer 114 laterally seals the die connector 112, and the dielectric layer 114 is laterally co-boundary with the wafer 100. Initially, the dielectric layer 114 can bury the die connector 112 so that the topmost surface of the dielectric layer 114 is located above the topmost surface of the die connector 112. In some embodiments where the solder region is disposed on the die connector 112, the dielectric layer 114 can also bury the solder region. Alternatively, the solder region can be removed before the dielectric layer 114 is formed.

[0043] The dielectric layer 114 may be a polymer (such as PBO, polyimide, BCB, etc.), a nitride (such as silicon nitride, etc.), an oxide (such as silicon oxide, PSG, BSG, BPSG, etc.), etc., or a combination thereof. For example, the dielectric layer 114 may be formed by spin coating, lamination, CVD, etc. In some embodiments, during the formation of the wafer 100, the die connector 112 is exposed through the dielectric layer 114. In some embodiments, the die connector 112 remains buried, and the die connector 112 is exposed during subsequent processing. Exposing the die connector 112 may remove any solder area that may be present on the die connector 112.

[0044] exist Figure 8In the embodiment shown, the wafer 100 is flipped and the substrate 102 is thinned to expose the conductive via 104. The exposure of the conductive via 104 can be accomplished by a thinning process such as a grinding process, chemical mechanical polishing (CMP), etch back, a combination thereof, and the like. In the illustrated embodiment, a recessing process is performed to recess the back side of the substrate 102 so that the conductive via 104 protrudes at the back side 100BS of the wafer 100. The recessing process can be, for example, a suitable etch back process, chemical mechanical polishing (CMP), and the like. In some embodiments, the thinning process for exposing the conductive via 104 includes CMP, and due to the recess occurring during CMP, the conductive via 104 protrudes at the back side 100BS of the wafer 100. An insulating layer 122 is optionally formed on the back side of the substrate 102 to surround the protruding portion of the conductive via 104. In some embodiments, the insulating layer 122 is formed of a silicon-containing insulator, such as silicon nitride, silicon oxide, silicon oxynitride, etc., and the insulating layer 122 may be formed by a suitable deposition method, such as spin coating, CVD, plasma enhanced CVD (PECVD), high density plasma CVD (HDP-CVD), etc. Initially, the insulating layer 122 may bury the conductive via 104. A removal process may be applied to each layer to remove excess material above the conductive via 104. The removal process may be a planarization process, such as chemical mechanical polishing (CMP), etch back, a combination thereof, etc. After planarization, the exposed surfaces of the conductive via 104 and the insulating layer 122 are coplanar (within process variations) and are exposed at the back side 100BS of the wafer 100. In another embodiment, the insulating layer 122 is omitted, and the exposed surfaces of the substrate 102 and the conductive via 104 are coplanar (within process variations).

[0045] exist Fig. 9In the embodiment of the present invention, a UBM (not shown separately) and a conductive connector 124 are formed on the exposed surface of the insulating layer 122 (or substrate 102, when the insulating layer 122 is omitted) and the conductive via 104. As an example of forming a UBM, a seed layer (not shown separately) is formed on the exposed surface of the insulating layer 122 (if present) or the substrate 102 and the conductive via 104. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed by different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer located above the titanium layer. For example, PVD or the like can be used to form the seed layer. A photoresist is then formed on the seed layer and patterned. The photoresist can be formed by spin coating or the like, and the photoresist can be exposed to light for patterning. The pattern of the photoresist corresponds to the UBM. Patterning forms an opening through the photoresist to expose the seed layer. A conductive material is then formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating such as electroplating or chemical plating. The conductive material may include metals such as copper, titanium, tungsten, aluminum, etc. Then, the photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process. The remaining portion of the conductive material and the seed layer forms a UBM.

[0046] In addition, a conductive connector 124 is formed on the UBM. The conductive connector 124 can be a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by chemical nickel plating-chemical palladium plating-immersion gold technology (ENEPIG), etc. The conductive connector 124 can be formed by a reflowable conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. In some embodiments, the conductive connector 124 is formed by initially forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, reflow can be performed so that the material is formed into a desired bump shape. In another embodiment, the conductive connector 124 includes a metal column (such as a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column can be solder-free and have a substantially vertical sidewall. In some embodiments, a metal cap layer is formed on the top of the metal column. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof, and the metal capping layer may be formed by a plating process.

[0047] In addition, the singulation process is performed by segmenting along the scribe line area (e.g., around the die area 100A). The singulation process may include sawing, cutting, etc. For example, the singulation process may include sawing the insulating layer 122, the substrate 102, the interconnect structure 106, the passivation film 110, and the dielectric layer 114. The singulation process singulates the die area 100A from the adjacent die area. The resulting singulated integrated circuit die 150 originates from the die area 100A. The singulation process forms the die 150 from the singulated portion of the wafer 100.

[0048] Figures 10 to 12B is a cross-sectional view of an intermediate stage in forming package assembly 200 according to some embodiments. Fig.10 The integrated circuit die 150 is then flipped over and the integrated circuit die 150 is attached to the conductive connector 124. Figure 5 The partially packaged integrated circuit die is reflowed 124 to attach UBM 76 to the UBM of integrated circuit die 150. Conductive connector 124 connects integrated circuit die 150 (including metallization layers of interconnect structure 106) to integrated circuit die 50 (including metallization layers in interconnect structure 60). Thus, integrated circuit die 50 is electrically connected to integrated circuit die 150. In some embodiments, passive devices (e.g., surface mount devices (SMDs), not separately shown) may be attached to integrated circuit die 50 and / or integrated circuit die 150 (e.g., bonded to the UBM) before the dies are bonded together. In such embodiments, the passive devices may be bonded to the same surface of integrated circuit die 50 and / or integrated circuit die 150 as conductive connector 124.

[0049] Although a single set of integrated circuit dies 50 and integrated circuit dies 150 are shown bonded together, many integrated circuit dies 150 may be bonded to many integrated circuit dies 50 simultaneously in the form of a reconstructed wafer.

[0050] exist Fig.11 In the embodiment of the present invention, an underfill 202 is formed between the integrated circuit die 50 and the integrated circuit die 150 to surround the conductive connector 124 and the UBM. The underfill 202 may be formed by a capillary flow process after the integrated circuit die 150 is attached, or may be formed by a suitable deposition method before the integrated circuit die 150 is attached. The underfill 202 may be a continuous material extending from the integrated circuit die 50 (e.g., the redistribution structure 74) to the integrated circuit die 150 (e.g., the insulating layer 122).

[0051] After forming the bottom filler 202, an encapsulant 204 is formed on and around the integrated circuit die 150 and the bottom filler 202. After being formed, the encapsulant 204 seals the integrated circuit die 150 and the bottom filler 202. The encapsulant 204 can be a molding compound, an epoxy resin, etc. The encapsulant 204 can be applied by compression molding, transfer molding, etc., and the encapsulant 204 can be formed above the integrated circuit die 50 so that the integrated circuit die 150 is buried or covered. The encapsulant 204 is also formed in the gap area between adjacent integrated circuit dies 150. The encapsulant 204 can be applied in a liquid or semi-liquid form, and then the encapsulant 204 is subsequently cured. In some embodiments, the encapsulant 204 and the encapsulant 72 are formed of different materials. In some embodiments, the encapsulant 204 and the encapsulant 72 are formed of the same material.

[0052] Further in Fig.11 In the process, a planarization process is performed on the encapsulant 204 to expose the die connector 112 and the dielectric layer 114. The planarization process may also remove material of the dielectric layer 114 and / or the die connector 112 until the die connector 112 is exposed. After the planarization process, the top surfaces of the die connector 112, the dielectric layer 114, and the encapsulant 204 are substantially coplanar within process variations. The planarization process may be, for example, a CMP, a grinding process, etc. In some embodiments, for example, if the die connector 112 is already exposed, the planarization may be omitted.

[0053] exist Fig. 12A and Fig. 12B In the embodiment, dielectric layers 210 and 214 and connector 212 are formed over connector 112 , dielectric layer 114 , and sealant 204 . Fig. 12B Shows Fig. 12A Detailed view of a portion of the dielectric layer 210 and 214 including connector 212. Dielectric layers 210 and 214 and connector 212 can be formed by processes and materials similar to dielectric layer 114 and connector 112 described above. In some embodiments, dielectric layers 114, 210, and 214 are formed of different materials. In some embodiments, dielectric layers 114, 210, and 214 are formed of the same material. For example, in an embodiment, dielectric layer 114 can be polyimide, and dielectric layers 210 and 214 can be other types of polymers, such as PBO, BCB, etc.

[0054] Dielectric layer 210 may be formed to have a thickness T1, and dielectric layer 214 may be formed to have a thickness T2. In some embodiments, a ratio of T1 / T2 is in a range of 0.53 to 2.9.

[0055] The connector 112 may be formed in the dielectric layer 114 to have a width W1 and may be formed in the passivation film 110 to have a width W2. In some embodiments, the width W2 is greater than the width W1, while in other embodiments, the width W2 is less than the width W1. The connector 212 may be formed in the dielectric layer 214 to have a width W3 and may be formed in the dielectric layer 210 to have a width W4. In some embodiments, the width W4 is greater than the width W3, while in other embodiments, the width W4 is less than the width W3. In some embodiments, the ratio of W3 / W1 is in the range of 0.63 to 1.93. In some embodiments, the ratio of W4 / W2 is in the range of 0.8 to 2.

[0056] like Fig. 12A and Fig. 12B As shown, dielectric layers 210 and 214 overlap encapsulant 204 such that dielectric layer 210 is above and in contact with a top surface of encapsulant 204 .

[0057] In addition, the singulation process is performed by segmenting along the scribe line regions. The singulation process may include sawing, cutting, etc. For example, the singulation process may include sawing dielectric layers 214 and 210, encapsulant 204, redistribution structure 74, and encapsulant 72. The singulation process forms package assembly 200. After singulation, the sidewalls of dielectric layers 214 and 210, encapsulant 204, redistribution structure 74, and encapsulant 72 are continuous within process variations.

[0058] By having a stacked connector structure 112 / 212 and multiple dielectric layers 114 / 210 / 214, the ability to test the dies 50 and 150 is permitted while also permitting reduced chip package interaction (CPI) risk. For example, the stacked connectors 112 / 212 and multiple dielectric layers permit each die in the die structure 200 to be tested and served as a known good die (KGD) while providing protection to the die during and after testing.

[0059] Figures 13 to 26 A cross-sectional view of an intermediate step during a process of forming a package assembly 300 according to some embodiments is shown. A first package region 300A and a second package region 300B are shown, and one or more package assemblies 200 are packaged to form an integrated circuit package in each of the package regions 300A and 300B. The integrated circuit package may also be referred to as an integrated fan-out (InFO) package.

[0060] exist Fig.13In the embodiment, a carrier substrate 302 is provided, and a release layer 304 is formed on the carrier substrate 302. The carrier substrate 302 may be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 302 may be a wafer so that a plurality of packages may be formed on the carrier substrate 302 at the same time.

[0061] The release layer 304 may be formed of a polymer-based material that can be removed from the upper structure to be formed in a subsequent step together with the carrier substrate 302. In some embodiments, the release layer 304 is an epoxy-based thermal release material that loses its adhesive properties when heated, such as a light-to-heat conversion (LTHC) release coating. In other embodiments, the release layer 304 may be an ultraviolet (UV) glue that loses its adhesive properties when exposed to UV light. The release layer 304 may be dispensed in a liquid form and cured, and the release layer 304 may be a laminated film laminated to the carrier substrate 302, etc. The top surface of the release layer 304 may be horizontal and may have a high degree of flatness.

[0062] exist Fig.14 3, a backside redistribution structure 306 may be formed on the release layer 304. In the embodiment shown, the backside redistribution structure 306 includes a dielectric layer 308, a metallization pattern 310 (sometimes referred to as a redistribution layer or redistribution line), and a dielectric layer 312. The backside redistribution structure 306 is optional. In some embodiments, a dielectric layer without a metallization pattern is formed on the release layer 304 instead of the backside redistribution structure 306.

[0063] The dielectric layer 308 may be formed on the release layer 304. The bottom surface of the dielectric layer 308 may be in contact with the top surface of the release layer 304. In some embodiments, the dielectric layer 308 is formed of a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. In other embodiments, the dielectric layer 308 is formed of a nitride (such as silicon nitride), an oxide (such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.), etc. The dielectric layer 308 may be formed by any acceptable deposition process, such as spin coating, CVD, lamination, etc., or a combination thereof.

[0064] Metallization pattern 310 can be formed on dielectric layer 308. As an example of forming metallization pattern 310, a seed layer is formed above dielectric layer 308. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed by different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer located above the titanium layer. For example, physical vapor deposition (PVD) or the like can be used to form the seed layer. Then a photoresist (not shown) is formed on the seed layer and the photoresist is patterned. The photoresist can be formed by spin coating or the like, and the photoresist can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 310. Patterning forms an opening through the photoresist to expose the seed layer. Conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. Conductive material can be formed by plating such as electroplating or chemical plating. Conductive material can include metals, such as copper, titanium, tungsten, aluminum, etc. Then, the photoresist and the portion of the seed layer on which no conductive material is formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet etching or dry etching. The remaining portion of the conductive material and the seed layer forms a metallization pattern 310.

[0065] A dielectric layer 312 may be formed on the metallization pattern 310 and the dielectric layer 308. In some embodiments, the dielectric layer 312 is formed of a polymer, which may be a photosensitive material that can be patterned using a photolithography mask, such as PBO, polyimide, BCB, etc. In other embodiments, the dielectric layer 312 is formed of a nitride (such as silicon nitride), an oxide (such as silicon oxide, PSG, BSG, BPSG), etc. The dielectric layer 312 may be formed by spin coating, lamination, CVD, etc., or a combination thereof. The dielectric layer 312 is then patterned to form an opening 314 to expose a portion of the metallization pattern 310. Patterning may be performed by an acceptable process, such as by exposing the dielectric layer 312 to light when the dielectric layer 312 is a photosensitive material, or by etching using, for example, anisotropic etching. If the dielectric layer 312 is a photosensitive material, the dielectric layer 312 may be developed after exposure.

[0066] Fig.14A redistribution structure 306 having a single metallization pattern 310 is shown for illustration purposes only. In some embodiments, the backside redistribution structure 306 may include any number of dielectric layers and metallization patterns. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed above may be repeated. The metallization pattern may include one or more conductive elements. Conductive elements may be formed during the formation of the metallization pattern by forming a seed layer and conductive material of the metallization pattern in the opening of the underlying dielectric layer and above the surface of the underlying dielectric layer to interconnect and electrically couple the individual conductors.

[0067] exist Fig.15 In the embodiment, a through hole 316 can be formed in the opening 314, and the through hole 316 extends away from the topmost dielectric layer (e.g., dielectric layer 312) of the backside redistribution structure 306. As an example of forming a through hole 316, a seed layer (not shown) is formed above the backside redistribution structure 306, for example, on the dielectric layer 312 and the portion of the metallization pattern 310 exposed by the opening 314. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed by different materials. In a specific embodiment, the seed layer includes a titanium layer and a copper layer located above the titanium layer. For example, PVD, etc. can be used to form the seed layer. A photoresist is formed on the seed layer and the photoresist is patterned. The photoresist can be formed by spin coating, etc., and the photoresist can be exposed to light for patterning. The pattern of the photoresist corresponds to a conductive via. Patterning forms an opening through the photoresist to expose the seed layer. Conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating such as electroplating or chemical plating. The conductive material can include metals, such as copper, titanium, tungsten, aluminum, etc. The photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet etching or dry etching. The remaining portion of the conductive material and the seed layer forms a through hole 316.

[0068] exist Fig.16In the embodiment shown, the package component 200 is adhered to the dielectric layer 312 by the adhesive 318. The required type and number of package components 200 are adhered in each of the package areas 300A and 300B. In the illustrated embodiment, a single package component 200 is adhered in each of the first package area 300A and the second package area 300B. In some embodiments, multiple package components 200 can be adhered adjacent to each other in each of the package areas 300A and 300B. In the case of multiple package components 200, the package components 200 can have different sizes (e.g., different heights and / or surface areas), or can have the same size (e.g., the same height and / or surface area). The space available for through-holes 316 in the first package area 300A and the second package area 300B may be limited, especially when the package component 200 includes a device (such as a SoC) that occupies a large area. When the first package area 300A and the second package area 300B have limited space available for through-holes 316, the use of the backside redistribution structure 306 allows for improved interconnection arrangement.

[0069] Adhesive 318 is located on the back side of package component 200 and adheres package component 200 to back side redistribution structure 306, such as to dielectric layer 312. Adhesive 318 may be any suitable adhesive, epoxy, die attach film (DAF), etc. Adhesive 318 may be applied to the back side of package component 200, may be applied over the surface of carrier substrate 302 if back side redistribution structure 306 is not utilized, or may be applied to the upper surface of back side redistribution structure 306, if applicable.

[0070] exist Fig.17 In the embodiment of the present invention, a sealant 320 is formed on and around each component. After formation, the sealant 320 seals the through hole 316 and the package component 200. The sealant 320 can be a molding compound, an epoxy resin, etc. The sealant 320 can be applied by compression molding, transfer molding, etc., and the sealant 320 can be formed above the carrier substrate 302 so that the through hole 316 and / or the package component 200 are buried or covered. The sealant 320 is also formed in the gap area between the package component 200 and the through hole 316. The sealant 320 physically contacts the sealants 204 and 72 of the package component 200. The sealant 320 can be applied in a liquid or semi-liquid form, and then subsequently cured. In some embodiments, the sealants 320, 204, and 72 are formed of different materials. In some embodiments, the sealants 320, 204, and 72 are formed of the same material.

[0071] exist Fig.18In the embodiment of the present invention, a planarization process is performed on the sealant 320 to expose the through-hole 316 and the connector 212. The planarization process may also remove the material of the through-hole 316, the dielectric layer 214 and / or the connector 212 until the connector 212 and the through-hole 316 are exposed. After the planarization process, the top surfaces of the through-hole 316, the connector 212, the dielectric layer 214 and the sealant 320 are substantially coplanar within process variations. The planarization process may be, for example, a CMP, a grinding process, etc. In some embodiments, for example, if the through-hole 316 and / or the connector 212 are already exposed, the planarization may be omitted.

[0072] exist Figures 19 to 22 In the embodiment, a front side redistribution structure 322 is formed above the sealant 320, the through hole 316 and the package component 200 (see Fig. 22 ). The front side redistribution structure 322 includes a dielectric layer 324, a dielectric layer 328, a dielectric layer 332, and a dielectric layer 336; and a metallization pattern 326, a metallization pattern 330, and a metallization pattern 334. The metallization pattern may also be referred to as a redistribution layer or a redistribution line. The front side redistribution structure 322 is shown as an example having a three-layer metallization pattern. More or fewer dielectric layers and metallization patterns may be formed in the front side redistribution structure 322. If fewer dielectric layers and metallization patterns are to be formed, the steps and processes discussed below may be omitted. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed below may be repeated.

[0073] exist Fig.19 In the embodiment of the present invention, a dielectric layer 324 is deposited on the sealant 320, the through-hole 316 and the connector 212. In some embodiments, the dielectric layer 324 is formed of a photosensitive material that can be patterned using a photolithography mask, such as PBO, polyimide, BCB, etc. The dielectric layer 324 can be formed by spin coating, lamination, CVD, etc., or a combination thereof. The dielectric layer 324 is then patterned. The patterning forms openings to expose portions of the through-hole 316 and the connector 212. The patterning can be performed by an acceptable process, such as when the dielectric layer 324 is a photosensitive material, by exposing the dielectric layer 324 to light and developing it, or by etching using, for example, anisotropic etching.

[0074] Then form metallization pattern 326.Metallization pattern 326 includes conductive elements extending along the main surface of dielectric layer 324 and extending through dielectric layer 324, so as to be physically coupled and electrically coupled to through-hole 316 and package component 200.As an example of forming metallization pattern 326, a seed layer is formed above dielectric layer 324 and in an opening extending through dielectric layer 324.In some embodiments, seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed by different materials.In some embodiments, seed layer includes a titanium layer and a copper layer located above the titanium layer.For example, PVD etc. can be used to form seed layer.Then form photoresist on seed layer and pattern the photoresist.The photoresist can be formed by spin coating etc., and the photoresist can be exposed to light for patterning.The pattern of photoresist corresponds to metallization pattern 326.Patterning forms an opening through photoresist to expose seed layer.Then form conductive material in the opening of photoresist and on the exposed part of seed layer. The conductive material may be formed by plating such as electroplating or chemical plating. The conductive material may include a metal, such as copper, titanium, tungsten, aluminum, etc. The combination of the conductive material and a portion of the underlying seed layer forms the metallization pattern 326. The photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet etching or dry etching.

[0075] exist Fig. 20 In the embodiment of the present invention, a dielectric layer 328 is deposited on the metallization pattern 326 and the dielectric layer 324. The dielectric layer 328 may be formed in a similar manner as the dielectric layer 324 and may be formed of a similar material as the dielectric layer 324.

[0076] The metallization pattern 330 is then formed. The metallization pattern 330 includes a portion located on the main surface of the dielectric layer 328 and extending along the main surface of the dielectric layer 328. The metallization pattern 330 also includes a portion extending through the dielectric layer 328 to physically and electrically couple the metallization pattern 326. The metallization pattern 330 can be formed in a similar manner and with similar materials as the metallization pattern 326. In some embodiments, the metallization pattern 330 has a different size than the metallization pattern 326. For example, the wires and / or vias of the metallization pattern 330 can be wider or thicker than the wires and / or vias of the metallization pattern 326. In addition, the metallization pattern 330 can be formed with a larger pitch than the metallization pattern 326.

[0077] exist Fig.21In the embodiment of the present invention, a dielectric layer 332 is deposited on the metallization pattern 330 and the dielectric layer 328. The dielectric layer 332 may be formed in a similar manner as the dielectric layer 324 and may be formed of similar materials as the dielectric layer 324.

[0078] Then, a metallization pattern 334 is formed. The metallization pattern 334 includes a portion located on and extending along the main surface of the dielectric layer 332. The metallization pattern 334 also includes a portion extending through the dielectric layer 332 to physically and electrically couple the metallization pattern 330. The metallization pattern 334 can be formed in a similar manner and with similar materials as the metallization pattern 326. The metallization pattern 334 is the topmost metallization pattern of the front side redistribution structure 322. In this way, all the intermediate metallization patterns (e.g., the metallization pattern 326 and the metallization pattern 330) of the front side redistribution structure 322 are disposed between the metallization pattern 334 and the package assembly 200. In some embodiments, the metallization pattern 334 has a different size than the metallization pattern 326 and the metallization pattern 330. For example, the wires and / or vias of the metallization pattern 334 can be wider or thicker than the wires and / or vias of the metallization patterns 326 and 330. Furthermore, the metallization pattern 334 may be formed to have a larger pitch than the metallization pattern 330 .

[0079] exist Fig. 22 , a dielectric layer 336 is deposited on the metallization pattern 334 and the dielectric layer 332. The dielectric layer 336 may be formed in a similar manner to the dielectric layer 324, and the dielectric layer 336 may be formed of the same material as the dielectric layer 324. The dielectric layer 336 is the topmost dielectric layer of the front side redistribution structure 322. In this way, all metallization patterns (e.g., metallization pattern 326, metallization pattern 330, and metallization pattern 334) of the front side redistribution structure 322 are disposed between the dielectric layer 336 and the package component 200. In addition, all intermediate dielectric layers (e.g., dielectric layer 324, dielectric layer 328, dielectric layer 332) of the front side redistribution structure 322 are disposed between the dielectric layer 336 and the package component 200.

[0080] exist Fig.23 In the embodiment of the present invention, UBM 338 is formed for external connection to front-side redistribution structure 322. UBM 338 has a bump portion located on and extending along the main surface of dielectric layer 336, and has a through hole portion extending through dielectric layer 336 to physically and electrically couple to metallization pattern 334. As a result, UBM 338 is electrically coupled to through-via 316 and package component 200. UBM 338 may be formed of the same material as metallization pattern 326. In some embodiments, UBM 338 has a different size than metallization pattern 326, metallization pattern 330, and metallization pattern 334.

[0081] exist Fig.24 In the embodiment, a conductive connector 350 is formed on the UBM 338. The conductive connector 350 can be a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by chemical nickel plating-chemical palladium plating-immersion gold technology (ENEPIG), etc. The conductive connector 350 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. In some embodiments, the conductive connector 350 is formed by initially forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, reflow can be performed to shape the material into a desired bump shape. In another embodiment, the conductive connector 350 includes a metal column (such as a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column can be solder-free and have a substantially vertical sidewall. In some embodiments, a metal cap layer is formed on the top of the metal column. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof, and the metal capping layer may be formed by a plating process.

[0082] exist Fig.25 In the embodiment of the present invention, carrier substrate release is performed to separate (or "release") carrier substrate 302 from backside redistribution structure 306 (e.g., dielectric layer 308). According to some embodiments, release includes projecting light such as laser or ultraviolet light onto release layer 304, so that release layer 304 decomposes under the heat of the light and carrier substrate 302 can be removed. The structure is then flipped over and placed on tape (not shown).

[0083] exist Fig.26 In the embodiment of the present invention, the conductive connector 352 is formed to extend through the dielectric layer 308 to contact the metallization pattern 310. An opening is formed through the dielectric layer 308 to expose a portion of the metallization pattern 310. For example, the opening can be formed using laser drilling, etching, etc. The conductive connector 352 is formed in the opening. In some embodiments, the conductive connector 352 includes flux, and the conductive connector 352 is formed in a flux dipping process. In some embodiments, the conductive connector 352 includes a conductive paste, such as a solder paste, a silver paste, etc., and the conductive connector 352 is dispensed in a printing process. In some embodiments, the conductive connector 352 is formed in a manner similar to the conductive connector 350 and can be formed of a material similar to the conductive connector 350.

[0084] Fig. 27 and Fig.28The formation and implementation of a device stack according to some embodiments is shown. The device stack is formed of integrated circuit packages formed in a package assembly 300. The device stack may also be referred to as a package-on-package (PoP) structure.

[0085] exist Fig. 27 In the embodiment, the package component 400 is coupled to the package component 300 . One of the package components 400 is coupled in each of the package regions 300A and 300B to form an integrated circuit device stack in each region of the package component 300 .

[0086] The package assembly 400 includes, for example, a substrate 402 and one or more stacked dies 410 (e.g., 410A and 410B) coupled to the substrate 402. Although a set of stacked dies 410 (410A and 410B) is shown, in other embodiments, multiple stacked dies 410 (each having one or more stacked dies) may be arranged side by side to couple to the same surface of the substrate 402. The substrate 402 may be made of a semiconductor material such as silicon, germanium, diamond, etc. In some embodiments, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these, etc. may also be used. In addition, the substrate 402 may be a silicon on insulator (SOI) substrate. Typically, the SOI substrate includes a semiconductor material layer such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or a combination thereof. In an optional embodiment, the substrate 402 is based on an insulating core, such as a glass fiber reinforced resin core. An exemplary core material is a glass fiber resin such as FR4. Optional materials for the core material include bismaleimide-triazine (BT) resin, or alternatively, other printed circuit board (PCB) materials or films. Build-up films such as Ajinomoto Build-up Film (ABF) or other laminate materials can be used for substrate 402.

[0087] Substrate 402 may include active and passive devices (not shown). A wide variety of devices such as transistors, capacitors, resistors, combinations of these, etc. may be used to generate the structural and functional requirements for the design of package assembly 400. The devices may be formed using any suitable method.

[0088] The substrate 402 may also include metallization layers (not shown) and conductive vias 408. The metallization layers may be formed over active and passive devices and are designed to connect the devices to form functional circuits. The metallization layers may be formed of alternating layers of dielectric materials (e.g., low-k dielectric materials) and conductive materials (e.g., copper), wherein the vias interconnect the layers of conductive materials, and the metallization layers may be formed by any suitable process (such as deposition, damascene, dual damascene, etc.). In some embodiments, the substrate 402 is substantially free of active and passive devices.

[0089] The substrate 402 may have a bonding pad 404 on a first side of the substrate 402 to couple to the stacked die 410, and a bonding pad 406 on a second side of the substrate 402 to couple to the conductive connector 352, the second side of the substrate 402 being opposite to the first side of the substrate 402. In some embodiments, the bonding pad 404 and the bonding pad 406 are formed by forming a groove (not shown) in a dielectric layer (not shown) on the first side and the second side of the substrate 402. The groove may be formed to allow the bonding pad 404 and the bonding pad 406 to be embedded in the dielectric layer. In other embodiments, the bonding pad 404 and the bonding pad 406 may be formed on the dielectric layer, so the groove is omitted. In some embodiments, the bonding pad 404 and the bonding pad 406 include a thin seed layer (not shown) made of copper, titanium, nickel, gold, palladium, etc., or a combination thereof. The conductive material of the bonding pad 404 and the bonding pad 406 may be deposited above the thin seed layer. The conductive material may be formed by electrochemical plating, chemical plating, CVD, atomic layer deposition (ALD), PVD, etc., or a combination thereof. In an embodiment, the conductive material of bonding pad 404 and bonding pad 406 is copper, tungsten, aluminum, silver, gold, etc., or a combination thereof.

[0090] In some embodiments, the bonding pad 404 and the bonding pad 406 are UBMs including three layers of conductive material, such as a titanium layer, a copper layer, and a nickel layer. Other arrangements of materials and layers may be used to form the bonding pad 404 and the bonding pad 406, such as an arrangement of chromium / chromium copper alloy / copper / gold, an arrangement of titanium / titanium tungsten / copper, or an arrangement of copper / nickel / gold. Any suitable material or material layer that may be used for the bonding pad 404 and the bonding pad 406 is fully intended to be included in the current application. In some embodiments, the conductive via 408 extends through the substrate 402 and couples at least one bonding pad 404 to at least one bonding pad 406.

[0091] In the illustrated embodiment, the stacked die 410 is coupled to the substrate 402 via bonding wires 412, but other connectors, such as conductive bumps, may be used. In an embodiment, the stacked die 410 is a stacked memory die. For example, the stacked die 410 may be a memory die such as a low power (LP) double data rate (DDR) memory module (such as LPDDR1, LPDDR2, LPDDR3, LPDDR4, etc. memory module).

[0092] The stacked die 410 and the bonding wires 412 may be sealed by a molding material 414. The molding material 414 may be molded on the stacked die 410 and the bonding wires 412, for example, using compression molding. In some embodiments, the molding material 414 is a molding compound, a polymer, an epoxy resin, a silicon oxide filling material, etc., or a combination thereof. A curing process may be performed to cure the molding material 414; the curing process may be thermal curing, UV curing, etc., or a combination thereof.

[0093] In some embodiments, the stacked die 410 and the bonding wires 412 are buried in a molding material 414 , and after the molding material 414 is cured, a planarization step, such as grinding, is performed to remove excess portions of the molding material 414 , and the planarization step provides a substantially flat surface for the package assembly 400 .

[0094] After forming the package assembly 400, the package assembly 400 is mechanically and electrically bonded to the package assembly 300 via the conductive connectors 352, the bonding pads 406, and the metallization pattern of the backside redistribution structure 306. In some embodiments, the stacked die 410 can be coupled to the package assembly 200 through the bonding wires 412, the bonding pads 404 and 406, the conductive vias 408, the conductive connectors 352, the backside redistribution structure 306, the through-vias 316, and the frontside redistribution structure 322.

[0095] In some embodiments, solder resist (not shown) is formed on a side of substrate 402 opposite stacked die 410. Conductive connectors 352 may be disposed in openings in the solder resist to electrically and mechanically couple to conductive features (e.g., bonding pads 406) in substrate 402. The solder resist may be used to protect areas of substrate 402 from external damage.

[0096] In some embodiments, conductive connector 352 has epoxy flux (not shown) formed thereon prior to reflowing conductive connector 352 , and after attaching package assembly 400 to package assembly 300 , at least some of the epoxy portion of the epoxy flux remains.

[0097] In some embodiments, an underfill (not shown) is formed between package component 300 and package component 400 to surround conductive connector 352. The underfill can reduce stress and protect the joints created by reflowing conductive connector 352. The underfill can be formed by a capillary flow process after attaching package component 400, or can be formed by a suitable deposition method before attaching package component 400. In an embodiment where epoxy flux is formed, the epoxy flux can act as an underfill.

[0098] exist Fig.28In the embodiment, the singulation process is performed by sawing along the scribe line area (e.g., between the first package area 300A and the second package area 300B). The sawing singulates the first package area 300A from the second package area 300B. The resulting singulated device stack originates from one of the first package area 300A or the second package area 300B. In some embodiments, the singulation process is performed after the package component 400 is coupled to the package component 300. In other embodiments (not shown), the singulation process is performed before the package component 400 is coupled to the package component 300, such as after the carrier substrate 302 is detached and the conductive connector 352 is formed.

[0099] Each singulated package component 300 can then be mounted to a package substrate 500 using a conductive connector 350. The package substrate 500 includes a substrate core 502 and a bonding pad 504 above the substrate core 502. The substrate core 502 can be made of a semiconductor material such as silicon, germanium, diamond, etc. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations of these, etc. can also be used. In addition, the substrate core 502 can be an SOI substrate. Typically, the SOI substrate includes a semiconductor material layer such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or a combination thereof. In an optional embodiment, the substrate core 502 is based on an insulating core, such as a glass fiber reinforced resin core. An exemplary core material is a glass fiber resin, such as FR4. Optional materials for the core material include bismaleimide-triazine (BT) resin, or alternatively, other PCB materials or films. A build-up film such as ABF or other lamination materials may be used for the substrate core 502 .

[0100] The substrate core 502 may include active devices and passive devices (not shown). A wide variety of devices such as transistors, capacitors, resistors, combinations of these, etc. may be used to generate the structural and functional requirements for the design of the device stack. The devices may be formed using any suitable method.

[0101] The substrate core 502 may also include metallization layers and vias (not shown), wherein the bonding pads 504 are physically and / or electrically coupled to the metallization layers and vias. The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuits. The metallization layers may be formed of alternating layers of dielectric materials (e.g., low-k dielectric materials) and conductive materials (e.g., copper), wherein the vias interconnect the layers of conductive materials, and the metallization layers may be formed by any suitable process (such as deposition, inlay, dual inlay, etc.). In some embodiments, the substrate core 502 is substantially free of active and passive devices.

[0102] In some embodiments, the conductive connector 350 is reflowed to attach the package assembly 300 to the bonding pad 504. The conductive connector 350 electrically and / or physically couples the package substrate 500 (including the metallization layer located in the substrate core 502) to the package assembly 300. In some embodiments, a solder resist 506 is formed on the substrate core 502. The conductive connector 350 can be disposed in an opening in the solder resist 506 to electrically and mechanically couple to the bonding pad 504. The solder resist 506 can be used to protect areas of the substrate core 502 from external damage.

[0103] Before reflowing the conductive connector 350, the conductive connector 350 may have an epoxy flux (not shown) formed thereon, and after attaching the package component 300 to the package substrate 500, at least some of the epoxy portion of the epoxy flux remains. The remaining epoxy portion may act as an underfill to reduce stress and protect the joints created by the reflowed conductive connector 350. In some embodiments, an underfill 508 may be formed between the package component 300 and the package substrate 500 and around the conductive connector 350. The underfill 508 may be formed by a capillary flow process after attaching the package component 300, or may be formed by a suitable deposition method before attaching the package component 300.

[0104] In some embodiments, passive devices (e.g., surface mount devices (SMDs), not shown) may also be attached to the package assembly 300 (e.g., to the UBM 338) or to the package substrate 500 (e.g., to the conductive pads 504). For example, the passive device may be bonded to the same surface of the package assembly 300 or the package substrate 500 as the conductive connector 350. The passive device may be attached to the package assembly 300 before the package assembly 300 is mounted on the package substrate 500, or the passive device may be attached to the package substrate 500 before or after the package assembly 300 is mounted on the package substrate 500.

[0105] Package assembly 300 may be implemented in other device stacks. For example, a PoP structure is shown, but package assembly 300 may also be implemented in a flip chip ball grid array (FCBGA) package. In such an embodiment, package assembly 300 is mounted to a substrate (such as package substrate 500), but package assembly 400 is omitted. Instead, a lid or heat sink may be attached to package assembly 300. When package assembly 400 is omitted, backside redistribution structure 306 and through-via 316 may also be omitted.

[0106] Other components and processes may also be included. For example, a test structure may be included to assist in verification testing of a 3D package or 3DIC device. For example, the test structure may include a test pad formed in a redistribution layer or on a substrate, the test pad allowing testing of the 3D package or 3DIC, the use of a probe and / or a probe card, etc. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method that combines intermediate verification of known good dies to increase yield and reduce costs.

[0107] Advantages that can be achieved by embodiments. The embodiments discussed herein can be discussed in a specific context, namely, a through-hole or connector structure that can be integrated into a device (e.g., a chip or die) or a package (e.g., an integrated fan-out (InFO) packaging structure). The through-hole or connector structure includes stacked through-holes and multiple passivation layers to allow the ability to test the chips and dies of the packaging structure while also allowing for reduced chip-package interaction (CPI) risks of the packaging structure. For example, the stacked through-holes and multiple polymer layers allow each chip of the core structure to be tested and treated as a known good chip (KGD), while providing protection for the chip during and after testing.

[0108] An embodiment is a method, the method comprising forming a first tube core, the forming of the first tube core comprising: forming a through hole in a first substrate. The method also includes forming a first redistribution structure above the through hole and the first substrate, the first redistribution structure electrically coupled to the through hole. The method also includes forming a first group of tube core connectors above the first redistribution structure, and the first group of tube core connectors are electrically coupled to the first redistribution structure, and the first group of tube core connectors are located on a first side of the first substrate. The method also includes thinning the second side of the first substrate, and the thinning exposes the through hole. The method also includes bonding the first tube core to the second tube core. The method also includes sealing the first tube core with a first sealant. The method also includes forming a second group of tube core connectors above the first group of tube core connectors, and the second group of tube core connectors are electrically coupled to the first group of tube core connectors, and the first group of tube core connectors and the second group of tube core connectors form stacked tube core connectors.

[0109] Embodiments may include one or more of the following features. The method also includes forming a first dielectric layer on the first group of die connectors and the first redistribution structure, the first dielectric layer having sidewalls that share a boundary with the sidewalls of the first redistribution structure, and the first group of die connectors are located in the first dielectric layer. The method also includes forming a second dielectric layer on the first group of die connectors, the first dielectric layer, and the first packaging sealant, and the second group of die connectors are located in the second dielectric layer. The second dielectric layer has sidewalls that share a boundary with the sidewalls of the first sealant. The first dielectric layer and the second dielectric layer are polymer layers. The first dielectric layer and the second dielectric layer include different materials. The first sealant contacts the sidewalls of the first dielectric layer and the first redistribution structure. The first group of die connectors have a different width than the second group of die connectors. The first group of die connectors are wider than the second group of die connectors. The method also includes forming a conductive feature over the carrier substrate, attaching the bonded first and second dies to the carrier substrate adjacent to the conductive feature, encapsulating the bonded first and second dies and the conductive feature in a second encapsulant, and forming a second redistribution structure over the bonded first and second dies, the conductive feature, and the second encapsulant, the second redistribution structure electrically coupled to the second set of die connectors and the conductive feature. The method also includes forming a conductive connector over the second redistribution structure, the conductive connector electrically coupled to the second redistribution structure, removing the carrier substrate, and bonding the conductive connector to the package substrate.

[0110] An embodiment is a method, the method comprising sealing a first integrated circuit die in a first encapsulant, the first integrated circuit die comprising a first substrate and active devices. The method also comprises forming a first redistribution structure above the first integrated circuit die and the first encapsulant. The method also comprises forming a second integrated circuit die, the second integrated circuit die comprising a second substrate and active devices, the forming of the second integrated circuit die comprising forming a through hole in the second substrate. The method also comprises forming a second redistribution structure above the through hole and the second substrate, the second redistribution structure being electrically coupled to the through hole. The method also comprises forming a first group of conductive vias above the second redistribution structure, and the first group of conductive vias being electrically coupled to the second redistribution structure, the first group of conductive vias being located on a first side of the second substrate. The method also comprises thinning the second side of the second substrate, the thinning exposing the through hole. The method also comprises bonding the first integrated circuit die to the second integrated circuit die. The method also comprises sealing the second integrated circuit die with a second encapsulant. The method also comprises forming a second group of conductive vias above the first group of conductive vias, and the second group of conductive vias being electrically coupled to the first group of conductive vias, the first group of conductive vias and the second group of conductive vias forming stacked conductive vias.

[0111] Embodiments may include one or more of the following features. The method also includes forming a first polymer layer on the first group of conductive vias and the second redistribution structure, the sidewalls of the first polymer layer co-bordering with the sidewalls of the second redistribution structure, and the first group of conductive vias are located in the first polymer layer. The method also includes forming a second polymer layer on the first group of conductive vias, the first polymer layer, and the second sealant, and the second group of conductive vias are located in the second polymer layer. The sidewalls of the second polymer layer co-bordering with the sidewalls of the second sealant. The method also includes forming a conductive component above a carrier substrate, attaching the bonded first integrated circuit die and the second integrated circuit die adjacent to the conductive component to the carrier substrate, sealing the bonded first integrated circuit die and the second integrated circuit die and the conductive component in a third sealant, the third sealant contacting the first sealant and the second sealant, and forming a third redistribution structure above the second integrated circuit die, the conductive component, and the third sealant, the third redistribution structure electrically coupled to the second group of conductive vias and the conductive component.

[0112] An embodiment is a structure comprising a first integrated circuit die bonded to a second integrated circuit die, the first integrated circuit die being located in a first encapsulant, the first integrated circuit die comprising a first substrate. The structure also comprises an active device. The structure also comprises a through-hole located in the first substrate. The structure also comprises a first redistribution structure located above the through-hole and the first substrate, the first redistribution structure being electrically coupled to the through-hole. The structure also comprises a first group of conductive vias located above the first redistribution structure and electrically coupled to the first redistribution structure, the first group of conductive vias being located on a first side of the first substrate. The structure also comprises a second group of conductive vias located above the first group of conductive vias and electrically coupled to the first group of conductive vias, the first group of conductive vias and the second group of conductive vias forming a stacked conductive via.

[0113] Embodiments may include one or more of the following features. The structure also includes a second encapsulant located on a second integrated circuit die, the second integrated circuit die including a second substrate and active devices, and a second redistribution structure located above the second integrated circuit die and the first encapsulant. The structure also includes a first polymer layer located on the first group of conductive vias and the second redistribution structure, the first polymer layer having sidewalls that share a boundary with sidewalls of the second redistribution structure, the first group of conductive vias being located in the first polymer layer, and a second polymer layer located on the first group of conductive vias, the first polymer layer, and the second encapsulant, the second group of conductive vias being located in the second polymer layer, the second polymer layer having sidewalls that share a boundary with sidewalls of the second encapsulant. The first group of conductive vias has a different width than the second group of conductive vias.

[0114] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor package structure, comprising: Forming a first tube core, forming the first tube core includes: forming a through hole in the first substrate; forming a first redistribution structure over the through-hole and the first substrate, the first redistribution structure being electrically coupled to the through-hole; forming a first set of die connections over the first redistribution structure and electrically coupled to the first redistribution structure, the first set of die connections being located on a first side of the first substrate; Thinning the second side of the first substrate, wherein the thinning exposes the through hole; bonding the first die to a second die; encapsulating the first die with a first encapsulant; and A second set of die connections are formed over the first set of die connections and are electrically coupled to the first set of die connections, the first set of die connections and the second set of die connections forming a stacked die connection.

2. The method according to claim 1, further comprising: A first dielectric layer is formed on the first group of die connectors and the first redistribution structure, wherein the first dielectric layer has sidewalls that are common to the sidewalls of the first redistribution structure, and the first group of die connectors are located in the first dielectric layer.

3. The method according to claim 2, further comprising: A second dielectric layer is formed over the first set of die connections, the first dielectric layer, and the first package encapsulant, the second set of die connections being located in the second dielectric layer.

4. The method according to claim 3, wherein: The second dielectric layer has sidewalls that are coterminous with sidewalls of the first sealant.

5. The method according to claim 3, wherein: The first dielectric layer and the second dielectric layer are polymer layers.

6. The method according to claim 5, wherein: The first dielectric layer and the second dielectric layer include different materials.

7. The method according to claim 3, wherein: The first encapsulant contacts the first dielectric layer and sidewalls of the first redistribution structure.

8. The method according to claim 1, wherein: The first set of die connections has a different width than the second set of die connections.

9. A method for forming a semiconductor package structure, comprising: encapsulating a first integrated circuit die in a first encapsulant, the first integrated circuit die comprising a first substrate and active devices; forming a first redistribution structure over the first integrated circuit die and the first encapsulant; Forming a second integrated circuit die, the second integrated circuit die comprising a second substrate and active devices, the forming the second integrated circuit die comprising: forming a through hole in the second substrate; forming a second redistribution structure over the through-hole and the second substrate, the second redistribution structure being electrically coupled to the through-hole; forming a first set of conductive vias over the second redistribution structure and electrically coupled to the second redistribution structure, the first set of conductive vias being located on a first side of the second substrate; thinning the second side of the second substrate, wherein the thinning exposes the through hole; bonding the first integrated circuit die to the second integrated circuit die; encapsulating the second integrated circuit die with a second encapsulant; and A second group of conductive vias is formed over the first group of conductive vias and electrically coupled to the first group of conductive vias, the first group of conductive vias and the second group of conductive vias forming a stacked conductive via.

10. A semiconductor packaging structure, comprising: A first integrated circuit die bonded to a second integrated circuit die, the first integrated circuit die being located in a first encapsulant, the first integrated circuit die comprising: a first substrate; Active devices; a through hole located in the first substrate; a first redistribution structure located above the through hole and the first substrate, the first redistribution structure being electrically coupled to the through hole; a first set of conductive vias over and electrically coupled to the first redistribution structure, the first set of conductive vias being on a first side of the first substrate; and A second group of conductive vias is located above the first group of conductive vias and electrically coupled to the first group of conductive vias, the first group of conductive vias and the second group of conductive vias forming a stacked conductive via.

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