Low burr level conversion circuit for I2C low voltage detection

Abstract

The invention discloses a low-burr level conversion circuit for I2C low-voltage detection, which comprises a transmission response module, a voltage regulation module, a first level conversion module, a second level conversion module and an electrostatic protection module, and is characterized in that the transmission response module is used for pulling down external serial data SDA after a transmitter transmits one byte data; the voltage adjusting module is used for outputting a first adjustable voltage Vb1 and a second adjustable voltage Vb2, and the first level conversion module converts external serial data SDA into high-voltage serial data SDAIN based on the first adjustable voltage Vb1 and the second adjustable voltage Vb2. The second level conversion module converts the external clock pulse SCL into a high-voltage clock pulse SCLIN based on the first adjustable voltage Vb1 and the second adjustable voltage Vb2, and the electrostatic protection module is used for performing high-voltage pulse discharge protection on the external clock pulse SCL. The circuit is suitable for relatively low voltage detection and level conversion, so that a low-voltage serial data signal can be smoothly written into target equipment.

Description

Technical Field

[0001] The invention relates to a level conversion circuit, in particular to a low-burr level conversion circuit for I2C low voltage detection, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] I2C is a two-wire serial communication protocol that uses a serial data line SDA (Serial Data Line) and a serial clock line (Serial Clock Line). It is mainly used for low-speed, short-distance communication. The protocol supports multiple target devices on the communication bus. Communications are sent in the form of byte packets, and each target device has a unique address. In areas such as mobile phone CPUs, many IO voltage domains have low voltages, while the voltages commonly used in peripheral device circuits are 3.3V and 5V. When the CPU (side A) communicates with the peripheral device (side B), there will be a mismatch in the communication interface voltage, and level conversion is required at this time. The lower the voltage on the A side, the higher the low-voltage detection capability required for the level conversion circuit. In addition, the parasitic capacitance introduced by ESD will cause the high and low level flipping of the clock pulse signal during the communication process to generate spike currents, and stray inductance is often inevitably introduced in process links such as chip packaging, and these parasitic inductances will cause large glitches due to spike currents. Nowadays, many mobile phone manufacturers have put forward higher requirements for the voltage detection, glitch amplitude and other performance of level conversion circuits.

[0003] Chinese Patent Publication No. CN111313887B discloses a level conversion circuit and a corresponding driving circuit, which realizes high-speed conversion between two levels by connecting four modules including an input module, a positive feedback module, a level conversion module and an output module. Chinese Patent Publication No. CN111313887B discloses an I2C level conversion circuit, an implementation method, a chip and a communication system. The provided I2C level conversion circuit can be used to transmit high and low levels between a master device and a slave device, so that the master device can read or write to the slave device. Chinese Patent Publication No. CN118646404A discloses a level converter and a digital logic circuit, which realizes level conversion by sequentially coupling an input circuit, a protection circuit, a voltage holding circuit and a latch circuit, and outputs a corresponding switch signal based on the voltage of the voltage signal, so as to instruct the corresponding control module to conduct according to the switch signal, thereby realizing the multi-mode compatibility of the level converter.

[0004] The prior art does not take into account the circuit's level conversion capability at extremely low voltages (as low as 0.8V) and the glitch interference that may occur during I2C data transmission. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a low-glitch level conversion circuit for I2C low voltage detection, which can realize level conversion under extremely low voltage and prevent glitch interference.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is: A low-glitch level conversion circuit for I2C low voltage detection comprises a transmission response module, a voltage regulation module, a first level conversion module, a second level conversion module and an electrostatic protection module. The transmission response module is used to pull down external serial data SDA after a transmitter sends one byte of data. The voltage regulation module is used to output a first adjustable voltage Vb1 and a second adjustable voltage Vb2. The first level conversion module converts the external serial data SDA into high-voltage serial data SDA_IN based on the first adjustable voltage Vb1 and the second adjustable voltage Vb2. The second level conversion module converts an external clock pulse SCL into a high-voltage clock pulse SCL_IN based on the first adjustable voltage Vb1 and the second adjustable voltage Vb2. The electrostatic protection module is used to perform high-voltage pulse discharge protection on the external clock pulse SCL.

[0007] Further, the transmission response module includes an inverter G1, an inverter G2, an inverter G3, a resistor R1, a resistor R2, a capacitor C1, a PMOS tube M0, an NMOS tube M1 and an NMOS tube M2, the input end of the inverter G1 is connected to the transmission response signal SDA_OUT, the output end of the inverter G1 is connected to the input end of the inverter G2, the output end of the inverter G2 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the input end of the inverter G3 and one end of the capacitor C1. The other end of the capacitor C1 is connected to the ground, the other end of the inverter G3 is connected to the gate of the PMOS tube M0 and the gate of the NMOS tube M1, the source of the PMOS tube M0 is connected to the power supply VDD, the drain of the PMOS tube M0 is connected to the drain of the NMOS tube M1 and one end of the resistor R2, the source of the NMOS tube M1 is grounded, the other end of the resistor R2 is connected to the gate of the NMOS tube M2, the drain of the NMOS tube M2 is connected to the external serial data SDA, and the source of the NMOS tube M2 is grounded.

[0008] Furthermore, the resistor R1 and the capacitor C1 form a first-order low-pass filter.

[0009] Further, the voltage regulating module includes a capacitor C2, a capacitor C3, a capacitor C4, a resistor R3, a resistor R4, a resistor R5, an NMOS tube M3, an NMOS tube M4, a PMOS tube M5, a PMOS tube M6, an NMOS tube M7, an NMOS tube M8, a PMOS tube M9 and a PMOS tube M10, one end of the capacitor C2 is connected to the source of the PMOS tube M5, the source of the PMOS tube M6 and the source of the PMOS tube M9 and is connected to the power supply VDD, the other end of the capacitor C2 is connected to the gate of the NMOS tube M3 and the drain of the NMOS tube M4, the drain of the NMOS tube M3 is connected to the drain of the PMOS tube M6, the gate of the PMOS tube M6, the gate of the PMOS tube M5, the gate of the PMOS tube M9 and the drain of the NMOS tube M8, and the NMOS tube M10 is connected to the gate of the PMOS tube M5. The gate of the OS transistor M4 is connected to the gate of the NMOS transistor M7, the drain of the NMOS transistor M7, the drain of the PMOS transistor M5, and the gate of the NMOS transistor M8; the source of the NMOS transistor M8 is connected to one end of the resistor R3; the drain of the PMOS transistor M9 is connected to one end of the resistor R4 and one end of the capacitor C4 to generate a first adjustable voltage Vb1; the other end of the resistor R4 is connected to one end of the resistor R5 and one end of the capacitor C3 to generate a second adjustable voltage Vb2; the other end of the resistor R5 is connected to the source of the PMOS transistor M10; the source of the NMOS transistor M4, the source of the NMOS transistor M3, the source of the NMOS transistor M7, the other end of the resistor R3, the drain of the PMOS transistor M10, the gate of the PMOS transistor M10, the other end of the capacitor C3, and the other end of the capacitor C4 are grounded.

[0010] Furthermore, the PMOS tube M5, PMOS tube M6, NMOS tube M7, NMOS tube M8 and resistor R3 form a current source independent of the power supply VDD, and the capacitor C2, NMOS tube M3 and NMOS tube M4 form a coupled start-up circuit.

[0011] Further, the first level conversion module and the second level conversion module respectively include a resistor R6, a resistor R7, an inverter G4, an inverter G5, an NMOS tube M11, an NMOS tube M12, a PMOS tube M13, a PMOS tube M14, an NMOS tube M15, a PMOS tube M16, a PMOS tube M17, an NMOS tube M18, a PMOS tube M19, an NMOS tube M20, an NMOS tube M21, an NMOS tube M22, a PMOS tube M23 and a PMOS tube M24, one end of the resistor R6 is connected to the external serial data SDA or the external clock pulse SCL, and the other end of the resistor R6 is connected to the external serial data SDA or the external clock pulse SCL. The gate of the PMOS tube M13, the gate of the PMOS tube M14 and the gate of the NMOS tube M15 are connected, the source of the PMOS tube M13 is connected to the source of the NMOS tube M12, the gate of the NMOS tube M12 is connected to the second adjustable voltage Vb2, the drain of the NMOS tube M12 is connected to the source of the NMOS tube M11, the gate of the NMOS tube M11 is connected to the first adjustable voltage Vb1, the drain of the NMOS tube M11 is connected to one end of the resistor R7, the other end of the resistor R7 is connected to the source of the PMOS tube M23 and the source of the PMOS tube M24 and connected to the power supply VDD, the drain of the PMOS tube M13 is connected to the PMOS tube M24, and the gate of the NMOS tube M12 is connected to the second adjustable voltage Vb2. The source of the OS transistor M14, the source of the PMOS transistor M16, the source of the PMOS transistor M17 and the source of the PMOS transistor M19 are connected; the drain of the PMOS transistor M14 is connected to the drain of the NMOS transistor M15, the gate of the PMOS transistor M16, the gate of the PMOS transistor M17 and the gate of the NMOS transistor M18; the drain of the PMOS transistor M17 is connected to the drain of the NMOS transistor M18, the gate of the PMOS transistor M19, the gate of the NMOS transistor M20 and the gate of the NMOS transistor M21; the drain of the PMOS transistor M19 is connected to the drain of the NMOS transistor M20 and the gate of the NMOS transistor M22; The drain of the transistor M21 is connected to the drain of the PMOS transistor M23 and the gate of the PMOS transistor M24, the drain of the NMOS transistor M22 is connected to the input end of the inverter G4, the drain of the PMOS transistor M24 and the gate of the PMOS transistor M23, the output end of the inverter G4 is connected to the input end of the inverter G5, the output end of the inverter G5 generates high-voltage serial data SDA_IN or high-voltage clock pulse SCL_IN, and the source of the NMOS transistor M15, the drain of the PMOS transistor M16, the source of the NMOS transistor M18, the source of the NMOS transistor M20, the source of the NMOS transistor M21 and the source of the NMOS transistor M22 are grounded.

[0012] Furthermore, the NMOS tube M21, NMOS tube M22 and the PMOS tube M23, PMOS tube M24 form a latch structure.

[0013] Furthermore, the electrostatic protection module includes a Zener diode Z1, a resistor R8 and an NMOS tube M25, the cathode of the Zener diode Z1 is connected to the drain of the NMOS tube M25 and connected to the external clock pulse SCL, the anode of the Zener diode Z1 is connected to the gate of the NMOS tube M25 and one end of the resistor R8, and the other end of the resistor R8 and the source of the NMOS tube M25 are grounded.

[0014] Compared with the prior art, the present invention has the following advantages and effects: 1. The present invention provides a low-glitch level conversion circuit for I2C low-voltage detection, which can be applied to lower voltage (as low as 0.8V) detection and level conversion, so that low-voltage serial data signals can be smoothly written into the target device; 2. The present invention can meet the conversion requirements of different degrees of low-voltage scenarios by adjusting the device (resistance) parameters, thereby expanding the application scope of the level conversion circuit; 3. The present invention can prevent spike voltage (burr) generated by parasitic inductance during data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 The present invention is a schematic diagram of a low-glitch level conversion circuit for I2C low voltage detection.

[0016] Figure 2 It is a circuit diagram of the voltage regulation module of the present invention.

[0017] Figure 3 It is a circuit diagram of the first level conversion module and the second level conversion module of the present invention.

[0018] Figure 4 is a circuit diagram of the electrostatic protection module of the present invention. DETAILED DESCRIPTION

[0019] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0020] like Figure 1As shown, a low-glitch level conversion circuit for I2C low voltage detection of the present invention comprises a transmission response module, a voltage adjustment module, a first level conversion module, a second level conversion module and an electrostatic protection module. The transmission response module is used to send a one-bit response signal to respond to the transmitter after the transmitter sends a byte of data, indicating that the transmission is completed, that is, when the transmitter sends a byte of data, the transmission response signal SDA_OUT will flip to a high level. At this time, the external serial data SDA is pulled to a low level, indicating that the transmission is successful. The voltage regulation module is used to output a first adjustable voltage Vb1 and a second adjustable voltage Vb2. The first level conversion module converts the external serial data SDA into high-voltage serial data SDA_IN based on the first adjustable voltage Vb1 and the second adjustable voltage Vb2. The second level conversion module converts the external clock pulse SCL into a high-voltage clock pulse SCL_IN based on the first adjustable voltage Vb1 and the second adjustable voltage Vb2. The electrostatic protection module is used to realize the discharge protection of high-voltage pulses caused by human body, machine, electronic components, etc. At the same time, the module adopts coupling to greatly enhance the discharge capacity of NMOS, thereby achieving the purpose of reducing the burr amplitude caused by parasitic capacitance and stray inductance.

[0021] like Figure 1 As shown, the transmission response module includes an inverter G1, an inverter G2, an inverter G3, a resistor R1, a resistor R2, a capacitor C1, a PMOS tube M0, an NMOS tube M1 and an NMOS tube M2. The input end of the inverter G1 is connected to the transmission response signal SDA_OUT, the output end of the inverter G1 is connected to the input end of the inverter G2, the output end of the inverter G2 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the input end of the inverter G3 and one end of the capacitor C1. The other end of the capacitor C1 is grounded, the other end of the inverter G3 is connected to the gate of the PMOS tube M0 and the gate of the NMOS tube M1, the source of the PMOS tube M0 is connected to the power supply VDD, the drain of the PMOS tube M0 is connected to the drain of the NMOS tube M1 and one end of the resistor R2, the source of the NMOS tube M1 is grounded, the other end of the resistor R2 is connected to the gate of the NMOS tube M2, the drain of the NMOS tube M2 is connected to the external serial data SDA, and the source of the NMOS tube M2 is grounded.

[0022] Among them, the NMOS tube M2 plays the role of strongly pulling down the external serial data SDA to a low level, so as to serve as an ACK signal to indicate that the signal transmission is completed. That is, after the transmitter sends a byte of data, the transmission response signal SDA_OUT turns high, making the NMOS tube M2 turn on, thereby pulling down the external serial data SDA level to respond to the transmitter, indicating that the transmission is successful. In addition, the NMOS tube M2 also has the function of electrostatic discharge protection. When a high-voltage pulse caused by the human body, machines, electronic components, etc. comes: if the NMOS tube M2 is turned off, its function is the same as that of the GGNMOS, that is, the high-voltage pulse turns on the NMOS tube M2 by breaking through the parasitic diode, and discharges the energy, thereby protecting the inside of the chip from damage; if the NMOS tube M2 is turned on, its sufficiently strong overcurrent capability can also discharge the energy, thereby protecting the inside of the chip from damage. The inverter composed of PMOS tube M0 and NMOS tube M1 plays the role of driving NMOS tube M2. Considering that NMOS tube M2 is used to strongly pull down the ACK signal and also serves as the ESD protection of the SDA port, its size is much larger than that of general devices. Therefore, a stronger pre-stage driver is required to quickly charge and discharge the gate capacitance of the NMOS tube. Resistor R2 is a current limiting resistor and plays a protective role. Inverters G1 and G2 rectify the transmission response signal SDA_OUT to prevent the digital signal from being interfered by the long wiring of the layout. Similarly, the first-order low-pass filter composed of resistor R1 and capacitor C1 plays the role of filtering high-frequency glitches such as noise to ensure the correct transmission of the signal.

[0023] like Figure 2As shown, the voltage regulation module includes a capacitor C2, a capacitor C3, a capacitor C4, a resistor R3, a resistor R4, a resistor R5, an NMOS tube M3, an NMOS tube M4, a PMOS tube M5, a PMOS tube M6, an NMOS tube M7, an NMOS tube M8, a PMOS tube M9 and a PMOS tube M10. One end of the capacitor C2 is connected to the source of the PMOS tube M5, the source of the PMOS tube M6 and the source of the PMOS tube M9 and is connected to the power supply VDD. The other end of the capacitor C2 is connected to the gate of the NMOS tube M3 and the drain of the NMOS tube M4. The drain of the NMOS tube M3 is connected to the drain of the PMOS tube M6, the gate of the PMOS tube M6, the gate of the PMOS tube M5, the gate of the PMOS tube M9 and the drain of the NMOS tube M8. The gate of the transistor M4 is connected to the gate of the NMOS transistor M7, the drain of the NMOS transistor M7, the drain of the PMOS transistor M5 and the gate of the NMOS transistor M8, the source of the NMOS transistor M8 is connected to one end of the resistor R3, the drain of the PMOS transistor M9 is connected to one end of the resistor R4 and one end of the capacitor C4 to generate a first adjustable voltage Vb1, the other end of the resistor R4 is connected to one end of the resistor R5 and one end of the capacitor C3 to generate a second adjustable voltage Vb2, the other end of the resistor R5 is connected to the source of the PMOS transistor M10, the source of the NMOS transistor M4, the source of the NMOS transistor M3, the source of the NMOS transistor M7, the other end of the resistor R3, the drain of the PMOS transistor M10, the gate of the PMOS transistor M10, the other end of the capacitor C3 and the other end of the capacitor C4 are grounded.

[0024] PMOS tubes M5 and M6, together with NMOS tubes M7 and M8 and resistor R3, form a current source that is independent of the power supply VDD. The current source flows through resistors R4 and R5 and diode-connected PMOS tube M10 through a current mirror formed by PMOS tubes M6 and M9, thereby outputting a bias voltage that is independent of the power supply voltage VDD, namely, a first adjustable voltage Vb1 and a second adjustable voltage Vb2. Capacitor C2, NMOS tubes M3 and NMOS tubes M4 form a coupling startup circuit. When the chip is powered on, VDD is coupled to the gate of NMOS tube M3 through capacitor C2 to turn it on, thereby lowering the gate voltage of PMOS tubes M5 and M6, helping the current source to leave the zero current merger point after power-on. When the current source is started, NMOS tube M4 is turned on, so that the gate voltage of NMOS tube M3 is lowered, thereby turning off NMOS tube M3, that is, turning off the entire startup circuit. The purpose of this is to reduce the static current of the chip. In addition, according to the need for low voltage detection range in practical applications, the circuit can also use R4 and R5 resistors with different resistance values ​​to meet the needs of different application scenarios.

[0025] like Figure 3As shown, the first level conversion module and the second level conversion module respectively include a resistor R6, a resistor R7, an inverter G4, an inverter G5, an NMOS tube M11, an NMOS tube M12, a PMOS tube M13, a PMOS tube M14, an NMOS tube M15, a PMOS tube M16, a PMOS tube M17, an NMOS tube M18, a PMOS tube M19, an NMOS tube M20, an NMOS tube M21, an NMOS tube M22, a PMOS tube M23 and a PMOS tube M24, one end of the resistor R6 is connected to the external serial data SDA or the external clock pulse SCL, and the other end of the resistor R6 is connected to the PMOS tube M16. The gate of the S transistor M13, the gate of the PMOS transistor M14 and the gate of the NMOS transistor M15 are connected, the source of the PMOS transistor M13 is connected to the source of the NMOS transistor M12, the gate of the NMOS transistor M12 is connected to the second adjustable voltage Vb2, the drain of the NMOS transistor M12 is connected to the source of the NMOS transistor M11, the gate of the NMOS transistor M11 is connected to the first adjustable voltage Vb1, the drain of the NMOS transistor M11 is connected to one end of the resistor R7, the other end of the resistor R7 is connected to the source of the PMOS transistor M23 and the source of the PMOS transistor M24 and connected to the power supply VDD, the drain of the PMOS transistor M13 is connected to the PMOS The source of the transistor M14, the source of the PMOS transistor M16, the source of the PMOS transistor M17 and the source of the PMOS transistor M19 are connected; the drain of the PMOS transistor M14 is connected to the drain of the NMOS transistor M15, the gate of the PMOS transistor M16, the gate of the PMOS transistor M17 and the gate of the NMOS transistor M18; the drain of the PMOS transistor M17 is connected to the drain of the NMOS transistor M18, the gate of the PMOS transistor M19, the gate of the NMOS transistor M20 and the gate of the NMOS transistor M21; the drain of the PMOS transistor M19 is connected to the drain of the NMOS transistor M20 and the gate of the NMOS transistor M22; the drain of the NMOS transistor M21 is connected to the drain of the NMOS transistor M22 and the gate of the NMOS transistor M23. The drain of M21 is connected to the drain of the PMOS tube M23 and the gate of the PMOS tube M24, the drain of the NMOS tube M22 is connected to the input end of the inverter G4, the drain of the PMOS tube M24 and the gate of the PMOS tube M23, the output end of the inverter G4 is connected to the input end of the inverter G5, the output end of the inverter G5 generates high-voltage serial data SDA_IN or high-voltage clock pulse SCL_IN, the source of the NMOS tube M15, the drain of the PMOS tube M16, the source of the NMOS tube M18, the source of the NMOS tube M20, the source of the NMOS tube M21 and the source of the NMOS tube M22 are grounded.

[0026] The function of the NMOS tubes M11 and M12 is to compress the detection window of the level conversion circuit, thereby realizing the function of low input voltage detection. The input detection voltage rail is determined by the gate voltage of the NMOS tube M12, that is, the second adjustable voltage Vb2. The NMOS tube M11 and the NMOS tube M12 form a common source and common gate structure. As a common gate tube, the NMOS tube M12 also plays a role in shielding the interference of the power supply voltage jitter on the detection window voltage rail (the source voltage of the PMOS tube M13). Similarly, the function of the PMOS tubes M14 and M16 is also to avoid the repeated flipping of the level shift signal caused by the jitter of the electrical signal under critical conditions. It is a level shift circuit. The circuit introduces hysteresis. By adjusting the size of the PMOS tubes M13, M14, and M16, the hysteresis interval can be changed, thereby ensuring the transmission reliability of the level shift circuit. The input signal is converted to the power supply voltage rail where the PMOS tubes M23, M24 and the inverters G4 and G5 are located through the inverter composed of the PMOS tubes M17, M19 and the NMOS tubes M18, M20 and the low-voltage rail where the NMOS tubes M21 and M22 are located. The latch structure composed of the NMOS tubes M21, M22 and the PMOS tubes M23, M24 accelerates the signal flipping and reduces the transmission delay, making the circuit also applicable to some high-speed application scenarios.

[0027] like Figure 4 As shown, the electrostatic protection module includes a Zener diode Z1, a resistor R8 and an NMOS tube M25, the cathode of the Zener diode Z1 is connected to the drain of the NMOS tube M25 and connected to the external clock pulse SCL, the anode of the Zener diode Z1 is connected to the gate of the NMOS tube M25 and one end of the resistor R8, and the other end of the resistor R8 and the source of the NMOS tube M25 are grounded.

[0028] Compared with the GGNMOS structure used in the traditional ESD protection module, the present invention adopts the Zener diode coupling method to greatly reduce the size of the NMOS tube M25 under the same discharge capacity of the circuit, that is, its parasitic capacitance is also reduced, which will reduce the peak current caused by the flip of the clock pulse signal SCL during the communication process. For the inevitable parasitic inductance caused by the chip package and the PCB board, the induced electromotive force against the rapid change of current will also become smaller, and the flip burrs reflected in the clock pulse will be greatly reduced, thereby meeting the new generation requirements of many mobile phone manufacturers such as Samsung and OPPO for level conversion circuits.

[0029] The present invention provides a low-glitch level conversion circuit for I2C low-voltage detection, which can be applicable to relatively low voltage (as low as 0.8V) detection and level conversion, so that low-voltage serial data signals can be smoothly written into a target device; the present invention can meet the conversion requirements of low-voltage scenes of different degrees by adjusting device (resistance) parameters, and expand the application scope of the level conversion circuit; the present invention can prevent spike voltage (glitch) generated by parasitic inductance during data transmission.

[0030] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A low glitch level conversion circuit for I2C low voltage detection, characterized in that: It includes a transmission response module, a voltage regulation module, a first level conversion module, a second level conversion module and an electrostatic protection module. The transmission response module is used to pull down the external serial data SDA after the transmitter sends one byte of data. The voltage regulation module is used to output a first adjustable voltage Vb1 and a second adjustable voltage Vb2. The first level conversion module converts the external serial data SDA into high-voltage serial data SDA_IN based on the first adjustable voltage Vb1 and the second adjustable voltage Vb2. The second level conversion module converts the external clock pulse SCL into a high-voltage clock pulse SCL_IN based on the first adjustable voltage Vb1 and the second adjustable voltage Vb2. The electrostatic protection module is used to perform high-voltage pulse discharge protection on the external clock pulse SCL.

2. A low glitch level conversion circuit for I2C low voltage detection according to claim 1, characterized in that: The transmission response module comprises an inverter G1, an inverter G2, an inverter G3, a resistor R1, a resistor R2, a capacitor C1, a PMOS tube M0, an NMOS tube M1 and an NMOS tube M2. The input end of the inverter G1 is connected to the transmission response signal SDA_OUT, the output end of the inverter G1 is connected to the input end of the inverter G2, the output end of the inverter G2 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the input end of the inverter G3 and one end of the capacitor C1, the other end of the capacitor C1 is grounded, the other end of the inverter G3 is connected to the gate of the PMOS tube M0 and the gate of the NMOS tube M1, the source of the PMOS tube M0 is connected to the power supply VDD, the drain of the PMOS tube M0 is connected to the drain of the NMOS tube M1 and one end of the resistor R2, the source of the NMOS tube M1 is grounded, the other end of the resistor R2 is connected to the gate of the NMOS tube M2, the drain of the NMOS tube M2 is connected to the external serial data SDA, and the source of the NMOS tube M2 is grounded.

3. A low glitch level conversion circuit for I2C low voltage detection according to claim 2, characterized in that: The resistor R1 and the capacitor C1 form a first-order low-pass filter.

4. The low glitch level conversion circuit for I2C low voltage detection according to claim 1, characterized in that: The voltage regulating module comprises a capacitor C2, a capacitor C3, a capacitor C4, a resistor R3, a resistor R4, a resistor R5, an NMOS tube M3, an NMOS tube M4, a PMOS tube M5, a PMOS tube M6, an NMOS tube M7, an NMOS tube M8, a PMOS tube M9 and a PMOS tube M10. One end of the capacitor C2 is connected to the source of the PMOS tube M5, the source of the PMOS tube M6 and the source of the PMOS tube M9 and is connected to a power supply VDD. The other end of the capacitor C2 is connected to the gate of the NMOS tube M3 and the drain of the NMOS tube M4. The drain of the NMOS tube M3 is connected to the drain of the PMOS tube M6, the gate of the PMOS tube M6, the gate of the PMOS tube M5, the gate of the PMOS tube M9 and the drain of the NMOS tube M8. The gate of M4 is connected to the gate of NMOS tube M7, the drain of NMOS tube M7, the drain of PMOS tube M5 and the gate of NMOS tube M8, the source of NMOS tube M8 is connected to one end of resistor R3, the drain of PMOS tube M9 is connected to one end of resistor R4 and one end of capacitor C4 to generate a first adjustable voltage Vb1, the other end of resistor R4 is connected to one end of resistor R5 and one end of capacitor C3 to generate a second adjustable voltage Vb2, the other end of resistor R5 is connected to the source of PMOS tube M10, the source of NMOS tube M4, the source of NMOS tube M3, the source of NMOS tube M7, the other end of resistor R3, the drain of PMOS tube M10, the gate of PMOS tube M10, the other end of capacitor C3 and the other end of capacitor C4 are grounded.

5. A low glitch level conversion circuit for I2C low voltage detection according to claim 4, characterized in that: The PMOS tube M5, PMOS tube M6, NMOS tube M7, NMOS tube M8 and resistor R3 form a current source independent of the power supply VDD, and the capacitor C2, NMOS tube M3 and NMOS tube M4 form a coupling start circuit.

6. A low glitch level conversion circuit for I2C low voltage detection according to claim 1, characterized in that: The first level conversion module and the second level conversion module respectively include a resistor R6, a resistor R7, an inverter G4, an inverter G5, an NMOS tube M11, an NMOS tube M12, a PMOS tube M13, a PMOS tube M14, an NMOS tube M15, a PMOS tube M16, a PMOS tube M17, an NMOS tube M18, a PMOS tube M19, an NMOS tube M20, an NMOS tube M21, an NMOS tube M22, a PMOS tube M23 and a PMOS tube M24, one end of the resistor R6 is connected to an external serial data SDA or an external clock pulse SCL, and the other end of the resistor R6 is connected to the PMOS The gate of the transistor M13, the gate of the PMOS transistor M14 and the gate of the NMOS transistor M15 are connected, the source of the PMOS transistor M13 is connected to the source of the NMOS transistor M12, the gate of the NMOS transistor M12 is connected to the second adjustable voltage Vb2, the drain of the NMOS transistor M12 is connected to the source of the NMOS transistor M11, the gate of the NMOS transistor M11 is connected to the first adjustable voltage Vb1, the drain of the NMOS transistor M11 is connected to one end of the resistor R7, the other end of the resistor R7 is connected to the source of the PMOS transistor M23 and the source of the PMOS transistor M24 and connected to the power supply VDD, the drain of the PMOS transistor M13 is connected to the PMOS The source of the transistor M14, the source of the PMOS transistor M16, the source of the PMOS transistor M17 and the source of the PMOS transistor M19 are connected; the drain of the PMOS transistor M14 is connected to the drain of the NMOS transistor M15, the gate of the PMOS transistor M16, the gate of the PMOS transistor M17 and the gate of the NMOS transistor M18; the drain of the PMOS transistor M17 is connected to the drain of the NMOS transistor M18, the gate of the PMOS transistor M19, the gate of the NMOS transistor M20 and the gate of the NMOS transistor M21; the drain of the PMOS transistor M19 is connected to the drain of the NMOS transistor M20 and the gate of the NMOS transistor M22; the drain of the NMOS transistor M21 is connected to the drain of the NMOS transistor M22 and the gate of the NMOS transistor M23. The drain of M21 is connected to the drain of the PMOS tube M23 and the gate of the PMOS tube M24, the drain of the NMOS tube M22 is connected to the input end of the inverter G4, the drain of the PMOS tube M24 and the gate of the PMOS tube M23, the output end of the inverter G4 is connected to the input end of the inverter G5, the output end of the inverter G5 generates high-voltage serial data SDA_IN or high-voltage clock pulse SCL_IN, the source of the NMOS tube M15, the drain of the PMOS tube M16, the source of the NMOS tube M18, the source of the NMOS tube M20, the source of the NMOS tube M21 and the source of the NMOS tube M22 are grounded.

7. A low glitch level conversion circuit for I2C low voltage detection according to claim 6, characterized in that: The NMOS tube M21, NMOS tube M22 and the PMOS tube M23, PMOS tube M24 form a latch structure.

8. The low glitch level conversion circuit for I2C low voltage detection according to claim 1, characterized in that: The electrostatic protection module includes a Zener diode Z1, a resistor R8 and an NMOS tube M25, the cathode of the Zener diode Z1 is connected to the drain of the NMOS tube M25 and connected to the external clock pulse SCL, the anode of the Zener diode Z1 is connected to the gate of the NMOS tube M25 and one end of the resistor R8, and the other end of the resistor R8 and the source of the NMOS tube M25 are grounded.

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