Method of controlling a high-gain image sensor

Abstract

The application provides a control method of a high-gain image sensor, which comprises the following steps: setting a column bias current source and a column PMOS amplifier in a column signal readout unit, connecting the column bias current source with a current output connection line shared by columns, connecting a drain of the column PMOS amplifier with a current input connection line shared by columns, and connecting a gate of the column PMOS amplifier with the current output connection line shared by columns directly or through a capacitor, so that the signal of a readout row pixel unit floating diffusion region amplified on the current input connection line shared by columns is obtained, the super high conversion gain is realized, and the dynamic range in a dark light scene is expanded; the device structure size in the column signal readout unit can be far greater than the transistor in the pixel, the process consistency is better, and the conversion gain can be adjusted more flexibly; and the switching between the SHCG mode and the STD mode is realized by driving a switch module in the column signal readout unit, the impact on the power supply and the ground is smaller during operation, and the circuit stability is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to a control method of a high-gain image sensor. BACKGROUND

[0002] Standard image sensors have a limited dynamic range of approximately 60-70 dB. However, the dynamic range of real-world luminance is much larger. Natural scenes often span a range of 90 dB and above. Image sensors have a functional requirement of single-frame high dynamic range (HDR) in certain application scenarios, such as shooting moving objects or scenes that pursue high-frame-rate shooting readout.

[0003] In current CMOS image sensors, 3T or 4T pixel structures are commonly used. Figure 1 A conventional 4T pixel is shown as an example), the main reason being that the amplification tube M3 in the pixel is a source follower structure (SF), the pixel output voltage range is large, and the reset voltage has high freedom, and the conversion gain is approximately inversely proportional to the FD node (M3 gate) capacitance. In order to achieve better noise performance at low illumination, another approach in the industry is to change the amplification tube in the pixel to work in a common-source amplification structure, i.e., a so-called capacitor feedback transimpedance amplifier (CTIA) pixel structure (as shown in Figure 2 The conversion gain is approximately inversely proportional to the capacitance between the M3 gate and the drain. Since the CTIA pixel can achieve higher conversion gain than the conventional 4T pixel. However, the main problem of the CTIA pixel is that the working range is small, the reset voltage needs to be more accurate, the PVT robustness is poor, and the output voltage is easily saturated due to charge injection.

[0004] In order to integrate the advantages of the above two structures, patent US10277848B2 proposes a hybrid pixel structure combining the two structures, which can switch between SF and CTIA modes by switching the peripheral circuit, but requires an additional reference voltage, and still cannot solve the problems of the CTIA pixel itself. Patent CN110537366A proposes a differential pixel structure that can improve the problems of single-ended CTIA pixels to some extent, but the working process and timing of the differential structure are more complex, and the power consumption is also significantly increased, which will be limited in applications. Patent CN107770461 proposes a pixel structure with double-gain output, which combines the pixel and the amplifier in the column circuit to realize SF and CTIA mode signal output, but this structure requires additional capacitors and transistors in the pixel and additional signal output lines, increasing the complexity of the pixel. The amplifier in the column circuit also increases the overall power consumption. SUMMARY

[0005] The present application aims to provide a control method of high gain image sensor, which can realize higher conversion gain through simple structure improvement and lower power consumption cost on the basis of traditional pixel structure.

[0006] Based on the above consideration, the present application provides a control method of high gain image sensor, which comprises a plurality of pixel units arranged in an array, each column of pixel units having a column-shared current input line and a column-shared current output line, the gate of the source follower transistor of each pixel unit in each column being connected to a respective floating diffusion region, the drain of the source follower transistor being connected to the column-shared current input line, and the source of the source follower transistor being connected to the column-shared current output line directly or through a respective row select transistor; the column-shared current input line and the column-shared current output line being connected to a column signal readout unit; the column signal readout unit comprising a column bias current source and a column PMOS amplifier, the column bias current source being connected to the column-shared current output line, the drain of the column PMOS amplifier being connected to the column-shared current input line, and the gate of the column PMOS amplifier being connected to the column-shared current output line directly or through a capacitor, so that an amplified signal of the readout row pixel unit floating diffusion region can be obtained on the column-shared current input line.

[0007] Preferably, when the gate of the column PMOS amplifier is connected to the column-shared current output line through a first capacitor, a second capacitor is arranged between the gate and the drain of the column PMOS amplifier, and the amplification multiple of the column signal readout unit on the column-shared current input line for the readout row pixel unit floating diffusion region signal can be changed by changing the ratio of the first capacitor and the second capacitor.

[0008] Preferably, the column signal readout unit further comprises a related power generation module, which latches the first bias voltage and outputs a column second power voltage to the source of the column PMOS amplifier, so that the power supply of the column signal readout unit has correlation when sampling the reference signal and the image signal, thereby eliminating the influence of power supply noise on the correlated double sampling.

[0009] Preferably, the related power generation module comprises at least one source follower transistor, the drain of the source follower transistor of the related power generation module being connected to a first power voltage, the source being connected to a column second power voltage output end, and the gate sampling and latching the first bias voltage before the time of sampling the reference signal, so as to generate the column second power voltage required by the column signal readout unit, which has correlation when sampling the reference signal and the image signal.

[0010] Preferably, the gate of the source follower transistor of the relevant power generation module samples the first bias voltage through the seventh switch and is held on the third capacitor, and the sample and hold is performed line by line or frame by frame before the sampling of the reference signal.

[0011] Preferably, the column signal readout unit further comprises a noise compensation module which senses the fluctuation of the first power supply voltage or the column second power supply voltage and generates a negative feedback signal acting on the column second power supply voltage to suppress the fluctuation of the column second power supply voltage.

[0012] Preferably, the noise compensation module comprises a current mirror unit, the bias end of the current mirror unit is connected to the first power supply voltage output end through the fourth capacitor, and the drain of the current mirror unit is connected to the column second power supply voltage output end.

[0013] Preferably, the bias end of the current mirror unit further samples the second bias voltage through the eighth switch and is held on the fifth capacitor to perform sample and hold line by line or frame by frame.

[0014] Preferably, the current mirror unit is a common source and common gate current mirror.

[0015] Preferably, the noise compensation module comprises an amplification transistor, the gate of the amplification transistor is connected to the column second power supply voltage output end through the sixth capacitor, the drain is connected to a current source, and the gate is connected to the gate of the source follower transistor of the relevant power generation circuit through the seventh capacitor, and the gate and the drain of the amplification transistor are connected with the ninth switch, and the direct current bias of the amplification transistor can be realized by closing the ninth switch line by line or frame by frame.

[0016] Preferably, the column signal readout unit further comprises a clamping module, and the voltage of the source follower transistor drain of the pixel unit is clamped to the same level through the clamping module before the sampling of the reference signal and the sampling of the image signal.

[0017] Preferably, the clamping module comprises a clamping transistor, the source of the clamping transistor is connected to the column second power supply voltage, the gate and the drain are connected to each other, and the drain is connected to the source follower transistor drain of the pixel unit through the tenth switch.

[0018] Preferably, the size of the clamping transistor is a fixed size or an array adjustable size.

[0019] Preferably, each column signal readout unit corresponds to one relevant power generation module, or a plurality of column signal readout units correspond to one relevant power generation module.

[0020] Preferably, each column signal readout unit corresponds to one noise compensation module, or a plurality of column signal readout units correspond to one noise compensation module.

[0021] Preferably, each column signal readout unit corresponds to one noise compensation module, or a plurality of column signal readout units correspond to one noise compensation module.

[0022] Preferably, the control method of the high-gain image sensor comprises: sampling a source output of a source follower transistor of the pixel unit to the column signal readout unit as a first reference signal; sampling a drain output of the source follower transistor of the pixel unit to the column signal readout unit as a second reference signal; opening a transfer transistor of the pixel unit, and sampling an image signal output by the pixel unit to the column signal readout unit.

[0023] Preferably, the step of sampling the image signal output by the pixel unit to the column signal readout unit comprises: judging according to a voltage signal read from the pixel unit; if the judging result is a high-illumination condition, sampling a source output of a source follower transistor of the pixel unit to the column signal readout unit as a first image signal, the pixel unit having a first conversion gain; if the judging result is a low-illumination condition, sampling a drain output of the source follower transistor of the pixel unit to the column signal readout unit as a second image signal, the pixel unit having a second conversion gain; the second conversion gain being higher than the first conversion gain.

[0024] Preferably, the step of judging according to a voltage signal read from the pixel unit comprises: comparing a change amplitude of the voltage signal read from the pixel unit before and after opening the transfer transistor with a threshold voltage, if the change amplitude is less than or equal to the threshold voltage, it is a low-illumination condition, and if the change amplitude is greater than the threshold voltage, it is a high-illumination condition.

[0025] Preferably, a falling interval of a slope voltage of analog-to-digital conversion is used as the threshold voltage.

[0026] Preferably, the step of sampling the image signal output by the pixel unit to the column signal readout unit comprises: sampling a drain output of a source follower transistor of the pixel unit to the column signal readout unit as a second image signal, the pixel unit having a second conversion gain; sampling a source output of the source follower transistor of the pixel unit to the column signal readout unit as a first image signal, the pixel unit having a first conversion gain; the second conversion gain being higher than the first conversion gain.

[0027] Preferably, when the source output of the source follower transistor of the pixel unit is output to the column signal readout unit, the first conversion gain is adjusted by a double-conversion-gain control transistor of the pixel unit.

[0028] Preferably, the step of adjusting the first conversion gain by the double conversion gain control transistor of the pixel unit comprises: opening the double conversion gain control transistor to obtain a relatively low first conversion gain, or closing the double conversion gain control transistor to obtain a relatively high first conversion gain.

[0029] Preferably, the source or drain of the source follower transistor of the pixel unit is controlled by the switch module to output to the column signal readout unit.

[0030] Compared with the prior art, the internal structure of the pixel unit of the high-gain image sensor of the present application is consistent with that of the conventional 3T or 4T pixel, and has good process compatibility; only the circuit structure and connection mode of the column signal readout unit are improved, so that super high conversion gain (SHCG) can be realized, the dynamic range in a dark light scene is expanded, and the power consumption caused by the introduction of an additional reference voltage and an additional amplification circuit is avoided; the device structure size in the column signal readout unit can be much larger than that of the transistor in the pixel, the process consistency is better, and the conversion gain can be adjusted more flexibly; the switch module in the column signal readout unit can be driven without driving the signal in the pixel array, so that the switching between the SHCG mode and the STD mode (standard mode, i.e. the conventional source follower mode) can be realized, the impact on the power supply and ground during operation is smaller, and the circuit stability is improved.

[0031] Preferably, the first bias voltage is latched by the related power generation module and the column second power voltage is output to the source of the column PMOS amplifier tube, so that the power supply of the column signal readout unit has correlation when sampling the reference signal and the image signal, thereby eliminating the influence of power supply noise on the correlated double sampling and improving the imaging quality; the fluctuation of the first power voltage or the column second power voltage is sensed by the noise compensation module and a negative feedback signal is generated to act on the column second power voltage, so as to suppress the fluctuation of the column second power voltage and further reduce the power supply noise; before sampling the reference signal and the image signal, the voltage of the source follower transistor drain of the pixel unit is clamped to the same level by the clamping module, so as to speed up the signal stabilization speed, improve the consistency of the reference signal and the image signal, and improve the image quality. BRIEF DESCRIPTION OF DRAWINGS

[0032] Other features, objects and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments, read in conjunction with the accompanying drawings.

[0033] Figure 1 a circuit schematic diagram of a 4T pixel structure image sensor of the prior art;

[0034] Figure 2 Circuit schematic diagram of a CTIA pixel structure image sensor of the prior art;

[0035] Figure 3 System schematic diagram of a high-gain image sensor of the present application;

[0036] Figure 4 Circuit schematic diagram of a 4T pixel cell of a high-gain image sensor of the present application;

[0037] Figure 5 Circuit schematic diagram of a high-gain image sensor according to embodiment one of the present application;

[0038] Figure 6 Equivalent circuit diagram of the high-gain image sensor of Figure 5 in STD mode;

[0039] Figure 7 Signal timing diagram of the high-gain image sensor of Figure 5 in STD mode;

[0040] Figure 8 Equivalent circuit diagram of the high-gain image sensor of Figure 5 in SHCG mode;

[0041] Figure 9 Signal timing diagram of the high-gain image sensor of Figure 5 in SHCG mode;

[0042] Figure 10 Conversion gain curve of the high-gain image sensor of Figure 5 in both modes;

[0043] Figure 11 Circuit schematic diagram of a high-gain image sensor according to embodiment two of the present application;

[0044] Figure 12 Circuit schematic diagram of a high-gain image sensor according to embodiment three of the present application;

[0045] Figure 13 Flowchart of a control method of the high-gain image sensor of Figure 12 ;

[0046] Figure 14 Signal timing diagram of the control method of Figure 13 under high-illumination conditions;

[0047] Figure 15 Signal timing diagram of the control method of Figure 13 under low-illumination conditions;

[0048] Figure 16 isFigure 12 Another flowchart illustrating the control method for a high-gain image sensor;

[0049] Figure 17 for Figure 16 Signal timing diagram of the control method;

[0050] Figure 18 This is a circuit diagram of a high-gain image sensor according to Embodiment 4 of the present invention;

[0051] Figure 19 for Figure 18 A circuit diagram of a related power generation module and a noise compensation module in a high-gain image sensor;

[0052] Figure 20 for Figure 18 Another circuit diagram of the relevant power generation module and noise compensation module in a high-gain image sensor;

[0053] Figure 21 for Figure 20 The signal timing diagrams for the relevant power generation module and noise compensation module;

[0054] Figure 22 for Figure 18 A circuit diagram of a clamping module in a high-gain image sensor;

[0055] Figure 23 for Figure 22 Signal timing diagram of a high-gain image sensor in SHCG mode.

[0056] Throughout the figures, the same or similar reference numerals denote the same or similar devices (modules) or steps. Implementation

[0057] To address the problems in the prior art, this invention provides a control method for a high-gain image sensor. By configuring a column bias current source and a column PMOS amplifier in the column signal readout unit, the column bias current source is connected to a shared column current output line, the drain of the column PMOS amplifier is connected to a shared column current input line, and the gate of the column PMOS amplifier is directly or via a capacitor connected to the shared column current output line. This allows an amplified signal from the floating diffusion region of the readout row pixel unit to be obtained on the shared column current input line.

[0058] In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings that form a part hereof. The drawings illustrate a particular embodiment of the invention, and a person skilled in the art can understand that other embodiments can be made without departing from the scope of the invention. It is also to be understood that features shown in the drawings are for illustration only. Therefore, the following detailed description is not intended to limit the scope of the invention, and the scope of the present invention is defined by the appended claims.

[0059] The specific embodiments will be described in detail in the following.

[0060] As shown in Figure 3 , Figure 4 , Figure 5 The high-gain image sensor according to the first embodiment of the present application includes a plurality of column pixel units 101 arranged in an array and a plurality of column signal readout units 201, each of which corresponds to one or more column pixel units 101 in the pixel array 100 and is configured to read out a voltage signal (Vout) from the corresponding column pixel units 101. Figure 5 Fig. 4 shows one of the pixel units P in the Mth column of pixel units 101. <n>and the specific circuit of the corresponding column signal readout unit M as an example.

[0061] Specifically, each pixel unit 101 includes a photodiode PD and a plurality of pixel transistors, i.e. a transfer transistor Ml, a reset transistor M2, a source follower transistor M3, and a row selection transistor M4. The photodiode PD is configured to photoelectrically convert incident light to obtain a corresponding electric charge, the transfer transistor Ml is configured to transfer the electric charge accumulated in the photodiode PD to a floating diffusion region FD, the reset transistor M2 is configured to reset the electric potential of the floating diffusion region FD, the source follower transistor M3 is configured to convert the electric charge of the floating diffusion region FD into a corresponding voltage signal, and the row selection transistor M4 is configured to output the voltage signal to the corresponding column signal readout unit 201.

[0062] Each column of pixel units 101 has a column-shared current input line 112 and a column-shared current output line 111, the gate of the source follower transistor M3 of each pixel unit 101 in each column is connected to the respective floating diffusion region FD, the drain of the source follower transistor M3 is connected to the column-shared current input line 112, and the source of the source follower transistor M3 is connected to the column-shared current output line 111 through the respective row selection transistor M4. It should be noted that in the 4T pixel structure shown in FIG. 1, the row selection transistor M4 is connected between the source of the source follower transistor M3 and the column-shared current output line 111, and in other 4T pixel structures not shown, the row selection transistor M4 can also be connected between the drain of the source follower transistor M3 and the column-shared current input line 112, and in 3T pixel structures, the row selection transistor M4 can also be omitted, so that the source of the source follower transistor M3 is directly connected to the column-shared current output line 111. Figure 4 、 Figure 5 In the 4T pixel structure shown in FIG. 1, the row selection transistor M4 is connected between the source of the source follower transistor M3 and the column-shared current output line 111, and in other 4T pixel structures not shown, the row selection transistor M4 can also be connected between the drain of the source follower transistor M3 and the column-shared current input line 112, and in 3T pixel structures, the row selection transistor M4 can also be omitted, so that the source of the source follower transistor M3 is directly connected to the column-shared current output line 111.

[0063] The column-shared current input line 112 and the column-shared current output line 111 are connected to a corresponding column signal readout unit 201, which includes a column bias current source CS and a column PMOS amplifier M5. In this embodiment, one column PMOS amplifier M5 is shown as an example, and those skilled in the art can understand that in other embodiments not shown, there can be multiple column PMOS amplifiers M5. The column bias current source CS is connected to the column-shared current output line 111, the drain of the column PMOS amplifier M5 is connected to the column-shared current input line 112, and the gate of the column PMOS amplifier M5 is connected to the column-shared current output line 111, so that the signal of the readout row pixel unit floating diffusion region can be amplified on the column-shared current input line 112. In addition, the source of the column PMOS transistor M5 is connected to the first power supply voltage VDD1, which is used to provide a power supply voltage for the column PMOS transistor M5. By using the column PMOS amplifier M5 to amplify the signal of the readout row pixel unit floating diffusion region, the structure is simple, the noise is small, and the voltage margin is large.

[0064] Preferably, when the gate of the column PMOS amplifier M5 is connected to the column-shared current output line 111 through the first capacitor C1, a second capacitor C2 is provided between the gate and the drain of the column PMOS amplifier M5. Specifically, the column-shared current output line 111 is connected to the first end of the first capacitor C1, the second end of the first capacitor C1 is connected to the first end of the second capacitor C2 and the gate of the column PMOS amplifier M5, and the second end of the second capacitor C2 and the drain of the column PMOS amplifier M5 are connected to the column-shared current input line 112. The second capacitor C2 can be a parasitic capacitor of the column PMOS amplifier M5, or it can be an independent capacitor device like the first capacitor C1. The first capacitor C1 and the second capacitor C2 can be fixed capacitors or variable capacitor arrays, so that by changing the ratio of the first capacitor C1 and the second capacitor C2, the amplification factor of the column signal readout unit 201 on the column-shared current input line 112 for the signal of the readout row pixel unit floating diffusion region can be changed, so as to flexibly adjust the conversion gain of the pixel unit. Preferably, the column signal readout unit 201 further includes a first switch S4 connected in parallel with the second capacitor C2, which is used for self-clearing operation of the column PMOS amplifier M5.

[0065] Based on the above structure, the column signal readout unit 201 can read out the voltage signal V HG from the drain of the source follower transistor M3, and the transconductance Gm of the first capacitor C1, the second capacitor C2, and the column PMOS amplifier M5 provides the floating diffusion region FD to the output node V HG , so it can be called as Super High Conversion Gain (SHCG) mode. Since the first capacitor C1, the second capacitor C2 and the column PMOS amplifier M5 are located in the peripheral circuit, the size can be much larger than the in-pixel transistor M3, and the process consistency is better than the traditional CTIA pixel structure, and the conversion gain can be adjusted more flexibly.

[0066] Further preferably, the source or the drain of the source follower transistor M3 of the pixel unit 101 can be output to the column signal reading unit 201 through a switch module to realize the switching between the SHCG mode and the STD mode. Specifically, the column signal reading unit 201 further comprises a first switch S1, a second switch S2 and a third switch S3. The column-shared current output line 111 is connected to the first end of the first capacitor C1, the second end of the second capacitor C2 and the drain of the column PMOS amplifier M5 through the first switch S1. The column-shared current input line 112 is connected to the drain of the column PMOS amplifier M5 through the second switch S2. The column-shared current input line 112 is connected to the first power supply voltage VDD1 through the third switch S3.

[0067] Therefore, when the third switch S3 is closed and the first switch S1 and the second switch S2 are disconnected, the image sensor works in the equivalent circuit of the STD mode as shown in Figure 6 , and the signal timing is as shown in Figure 7 In this mode, the rear-stage reading circuit 207 reads the first voltage signal V SF from the source of the source follower transistor M3, which is equivalent to the traditional source follower mode. At this time, the first conversion gain CG1 is relatively low:

[0068] .

[0069] When the third switch S3 is disconnected and the first switch S1 and the second switch S2 are connected, the image sensor works in the equivalent circuit of the SHCG mode as shown in Figure 8 , and the signal timing is as shown in Figure 9 In this mode, the rear-stage reading circuit 207 reads the second voltage signal V HG from the drain of the source follower transistor M3. At this time, the second conversion gain CG2 is relatively high:

[0070] .

[0071] The conversion gain curves in the two modes are shown in Figure 10 .

[0072] As shown in Figure 11 As shown, in another preferred embodiment of the image sensor of the present application, the first capacitor C1, the second capacitor C2 and the fourth switch S4 can also be omitted, that is, the gate of the column PMOS amplifier M5 is directly connected to the column-shared current output line 111. It should be noted that when this capacitor-omitted structure is adopted, the connection mode of the drain of the reset transistor M2 to the drain of the source follower transistor M3 in the pixel unit 101 (different from the connection of the drain of the reset transistor M2 to the third power supply voltage VDD3 in the first embodiment) should be matched accordingly, so as to realize self-clearing of the pixel unit.

[0073] Further preferably, the column signal readout unit 201 further comprises a fifth switch S5 and a sixth switch S6, the column-shared current output line 111 is connected to the gate of the column PMOS amplifier M5 through the fifth switch S5, and the gate of the column PMOS amplifier M5 is also connected to the ground voltage through the sixth switch S6.

[0074] Thus, when the sixth switch S6 is closed and the fifth switch S5 is opened, the column PMOS amplifier M5 functions as a switch and is turned on, the image sensor operates in the STD mode, and the later-stage readout circuit 207 reads out the first voltage signal V SF , which is equivalent to the conventional source follower mode, and the first conversion gain CG1 is low at this time.

[0075] When the sixth switch S6 is opened and the fifth switch S5 is closed, the column PMOS amplifier M5 functions as an amplifier unit, the image sensor operates in the SHCG mode, and the later-stage readout circuit 207 reads out the second voltage signal V HG from the drain of the source follower transistor M3, and the second conversion gain CG2 is high at this time.

[0076] In addition, the existing variable conversion gain image sensor often uses a dual conversion gain (DCG) design. This design introduces an additional capacitor and adds a control switch, for example, a metal oxide semiconductor field effect transistor (MOSFET). When a higher signal strength needs to be read out, the switch is opened to connect the FD to the capacitor, helping to extract the charge, and the conversion gain is low (LCG mode) at this time; when a lower signal strength needs to be read out, the switch is closed, so as to obtain a higher conversion gain (HCG mode) and improve the readout signal-to-noise ratio. This scheme performs well in the existing pixel design and can effectively expand the dynamic range without changing the PD design.

[0077] The readout operation of the existing row control type dual conversion gain (row-DCG) image sensor includes four stages of sampling LCG reference signal, sampling HCG reference signal, sampling HCG image signal and sampling LCG image signal (i.e., LCG ref, HCG ref, HCGsig, LCG sig), and the image signals output by the pixel units under two conversion gains need to be quantized and stored respectively, which is not conducive to high-speed operation; when the existing column control type dual conversion gain (col-DCG) image sensor performs readout operation, the conversion gain of the pixel unit is adjusted by each column readout circuit according to the bit line voltage, but since the control signals of each column pixel unit are shared, the column control circuit has a heavy load, and there is a problem of too large impact on the power supply when the control signal flips.

[0078] The high-gain image sensor can be multiplexed with the conventional DCG scheme, for example, the drain of the source follower transistor M3 is output in the SHCG mode (second conversion gain CG2) in an extremely dark scene, and the source of the source follower transistor M3 is output in the STD mode (first conversion gain CG1) in a relatively dark or relatively bright scene; in the STD mode, the first conversion gain CG1 is further adjusted by the row control circuit by opening or closing the DCG transistor according to the applied scene, specifically, the DCG transistor is opened to obtain a relatively low first conversion gain (Low-CG1), or the DCG transistor is closed to obtain a relatively high first conversion gain (High-CG1), so as to select a relatively high HCG or a relatively low LCG readout mode, thereby further expanding the dynamic range.

[0079] The following will be based on the circuit structure of Figure 12 , and the control method of the high-gain image sensor will be described in detail, which can reduce the impact of switching operation, improve circuit stability and improve reading efficiency while achieving high dynamic range by adjusting the conversion gain of the pixel unit.

[0080] The floating diffusion region FD is connected with the DCG control transistor M0, the equivalent capacitances of the FD point in the on and off states of the DCG control transistor M0 are different, the FD capacitance increases when M0 is turned on, and more electrons can be collected from the PD tube to expand the dynamic range. The connection modes of the other transistors are all prior art, and will not be described in detail. The third switch S3 is controlled by the signal SHCG_ENB, the first switch S1 and the second switch S2 are controlled by the signal SHCG_EN, and the high level represents that the switch is closed, and the low level represents that the switch is opened; the signals SHCG_EN and SHCG_ENB are reverse digital control signals, which are automatically output by the rear-stage readout circuit 207 according to the size of the input signal.

[0081] As Figure 13 As shown, a flow of the conversion gain control method of the high-gain image sensor includes:

[0082] Step S11: sampling the source output of the source follower transistor of the pixel unit to the first reference signal of the column signal reading unit;

[0083] Step S12: sampling the drain output of the source follower transistor of the pixel unit to the second reference signal of the column signal reading unit;

[0084] Step S13: turning on the transfer transistor of the pixel unit;

[0085] Step S14: judging the light intensity of the pixel unit according to the voltage signal read from the pixel unit;

[0086] Step S15: according to the judgment result, sampling the image signal output by the pixel unit to the column signal reading unit (step S151: under high-illumination conditions, sampling the source output of the source follower transistor of the pixel unit to the first image signal of the column signal reading unit; or step S152: under low-illumination conditions, sampling the drain output of the source follower transistor of the pixel unit to the second image signal of the column signal reading unit).

[0087] Specifically, Figure 14 is Figure 13 The timing diagram of the embodiment shown under high-illumination conditions includes four stages:

[0088] (1) STD_ref stage

[0089] The SHCG_EN signal is low, the third switch S3 is closed, and the first switch S1 and the second switch S2 are disconnected. At this time, the column PMOS amplifier M5 is not connected with the pixel circuit, V HG The voltage is connected to the first power supply voltage VDD1 through the third switch S3, and the column signal reading unit 201 is in the STD mode. In this mode, the output node of the pixel unit 101 is the source of the source follower transistor M3, and the voltage V SF is the effective signal input to the post-stage reading circuit 207. In the pixel unit 101, the SEL becomes high to select this row, and the DCG and RST signals are high at the same time to reset the FD point in the pixel unit 101. Then, the RST signal becomes low, and the DCG has two states, which are keeping high or becoming low, representing that the STD mode can support the LCG mode or the HCG mode, and the dynamic range can be more flexibly selected. The post-stage reading circuit 207 quantizes the V SF voltage to read out the STD_ref reset information, that is, to complete the step of sampling the source output of the source follower transistor M3 of the pixel unit 101 to the first reference signal STD_ref of the column signal reading unit 201.

[0090] (2) SHCG_ref stage

[0091] The SHCG_EN signal becomes high, the third switch S3 is opened, and the first switch S1 and the second switch S2 are closed. At this time, the column PMOS amplifier M5 is connected to the pixel circuit, forming a closed loop, and the V SF voltage is disconnected from the subsequent readout circuit 207. The column signal reading unit 201 is in the SHCG mode. In this mode, the output node of the pixel unit 101 is the drain of the source follower transistor M3, and the V HG voltage is the effective signal input to the subsequent readout circuit 207. Since the column PMOS amplifier M5 has a negative gain -AV, the miller effect causes most of the electrons flowing out of the PD tube in the pixel unit 101 to flow to the capacitor C GD , thereby obtaining a higher conversion gain than in the STD mode. The subsequent readout circuit 207 quantizes the V HG voltage to read the SHCG_ref reset information, i.e., to complete the step of outputting the drain of the source follower transistor M3 of the sampling pixel unit 101 to the second reference signal SHCG_ref of the column signal reading unit 201.

[0092] (3) flag (flag) determination stage

[0093] The circuit is still in the SHCG mode. The TX signal in the pixel unit 101 becomes high, and the electrons in the PD tube flow out through the open transfer transistor M1, and the V HG signal generates a corresponding voltage according to the number of electrons.

[0094] Next, the voltage signal read from the pixel unit is determined. Determining the strength of the light requires a reference threshold voltage V flag . The V flag voltage can be designed to be adjustable in amplitude to achieve the best image effect. In this embodiment, the falling interval of the slope voltage (V ramp ) of the analog-to-digital conversion is used as the threshold voltage V flag . In other embodiments not shown, a new threshold voltage can also be introduced. The change in amplitude of the voltage signal V HG read from the pixel unit 101 before and after opening the transfer transistor M1 is compared with the threshold voltage V flag . If the change in amplitude of V HG is less than or equal to the threshold voltage V flag , it is a low-illumination condition. If the change in amplitude of V HG is greater than the threshold voltage V flag , it is a high-illumination condition.

[0095] For example, if the result of the judgment is high-illumination condition, a relatively low conversion gain can be selected, and the circuit enters the STD_sig stage.

[0096] (4) STD_sig stage

[0097] The SHCG_EN signal becomes low, and the circuit switches to the STD mode, and the V HG signal is connected to the VDD1, and the subsequent readout circuit 207 quantizes the V SF signal according to the first reference signal STD_ref, the pixel unit 101 has a first conversion gain CG1.

[0098] Figure 15 is Figure 13 The timing diagram of the embodiment shown in FIG. 6 under low-illumination condition also includes four stages, the first two stages are the same as those of the embodiment shown in FIG. 5, and the difference lies in the last two stages. Figure 14

[0099] (3) flag (flag) judgment stage

[0100] The circuit is still in the SHCG mode, the TX signal in the pixel unit 101 becomes high, the electrons in the PD tube flow out through the opened transfer transistor M1, and the V HG signal is generated according to the number of electrons.

[0101] Next, the voltage signal read from the pixel unit is judged. The falling interval of the slope voltage (V ramp ) of the analog-to-digital conversion is used as the threshold voltage V flag , and the change amplitude of the voltage signal V HG read from the pixel unit 101 before and after the opening of the transfer transistor M1 is compared with the threshold voltage V flag , and if the change amplitude of the V HG is less than or equal to the threshold voltage V flag , the result of the judgment is low-illumination condition, and a higher conversion gain is needed to obtain good image quality, and the circuit enters the SHCG_sig stage.

[0102] (4) SHCG_sig stage

[0103] The SHCG_EN signal remains high, and the circuit is still in the SHCG mode, and the subsequent readout circuit 207 quantizes the V HG ​The signal readout and the light intensity related image information, i.e. the second image signal SHCG_sig sampled from the drain output of the source follower transistor M3 of the pixel unit to the column signal read unit, has a second conversion gain CG2 according to the second image signal SHCG_sig and the second reference signal SHCG_ref, and the second conversion gain CG2 is greater than the first conversion gain CG1.

[0104] As shown in Figures 13-15 the above embodiment, first, the source output of the source follower transistor of the pixel unit is sampled to the first reference signal STD_ref of the column signal read unit and the drain output of the source follower transistor is sampled to the second reference signal SHCG_ref of the column signal read unit, then the light intensity of the pixel unit is determined according to the voltage signal read from the pixel unit, and then the appropriate readout architecture is automatically selected, the second image signal SHCG_sig sampled from the drain output of the source follower transistor or the first image signal STD_sig sampled from the source output of the source follower transistor is sampled, so as to adaptively adjust the conversion gain of the image sensor, realize high dynamic range, and especially the SHCG readout mode from the drain output of the source follower transistor can expand the dynamic range in the dark light scene, and when adjusting the conversion gain of the pixel unit, only the switch module in the column signal read unit needs to be driven, and the impact on the power supply and ground during switching operation is smaller, and the circuit stability is improved. At the same time, in the reading period of each pixel unit, only two reference signals ref and one image signal sig need to be read, which is beneficial to improve the reading efficiency and generate HDR image with higher frame rate.

[0105] In addition, the SHCG_EN signal of the high-gain image sensor of the present application can also be switched to column circuit global control, and then readout is performed in cooperation with the row control signal, which can support the readout timing sequence as shown in Figure 17 , sequentially performing the four processes of STD ref, SHCGref, SHCGsig and STD sig to generate the HDR image. As shown in Figure 15 , another process of the conversion gain control method of the high-gain image sensor of the present application includes:

[0106] Step S21: sampling the source output of the source follower transistor of the pixel unit to the first reference signal (STD_ref stage) of the column signal read unit;

[0107] Step S22: sampling the drain output of the source follower transistor of the pixel unit to the second reference signal (SHCG_ref stage) of the column signal read unit;

[0108] Step S23: turning on the transfer transistor of the pixel unit;

[0109] Step S24: sampling the drain output of the source follower transistor of the pixel unit to the second image signal of the column signal reading unit, the pixel unit having a second conversion gain (SHCG_sig stage);

[0110] Step S25: sampling the source output of the source follower transistor of the pixel unit to the first image signal of the column signal reading unit, the pixel unit having a first conversion gain, the second conversion gain being higher than the first conversion gain (STD_sig stage).

[0111] The circuit principle and switching process of each stage are similar to the foregoing embodiments, and will not be described here again.

[0112] It should be noted that the specific circuit and signal timing of the embodiments of the present application are only examples, and other variants or implementations can be made by those skilled in the art according to common knowledge in the art, for example, controlling the source or drain output of the source follower transistor of the pixel unit to the column signal reading unit through other forms of switching module, as long as the source output of the source follower transistor of the pixel unit to the first reference signal of the column signal reading unit and the drain output of the source follower transistor to the second reference signal of the column signal reading unit are sampled first, and the image signal output from the pixel unit to the column signal reading unit is sampled as needed, so that the conversion gain of the pixel unit is adjusted to realize high dynamic range, which can be used to achieve the purpose of the present application, and should be included in the protection scope of the present application.

[0113] In addition, since the column PMOS amplifier M5 is introduced in the column signal reading unit, it is more dependent on the low-noise analog power supply. In actual image sensors, the circuit structure of column reading is mostly used and the analog power supply VDD1 is shared, however, in the quantization process, the sizes of the column image signals are inconsistent, the inversion points are different, the dynamic currents are different, the time and amplitude of the power supply impact are also different, and the fluctuations generated by the impact of the power supply will in turn affect the quantization of the column signal; in addition, the noise input by the power supply will also be coupled into the reading circuit, affecting the quantization result of the correlated double sampling, and thus various image abnormalities such as horizontal stripes, tailing, etc. will occur.

[0114] In addition, because the output impedance of V HG in the SHCG mode is greater than the output impedance of V SF in the STD mode, the V HG signal has a relatively slow setup time, and the long setup time will affect the reading frame rate and image quality of the image sensor. Before reading the ref signal, the S4 switch acts, and due to the channel charge injection effect and clock feedthrough effect, the gate voltage of the column PMOS amplifier M5 fluctuates, thereby causing the V HG Voltage fluctuation; and before reading the sig signal, the switching action of the pixel transfer transistor M1 also causes the voltage fluctuation of the pixel FD point, thereby causing V HG Voltage fluctuation.

[0115] To further solve the above problems, the present inventors have found, by research, that Figure 18 As shown in another preferred embodiment, a related power generation module 205 can be added in the column signal readout unit 201, the first bias voltage Vbias is latched by the related power generation module 205 and the column second power voltage VDD2 is output to the column PMOS amplifier M5, so that the power supply of the column PMOS amplifier M5 has correlation when sampling the reference signal and the image signal, thereby eliminating the influence of power supply noise on the correlated double sampling, and improving the imaging quality;

[0116] Preferably, a noise compensation module 206 can also be added in the column signal readout unit 201, the fluctuation of the first power voltage VDD1 or the column second power voltage VDD2 is sensed by the noise compensation module 206 and a negative feedback signal is generated to act on the column second power voltage VDD2, so as to suppress the fluctuation of the column second power voltage VDD2 and further reduce the power supply noise;

[0117] Preferably, a clamping module 203 can also be added in the column signal readout unit 201, before sampling the reference signal and the image signal, the voltage of the source follower transistor M3 drain of the pixel unit is clamped to the same level by the clamping module 203, so as to accelerate the signal stabilization speed, improve the consistency of the reference signal and the image signal, and improve the image quality.

[0118] Specifically, Figure 19 For Figure 18 A circuit schematic diagram of the related power generation module 205 and the noise compensation module 206 in the high-gain image sensor.

[0119] The related power generation module 205 includes a source follower transistor M7, the drain of the source follower transistor M7 is connected to the first power voltage VDD1, the source is connected to the column second power voltage output end VDD2, and the gate samples and latches the first bias voltage Vbias before the sampling of the reference signal, thereby generating the column second power voltage VDD2 required by the column signal readout unit, which has correlation when sampling the reference signal and the image signal. In other embodiments not shown, those skilled in the art can also select to use a combination of multiple source follower transistors as a source follower according to the needs, so as to realize the function of the related power generation module 205. The related power generation circuit 205 is realized by the source follower transistor, the circuit structure is simple, the area consumption is small, and the output voltage is easy to program and control.

[0120] Preferably, the gate of the source follower transistor M7 of the related power generation module 205 samples the first bias voltage Vbias through the seventh switch S7 and is held on the third capacitor C3, and the sampling and holding is performed row by row or frame by frame before the sampling of the reference signal.

[0121] The noise compensation module 206 includes a current mirror unit 208 with feedback. The bias end of the current mirror unit 208 is connected to the first power supply voltage VDD1 output end through the fourth capacitor C4, and the drain of the current mirror unit 208 is connected to the column second power supply voltage VDD2 output end. The working principle is that the bias end of the current mirror unit 208 receives the fluctuation of the first power supply voltage VDD1 to change the current size of the column second power supply voltage VDD2 flowing out, thereby affecting the voltage fluctuation of the column second power supply voltage VDD2, forming a negative feedback compensation.

[0122] Preferably, the current mirror unit 208 in the embodiment is a cascode current mirror composed of NMOS M8 and M9. The common gate tube M9 functions to increase the output resistance of the current mirror unit and reduce the influence of the drain voltage change on the current of the current mirror unit. The gate Vnbin of the amplifier tube M8 is connected to the second bias voltage Nbias through the eighth switch S8. S8 is turned on once per row or per frame to sample the second bias voltage Nbias and hold it on the fifth capacitor C5. Vnbin is also coupled to the first power supply voltage VDD1 through the fourth capacitor C4. When there is an upward disturbance on the input first power supply voltage VDD1, there will also be an upward disturbance on the column second power supply voltage VDD2. However, through the processing of the aforementioned related power generation module 205, the disturbance amplitude on the column second power supply voltage VDD2 will be greatly attenuated. The Vnbin voltage coupled to the first power supply voltage VDD1 rises accordingly, and the current of the amplifier tube M8 controlled by Vnbin increases, and the current flowing out of the node VDD2 increases, and the voltage of VDD2 decreases accordingly, forming a negative feedback compensation and further suppressing the slight disturbance on VDD2. Conversely, the same is true.

[0123] Figure 20 For Figure 18 Another circuit schematic diagram of the related power generation module 205 and the noise compensation module 206 in the high-gain image sensor.

[0124] In the embodiment, the structure of the related power generation module 205 is the same as that of Figure 19 The difference is that the noise compensation circuit 206 includes an amplifier transistor M10, capacitors C6 and C7, a switch S9 and a current source CS2, and the working timing is shown in Figure 21 In this circuit, the gate of the amplifying transistor M10 is connected to the output terminal of the second power supply voltage VDD2 via a sixth capacitor C6, and the drain is connected to the current source CS2 and the gate of the source follower transistor M7 of the related power generation circuit via a seventh capacitor C7. A ninth switch S9 is connected between the gate and drain of the amplifying transistor M10, and the DC bias of the amplifying transistor M10 can be achieved by closing the ninth switch S9 row by row or frame by frame.

[0125] like Figure 21 As shown, the gate voltage of the source follower transistor M7 in the relevant power generation module 205 is sampled when the seventh switch S7 is turned on. The ninth switch S9 in the noise compensation circuit 206 samples the first bias voltage Vbias during the time period t1'~t2'. At the same time, the amplifying transistor M10 performs a reset operation. The sixth capacitor C6 and the seventh capacitor C7 have a voltage blocking function, which allows the gate of the amplifying transistor M10 to be at a suitable voltage bias. After time t2', the seventh switch S7 is turned off, and the gate voltage of the M7 transistor is sampled. Then, after time t3', the ninth switch S9 is turned off, and the closed-loop negative feedback circuit composed of the M7 and M10 transistors works. Under the action of voltage negative feedback, the output impedance of the column second power supply voltage VDD2 node is greatly reduced, further reducing the impact of power supply noise on the column second power supply voltage VDD2 node.

[0126] Figure 22 for Figure 18 A circuit diagram of a clamping module in a high-gain image sensor. In this embodiment, the clamping module 203 includes a clamping transistor M6 and a tenth switch S10. The source of the clamping transistor M6 is connected to the column second power supply voltage VDD2; the gate and drain are connected together, and the drain is connected to the column common current input line 112 (VDD2) of the source follower transistor drain of the pixel unit through the tenth switch S10. HG Among them, the clamping transistor M6 can be a fixed size or a variable array with adjustable array size.

[0127] Figure 23 for Figure 22 The signal timing diagram of a high-gain image sensor in SHCG mode. First, let's explain... Figure 23 During the timing sequence shown, the first switch S1 is always on, and the third switch S3 is always off.

[0128] During the time period t1~t2, the reset transistor M2 in pixel unit 101 is turned on, resetting FD to the first power supply voltage VDD1, and the fourth switch S4 of column amplifier PMOS transistor M5 is turned on, resetting column amplifier PMOS transistor M5.

[0129] The period from t2 to t3, the column amplification PMOS tube M5 completes reset, and the fourth switch S4 is disconnected after t3;

[0130] The period from t3 to t4, the S10 switch is turned on, the S2 switch is turned off, and the clamping module 203 clamps the voltage V HG of the source follower transistor drain of the pixel unit to a preset fixed voltage. After t4, the clamping is completed, the switch S10 is disconnected, the switch S2 is turned on, the column-shared current input line 112 (V HG ) establishes the reset signal ref of the SHCG mode;

[0131] The period from t4 to t7, the ref signal of the SHCG mode is sampled and quantized;

[0132] The period from t8 to t10, the transfer transistor M1 in the pixel unit 101 is turned on and then turned off, and similarly, the clamping module 203 clamps V HG to the same preset fixed voltage;

[0133] The period from t11 to t12, the sig signal of the SHCG mode is quantized.

[0134] Therefore, before the sampling of the reference signal and the sampling of the image signal, the voltage of the source follower transistor drain of the pixel unit is clamped to the same level by the clamping module, which can accelerate the signal stabilization speed, improve the consistency of the reference signal and the image signal, and improve the image quality.

[0135] It should be noted that in the above embodiments, each column signal readout unit corresponds to a related power generation module, each column signal readout unit corresponds to a noise compensation module, and each column signal readout unit corresponds to a clamping module. In other embodiments not shown, those skilled in the art can select an appropriate number of column signal readout units corresponding to a related power generation module, a plurality of column signal readout units corresponding to a noise compensation module, and a plurality of column signal readout units corresponding to a clamping module according to the needs.

[0136] In summary, the internal structure of the pixel unit of the high-gain image sensor of the present application is consistent with the conventional 3T or 4T pixel, and has good process compatibility; only the circuit structure and connection mode of the column signal readout unit are improved, so that the ultra-high conversion gain is realized, the dynamic range in the dark light scene is expanded, and the power consumption caused by the introduction of an additional reference voltage and an additional amplification circuit is avoided; the device structure size in the column signal readout unit can be much larger than the transistor in the pixel, and the process consistency is better, and the conversion gain can be adjusted more flexibly; the switching between the SHCG mode and the STD mode can be realized by driving the switching module in the column signal readout unit without driving the signal in the pixel array, the impact on the power supply and ground during operation is smaller, and the circuit stability is improved.

[0137] Preferably, the first bias voltage is latched by the related power generation module and a column second power voltage is output to the source of the column PMOS amplifier tube, so that the power supply of the column signal readout unit has correlation when sampling the reference signal and the image signal, thereby eliminating the influence of power supply noise on the correlated double sampling and improving the imaging quality. The fluctuation of the first power voltage or the column second power voltage is sensed by the noise compensation module and a negative feedback signal is generated to act on the column second power voltage, so as to suppress the fluctuation of the column second power voltage and further reduce the power supply noise. Before sampling the reference signal and the image signal, the voltages of the source follower transistors of the pixel units are clamped to the same level by the clamping module, so as to accelerate the signal stabilization speed, improve the consistency of the reference signal and the image signal, and improve the image quality.

[0138] It is obvious to a person skilled in the art that the present application is not limited to the details of the above exemplary embodiments, and the present application can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be regarded as exemplary and non-limiting in any way. Furthermore, it is obvious that the word "comprising" does not exclude other elements and steps, and the word "one" does not exclude a plurality. The plurality of elements stated in the device claims can also be implemented by one element. The words first, second, etc. are used to indicate names, and do not indicate any particular order.< / n>

Claims

1. A control method of a high-gain image sensor, characterized in that, the image sensor comprises a plurality of pixel units arranged in an array, each column of pixel units has a column-shared current input line and a column-shared current output line, the gate of the source follower transistor of each pixel unit in each column is connected to a respective floating diffusion region, the drain of the source follower transistor is connected to the column-shared current input line, and the source of the source follower transistor is connected to the column-shared current output line directly or through a respective row select transistor; the column-shared current input line and the column-shared current output line are connected to a column signal readout unit; the column signal readout unit comprises a column bias current source and a column PMOS amplifier, the column bias current source is connected to the column-shared current output line, the drain of the column PMOS amplifier is connected to the column-shared current input line, and the gate of the column PMOS amplifier is connected to the column-shared current output line directly or through a capacitor, and an amplified signal of the readout row pixel unit floating diffusion region can be obtained on the column-shared current input line.

2. The control method of a high-gain image sensor according to claim 1, characterized by, when the gate of the column PMOS amplifier is connected to the column-shared current output line through a first capacitor, a second capacitor is arranged between the gate and the drain of the column PMOS amplifier, and the amplification factor of the column signal readout unit on the readout row pixel unit floating diffusion region signal on the column-shared current input line is changed by changing the ratio of the first capacitor and the second capacitor.

3. The control method of a high-gain image sensor according to claim 1, wherein the column signal readout unit further comprises a related power generation module, the first bias voltage is latched by the related power generation module, and a column second power voltage is output to the source of the column PMOS amplifier, so that the power supply of the column signal readout unit has correlation when sampling the reference signal and the image signal, thereby eliminating the influence of power supply noise on the correlated double sampling.

4. The control method of a high-gain image sensor according to claim 3, characterized by, the related power generation module comprises at least one source follower transistor, the drain of the source follower transistor of the related power generation module is connected to a first power voltage, the source is connected to a column second power voltage output end, the gate samples and latches the first bias voltage before the time of the sampling reference signal, and generates the column second power voltage required by the column signal readout unit, which has correlation when sampling the reference signal and the image signal.

5. The control method of a high-gain image sensor according to claim 4, characterized by, the gate of the source follower transistor of the related power generation module samples the first bias voltage through a seventh switch and holds it on a third capacitor, and the sampling and holding is performed row by row or frame by frame before the time of the sampling reference signal.

6. The control method of a high-gain image sensor according to claim 4, wherein the column signal readout unit further comprises a noise compensation module, the noise compensation module senses the fluctuation of the first power voltage or the column second power voltage and generates a negative feedback signal acting on the column second power voltage to suppress the fluctuation of the column second power voltage.

7. The control method of a high-gain image sensor according to claim 6, wherein the noise compensation module comprises a current mirror unit, the bias end of the current mirror unit is connected to the first power voltage output end through a fourth capacitor, and the drain of the current mirror unit is connected to the column second power voltage output end.

8. The control method of a high-gain image sensor according to claim 7, wherein The bias end of the current mirror unit also samples a second bias voltage through an eighth switch and keeps on a fifth capacitor to perform sample and hold line by line or frame by frame.

9. The control method of a high-gain image sensor according to claim 7, wherein The current mirror unit is a common source and common gate current mirror.

10. The method of controlling a high-gain image sensor according to claim 6, wherein, The noise compensation module comprises an amplification transistor, a gate of the amplification transistor is connected with the column second power voltage output end through a sixth capacitor, a drain is connected with a current source, and a gate is connected with a source follower transistor of the related power generation module through a seventh capacitor, a ninth switch is connected between the gate and the drain of the amplification transistor, and direct current bias of the amplification transistor is realized by closing the ninth switch line by line or frame by frame.

11. The method of controlling a high-gain image sensor according to claim 3, wherein, The column signal readout unit further comprises a clamping module, and the voltage of the source follower transistor drain of the pixel unit is clamped to the same level through the clamping module respectively before sampling the reference signal and the sampling image signal.

12. The control method of a high-gain image sensor according to claim 11, wherein The clamping module comprises a clamping transistor, a source of the clamping transistor is connected with the column second power voltage, a gate and a drain are connected with each other, and the drain is connected with the source follower transistor drain of the pixel unit through a tenth switch.

13. The method of controlling a high-gain image sensor according to claim 12, wherein, The size of the clamping transistor is a fixed size or an array adjustable size.

14. The method of controlling a high-gain image sensor according to claim 3, wherein, Each column signal readout unit corresponds to one related power generation module, or a plurality of column signal readout units correspond to one related power generation module.

15. The method of controlling a high-gain image sensor according to claim 6, wherein, Each column signal readout unit corresponds to one noise compensation module, or a plurality of column signal readout units correspond to one noise compensation module.

16. The method of controlling a high-gain image sensor according to claim 11, wherein, Each column signal readout unit corresponds to one clamping module, or a plurality of column signal readout units correspond to one clamping module.

17. The method of controlling a high-gain image sensor according to claim 1, wherein, It comprises: The source of the source follower transistor of the pixel unit is sampled and output to the first reference signal of the column signal readout unit. The drain of the source follower transistor of the pixel unit is sampled and output to the second reference signal of the column signal readout unit. The transfer transistor of the pixel unit is opened, and the image signal output to the column signal readout unit is sampled.

18. The method of controlling a high-gain image sensor according to claim 17, wherein, The step of sampling the image signal output to the column signal readout unit comprises: According to the voltage signal read from the pixel unit, a judgment is made. If the judgment result is a high-illumination condition, the source of the source follower transistor of the pixel unit is sampled and output to the first image signal of the column signal readout unit, and the pixel unit has a first conversion gain. If the judgment result is a low-illumination condition, the drain of the source follower transistor of the pixel unit is sampled and output to the second image signal of the column signal readout unit, and the pixel unit has a second conversion gain. The second conversion gain is higher than the first conversion gain.

19. The method of controlling a high-gain image sensor according to claim 18, wherein, The step of judging according to the voltage signal read from the pixel unit comprises: The change amplitude of the voltage signal read from the pixel unit before and after the transfer transistor is opened is compared with a threshold voltage, if the change amplitude is less than or equal to the threshold voltage, it is a low-illumination condition, and if the change amplitude is greater than the threshold voltage, it is a high-illumination condition.

20. The method of controlling a high-gain image sensor according to claim 19, wherein, The falling interval of the slope voltage of the analog-to-digital conversion is used as the threshold voltage.

21. The method of controlling a high-gain image sensor of claim 17, wherein, The step of sampling the image signal outputted from the pixel unit to the column signal readout unit comprises: sampling a second image signal outputted from a drain of a source follower transistor of the pixel unit to the column signal readout unit, the pixel unit having a second conversion gain; sampling a first image signal outputted from a source of the source follower transistor of the pixel unit to the column signal readout unit, the pixel unit having a first conversion gain; the second conversion gain is higher than the first conversion gain.

22. The control method of a high-gain image sensor according to claim 18 or 21, wherein The first conversion gain is adjusted by a double conversion gain control transistor of the pixel unit when the source of the source follower transistor of the pixel unit outputs to the column signal readout unit.

23. The method of controlling a high-gain image sensor according to claim 22, wherein, The step of adjusting the first conversion gain by the double conversion gain control transistor of the pixel unit comprises: opening the double conversion gain control transistor to obtain a relatively lower first conversion gain, or closing the double conversion gain control transistor to obtain a relatively higher first conversion gain.

24. The method of controlling a high-gain image sensor of claim 17, wherein, The source or the drain of the source follower transistor of the pixel unit is controlled by a switch module to output to the column signal readout unit.

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