Parallel-serial conversion circuit based on composite dielectric gate photosensitive detector

Abstract

The application discloses a parallel-serial conversion circuit based on a composite medium grating photosensitive detector and belongs to the integrated circuit field.The parallel-serial conversion circuit comprises a composite medium grating photosensitive detector pixel, a slope generator, a clamping circuit, a switch S1, a pre-charge circuit, a comparator, a counter, an 8-256 decoder, a first AND gate and 256 second AND gates, and a 256-input OR gate.The parallel-serial conversion circuit converts all digital circuit parts into analog circuits, thereby reducing the circuit design complexity, shortening the circuit simulation and layout design iteration period, effectively reducing the power consumption and area of the chip, and being beneficial to the design of a subsequent miniaturized system.

Description

TECHNICAL FIELD

[0001] The present application relates to a parallel-to-serial conversion circuit based on a composite gate photodetector, belonging to the field of integrated circuits. BACKGROUND

[0002] At present, CCD and CMOS-APS are the most common two kinds of imaging devices, but each has certain limitations. CCD has slow running speed and is difficult to achieve high integration due to the need for complex timing control and voltage requirements; and CMOS-APS has low fill factor and small full well charge capacity due to the use of photodiodes and complex structure.

[0003] Chinese Patent No. CN102938409A discloses a composite gate dual transistor photosensitive detector, which has the characteristics of single device having reset, photosensitive and readout functions, thereby forming a complete pixel. The detector of this structure can greatly improve the fill factor of the pixel, has faster working speed, larger fill factor, more full well charge and can be integrated with CMOS process. The device uses a threshold variable MOSFET signal readout area for readout, which has an inherent advantage compared with CCD and CMOS-APS.

[0004] Based on the above characteristics, the device readout current can be quantized and the circuit for detecting the change of device readout current caused by threshold voltage change can realize stable and high-speed readout of the composite gate dual transistor photosensitive detector. Chinese Patents No. CN116017184A and CN117135478A respectively disclose a composite gate dual transistor pixel readout circuit based on an inverter chain transimpedance amplifier and a composite gate transistor pixel readout circuit based on a double transimpedance amplifier, which uses a slope generator, a transimpedance amplifier, a driving stage and a counter to realize analog conversion and digital readout of the device current. However, the analog circuit part of the imaging device readout current is converted into digital output by the counter, and then the digital circuit is used to convert the parallel data into serial data, which requires an analog-digital hybrid circuit, which increases the difficulty of circuit design, verification and testing. In addition, the analog-digital hybrid circuit also needs the fusion of different process requirements and the matching of process parameters. At the same time, process non-ideality increases the difficulty of circuit layout design, requires additional noise isolation and increases the wiring complexity, resulting in longer cycle for iteration of front-end circuit simulation and back-end layout design. SUMMARY

[0005] In order to solve the problem of complex analog-digital hybrid circuit design, the present application provides a parallel-to-serial conversion circuit based on a composite gate photodetector, which uses pure analog circuit to convert parallel imaging device readout current data into serial data, thereby reducing the complexity of circuit design and shortening the iteration cycle of circuit simulation and layout design.

[0006] The technical scheme of the present application is as follows:

[0007] The parallel-serial conversion circuit based on the composite medium gate photosensitive detector comprises a composite medium gate photosensitive detector pixel, a slope generator, a clamping circuit, a switch S1, a pre-charge circuit, a comparator, a counter, an 8-256 decoder, a first AND gate and a second AND gate, and a 256-input OR gate.

[0008] Further, the composite medium gate photosensitive detector pixel comprises a MOS-C (Metal-Oxide-Semiconductor-Capacitor) signal collection region and a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) signal readout region. In the exposure mode, the MOS-C signal collection region generates a depletion region in the substrate under the action of the gate-substrate forward bias, thereby realizing the collection of the photo-generated carriers; in the readout mode, the threshold voltage of the transistor of the MOSFET signal readout region changes according to the amount of the collected photo-generated carrier charges, thereby realizing the readout of the photo-generated carrier signals.

[0009] Further, the clamping circuit is composed of an amplifier and a transistor; the pre-charge circuit is composed of an integral capacitor C INT and a transistor; and the first AND gate serves as the enable switch of the counter.

[0010] Further, the transistor in the clamping circuit is denoted as a first transistor M1, the gate of the first transistor M1 is connected to the output of the amplifier, the drain of the composite medium gate photosensitive detector pixel is connected to one input of the amplifier, the other input of the amplifier is provided with a clamping voltage V REF,CLAMP from outside; the source of the first transistor M1 is connected to the drain of the composite medium gate photosensitive detector pixel, thereby forming a feedback loop; and the drain of the first transistor M1 is connected to one end of the switch S1.

[0011] Further, the transistor in the pre-charge circuit is denoted as a second transistor M2, the gate of the second transistor M2 is connected to a pre-charge voltage V Precharge provided from outside, the drain is connected to an external power supply V DD , and the source is connected to the integral capacitor C INT ; the other end of the integral capacitor C INT is grounded.

[0012] Further, the other end of the switch S1 is connected with the integral capacitor C INT , the source end of the second transistor M2 and one input end of the comparator; the other input end of the comparator is provided with a reference voltage V REF,COMP .

[0013] Further, the output voltage V COMPOUT of the comparator is used as an input of the first AND gate together with the read-out enable signal EN_READ.

[0014] Further, when the enable signal of the counter is logic 1, the counter is enabled; during the timing of the counter, the value of the output port of the counter is increased by 1 at the end of each clock cycle.

[0015] Further, all the circuit parts from the negative feedback clamping circuit to the counter are the read-out circuit of the 256-column composite gate photosensitive detector pixel.

[0016] Further, the input end of the 8-256 decoder is provided with an 8-bit column selection signal from outside, and the output end is connected with one input end of the second AND gate.

[0017] Further, the output of the second AND gate is connected with one input end of the 256-input OR gate; the read-out circuit of the 256-column composite gate photosensitive detector pixel provides the other input of the second AND gate, and the output end of the second AND gate is connected with the input end of the 256-input OR gate.

[0018] The beneficial effects of the present application are as follows:

[0019] The parallel-serial conversion circuit of the present application converts all the digital circuit parts into analog circuits, and the pure analog circuit can directly process the input signal without analog-digital conversion or digital-analog conversion, so that the signal processing is continuous and the delay is small. The digital part in the digital-analog hybrid circuit usually depends on the clock signal, and problems such as clock deviation and clock jitter may occur, especially in high-speed digital circuits. These clock problems will affect the processing accuracy of the signal and the reliability of the system. The pure analog circuit does not need to process the internal clock signal, avoiding the problems related to timing and synchronization. Since the pure analog circuit does not have high-speed digital switching signals, the electromagnetic interference and overall circuit noise are relatively low.

[0020] For the circuit that does not need the internal clock of the circuit and has a short signal processing chain and a relatively simple circuit topology, the digital-analog hybrid circuit involves complex architecture, including analog-digital converters, digital-analog converters, digital processing parts, etc., which increases the complexity of circuit design, verification and testing. The circuit structure of the analog circuit is usually linear, the circuit topology is relatively simple, the signal processing chain is short, and the design steps and debugging process are reduced.

[0021] The present invention utilizes the 8-256 decoder, the AND gate implemented by the analog circuit, and the 256-input OR gate to convert parallel data into serial data. This reduces circuit design complexity, shortens circuit simulation and layout design iteration cycles, effectively reduces chip power consumption and area, and facilitates the design of subsequent miniaturized systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 This is a schematic diagram of a parallel-to-serial conversion circuit based on a composite dielectric grating photosensitive detector.

[0024] Figure 2 It is a 256-input gate block diagram based on analog circuit implementation.

[0025] Figure 3 This is a block diagram of the basic 4-input OR gate structure in the 256-input OR gate of the present invention.

[0026] Figure 4 This is a timing diagram of the working stages of the parallel-to-serial conversion circuit based on the composite dielectric grating photodetector. DETAILED DESCRIPTION

[0027] To make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0028] Example 1

[0029] This embodiment provides a parallel-to-serial conversion circuit based on a composite dielectric grating photosensitive detector, such as Figure 1 As shown. The circuit includes a composite dielectric grating photosensitive detector pixel, a ramp generator, a clamping circuit, a switch S1, a precharge circuit, a comparator, a counter, an 8-256 decoder, two AND gates (including a first AND gate and a second AND gate), and a 256-input OR gate. Among them, the gate end of the composite dielectric grating photosensitive detector pixel is connected to the ramp generator, the source end is grounded, and the drain end is connected to the input end of the clamping circuit; the clamping circuit is composed of an amplifier and a transistor M1 (hereinafter referred to as the first transistor M1); the precharge circuit is composed of an integrating capacitor C INT and a transistor M2 (hereinafter referred to as the second transistor M2 ); the first AND gate serves as an enable switch of the counter.

[0030] In the clamping circuit, the gate of the first transistor M1 is connected to the output of the amplifier, the drain of the composite gate photodetector pixel is connected to one input of the amplifier, and the other input of the amplifier is provided with a clamping voltage V REF,CLAMP The source of the first transistor M1 is connected to the drain of the composite gate photodetector pixel, forming a feedback loop.

[0031] The drain of the first transistor M1 is connected to one end of the switch S1, the other end of the switch S1 is connected to the integral capacitor C INT , the source of the second transistor M2 and one input of the comparator; in the pre-charge circuit, the gate of the second transistor M2 is connected to a pre-charge voltage V Precharge provided externally, the drain is connected to an external power supply V DD , and the source is connected to the integral capacitor C INT ; the integral capacitor C INT is connected to the ground at the other end.

[0032] The other input of the comparator is provided with a reference voltage V REF,COMP , and the output voltage V COMPOUT of the comparator and the read enable signal EN_READ are used as inputs of the first AND gate; the output of the first AND gate is connected to the input of the counter, and the output voltage V COMPOUT of the comparator and the read enable signal EN_READ are used as the counting basis of the counter; when the enable signal of the counter is logic 1, the counter is enabled, and at the end of each clock cycle during the timing process of the timer, the value of the output port of the counter increases by 1.

[0033] All circuit parts from the negative feedback clamping circuit to the counter are the readout circuit of a column of composite gate photodetector pixels.

[0034] The input of the 8-256 decoder is provided with an 8-bit column selection signal externally, and the output is connected to one input of the second AND gate.

[0035] The readout circuit of the 256-column composite gate photodetector pixel provides the other input of the second AND gate. The output of the second AND gate is connected to the input of the 256-input OR gate.

[0036] The circuit has three working stages, including the exposure stage, the readout stage and the reset stage:

[0037] 1. Exposure stage: when the switch S1 is open, the circuit is in the exposure stage, and the current signal path of the composite gate photodetector pixel does not pass through the integral capacitor C INTThe negative feedback operational amplifier of the clamp circuit is still located in the signal path, so that the drain voltage of the composite dielectric grating photosensitive detector pixel remains constant at a stable voltage V REF,CLAMP The MOS-C signal collection area of ​​the composite dielectric grating photosensitive detector pixel generates a depletion region in the substrate under the action of the gate-substrate forward bias, thereby collecting photogenerated carriers and realizing exposure.

[0038] 2. Readout stage: When switch S1 is closed, the circuit is in the readout stage, and the precharge voltage V Precharge Pull down the integral capacitor C INT Precharge to external voltage V DD . After that, the precharge voltage V Precharge Pull high to turn on the readout enable signal EN_READ, and the ramp generator provides the gate of the composite dielectric gate photosensitive detector pixel with a voltage from V RampStart Start to gradually increase the voltage until it reaches V RampEnd At this time, turn off the read signal EN_READ to enable reading.

[0039] 3. Reset phase: After the readout phase, switch S1 is disconnected and the circuit is in the reset phase. The drain voltage of the composite dielectric grating photosensitive detector pixel remains constant and is at a stable voltage V REF,CLAMP .

[0040] Please refer to Figure 4 , combined with Figure 4 The timing diagram shown provides a detailed introduction to the working process of each stage of the circuit:

[0041] In the exposure phase, when the switch S1 is disconnected, the circuit is in the exposure phase, and the current signal path of the composite dielectric grating photosensitive detector pixel does not pass through the integral capacitor C. INT The negative feedback operational amplifier of the clamp circuit is still located in the signal path, so that the drain voltage of the composite dielectric grating photosensitive detector pixel remains constant at a stable voltage V REF,CLAMP . Precharge voltage V Precharge At high level V DD , does not affect the integral capacitor C INT Turning off the readout signal EN_READ disables the counter. Under the action of the gate-substrate forward bias, the signal collection area of ​​the composite dielectric grating photodetector pixel MOS-C generates a depletion region in the substrate, collecting photogenerated carriers and achieving exposure.

[0042] In the readout phase, the drain voltage of the composite dielectric grating photosensitive detector pixel is stabilized at V REF,CLAMP The ramp generator maintains the initial voltage VRampStart unchanged, the pre-charge voltage V Precharge is pulled down, transistor M2 is turned on and the integral capacitor C INT is pre-charged to V DD , at this time the voltage V X on the plate of the integral capacitor is V DD >V REF,COMP , thus the comparator output V COMPOUT is high. After the pre-charge is finished, the pre-charge voltage V Precharge is pulled up to V DD , at the same time the readout enable signal EN_READ is turned on, V COMPOUT is also logic 1. V RampStart and EN_READ pass through an AND gate as the enable signal of the counter, the counter starts counting. At the same time, the ramp voltage generated by the ramp generator starts to rise from V INT , the compound medium gate photosensitive detector pixel discharges the integral capacitor C X , the voltage V X on the plate of the integral capacitor gradually decreases, when V REF,COMP drops to less than the reference voltage V COMPOUT of the comparator, the comparator output V OUT,CNT flips from logic 1 to logic 0, its output bit logic 0 after passing through the AND gate with EN_READ, and as the enable signal of the counter, makes the counter stop counting, the count value is V RampEnd . After that, when the ramp voltage provided by the ramp generator reaches V

[0043] In the reset phase, a suitable negative bias V Reset is applied between the gate and the substrate of the compound medium gate photosensitive detector pixel, the photoelectrons collected at the P-type substrate interface of the MOS-C will be discharged through the electrode connected to the substrate under the action of the electric field. The readout enable signal EN_READ is turned off, the counter enable signal is always logic 0 through the AND gate, and the count value of the counter remains unchanged V OUT,CNT .

[0044] All circuit parts from the negative feedback clamping circuit to the counter are the readout circuit of a column of compound medium gate photosensitive detector pixels, refer to the yellow dashed box in Figure 1 . The 256-column readout circuit is taken as a group, the present application aims to output the 256 columns of parallel data V OUT,CNT<255:0> are converted into serial output data by analog circuit. The 8-bit column selection signal inputted from outside is converted into 256 column output enable signals by 8-256 decoder, in which the output enable signal corresponding to the selected column is logic 1 and the output enable signals of the other 255 columns are all logic 0. The 256 column output enable signals and the output signals of each bit of the counter of the 256 column readout circuit are inputted into 256 AND gates, and the 256 voltage V OUT,256 OUT<255:0> respectively include logic 0 of the 255 unselected columns and the counter output signal V OUT,CNT OUT<255:0> of the selected column. OUT,256 As the input of 256-input OR gate, the output result V FO OUT<255:0> is the counter output signal V OUT,CNT OUT<255:0> of the selected column. The present application can convert parallel output data into serial data by changing the 8-bit column selection signal inputted from outside to select the corresponding column for readout.

[0045] Figure 1 The structure of 256-input OR gate realized based on analog circuit is shown in Figure 2 .

[0046] The 256-input OR gate is composed of 4 64-input OR gates, 1 4-input OR gate and 2 buffers composed of 4-input NOR gates. The 64-input OR gate is composed of 4 16-input OR gates, 1 4-input OR gate and 2 buffers composed of 4-input NOR gates. The 16-input OR gate is composed of 4 4-input OR gates, 1 4-input OR gate and 2 buffers composed of 4-input NOR gates. A single 4-input OR gate outputs logic 1 when any of the inputs is logic 1, and outputs logic 0 when all the 4 inputs are logic 0. The 16-input OR gate divides the 16 input signals IN<15:0> into 4 groups of 4 signals, and inputs each group of 4 signals into a 4-input OR gate. If any of the input signals IN<15:0> is logic 1, the corresponding 4-input OR gate outputs one of the signals C<3:0> as logic 1. Then, the 4-input OR gate inputs C<3:0> as input signals, and outputs OUT as logic 1. The 2 buffers composed of 4-input NOR gates improve the driving ability of the circuit. If all the input signals IN<15:0> are logic 0, the corresponding C<3:0> are also all logic 0, and the output signals OUT and OUT BUF are also all logic 0. Similarly, the 64-input OR gate and the 256-input OR gate realize the corresponding functions in this structure.

[0047] In which, a single 4-input OR gate is composed of 4-input NOR gate and NOR gate, as shown in Figure 3 , the 4-input NOR gate is composed of 4 P-type MOSFET transistors and 4 N-type MOSFET transistors, and the NOR gate is composed of 1 P-type MOSFET transistor and 1 N-type MOSFET transistor.

[0048] Part of the steps in the embodiments of the present application can be realized by software, and the corresponding software program can be stored in a readable storage medium, such as an optical disc or a hard disk.

[0049] The above merely describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A parallel-to-serial conversion circuit based on a composite medium gate photodetector, characterized by, The circuit comprises a composite medium gate photosensitive detector pixel, a slope generator, a clamping circuit, a switch S1, a pre-charge circuit, a comparator, a counter, an 8-256 decoder, a first AND gate, a second AND gate and a 256-input OR gate; wherein the gate end of the composite medium gate photosensitive detector pixel is connected to the slope generator, the source end is grounded, and the drain end is connected to the input end of the clamping circuit; the output of the clamping circuit is connected to the pre-charge circuit and the comparator through the switch S1, the output of the comparator is connected to the first AND gate, the counter, the second AND gate and the 256-input OR gate in sequence; the 8-256 decoder receives an 8-bit column selection signal at the input end and is connected to the second AND gate at the output end; the clamping circuit is composed of an amplifier and a transistor; the pre-charge circuit is composed of an integration capacitor C INT and a transistor; and the first AND gate is used as an enabling switch of the counter.

2. The parallel-to-serial conversion circuit of claim 1, wherein, The transistor in the clamping circuit is denoted as a first transistor M1, a gate end of the first transistor M1 is connected to an output end of an amplifier, a drain end of a composite dielectric gate photosensitive detector pixel is connected to one input end of the amplifier, and the other input end of the amplifier is provided with a clamping voltage V REF,CLAMP by an external source; a source end of the first transistor M1 is connected to the drain end of the composite dielectric gate photosensitive detector pixel, forming a feedback loop; and a drain end of the first transistor M1 is connected to one end of a switch S1.

3. The parallel-to-serial conversion circuit of claim 2, wherein, The transistor in the pre-charge circuit is denoted as the second transistor M2, the gate end of the second transistor M2 is connected with the externally provided pre-charge voltage V Precharge The drain end is connected with the external power supply V DD The source end is connected with the integration capacitor C INT The integration capacitor C INT The other end is grounded.

4. The parallel-to-serial conversion circuit of claim 3, wherein, The other end of the switch S1 is connected to the integrating capacitor C INT , the source terminal of the second transistor M2 and one input terminal of a comparator; the other input terminal of the comparator is provided with a reference voltage V REF,COMP .

5. The parallel-to-serial conversion circuit of claim 4, wherein, The output voltage V of the comparator COMPOUT The output of the comparator is connected to the input of a first AND gate, the output of which is connected to the input of a counter. The output voltage V of the comparator is also connected to the input of a second AND gate, the output of which is connected to the input of a second counter. COMPOUT The output of the second AND gate is connected to the input of a third AND gate, the output of which is connected to the input of a third counter. The output of the third AND gate is also connected to the input of a fourth AND gate, the output of which is connected to the input of a fourth counter.

6. The parallel-to-serial conversion circuit of claim 5, wherein, The input of the 8-256 decoder is provided with an 8-bit selection signal from outside, and the output is connected with one input of a second AND gate.

7. The parallel-to-serial conversion circuit of claim 6, wherein, The output of the second AND gate is connected with one input of a 256-input OR gate.

8. A composite interdigital photodetector, comprising: The composite medium gate photodetector includes the parallel-serial conversion circuit based on the composite medium gate photodetector according to any one of claims 1-7.

9. An image forming apparatus characterized by comprising: The imaging device includes the parallel-serial conversion circuit based on the composite medium gate photodetector according to any one of claims 1-7 or the composite medium gate photodetector according to claim 8.

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