Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes: a substrate; a first transistor and a second transistor on the substrate; a bit line electrically connected to the first transistor; a channel layer on the bit line; a gate insulating layer on the channel layer; a word line on the gate insulating layer; a bonding pad electrically connected to the channel layer; a connection pad electrically connected to the word line and the second transistor; and a partition structure separating the bonding pad from the connection pad. The partition structure includes an intermediate portion between the bond pad and the connection pad.

Description

[0001] This U.S. non-provisional patent application claims the priority of Korean Patent Application No. 10-2023-0087073 filed in the Korean Intellectual Property Office on July 5, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a semiconductor device, and in particular, to a semiconductor device including a vertical channel transistor. Background Art

[0003] As semiconductor devices shrink in size, it may be necessary to develop manufacturing technologies that can increase the integration density of semiconductor devices and improve operating speed and production yield. Therefore, in order to increase the integration density of semiconductor devices and improve the resistance and current driving characteristics of transistors, semiconductor devices with vertical channel transistors have been proposed. Summary of the invention

[0004] Some embodiments of the inventive concepts provide semiconductor devices having improved electrical characteristics and high integration density.

[0005] According to an embodiment of the inventive concept, a semiconductor device may include: a substrate; a first transistor and a second transistor on the substrate; a bit line electrically connected to the first transistor; a channel layer on the bit line; a gate insulating layer on the channel layer; a word line on the gate insulating layer; a bonding pad electrically connected to the channel layer; a connection pad electrically connected to the word line and the second transistor; and a separation structure separating the bonding pad from the connection pad. The separation structure may include an intermediate portion between the bonding pad and the connection pad, and the intermediate portion may include a first side surface in contact with the bonding pad and a second side surface in contact with the connection pad.

[0006] According to an embodiment of the inventive concept, a semiconductor device may include: a substrate; a first transistor and a second transistor on the substrate; a bit line electrically connected to the first transistor; a channel layer on the bit line; a gate insulating layer on the channel layer; a word line on the gate insulating layer; a bonding pad electrically connected to the channel layer; and a first connection pad electrically connected to the word line and the second transistor. In a plan view, the first connection pad may overlap with a first end of the word line, and a top surface of the bonding pad may be at substantially the same height relative to the substrate as a top surface of the first connection pad.

[0007] According to an embodiment of the inventive concept, a semiconductor device may include: a substrate; a first transistor and a second transistor on the substrate; a lower insulating structure on the first transistor and the second transistor; a first interlayer insulating layer on the lower insulating structure; a second interlayer insulating layer on the first interlayer insulating layer; a bit line in the second interlayer insulating layer; a conductive connection pattern in the first interlayer insulating layer; a channel layer on the bit line; a gate insulating layer on the channel layer; a word line on the gate insulating layer; a gate capping pattern on the word line; a bonding pad and a connection pad on the gate capping pattern; a separation structure separating the bonding pad from the connection pad; and a data storage pattern on the bonding pad. The bonding pad may be electrically connected to the first transistor through the channel layer and the bit line, and the connection pad may be electrically connected to the word line. The connection pad may be electrically connected to the second transistor through the conductive connection pattern.

[0008] According to an embodiment of the inventive concept, a method of manufacturing a semiconductor device may include: forming a first transistor and a second transistor on a substrate, forming a bit line and a conductive connection pattern electrically connected to the first transistor and the second transistor, respectively, forming a channel layer on the bit line, forming a gate insulating layer on the channel layer, forming a word line on the gate insulating layer, forming a gate capping pattern on the word line, forming a preliminary pad structure on the gate capping pattern, and patterning the preliminary pad structure to form a bonding pad and a connection pad. The bonding pad may be electrically connected to the bit line, and the connection pad may be electrically connected to the conductive connection pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating a semiconductor device according to an embodiment of the inventive concept.

[0010] Figure 2 and Figure 3 is a perspective view schematically illustrating a semiconductor device according to an embodiment of the inventive concept.

[0011] Figure 4A is a plan view illustrating a semiconductor device according to an embodiment of the inventive concept.

[0012] Figure 4B is along Figure 4A A cross-sectional view taken along line AA'.

[0013] Figure 4C is along Figure 4A A cross-sectional view taken along line BB'.

[0014] Figure 4D It is shown Figure 4B An enlarged cross-sectional view of portion E1.

[0015] Figure 4E It is shown Figure 4C An enlarged cross-sectional view of portion E2.

[0016] Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig. 9 , Fig.10 , Fig.11A , Fig. 11B , Fig.12 and Fig.13 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

[0017] Fig.14A is a plan view illustrating a semiconductor device according to an embodiment of the inventive concept.

[0018] Fig. 14B is along Fig.14A A cross-sectional view taken along line CC'.

[0019] Fig.15 is a plan view illustrating a semiconductor device according to an embodiment of the inventive concept.

[0020] Fig.16 is a plan view illustrating a semiconductor device according to an embodiment of the inventive concept.

[0021] Fig.17 is a plan view illustrating a semiconductor device according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0022] Figure 1 is a block diagram illustrating a semiconductor device according to an embodiment of the inventive concept.

[0023] Reference Figure 1 , the semiconductor device may include a memory cell array 1, a row decoder 2, a sense amplifier 3, a column decoder 4, and a control logic 5. When used herein, the terms “comprising” and / or “including” specify the presence of stated elements but do not exclude the presence of additional elements.

[0024] The memory cell array 1 may include a plurality of memory cells MC arranged two-dimensionally or three-dimensionally. Each of the memory cells MC may be disposed between and connected to a word line WL and a bit line BL disposed to cross or intersect each other.

[0025] Each of the memory cells MC may include a selection element TR and a data storage element DA. The selection element TR and the data storage element DA may be electrically connected to each other. The selection element TR may be connected to both the word line WL and the bit line BL. In other words, the selection element TR may be disposed at the intersection of the word line WL and the bit line BL.

[0026] The selection element TR may include a field effect transistor. The data storage element DA may include a capacitor, a magnetic tunnel junction pattern, or a variable resistor. As an example, the selection element TR may be a transistor whose gate, source, and drain terminals are connected to a word line WL, a bit line BL, and the data storage element DA, respectively.

[0027] The row decoder 2 may be configured to decode address information input from the outside (e.g., from an external device) and select one of the word lines WL of the memory cell array 1 based on the decoded address information. The address information decoded by the row decoder 2 may be provided to a row driver (not shown), and in this case, the row driver may provide corresponding voltages to a selected word line among the word lines WL and unselected word lines among the word lines WL in response to control of the control circuit.

[0028] The sense amplifier 3 may be configured to sense, amplify, and output a voltage difference between one of the bit lines BL selected based on address information decoded by the column decoder 4 and a reference bit line.

[0029] The column decoder 4 may establish a data transmission path between the sense amplifier 3 and an external device (eg, a memory controller). The column decoder 4 may be configured to decode address information input from the outside and select one of the bit lines BL based on the decoded address information.

[0030] The control logic 5 may generate a control signal for controlling an operation of writing data into the memory cell array 1 or reading data from the memory cell array 1 .

[0031] Figure 2 and Figure 3 is a perspective view schematically illustrating a semiconductor device according to an embodiment of the inventive concept.

[0032] Reference Figure 2 and Figure 3 , the semiconductor device may include a peripheral circuit structure PS and a cell array structure CS connected to each other. The term "connected" may be used herein to indicate physical and / or electrical connection. The term "separated" may be used herein to indicate physical separation and / or electrical isolation.

[0033] The peripheral circuit structure PS may include a core circuit and a peripheral circuit formed on a substrate SUB. The core circuit and the peripheral circuit may include a reference Figure 1 The row decoder 2, column decoder 4, sense amplifier 3 and control logic 5 are described.

[0034] The cell array structure CS may include a memory cell array (eg, Figure 1 In the memory cell array 1), in the memory cell array, the memory cells (e.g., Figure 1 As described above, each of the memory cells MC may include a selection element TR and a data storage element DA.

[0035] In one embodiment, a memory cell (e.g., Figure 1 Each selection element TR of the MC in the memory cell (eg, MC in the memory cell) may include a vertical channel transistor (VCT). The vertical channel transistor may be configured to have a channel region whose length direction is substantially perpendicular to the top surface of the substrate SUB. Figure 1 Each of the data storage elements DA in the MC) may include a capacitor.

[0036] exist Figure 2 In an embodiment of the present invention, the peripheral circuit structure PS may be disposed on the substrate SUB, and the cell array structure CS may be disposed on the peripheral circuit structure PS.

[0037] exist Figure 3 In an embodiment of the present invention, the peripheral circuit structure PS may be disposed on a first substrate SUB1, and the cell array structure CS may be disposed on a second substrate SUB2 disposed facing the first substrate SUB1. The terms "first", "second", etc. may be used herein only to distinguish one component, layer, direction, etc. from another component, layer, direction, etc.

[0038] The first metal pad LMP may be disposed in the uppermost portion of the peripheral circuit structure PS. The first metal pad LMP may be electrically connected to the core circuit and the peripheral circuit (eg, Figure 1 3, column decoder 4, and control logic 5 in FIG. 4). Spatially relative terms such as "above," "on," "below," "under," "to the side," and the like are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures were turned over, elements described as "below" or "beneath" other elements or features would be oriented "above" the other elements or features. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0039] The second metal pad UMP may be disposed in the lowermost portion of the cell array structure CS. The second metal pad UMP may be electrically connected to the memory cell array (eg, Figure 1The memory cell array 1 in the peripheral circuit structure PS). The second metal pad UMP can be directly bonded to the first metal pad LMP of the peripheral circuit structure PS (i.e., directly contacted with the first metal pad LMP of the peripheral circuit structure PS). When a component or layer is referred to herein as being "directly" on, "directly" in contact, or "directly" connected, there are no intermediate components or layers.

[0040] Figure 4A is a plan view illustrating a semiconductor device according to an embodiment of the inventive concept. Figure 4B is along Figure 4A A cross-sectional view taken along line AA'. Figure 4C is along Figure 4A A cross-sectional view taken along line BB'. Figure 4D It is shown Figure 4B An enlarged cross-sectional view of portion E1. Figure 4E It is shown Figure 4C An enlarged cross-sectional view of portion E2.

[0041] Reference FIG. 4A to FIG. 4C , the lower insulation structure LIS may be disposed on the substrate SUB. The substrate SUB may be a plate-like structure (e.g., having a flat surface) extending parallel to a plane defined by the first direction D1 and the second direction D2. The first direction D1 and the second direction D2 may not be parallel to each other. In one embodiment, the first direction D1 and the second direction D2 may be two different horizontal directions orthogonal to each other.

[0042] The lower insulation structure LIS may include a first lower insulation layer 21 on the substrate SUB, a second lower insulation layer 22 on the first lower insulation layer 21 , a third lower insulation layer 23 on the second lower insulation layer 22 , and a fourth lower insulation layer 24 on the third lower insulation layer 23 .

[0043] The first to fourth lower insulating layers 21, 22, 23, and 24 may include at least one of the insulating materials. As an example, the first lower insulating layer 21 may be formed of or may include an oxide material, and at least one of the second to fourth lower insulating layers 22, 23, and 24 may be formed of or may include a nitride material.

[0044] The first transistor TR1 and the second transistor TR2 may be disposed on the substrate SUB. The first transistor TR1 and the second transistor TR2 may be disposed between the substrate SUB and the lower insulating structure LIS. The lower insulating structure LIS may cover the first transistor TR1 and the second transistor TR2.

[0045] Each of the first transistor TR1 and the second transistor TR2 may include an impurity region 11, a peripheral gate insulating layer 12, a first peripheral gate conductive layer 13, and a second peripheral gate conductive layer 14. The impurity region 11 may be formed by doping the substrate SUB with impurities. The peripheral gate insulating layer 12 may include an insulating material. The first peripheral gate conductive layer 13 and the second peripheral gate conductive layer 14 may include at least one of a conductive material. As an example, the first peripheral gate conductive layer 13 may be formed of polysilicon or may include polysilicon, and the second peripheral gate conductive layer 14 may be formed of a metal material or may include a metal material.

[0046] The lower conductive pattern 25 may be disposed in the lower insulating structure LIS. The lower conductive pattern 25 may be electrically connected to the first transistor TR1 or the second transistor TR2. The lower conductive pattern 25 may be surrounded by at least one of the first to fourth lower insulating layers 21, 22, 23, and 24. The lower conductive pattern 25 may include at least one of a conductive contact plug, a conductive line, or a conductive pad. The term "surrounding" or "covering" or "filling" or "surrounding" as used herein may not require completely surrounding or covering or filling or surrounding the element or layer described, but may, for example, represent partially surrounding or covering or filling or surrounding the element or layer described. The lower conductive pattern 25 may be formed of at least one of the conductive materials or may include at least one of the conductive materials.

[0047] In one embodiment, the first transistor TR1 and the second transistor TR2, the lower insulating structure LIS and the lower conductive pattern 25 may constitute a reference Figure 2 In one embodiment, the first transistor TR1 can be used as a reference Figure 1 A portion of the sense amplifier 3 is described. In one embodiment, the second transistor TR2 can be used as a portion of a sub-word line driver.

[0048] The first interlayer insulating layer 31 may be disposed on the lower insulating structure LIS. The first interlayer insulating layer 31 may include a lower portion 31a and an upper portion 31b. The second interlayer insulating layer 32 may be disposed on the lower portion 31a of the first interlayer insulating layer 31. The upper portion 31b of the first interlayer insulating layer 31 may be disposed at the same level as the second interlayer insulating layer 32. The term "height" as used herein may represent a relative distance from a reference point / element / surface (such as, the surface of the substrate SUB). The top surface of the upper portion 31b of the first interlayer insulating layer 31 may be located at the same height as the top surface of the second interlayer insulating layer 32. The second interlayer insulating layer 32 may be disposed in the first interlayer insulating layer 31. The first interlayer insulating layer 31 and the second interlayer insulating layer 32 may be formed of at least one of the insulating materials or may include at least one of the insulating materials. As an example, the first interlayer insulating layer 31 may be formed of or may include at least one of the nitride materials, and the second interlayer insulating layer 32 may be formed of or may include at least one of the oxide materials.

[0049] A plurality of bit lines BL may be provided in the second interlayer insulating layer 32. The bit lines BL may extend along the second direction D2. The bit lines BL may be arranged in the first direction D1. The bit lines BL may be spaced apart from each other in the first direction D1. The number of bit lines BL may not be limited to the number in the illustrated example. In one embodiment, five or more or fewer bit lines BL may be provided.

[0050] The bit line BL may be formed of or may include at least one of the conductive materials. In one embodiment, the bit line BL may be formed of or may include at least one of the doped semiconductor materials (e.g., doped silicon and doped germanium), conductive metal nitride materials (e.g., titanium nitride and tantalum nitride), metal materials (e.g., tungsten, titanium and tantalum), and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, and titanium silicide). The bit line BL may be a single conductive layer or a plurality of conductive layers.

[0051] A first contact 33 may be provided. The first contact 33 may connect the bit line BL to the lower conductive pattern 25. The bit line BL may be electrically connected to the first transistor TR1 through the first contact 33 and the lower conductive pattern 25. The first contact 33 may be surrounded by the second interlayer insulating layer 32 and the lower portion 31a of the first interlayer insulating layer 31. The first contact 33 may be formed of or may include at least one of the conductive materials.

[0052] The shielding pattern 34 may be disposed in the second interlayer insulating layer 32. The shielding pattern 34 may be formed of or may include at least one of the conductive materials. The shielding pattern 34 may serve as an electrical shielding layer.

[0053] The conductive connection pattern 37 may be disposed in the upper portion 31b of the first interlayer insulating layer 31. The conductive connection pattern 37 may be a conductive line or a conductive pad. The conductive connection pattern 37 may be formed of or may include at least one of the conductive materials.

[0054] A second contact 36 may be provided. The second contact 36 may connect the conductive connection pattern 37 to the lower conductive pattern 25. The conductive connection pattern 37 may be electrically connected to the second transistor TR2 through the second contact 36 and the lower conductive pattern 25. The second contact 36 may be surrounded by the upper portion 31b and the lower portion 31a of the first interlayer insulating layer 31. The second contact 36 may be formed of or may include at least one of the conductive materials.

[0055] The channel layers CL may be disposed on the bit lines BL. Each of the bit lines BL may be in contact with a plurality of the channel layers CL. The channel layers CL on each of the bit lines BL may be arranged in the second direction D2.

[0056] The channel layer CL may be formed of at least one of a semiconductor material and an oxide semiconductor material, or may include at least one of a semiconductor material and an oxide semiconductor material. For example, the oxide semiconductor material may include at least one of InGaZnO, InGaSiO, InSnZnO, InZnO, ZnO, ZnSnO, ZnON, ZrZnSnO, SnO, HfInZnO, GaZnSnO, AlZnSnO, YbGaZnO, and InGaO. The semiconductor material may be formed of, for example, at least one of Si and Ge, or may include, for example, at least one of Si and Ge. In one embodiment, the channel layer CL may have a multilayer structure including a plurality of layers. In one embodiment, the channel layer CL may include a two-dimensional material.

[0057] The gate insulating layer GI may be disposed on the channel layer CL. In one embodiment, each gate insulating layer GI may be in contact with a plurality of channel layers CL. The gate insulating layer GI may be formed of or may include at least one of the insulating materials. As an example, the gate insulating layer GI may be formed of or may include at least one of the oxide materials.

[0058] The word line WL may be disposed on the gate insulating layer GI. The word line WL may include a conductive material. For example, the word line WL may be formed of at least one of a doped semiconductor material (e.g., doped silicon and doped germanium), a conductive metal nitride material (e.g., titanium nitride and tantalum nitride), a metal material (e.g., tungsten, titanium and tantalum), and a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, and titanium silicide), or may include at least one of a doped semiconductor material (e.g., doped silicon and doped germanium), a conductive metal nitride material (e.g., titanium nitride and tantalum nitride), a metal material (e.g., tungsten, titanium and tantalum), and a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, and titanium silicide).

[0059] The word line WL may include a first end portion EP1 and a second end portion EP2. The first end portion EP1 and the second end portion EP2 may be spaced apart from each other in the first direction D1. A plurality of channel layers CL may be disposed between the first end portion EP1 and the second end portion EP2. The number of channel layers CL disposed between the first end portion EP1 and the second end portion EP2 may not be limited to the number in the illustrated example.

[0060] The first end EP1 may be a portion of the word line WL that overlaps with a first connection pad 43 to be described below in the third direction D3. The second end EP2 may be a portion of the word line WL that overlaps with a second connection pad 44 to be described below in the third direction D3. When viewed along a line extending in a specific direction or in a plane perpendicular to the specific direction, components or layers described with respect to "overlapping" in a specific direction may be at least partially blocked from each other. The third direction D3 may not be parallel to the first direction D1 and the second direction D2. As an example, the third direction D3 may be a vertical direction orthogonal to the first direction D1 and the second direction D2.

[0061] The first molded insulating layer 46 and the second molded insulating layer 45 may be disposed on the bit line BL. The side surface of the first molded insulating layer 46 may be in contact with the word line WL, the gate insulating layer GI, and the channel layer CL. The side surface of the second molded insulating layer 45 may be in contact with the channel layer CL and the bonding pad LP to be described below. The first molded insulating layer 46 and the second molded insulating layer 45 may be alternately arranged in the second direction D2. The first molded insulating layer 46 and the second molded insulating layer 45 may be formed of at least one of the insulating materials or may include at least one of the insulating materials. In one embodiment, each of the first molded insulating layer 46 and the second molded insulating layer 45 may have a multilayer structure including a plurality of insulating layers. In one embodiment, an air gap may be provided in each of the first molded insulating layer 46 and the second molded insulating layer 45.

[0062] The filling insulating layer 41 may be disposed on the upper portion 31b of the first interlayer insulating layer 31. The filling insulating layer 41 may be in contact with the first end portion EP1 of the word line WL. The filling insulating layer 41 may be formed of or may include at least one of the insulating materials. As an example, the filling insulating layer 41 may be formed of or may include at least one of the nitride materials. In one embodiment, the filling insulating layer 41 may have a multilayer structure including a plurality of insulating layers.

[0063] The gate capping pattern GP may be disposed on the word line WL, the first mold insulating layer 46, and the filling insulating layer 41. The gate capping pattern GP may be disposed between the gate insulating layers GI spaced apart from each other in the second direction D2. The gate capping pattern GP may be disposed on the top surface of the word line WL. The gate capping pattern GP may be formed of or may include at least one of the insulating materials. As an example, the gate capping pattern GP may be formed of or may include at least one of the nitride materials. In one embodiment, the gate capping pattern GP may have a multilayer structure including a plurality of insulating layers. In one embodiment, the gate capping pattern GP may be formed of or may include the same material as the filling insulating layer 41. In one embodiment, the gate capping pattern GP may be formed of or may include a material different from the filling insulating layer 41.

[0064] The bonding pad LP may be provided. The bonding pad LP may be provided on the channel layer CL and the gate capping pattern GP. The bonding pad LP may be in contact with the channel layer CL and the gate capping pattern GP. The bonding pad LP may include a barrier layer BA and a conductive layer CO. The barrier layer BA of the bonding pad LP may be in contact with the channel layer CL and the gate capping pattern GP. The conductive layer CO of the bonding pad LP may be provided on the barrier layer BA of the bonding pad LP. The barrier layer BA and the conductive layer CO of the bonding pad LP may be formed of or may include at least one of the conductive materials. As an example, the barrier layer BA of the bonding pad LP may be formed of or may include at least one of titanium and tantalum, and the conductive layer CO of the bonding pad LP may be formed of or may include tungsten.

[0065] The bonding pad LP may be electrically connected to the channel layer CL. The bonding pad LP may be electrically connected to the first transistor TR1 through the channel layer CL, the bit line BL, the first contact 33 and the lower conductive pattern 25.

[0066] The first connection pad 43 and the second connection pad 44 may be provided. The first connection pad 43 and the second connection pad 44 may be provided on the gate capping pattern GP. The first connection pad 43 and the second connection pad 44 may contact the gate capping pattern GP. Each of the word lines WL may overlap with one of the first connection pads 43 and one of the second connection pads 44 in the third direction D3. The first connection pad 43 and the second connection pad 44 overlapped with one of the word lines WL in the third direction D3 may be spaced apart from each other in the first direction D1. The bonding pad LP placed between the first connection pad 43 and the second connection pad 44 overlapped with one of the word lines WL in the third direction D3 may be arranged in the first direction D1. The first connection pad 43 may be arranged in the second direction D2. The second connection pad 44 may be arranged in the second direction D2. The width of each of the first connection pad 43 and the second connection pad 44 in the second direction D2 may be equal to the width of the bonding pad LP in the second direction D2.

[0067] Each of the first connection pad 43 and the second connection pad 44 may include a barrier layer BA and a conductive layer CO on the barrier layer BA. The barrier layer BA of each of the first connection pad 43 and the second connection pad 44 may be formed of the same conductive material as the barrier layer BA of the bonding pad LP, or may include the same conductive material as the barrier layer BA of the bonding pad LP. The conductive layer CO of each of the first connection pad 43 and the second connection pad 44 may be formed of the same conductive material as the conductive layer CO of the bonding pad LP, or may include the same conductive material as the conductive layer CO of the bonding pad LP.

[0068] The gate capping pattern GP may be disposed between the bonding pad LP and the word line WL. The gate capping pattern GP may be disposed between the first connection pad 43 and the word line WL. The gate capping pattern GP may be disposed between the second connection pad 44 and the word line WL.

[0069] A through contact 42 may be provided. The through contact 42 may contact the gate capping pattern GP, ​​the word line WL, and the gate insulating layer GI. The through contact 42 may be provided to penetrate the gate capping pattern GP, ​​the word line WL, and the gate insulating layer GI. The through contact 42 may be surrounded by the gate capping pattern GP, ​​the word line WL, and the gate insulating layer GI. The through contact 42 may penetrate the first end EP1 or the second end EP2 of the word line WL. The top surface of the through contact 42 may contact the bottom surface of the first connection pad 43 or the bottom surface of the second connection pad 44. The bottom surface of the through contact 42 may contact the top surface of the conductive connection pattern 37.

[0070] The through contact 42 may electrically connect the first connection pad 43 to the word line WL and the second transistor TR2. The through contact 42 may electrically connect the second connection pad 44 to the word line WL and the second transistor TR2. The first connection pad 43 may be electrically connected to the word line WL through the corresponding through contact 42. The second connection pad 44 may be electrically connected to the word line WL through the corresponding through contact 42. The first connection pad 43 may be electrically connected to the second transistor TR2 through the corresponding through contact 42, the conductive connection pattern 37, the second contact 36, and the lower conductive pattern 25. The second connection pad 44 may be electrically connected to the second transistor TR2 through the corresponding through contact 42, the conductive connection pattern 37, the second contact 36, and the lower conductive pattern 25.

[0071] The through contact 42 may include a barrier layer BA in contact with the word line WL, the gate capping pattern GP, ​​the gate insulating layer GI, and the conductive connection pattern 37, and a conductive layer CO surrounded by the barrier layer BA. The barrier layer BA of the through contact 42 may be formed of the same conductive material as the barrier layer BA of the bonding pad LP or may include the same conductive material as the barrier layer BA of the bonding pad LP. The conductive layer CO of the through contact 42 may be formed of the same conductive material as the conductive layer CO of the bonding pad LP or may include the same conductive material as the conductive layer CO of the bonding pad LP.

[0072] The first connection pad 43, the first end portion EP1 of the word line WL, and the conductive connection pattern 37 may overlap each other in the third direction D3. The first connection pad 43, the through-contact 42, and the conductive connection pattern 37 may overlap each other in the third direction D3.

[0073] The separation structure DS may be provided to separate the bonding pad LP, the first connection pad 43 and the second connection pad 44 from each other. The separation structure DS may be provided on the gate capping pattern GP. The separation structure DS may be formed of or may include at least one of the insulating materials. In one embodiment, the separation structure DS may have a multilayer structure including a plurality of insulating layers.

[0074] The separation structure DS may include an intermediate portion IN interposed between the first connection pad 43 and the bonding pad LP. The intermediate portion IN may separate (ie, physically and electrically separate) the first connection pad 43 from the bonding pad LP.

[0075] The data storage patterns DSP may be respectively disposed on and connected to the plurality of bonding pads LP. The data storage patterns DSP may be electrically connected to the channel layer CL through the bonding pads LP.

[0076] In one embodiment, the data storage pattern DSP may be a capacitor. In this case, the data storage pattern DSP may include a bottom electrode, a top electrode, and a capacitor dielectric layer interposed between the bottom electrode and the top electrode.

[0077] In one embodiment, the data storage pattern DSP may be a variable resistance pattern, the resistance of which may be switched to one of at least two states by an electric pulse applied to the variable resistance pattern. For example, the data storage pattern DSP may be formed of or may include at least one of a phase change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, and an antiferromagnetic material, and the crystal state of the phase change material may change according to the amount of current applied to the phase change material.

[0078] Reference Figure 4D and Figure 4E , the side surface S1 of the gate insulating layer GI and the side surface S2 of the first end portion EP1 of the word line WL may contact the side surface S3 of the filling insulating layer 41. The side surface S3 of the filling insulating layer 41 may cover the side surface S1 of the gate insulating layer GI and the side surface S2 of the first end portion EP1 of the word line WL.

[0079] The side surface S3 of the filling insulating layer 41 may be spaced apart from the channel layer CL adjacent to the filling insulating layer 41 in the first direction D1. The channel layer CL adjacent to the filling insulating layer 41 may not overlap the upper portion 31b of the first interlayer insulating layer 31 in the third direction D3. The channel layer CL adjacent to the filling insulating layer 41 may be spaced apart from the upper portion 31b of the first interlayer insulating layer 31 in the first direction D1.

[0080] The middle portion IN of the separation structure DS may include a first side surface S4 in contact with the bonding pad LP and a second (e.g., opposite) side surface S5 in contact with the first connection pad 43. The length of the first side surface S4 and the second side surface S5 of the middle portion IN in the third direction D3 may be greater than the length of the first connection pad 43 in the third direction D3. For example, the lower portion of the middle portion IN may be disposed in the gate capping pattern GP. That is, the middle portion IN of the separation structure DS may extend beyond the first connection pad 43 toward the substrate SUB (i.e., extend to a greater depth than the first connection pad 43).

[0081] The top surface S6 of the middle portion IN of the separation structure DS, the top surface S7 of the first connection pad 43, and the top surface S8 of the bonding pad LP may be coplanar with each other. The top surface S6 of the middle portion IN of the separation structure DS, the top surface S7 of the first connection pad 43, and the top surface S8 of the bonding pad LP may be placed at the same height in the third direction D3 (e.g., relative to the substrate SUB). The top surface S7 of the first connection pad 43 may be the top surface of the conductive layer CO of the first connection pad 43. The top surface S8 of the bonding pad LP may be the top surface of the conductive layer CO of the bonding pad LP.

[0082] The bonding pad LP may include a lower portion LPa and an upper portion LPb. The lower portion LPa of the bonding pad LP may contact the channel layer CL. The upper portion LPb of the bonding pad LP may have a width greater than a width of the lower portion LPa of the bonding pad LP in the second direction D2.

[0083] The barrier layer BA of the bonding pad LP may include a first portion and a second portion. Here, the first portion of the barrier layer BA may be included in the lower portion LPa of the bonding pad LP, and the second portion of the barrier layer BA may be included in the upper portion LPb of the bonding pad LP. The conductive layer CO of the bonding pad LP may include a first portion and a second portion. Here, the first portion of the conductive layer CO may be included in the lower portion LPa of the bonding pad LP, and the second portion of the conductive layer CO may be included in the upper portion LPb of the bonding pad LP. The first portion of the barrier layer BA of the bonding pad LP may surround the first portion of the conductive layer CO of the bonding pad LP.

[0084] The lower portion LPa of the bonding pad LP may be disposed at a lower height than the first connection pad 43. The first portion of the barrier layer BA of the bonding pad LP may be disposed at a lower height than the first connection pad 43. The first portion of the conductive layer CO of the bonding pad LP may be disposed at a lower height than the first connection pad 43. The upper portion LPb of the bonding pad LP may be disposed at the same height as the first connection pad 43. The bottom surface S9 of the first connection pad 43 may be placed at the same height as the bottom surface S10 of the upper portion LPb of the bonding pad LP in the third direction D3. The bottom surface S9 of the first connection pad 43 may be coplanar with the bottom surface S10 of the upper portion LPb of the bonding pad LP. The bottom surface S9 of the first connection pad 43 may contact the top surface of the through-contact 42 and the top surface of the gate capping pattern GP. The bottom surface S10 of the upper portion LPb of the bonding pad LP may contact the top surface of the gate capping pattern GP, ​​the top surface of the gate insulation layer GI, and the top surface of the second mold insulation layer 45. The bottom surface S9 of the first connection pad 43 may be a bottom surface of the barrier layer BA of the first connection pad 43 .

[0085] A side surface S11 of the upper portion 31b of the first interlayer insulating layer 31 may be in contact with a side surface S12 of the second interlayer insulating layer 32. A top surface S13 of the bit line BL may be coplanar with a top surface S14 of the conductive connection pattern 37. The top surface S13 of the bit line BL may be placed at the same height as the top surface S14 of the conductive connection pattern 37 in the third direction D3. The top surface S14 of the conductive connection pattern 37 may be in contact with the gate insulating layer GI.

[0086] In the semiconductor device according to the embodiment of the inventive concept, the word line WL and the second transistor TR2 may be electrically connected to each other through the first connection pad 43 or the second connection pad 44 and the corresponding through-contact 42. Therefore, the length of the conductive path between the word line WL and the second transistor TR2 may be relatively reduced, and this may make it possible to increase the integration density of the semiconductor device and the signal transmission speed between the word line WL and the second transistor TR2.

[0087] Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig. 9 , Fig.10 , Fig.11A , Fig. 11B , Fig.12 and Fig.13 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the inventive concept.

[0088] Reference Figure 5A and Figure 5B , a lower insulating structure LIS, a first transistor TR1, and a second transistor TR2 may be formed on the substrate SUB. A lower conductive pattern 25 may be formed in the lower insulating structure LIS.

[0089] A first interlayer insulating layer 31 may be formed on the lower insulating structure LIS. A second interlayer insulating layer 32 may be formed in the first interlayer insulating layer 31. In one embodiment, the formation of the second interlayer insulating layer 32 may include etching the first interlayer insulating layer 31 to form an empty space, and forming the second interlayer insulating layer 32 in the empty space.

[0090] A first contact 33 and a second contact 36 may be formed. The bit line BL and the conductive connection pattern 37 may be formed, for example, from portions of the same conductive layer. Thus, the conductive connection pattern 37 and the bit line BL may include the same conductive material. A shielding pattern 34 may be formed.

[0091] A second mold insulating layer 45 may be formed. The second mold insulating layer 45 placed on one of the bit lines BL may be arranged in the second direction D2.

[0092] A first preliminary channel layer pCL1 may be conformally formed on an upper portion 31b of the first interlayer insulating layer 31, the second interlayer insulating layer 32, the bit line BL, the conductive connection pattern 37, and the second mold insulating layer 45. The first preliminary channel layer pCL1 may cover the upper portion 31b of the first interlayer insulating layer 31, the second interlayer insulating layer 32, the bit line BL, the conductive connection pattern 37, and the second mold insulating layer 45. The first preliminary channel layer pCL1 may be formed of or may include at least one of a semiconductor material and an oxide semiconductor material.

[0093] A first sacrificial layer 51 may be formed on the first preliminary channel layer pCL1. The first sacrificial layer 51 may cover the first preliminary channel layer pCL1. The first sacrificial layer 51 may be formed of or may include at least one of the insulating materials. As an example, the first sacrificial layer 51 may be formed of or may include at least one of the spin-on hard mask (SOH) materials.

[0094] Reference Fig. 6A and Figure 6B , the first sacrificial layer 51 may be patterned to form a second sacrificial layer 52. The first sacrificial layer 51 may be divided into the second sacrificial layers 52. The second sacrificial layers 52 may be spaced apart from each other in the first direction D1. During the patterning process of the first sacrificial layer 51, a portion of the first sacrificial layer 51 overlapping the upper portion 31b of the first interlayer insulating layer 31 in the third direction D3 may be removed.

[0095] The first preliminary channel layer pCL1 may be patterned using the second sacrificial layer 52 as an etching mask. As a result of the patterning of the first preliminary channel layer pCL1, a second preliminary channel layer pCL2 may be formed. The first preliminary channel layer pCL1 may be divided into second preliminary channel layers pCL2. The second preliminary channel layers pCL2 may be spaced apart from each other in the first direction D1. During the patterning process of the first preliminary channel layer pCL1, a portion of the first preliminary channel layer pCL1 overlapping with the upper portion 31b of the first interlayer insulating layer 31 in the third direction D3 may be removed. During the patterning process of the first preliminary channel layer pCL1, a portion of the first preliminary channel layer pCL1 overlapping with the conductive connection pattern 37 in the third direction D3 may be removed.

[0096] The second preliminary channel layer pCL2 may be formed on the bit line BL. The first preliminary channel layer pCL1 may be patterned to expose the conductive connection pattern 37 .

[0097] Reference Fig. 7A and Figure 7B, a third sacrificial layer 53 may be formed. The third sacrificial layer 53 may be formed of or may include at least one of the insulating materials. As an example, the third sacrificial layer 53 may be formed of or may include a spin-on hard mask (SOH) material. The third sacrificial layer 53 may cover the conductive connection pattern 37, the upper portion 31b of the first interlayer insulating layer 31, and the second sacrificial layer 52.

[0098] The removal process may be performed to remove an upper portion of the third sacrificial layer 53, an upper portion of the second sacrificial layer 52, and an upper portion of the second preliminary channel layer pCL2. In one embodiment, the removal process may include a chemical mechanical polishing step.

[0099] As a result of the removal of the upper portion of the second preliminary channel layer pCL2, the third preliminary channel layer pCL3 may be formed. For example, the second preliminary channel layer pCL2 may be divided into third preliminary channel layers pCL3 separated from each other.

[0100] In one embodiment, the removal process may be performed to expose a top surface of the third preliminary channel layer pCL3 and a top surface of the second mold insulation layer 45 .

[0101] Reference Fig. 8A and Figure 8B , the second sacrificial layer 52 and the third sacrificial layer 53 may be removed. In one embodiment, the second sacrificial layer 52 and the third sacrificial layer 53 may be removed by a lift-off process. The removal of the second sacrificial layer 52 and the third sacrificial layer 53 may be performed to expose the third preliminary channel layer pCL3, the upper portion 31b of the first interlayer insulating layer 31, and the conductive connection pattern 37.

[0102] A gate insulating layer GI, a word line WL, and a channel layer CL may be formed. The formation of the gate insulating layer GI, the word line WL, and the channel layer CL may include: forming a preliminary gate insulating layer to cover the third preliminary channel layer pCL3, the upper portion 31b of the first interlayer insulating layer 31, and the conductive connection pattern 37, forming a preliminary word line layer on the preliminary gate insulating layer, performing an anisotropic etching process on the preliminary word line layer to form the word line WL, and performing an anisotropic etching process on the preliminary gate insulating layer and the third preliminary channel layer pCL3 to form the gate insulating layer GI and the channel layer CL.

[0103] As a result of the etching process, the preliminary word line layer may be divided into word lines WL separated from each other. As a result of the etching process, the preliminary gate insulating layer may be divided into gate insulating layers GI separated from each other. As a result of the etching process, the third preliminary channel layer pCL3 may be divided into channel layers CL separated from each other.

[0104] A first mold insulating layer 46 may be formed between the word lines WL. The formation of the first mold insulating layer 46 may include: forming a preliminary insulating layer to cover the word lines WL, and removing an upper portion of the preliminary insulating layer. As a result of the removal of the upper portion of the preliminary insulating layer, the first mold insulating layer 46 may be formed.

[0105] Reference Fig. 9 , a mask pattern MP may be formed on the word line WL. The mask pattern MP may be formed of, for example, at least one of a photoresist material and an insulating material or may include, for example, at least one of a photoresist material and an insulating material. The word line WL and the gate insulating layer GI may be etched using the mask pattern MP as an etching mask. As a result of etching of the word line WL and the gate insulating layer GI, the upper portion 31b of the first interlayer insulating layer 31 may be partially exposed. In one embodiment, an empty space, which will be referred to as a cavity CA, may be formed by etching of the word line WL and the gate insulating layer GI.

[0106] Reference Fig.10 , a filling insulating layer 41 may be formed. The filling insulating layer 41 may fill the cavity CA. The filling insulating layer 41 may be formed on the upper portion 31b of the first interlayer insulating layer 31. In one embodiment, the formation of the filling insulating layer 41 may include: forming a preliminary filling insulating layer to cover the word line WL, and removing the upper portion of the preliminary filling insulating layer to expose the top surface of the word line WL.

[0107] Reference Fig.11A and Fig. 11B , a gate capping pattern GP may be formed. In one embodiment, the formation of the gate capping pattern GP may include: forming a preliminary gate capping layer to cover the word line WL, the channel layer CL, the gate insulating layer GI, the first mold insulating layer 46 and the second mold insulating layer 45, and removing an upper portion of the preliminary gate capping layer to form the gate capping pattern GP.

[0108] Reference Fig.12 , a through contact 42 may be formed. The formation of the through contact 42 may include: forming a through hole to penetrate the gate capping pattern GP, ​​the word line WL, and the gate insulating layer GI, and forming the through contact 42 in the through hole.

[0109] The barrier layer BA and the conductive layer CO of the through-contact 42 may be sequentially formed in the through-hole. The top surface of the conductive connection pattern 37 may be exposed through the through-hole. The through-contact 42 may be formed on the exposed top surface of the conductive connection pattern 37.

[0110] Reference Fig.13, a preliminary pad structure pPA may be formed. The preliminary pad structure pPA may be formed on the top surface of the gate capping pattern GP and the top surface of the through-contact 42. The preliminary pad structure pPA may include a barrier layer BA and a conductive layer CO on the barrier layer BA.

[0111] Reference Figure 4A , Figure 4B and Figure 4C , the preliminary pad structure pPA may be patterned to form a bonding pad LP, a first connection pad 43, and a second connection pad 44. The preliminary pad structure pPA may be divided into the bonding pad LP, the first connection pad 43, and the second connection pad 44. That is, the bonding pad LP and the first connection pad 43 and the second connection pad 44 may be formed from the same part of one or more preliminary pad structures pPA. In one embodiment, the gate capping pattern GP may also be patterned during the process of patterning the preliminary pad structure pPA.

[0112] The separation structure DS may be formed in the empty space formed by patterning the preliminary pad structure pPA.

[0113] Fig.14A is a plan view illustrating a semiconductor device according to an embodiment of the inventive concept. Fig. 14B is along Fig.14A In addition to the technical features described below, Fig.14A and Fig. 14B The semiconductor device may be configured to have a reference FIG. 4A to FIG. 4E The semiconductor device described has similar technical features.

[0114] Reference Fig.14A and Fig. 14B , the semiconductor device may include a first connection contact 47 and a second connection contact 48. The first connection contact 47 may electrically connect the first connection pad 43 or the second connection pad 44 to the word line WL. The first connection contact 47 may penetrate the gate capping pattern GP. The gate capping pattern GP may surround the first connection contact 47. The lowermost portion of the first connection contact 47 may be disposed in the word line WL.

[0115] The second connection contact 48 may electrically connect the first connection pad 43 or the second connection pad 44 to the corresponding conductive connection pattern 37. The first connection pad 43 or the second connection pad 44 may be electrically connected to the corresponding second transistor TR2 through the second connection contact 48, the conductive connection pattern 37, and the lower conductive pattern 25. The second connection contact 48 may penetrate the gate capping pattern GP and the filling insulating layer 41. The filling insulating layer 41 and the gate capping pattern GP may surround the second connection contact 48. In one embodiment, the filling insulating layer 41 may be on the side surface of the word line WL and separate the second connection contact 48 from the word line WL. The bottom surface of the second connection contact 48 may contact the top surface of the conductive connection pattern 37.

[0116] The length of the first connection contact 47 in the third direction D3 may be smaller than the length of the second connection contact 48 in the third direction D3.

[0117] Each of the first connection contact 47 and the second connection contact 48 may include a barrier layer BA and a conductive layer CO on the barrier layer BA. Formation of the first connection contact 47 may include forming a first penetration hole to penetrate the gate capping pattern GP, ​​and forming the first connection contact 47 in the first penetration hole. Formation of the second connection contact 48 may include forming a second penetration hole to penetrate the gate capping pattern GP and the filling insulating layer 41, and forming the second connection contact 48 in the second penetration hole.

[0118] The conductive connection pattern 37 may overlap the filling insulation layer 41 in the third direction D3. The conductive connection pattern 37 may not overlap the word line WL in the third direction D3.

[0119] Fig.15 1 is a plan view showing a semiconductor device according to an embodiment of the inventive concept. In addition to the technical features described below, Fig.15 The semiconductor device may be configured to have a reference FIG. 4A to FIG. 4E The semiconductor device described has similar technical features.

[0120] Reference Fig.15 , the first connection pads 43 connected to the corresponding through-contacts 42 and the first connection pads 43 not connected to the corresponding through-contacts 42 may be alternately arranged in the second direction D2. The second connection pads 44 connected to the corresponding through-contacts 42 and the second connection pads 44 not connected to the corresponding through-contacts 42 may be alternately arranged in the second direction D2.

[0121] The corresponding through-contact 42 may be connected to one of the first connection pad 43 and the second connection pad 44 overlapping one of the word lines WL in the third direction D3. Among the first connection pad 43 and the second connection pad 44 overlapping one of the word lines WL in the third direction D3, one of the first connection pad 43 and the second connection pad 44 may be electrically connected to the word line WL, and the other of the first connection pad 43 and the second connection pad 44 may be electrically isolated or disconnected from the word line WL.

[0122] Fig.16 1 is a plan view showing a semiconductor device according to an embodiment of the inventive concept. In addition to the technical features described below, Fig.16 The semiconductor device may be configured to have a reference Fig.14A and Fig. 14B The semiconductor device described has similar technical features.

[0123] Reference Fig.16 , the first connection pads 43 connected to the corresponding first connection contacts 47 and the second connection contacts 48 and the first connection pads 43 not connected to the corresponding first connection contacts 47 and the second connection contacts 48 may be alternately arranged in the second direction D2. The second connection pads 44 connected to the corresponding first connection contacts 47 and the second connection contacts 48 and the second connection pads 44 not connected to the corresponding first connection contacts 47 and the second connection contacts 48 may be alternately arranged in the second direction D2.

[0124] The respective first connection contacts 47 and second connection contacts 48 may be connected to one of the first connection pads 43 and second connection pads 44 overlapping one of the word lines WL in the third direction D3. Among the first connection pads 43 and second connection pads 44 overlapping one of the word lines WL in the third direction D3, one of the first connection pads 43 and second connection pads 44 may be electrically connected to the word line WL, and the other of the first connection pads 43 and second connection pads 44 may be electrically isolated or disconnected from the word line WL.

[0125] Fig.17 1 is a plan view showing a semiconductor device according to an embodiment of the inventive concept. In addition to the technical features described below, Fig.17 The semiconductor device may be configured to have a reference FIG. 4A to FIG. 4E The semiconductor device described has similar technical features.

[0126] Reference Fig.17, when viewed in a plan view, the first connection pads 43 may be arranged in a zigzag shape. The first connection pads 43 may be arranged so that adjacent ones of the first connection pads 43 are offset from each other in the first direction D1 or in the second direction D2. The second connection pads 44 may be arranged in a zigzag shape. The second connection pads 44 may be arranged so that adjacent ones of the second connection pads 44 are offset from each other in the first direction D1 or in the second direction D2.

[0127] In the case where the first connection pads 43 and the second connection pads 44 are arranged in a zigzag shape, difficulty in a process of forming the first connection pads 43 and the second connection pads 44 may be reduced.

[0128] According to an embodiment of the inventive concept, a semiconductor device may include a connection pad configured to reduce the length of a conductive path between a word line and a transistor, which may increase the integration density of the semiconductor device and increase the signal transmission speed between the word line and the transistor.

[0129] While example embodiments of the inventive concepts have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the scope of the appended claims.

Claims

1. A semiconductor device comprising: substrate; a first transistor and a second transistor on a substrate; a bit line electrically connected to the first transistor; Channel layer, on the bit line; a gate insulating layer, on the channel layer; word line, on the gate insulating layer; a bonding pad electrically connected to the channel layer; a connection pad electrically connected to the word line and the second transistor; as well as Separation structure, separates the bonding pad from the connection pad, The separation structure includes a middle portion between the bonding pad and the connecting pad, and The middle portion includes a first side surface in contact with the bonding pad and a second side surface in contact with the connection pad.

2. The semiconductor device according to claim 1, wherein A top surface of the bond pad is at the same height relative to the substrate as a top surface of the connection pad, wherein the bond pad and the connection pad comprise the same conductive material.

3. The semiconductor device according to claim 1, further comprising: a first connection contact electrically connecting the connection pad to the word line; as well as The second connection contact electrically connects the connection pad to the second transistor.

4. The semiconductor device according to claim 3, further comprising: a filling insulating layer extending around the second connecting contact, The filling insulating layer is on the side surface of the word line and separates the second connection contact from the word line.

5. The semiconductor device according to claim 4, further comprising: Gate capping pattern, between word line and connection pad, The first connecting contact penetrates the gate capping pattern.

6. The semiconductor device according to claim 3, further comprising: a conductive connection pattern in contact with a bottom surface of the second connection contact, Wherein, a top surface of the conductive connection pattern is at the same height as a top surface of the bit line relative to the substrate.

7. The semiconductor device according to claim 6, further comprising: a lower insulating structure on the first transistor and the second transistor; a first interlayer insulating layer on the lower insulating structure; as well as A second interlayer insulating layer, in the first interlayer insulating layer, wherein the conductive connection pattern is in a first interlayer insulating layer, and the bit line is in a second interlayer insulating layer, and The conductive connection pattern and the bit line include the same conductive material.

8. The semiconductor device according to any one of claims 1 to 7, further comprising: Penetrates the contacts, penetrates the word lines and gate insulation, The penetrating contact electrically connects the connection pad, the word line and the second transistor to each other.

9. The semiconductor device according to claim 8, wherein: The through-contact further includes a conductive layer and a barrier layer in contact with the word line, wherein the barrier layer is between the conductive layer and the word line.

10. A semiconductor device comprising: substrate; a first transistor and a second transistor on a substrate; a bit line electrically connected to the first transistor; Channel layer, on the bit line; a gate insulating layer, on the channel layer; word line, on the gate insulating layer; a bonding pad electrically connected to the channel layer; as well as a first connection pad electrically connected to the word line and the second transistor, wherein, in a plan view, the first connection pad overlaps with the first end of the word line, and The top surface of the bonding pad is at the same height relative to the substrate as the top surface of the first connection pad.

11. The semiconductor device according to claim 10, further comprising: a second connection pad overlapping the second end of the word line in plan view, In the plan view, the channel layer is between the first end and the second end of the word line, and the bonding pad is between the first connection pad and the second connection pad.

12. The semiconductor device according to claim 11, wherein The second connection pad is electrically isolated from the word line.

13. The semiconductor device according to claim 10, further comprising: A penetrating contact penetrates the first end portion of the word line and the gate insulating layer.

14. The semiconductor device according to claim 13, further comprising: a conductive connection pattern in contact with a bottom surface of the penetrating contact, The conductive connection pattern electrically connects the second transistor to the through-contact.

15. The semiconductor device according to claim 14, wherein: A top surface of the conductive connection pattern contacts the gate insulating layer.

16. The semiconductor device according to any one of claims 10 to 15, wherein: The bonding pad includes a lower portion contacting the channel layer and an upper portion wider than the lower portion, and A bottom surface of the upper portion of the bonding pad is at the same height relative to the substrate as a bottom surface of the first connection pad.

17. The semiconductor device according to any one of claims 10 to 15, further comprising: The gate capping pattern, on the top surface of the word line, The first connection pad and the bonding pad are in contact with the gate capping pattern.

18. The semiconductor device according to claim 17, further comprising: filling an insulating layer on a side surface of the word line; a first connection contact penetrating the gate capping pattern and electrically connecting the word line to the first connection pad; as well as The second connection contact penetrates the gate capping pattern and the filling insulating layer and electrically connects the first connection pad to the second transistor.

19. A semiconductor device comprising: substrate; a first transistor and a second transistor on a substrate; a lower insulating structure on the first transistor and the second transistor; a first interlayer insulating layer on the lower insulating structure; a second interlayer insulating layer on the first interlayer insulating layer; a bit line in the second interlayer insulating layer; a conductive connection pattern in the first interlayer insulating layer; Channel layer, on the bit line; a gate insulating layer, on the channel layer; word line, on the gate insulating layer; a gate capping pattern, on the word line; bonding pads and connection pads on the gate capping pattern; A separation structure that separates the bonding pad from the connection pad; as well as Data storage pattern, on the bonding pad, wherein the bonding pad is electrically connected to the first transistor through the channel layer and the bit line, The connection pads are electrically connected to the word lines, and The connection pad is electrically connected to the second transistor through the conductive connection pattern.

20. The semiconductor device according to claim 19, wherein The first interlayer insulating layer includes a lower portion and an upper portion, a second interlayer insulating layer on a lower portion of the first interlayer insulating layer, An upper portion of the first interlayer insulating layer contacts a side surface of the second interlayer insulating layer, and The conductive connection pattern is in an upper portion of the first interlayer insulating layer.

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