Semiconductor device

Abstract

A semiconductor device includes: an active array in which a plurality of active patterns are arranged on a substrate; a gate structure extending in the first direction and crossing a central portion of the active pattern; a bit line structure contacting a first portion of the active pattern adjacent to the first sidewall of the gate structure and extending in a second direction; and a capacitor electrically connected to a second portion of each of the active patterns adjacent to the second sidewall of the gate structure. In a plan view, an upper end portion of each of the active patterns and a lower end portion of each of the active patterns are arranged to be spaced apart in a third direction inclined with respect to the first direction. The active patterns arranged side by side in the second direction form active columns.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2023-0086196 filed on July 4, 2023 in the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a DRAM device including a transistor and a capacitor in a memory cell. Background Art

[0004] Typically, two memory cells may be formed within one isolated active pattern in a DRAM device. In order to realize a highly integrated DRAM device, the active patterns and transistors and capacitors on the active patterns are appropriately arranged. Summary of the invention

[0005] The present disclosure provides a semiconductor device with high integration. Various examples relate to DRAM devices.

[0006] In general, a semiconductor device includes: an active array in which a plurality of active patterns are arranged on a substrate; a gate structure extending in a first direction parallel to an upper surface of the substrate and intersecting a central portion of the active pattern; a bit line structure contacting a first portion of the active pattern adjacent to a first sidewall of the gate structure and extending in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction; and a capacitor electrically connected to a second portion of each of the active patterns adjacent to a second sidewall of the gate structure. In a plan view, an upper end portion of each of the active patterns and a lower end portion of each of the active patterns are arranged to be spaced apart in a third direction inclined relative to the first direction. Active patterns arranged side by side in the second direction form an active column.

[0007] In another general aspect, a semiconductor device includes: an active array, wherein a plurality of active patterns are arranged on a substrate; a gate structure extending in a first direction parallel to an upper surface of the substrate and intersecting a central portion of the active pattern, and wherein each of the active patterns is divided into a first portion and a second portion by the gate structure; a bit line structure contacting the first portion of the active pattern and extending in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction, and the bit line structure includes a stacked bit line pattern having a conductive material and a first insulating pattern; and capacitors electrically connected to the second portion of the active pattern, respectively. In a plan view, an upper end portion of each of the active patterns and a lower end portion of each of the active patterns are arranged to be spaced apart in a third direction inclined relative to the first direction. An upper surface of the first portion of each of the active patterns is lower than an upper surface of the second portion of each of the active patterns.

[0008] In another general aspect, a semiconductor device includes: an active array, wherein a plurality of active patterns are arranged on a substrate; a gate structure extending in a first direction parallel to an upper surface of the substrate and intersecting a central portion of the active pattern, and wherein each of the active patterns is divided into a first portion and a second portion by the gate structure; a bit line structure contacting the first portion of the active pattern and extending in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction, and the bit line structure includes stacked bit line patterns having a conductive material and a first insulating pattern; and an insulating spacer disposed between side walls of the second portion of the active pattern and a side wall of the bit line structure and extending in the second direction; first contact plugs contacting the upper surfaces of the second portion of the active pattern, respectively, and each of the first contact plugs having an isolated shape; a second insulating pattern between the first contact plugs in the second direction; and a capacitor electrically connected to each of the first contact plugs.

[0009] In some embodiments, in a plan view, the sidewall of each of the active patterns has one of a straight line shape extending in the third direction, a curved shape extending in the third direction, and a shape having an upper portion and a lower portion extending in the second direction and a middle portion between the upper portion and the lower portion and extending in the first direction.

[0010] In some embodiments, the third direction corresponds to a direction along which each of the active patterns extends.

[0011] In some embodiments, in a plan view, active patterns arranged side by side in the first direction define active rows. At least a portion of the active patterns included in the even-numbered active rows may be disposed between adjacent active patterns included in the odd-numbered active rows.

[0012] In some embodiments, the gate structure is in a first recess on the active pattern.

[0013] In some embodiments, an upper surface of the first portion of the active pattern is lower than an upper surface of the second portion of the active pattern.

[0014] In some embodiments, the insulating spacer extends in the second direction and is defined between a sidewall of the second portion of the active pattern and a sidewall of the bit line structure.

[0015] In some embodiments, the bit line structure includes a bit line pattern and a first insulating pattern, the bit line pattern including a conductive material.

[0016] In some embodiments, a semiconductor device includes a metal silicide pattern between a bit line pattern and an upper surface of a first portion of the active pattern.

[0017] In some embodiments, a semiconductor device includes: a first contact plug having an isolated shape and contacting an upper surface of a second portion of each of the active patterns; and a second contact structure contacting at least a portion of an upper surface of the first contact plug. A capacitor may contact the second contact structure.

[0018] In some embodiments, the second contact structure is arranged in a honeycomb structure, and the honeycomb structure is provided at each vertex of the connected hexagons and at the center of each of the hexagons.

[0019] In some embodiments, an uppermost surface of the first contact plug is lower than an uppermost surface of the bit line structure.

[0020] In some embodiments, the semiconductor device includes a second insulating pattern between the first contact plugs in the second direction. The first contact plugs and the second insulating pattern may be aligned with the second direction.

[0021] In some embodiments, a semiconductor device includes: a contact plug that contacts an upper surface of a second portion of an active pattern, and an upper portion of the contact plug includes a recessed portion; a landing pad pattern that contacts at least a portion of an upper surface of the contact plug; and a third insulating pattern that fills an opening between the landing pad patterns and contacts the recessed portion.

[0022] In some embodiments, the landing pad pattern is arranged in a honeycomb structure, with the honeycomb structure provided at each vertex of the connected hexagons and at the center of each of the hexagons.

[0023] In some embodiments, an uppermost surface of the contact plug is higher than an uppermost surface of the bit line structure.

[0024] In some embodiments, the semiconductor device includes a first contact plug having an isolated shape and contacting an upper surface of the second portion of each of the active patterns. The capacitor may contact at least a portion of an upper surface of the first contact plug.

[0025] In some embodiments, the capacitor includes a lower electrode, a dielectric layer, and an upper electrode. The lower electrode may be arranged in a honeycomb structure provided at each vertex of connected hexagons and at the center of each of the hexagons.

[0026] In some embodiments, active patterns arranged side by side in the second direction define active columns, and active patterns arranged side by side in the first direction define active rows. A first portion of the active patterns included in the active columns may be arranged along the second direction, and a central portion of the active patterns included in the active rows may be arranged along the first direction.

[0027] In some embodiments, in a plan view, the active columns are repeatedly arranged in a first direction.

[0028] In some embodiments, in a plan view, the sidewall of each of the active patterns has one of a straight line shape extending in the third direction, a curved shape extending in the third direction, and a shape having an upper portion and a lower portion extending in the second direction and a middle portion between the upper portion and the lower portion and extending in the first direction.

[0029] In some embodiments, a semiconductor device includes a metal silicide pattern between a bit line pattern and an upper surface of a first portion of the active pattern.

[0030] In some embodiments, the first contact plug has an isolated shape and contacts an upper surface of the second portion of each of the active patterns; and the second contact structure contacts at least a portion of an upper surface of the first contact plug. The capacitor may contact the second contact structure.

[0031] In some embodiments, in a plan view, an upper end portion of each of the active patterns and a lower end portion of each of the active patterns are arranged to be spaced apart in a third direction inclined relative to the first direction. The active patterns arranged side by side in the second direction define active columns, and the active columns are repeatedly arranged in the first direction.

[0032] In some embodiments, in a plan view, the sidewall of each of the active patterns has one of a straight line shape extending in the third direction, a curved shape extending in the third direction, and a shape having an upper portion and a lower portion extending in the second direction and a middle portion between the upper portion and the lower portion and extending in the first direction.

[0033] In some embodiments, the semiconductor device includes a second contact structure between the first contact plug and the capacitor. The second contact structure may contact at least a portion of an upper surface of the first contact plug.

[0034] In various examples, a process of forming an active pattern of a semiconductor device is described. In addition, one gate structure and one capacitor may be provided in each of the active patterns, and thus, one memory cell may be formed in each of the active patterns. The semiconductor device may be highly integrated, and elements included in the semiconductor device may be easily formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a plan view schematically showing an example semiconductor device.

[0036] Figures 2 to 4 are plan views and cross-sectional views illustrating an example semiconductor device.

[0037] FIG. 5A to FIG. 5H is a plan view illustrating an example active pattern included in a semiconductor device.

[0038] Figure 6 to Figure 43 are plan views and cross-sectional views illustrating an example of a method of manufacturing an example of a semiconductor device.

[0039] Fig.44A and Fig.44B is a cross-sectional view for illustrating an example semiconductor device.

[0040] Fig.45 is a cross-sectional view for illustrating an example method of manufacturing a semiconductor device.

[0041] Fig.46 is a cross-sectional view for illustrating an example method of manufacturing a semiconductor device.

[0042] Fig.47 is a plan view showing an example semiconductor device.

[0043] Fig.48A and Fig.48B is a cross-sectional view illustrating an example semiconductor device.

[0044] Fig.49A , Fig.49B , Fig.50A and Fig.50B is a cross-sectional view for illustrating an example method of manufacturing a semiconductor device.

[0045] Fig.51 , Fig.52 and Fig.53 are plan views and cross-sectional views for illustrating an example semiconductor device.

[0046] Fig.54 and Fig.55 is a cross-sectional view for illustrating an example semiconductor device. DETAILED DESCRIPTION

[0047] In the following detailed description, two directions parallel to the upper surface of the substrate and perpendicular to each other are defined as a first direction and a second direction, respectively. A direction parallel to the upper surface of the substrate and extending obliquely relative to the first direction is defined as a third direction.

[0048] Figure 1 is a plan view schematically showing an example of a semiconductor device.

[0049] In the following example of a semiconductor device, one memory cell may be provided in one isolated active pattern on a substrate. For example, one transistor and one capacitor may be formed on one isolated active pattern.

[0050] Reference Figure 1 , the active patterns A are repeatedly arranged in each of the first direction and the second direction. The active patterns A arranged in each of the first direction and the second direction form an active array.

[0051] The upper end portion of the active pattern A and the lower end portion of the active pattern A may be spaced apart in the third direction. When the upper end portion of the active pattern A and the lower end portion of the active pattern A are directly connected to each other, the active pattern A may have a line shape extending in the third direction. In some embodiments, the third direction corresponds to a longitudinal direction (e.g., an extension direction) of the active pattern A, that is, a direction in which the active pattern extends.

[0052] Active patterns A arranged side by side in the first direction may form active rows R. Active patterns A arranged side by side in the second direction may form active columns C. At least a portion of the active patterns A included in the even-numbered active rows R may be located between adjacent active patterns A included in the odd-numbered active rows R.

[0053] The same active columns C may be repeatedly arranged in the first direction. In some embodiments, adjacent active columns C may be symmetrically arranged about a straight line extending in the second direction. The active patterns A included in the active columns C may be arranged along the second direction.

[0054] In some embodiments, a preliminary mask pattern may be formed on a substrate, and then the preliminary mask pattern may be separated by performing an etching process to form a mask pattern. In addition, the substrate may be etched using the mask pattern as an etching mask to form an active pattern A.

[0055] The active pattern A may have various arrangements based on the arrangement of the mask pattern. The arrangement of the active pattern A will be described in detail later.

[0056] exist Figure 1 In a plan view of FIG. 1 , for example, one gate structure G extending in the first direction along a direction perpendicular to both the first direction and the second direction may be disposed on one active pattern A. The gate structure G intersects a central portion of the active pattern A included in the active row R. One active pattern A may be divided into a first portion P1 and a second portion P2 by the gate structure G. Hereinafter, in one active pattern A, a portion located above based on the gate structure G is referred to as a first portion P1, and a portion located below based on the gate structure G is referred to as a second portion P2.

[0057] The bit line structure B / L may extend in the second direction while being electrically connected to the first portion P1 of the active pattern A included in the active column C. For example, an additional contact plug may not be disposed between the bit line structure B / L and the first portion P1 of the active pattern A. The bit line structure B / L may directly contact the first portion P1 of the active pattern A. A contact region between the bit line structure B / L and the active pattern A may be denoted as DC.

[0058] The capacitor may be electrically connected to the second portion P2 of the active pattern A. For example, at least one of the contact plug BC and the landing pad pattern may be formed between the second portion P2 of the active pattern A and the capacitor. Therefore, the capacitor may be electrically connected to the second portion P2 of the active pattern A through at least one of the contact plug BC and the landing pad pattern.

[0059] Figures 2 to 4 are a plan view and a cross-sectional view illustrating an example of a semiconductor device. FIG. 5A to FIG. 5H is a plan view illustrating an example of an active pattern included in a semiconductor device.

[0060] Figure 2 Only some components of the semiconductor device are shown. Figure 3 Including along Figure 2 A cross-sectional view taken along lines AA' and BB'. Figure 4 Including along Figure 2 A cross-sectional view taken along lines CC' and D-D'.

[0061] Reference Figures 2 to 4 , a device isolation trench 112 and an active pattern 110 are located on a substrate 100. A device isolation pattern 114 may be formed in the device isolation trench 112.

[0062] The substrate 100 may include a semiconductor material such as silicon, germanium, silicon germanium, etc., or a III-V compound such as GaP, GaAs, GaSb, etc. In some embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0063] A protruding portion between the device isolation trenches 112 of the substrate 100 may be defined as an active pattern 110, and the active pattern 110 may include the same material as the substrate 100. The device isolation pattern 114 may include an insulating material, for example, silicon oxide.

[0064] In a plan view, the upper end portion and the lower end portion of the active pattern 110 may be spaced apart from each other in the third direction. For example, the active pattern 110 may have an isolated shape extending in the third direction. For example, the active pattern 110 does not contact other active patterns extending in the third direction. In a plan view, the sidewall of the active pattern 110 may have a straight line shape, a curved shape, or a wavy shape. In some embodiments, the acute angle between the first direction and the third direction may be in the range of about 30 degrees to about 75 degrees.

[0065] The active patterns 110 may be aligned in a first direction to form active rows R. The active patterns 110 may be aligned in a second direction to form active columns C. The active rows R and the active columns C may form an active array.

[0066] The same active columns C may be repeatedly arranged in the first direction. In some embodiments, adjacent active columns C may be disposed symmetrically about a straight line extending in the second direction. The active patterns 110 included in the active columns C may be arranged along the second direction.

[0067] At least a portion of the active pattern 110 included in the even-numbered active rows R may be located between adjacent active patterns 110 included in the odd-numbered active rows R.

[0068] In a plan view, lower end portions of the active patterns 110 included in the even-numbered active rows R may be adjacent to upper end portions of the active patterns 110 included in the odd-numbered active rows R in the first direction. Lower end portions of the active patterns 110 included in the even-numbered active rows R and upper end portions of the active patterns 110 included in the odd-numbered active rows R may be alternately disposed along the first direction. Upper end portions and lower end portions of the active patterns 110 disposed in different adjacent active rows R may be aligned in the first direction.

[0069] In addition, upper end portions of the active patterns 110 included in the same active column C may be aligned in the second direction. Lower end portions of the active patterns 110 included in the same active column C may be aligned in the second direction. In each of the active rows R, central portions of the active patterns 110 may be aligned in the first direction.

[0070] The active patterns 110 included in the active array may be designed to have various shapes to have the arrangement as described above.

[0071] exist FIG. 5A to FIG. 5H, the horizontal line HL indicates a position for forming a gate structure, and the vertical line VL indicates a position for forming a bit line structure. Hereinafter, the upper end portion, the lower end portion, the upper portion, and the lower portion of the active pattern may be the position of the active pattern in a plan view. FIG. 5A to FIG. 5H In , the upper portion of the active pattern refers to the portion above the horizontal line HL, and the lower portion of the active pattern refers to the portion below the horizontal line HL. FIG. 5A to FIG. 5H , an upper end portion of the active pattern refers to an uppermost portion in the second direction, and a lower end portion refers to a lowermost portion in the second direction.

[0072] In some embodiments, Figure 5A As shown, both sidewalls of the active pattern 110 are straight and extend in the third direction. The upper and lower end portions of the active pattern 110 are straight and extend in the second direction. The angle between the third direction (e.g., the direction in which the active pattern 110 extends the most) and the first direction may be in the range of about 50 degrees to about 75 degrees.

[0073] In some embodiments, Figure 5B As shown, both sidewalls of the active pattern 110 are straight and extend in the third direction. The lower portion of the active pattern 110 includes a bent portion bent in the first direction. In addition, the upper and lower end portions of the active pattern 110 are straight and extend in the second direction.

[0074] In some embodiments, Figure 5C As shown, both sidewalls of the active pattern 110 are straight and extend in the third direction. The lower and upper portions of the active pattern 110 may include a curved portion that is curved in the second direction. In addition, the upper and lower portions of the active pattern 110 may extend in the second direction.

[0075] In some embodiments, Figure 5D As shown, both sidewalls of the active pattern 110 are curved and extend in the third direction. The upper end portion and the lower end portion of the active pattern 110 may extend in the second direction. The length of the upper end portion of the active pattern 110 in the second direction may be greater than the length of the lower portion of the active pattern 110 in the second direction. The upper sidewall of the active pattern 110 may have a protruding shape.

[0076] In some embodiments, Figure 5E As shown, both sidewalls of the active pattern 110 are curved and extend in the third direction. The lower portion of the active pattern 110 may include a first curved portion curved in the first direction. The upper portion of the active pattern 110 may include a second curved portion curved in the second direction. The upper end portion of the active pattern 110 may extend in the second direction, and the lower end portion of the active pattern 110 may extend in the first direction.

[0077] In some embodiments, Fig. 5F As shown, both sidewalls of the active pattern 110 are straight and extend in the third direction. The upper and lower end portions of the active pattern 110 may extend in the second direction. For example, the angle between the extending direction of the active pattern 110 and the first direction may be in the range of about 30 degrees to about 50 degrees.

[0078] In some embodiments, Figure 5G As shown, the active pattern 110 may include a third portion (e.g., an upper portion) and a fifth portion (e.g., a lower portion) extending in the second direction, and a fourth portion (e.g., a middle portion) between the third portion and the fifth portion and extending in the first direction. Each of the third portion, the fourth portion, and the fifth portion of the active pattern 110 may have a straight line shape. In each of the active patterns, the upper end portion of the active pattern may be spaced apart from the lower end portion of the active pattern in the third direction.

[0079] In some embodiments, Figure 5H As shown, both sidewalls of the active pattern 110 are curved and extend in the third direction. The upper portion of the active pattern 110 may include a first curved portion curved in the second direction, and the lower portion of the active pattern 110 may include a second curved portion curved in the second direction.

[0080] Hereinafter, the formation of Figure 5H However, the semiconductor device may be formed on an active pattern 110 as shown in FIG. FIG. 5A to FIG. 5G The active patterns 110 have various shapes as shown.

[0081] Again, refer to Figures 2 to 4 , a first recess 120 extending in the first direction may be disposed on the active pattern 110 and the device isolation pattern 114, and a gate structure 130 may be located in the first recess 120. That is, the gate structure 130 may extend through portions of the active pattern 110 and the device isolation pattern 114. The gate structure 130 may function as a word line.

[0082] One gate structure 130 may be disposed on one active pattern 110. Each of the gate structures 130 may extend in the first direction while crossing a plurality of active patterns 110 included in the same active row R. As shown in FIG.

[0083] In some embodiments, the gate structure 130 may intersect a central portion of the active pattern 110 in the third direction. In a plan view, the active pattern 110 may be divided into a first portion and a second portion (P1 and P2, see FIG. 1 ) by the gate structure 130. Fig.12). In a plan view, in the active pattern 110, the first portion P1 may be above the gate structure 130, and the second portion P may be below the gate structure 130. In the active pattern 110, the first portion P1 may be a portion adjacent to a first sidewall of the first recess 120, and the second portion P2 may be a portion adjacent to a second sidewall of the first recess 120.

[0084] Although not shown, the first impurity region and the second impurity region may be formed in the first portion P1 and the second portion P2 of the active pattern 110, respectively. Therefore, the gate structure 130 and the first and second impurity regions may function as a cell transistor. For example, the first and second impurity regions may be doped with n-type impurities.

[0085] In some embodiments, the gate structures 130 may be regularly arranged to be spaced apart from each other. Distances between the gate structures 130 in the second direction may be substantially equal to each other.

[0086] In some embodiments, the gate structure 130 may include a gate insulating pattern 122, a first gate pattern 124, a second gate pattern 126, and a gate mask 128. The gate insulating pattern 122 may include an oxide, such as silicon oxide. The first gate pattern 124 may include a metal, and the second gate pattern 126 may include polysilicon. The metal included in the first gate pattern 124 may include tungsten. The gate mask 128 may include a nitride, such as silicon nitride.

[0087] In some embodiments, the gate insulating pattern 122 may be located on the upper surface and sidewalls of the active pattern 110 exposed by the lower portion of the first recess 120. Thus, the gate structure 130 may function as a gate of a fin field effect transistor.

[0088] Edges of different active patterns 110 may be exposed on a region between two adjacent gate structures 130. In the region between two adjacent gate structures 130, first portions P1 and second portions P2 of the active pattern 110 may be repeatedly and alternately arranged in the first direction.

[0089] The height (eg, vertical level) of the upper surface of the first portion P1 of the active pattern 110 may be lower than that of the upper surfaces of the second portions P2 of other active patterns 110 adjacent to the first portion of the active pattern 110 in the first direction.

[0090] The first contact plugs 146 having isolated shapes (e.g., the first contact plugs 146 do not contact other first contact plugs) may respectively contact the upper surfaces of the second portions P2 of the active pattern 110. The first insulating pattern 144 may be disposed between the first contact plugs 146 in the second direction. The first contact plugs 146 and the first insulating pattern 144 may be arranged to be aligned in the second direction. The first insulating pattern 144 may contact the upper surface of the gate mask 128 of the gate structure 130.

[0091] In some embodiments, the first contact plug 146 may include polysilicon doped with impurities. In some embodiments, the first insulating pattern 144 may include silicon nitride.

[0092] The first contact plugs 146 and the first insulating patterns 144 may be alternately and repeatedly arranged in the second direction. The structure in which the first contact plugs 146 and the first insulating patterns 144 are alternately arranged may have a line shape extending in the second direction and may be referred to as a first line structure. Each of the two sidewalls of the first line structure may have a straight line shape.

[0093] The first buffer layer pattern 150a and the second buffer layer pattern 152a may be located on an upper surface of the first wire structure. In some embodiments, the first buffer layer pattern 150a may include silicon oxide, and the second buffer layer pattern 152a may include silicon nitride.

[0094] The second opening 156 extending in the second direction may be disposed between the first line structures. The first portion P1 of the active pattern 110, the device isolation pattern 114, and the gate mask 128 of the gate structure 130 may be exposed through the bottom of the second opening 156. The first portion P1 of the active pattern 110 and the gate mask 128 of the gate structure 130 may be alternately and repeatedly arranged on the bottom of the second opening 156 along the second direction. The gate mask 128 exposed by the bottom of the second opening 156 may have a partially etched shape, and thus the upper surface of the gate mask 128 exposed by the bottom of the second opening 156 may be relatively lower than the upper surface of the gate mask 128 adjacent to the bottom of the second opening 156.

[0095] The insulating spacer 160 may be located on the sidewalls of the second opening 156. The insulating spacer 160 may cover the active pattern 110, the first contact plug 146, the first insulating pattern 144, the first and second buffer layer patterns 150a and 152a, and the gate mask 128 exposed by the sidewalls of the second opening 156. The first portion P1 of the active pattern 110 may be exposed by the bottom of the second opening 156 between the insulating spacers 160.

[0096] In some embodiments, the insulating spacer 160 may include silicon oxide.

[0097] The bit line structure 168 may be formed in the second opening 156 between the insulating spacers 160. The bit line structure 168 may extend in the second direction and may directly contact the upper surface of the first portion P1 of the active pattern 110. Therefore, the insulating spacer 160 may be located between the bit line structure 168 and the second portion P2 of the active pattern 110. The insulating spacer 160 may extend in the second direction.

[0098] In some embodiments, the bit line structure 168 may include a first metal silicide pattern 162 , a bit line pattern 164 , and a second insulation pattern 166 .

[0099] The first metal silicide pattern 162 may include a metal silicide such as cobalt silicide, nickel silicide, or titanium silicide. For example, the bit line pattern 164 may include a metal such as tungsten, niobium, copper, aluminum, etc. The second insulating pattern 166 may include silicon nitride.

[0100] In some embodiments, the first metal silicide pattern 162 may be disposed only on the first portion P1 of the active pattern 110 exposed by the second opening 156. Therefore, the first metal silicide patterns 162 may be arranged to be spaced apart from each other in the second direction. In this case, the bit line structure 168 may include the first metal silicide pattern 162, the bit line pattern 164, and the second insulating pattern 166 stacked on the first portion P1 of the active pattern 110 in the second opening 156. The bit line structure 168 may include the bit line pattern 164 and the second insulating pattern 166 stacked on the gate mask 128.

[0101] In some embodiments, the first metal silicide pattern 162 may be formed on the entire bottom of the second opening 156. That is, the first metal silicide pattern 162 may be disposed on the first portion P1 of the active pattern 110 and the upper surface of the gate mask 128 exposed by the second opening 156. Therefore, the first metal silicide pattern 162 may extend in the second direction. The bit line structure 168 may include the first metal silicide pattern 162, the bit line pattern 164, and the second insulation pattern 166 stacked on the first portion P1 of the active pattern 110 and the gate mask 128 exposed by the second opening 156.

[0102] In some embodiments, uppermost surfaces of the bit line structure 168 , the insulating spacer 160 , and the second buffer layer pattern 152 a may be coplanar with each other and may be substantially planar.

[0103] In some embodiments, a bottom surface of the bit line structure 168 may be lower than an uppermost surface of the second portion P2 of the active pattern 110. A sidewall of the bit line structure 168 may face at least a portion of a sidewall of the second portion P2 of the active pattern 110 in a cross-sectional view.

[0104] In some embodiments, an uppermost surface of the first contact plug 146 may be lower than an uppermost surface of the bit line structure 168 .

[0105] The first mold layer 170 may cover upper surfaces of the bit line structure 168, the insulating spacer 160, the second buffer layer pattern 152a, and the second insulating pattern 166. The first mold layer 170 may include an insulating material having an etching selectivity with respect to silicon oxide. The first mold layer 170 may include silicon nitride, SiOCN, or SiOC.

[0106] The second contact structure 180 may pass through the first mold layer 170 and may contact the first contact plug 146. The second contact structure 180 may contact a portion of the first contact plug 146. The second contact structure 180 and the first contact plug 146 may be electrically connected to the second portion P2 of the active pattern.

[0107] A central portion of the second contact structure 180 may be offset from a central portion of the first contact plug 146 in a vertical direction (eg, a direction perpendicular to both the first direction and the second direction).

[0108] In some embodiments, the second contact structure 180 may contact the first contact plug 146 and the insulating spacer 160 and the second insulating pattern 166 adjacent to the first contact plug 146. A bottom surface of the second contact structure 180 may be lower than an uppermost surface of the first contact plug 146.

[0109] In some embodiments, an uppermost surface of the second contact structure 180 may be higher than an uppermost surface of the bit line structure 168 .

[0110] In some embodiments, the second contact structure 180 may include a second silicon pattern 174 a doped with impurities, a second metal silicide pattern 175 , and a second contact plug 178 .

[0111] The second metal silicide pattern 175 may include a metal silicide such as cobalt silicide, nickel silicide, or titanium silicide. For example, the second contact plug 178 may include a metal such as tungsten, niobium, copper, or aluminum.

[0112] In some embodiments, the inner spacer 176 may surround the sidewall of the second contact plug 178. The inner spacer 176 may include an insulating material. The inner spacer 176 may include silicon nitride.

[0113] In some embodiments, the plurality of second contact plugs 178 may be arranged in a honeycomb structure provided at each vertex of connected hexagons and at a central portion of each of the hexagons.

[0114] An etch stop layer 182 may be on the second contact plug 178 and the first mold layer 170. The etch stop layer 182 may include silicon nitride.

[0115] The capacitor 190 may pass through the etch stop layer 182 and may be located on the second contact plug 178. The capacitor 190 may include a lower electrode 184, a dielectric layer 186, and an upper electrode 188. The lower electrode 184 may pass through the etch stop layer 182 and may contact the second contact plug 178. Therefore, the lower electrode 184 of the capacitor 190 may be electrically connected to the second portion P2 of the active pattern 110 via the second contact structure 180 and the first contact plug 146.

[0116] The plurality of lower electrodes 184 may be arranged in a honeycomb structure. In some embodiments, the lower electrode 184 may have a columnar or cylindrical shape.

[0117] One gate structure 130 and one capacitor 190 may be disposed on one active pattern 110. One memory cell may be disposed on one active pattern 110. The gate structure 130 may extend in the first direction to cross a central portion in the third direction of the active pattern 110. The bit line structure 168 may extend in the second direction and directly contact the first portion P1 of the active pattern 110.

[0118] Figure 6 to Figure 43 are plan views and cross-sectional views illustrating an example of a method of manufacturing a semiconductor device.

[0119] Reference Figure 6 and Figure 7 , a preliminary mask pattern 104 for forming an active pattern may be formed on a substrate.

[0120] Each of the preliminary mask patterns 104 may extend in a third direction inclined with respect to the first direction. The preliminary mask patterns 104 may be repeatedly arranged to be spaced apart from each other.

[0121] In some embodiments, the initial mask pattern 104 may be formed by a double patterning process. Figure 6 As shown, a first mold mask pattern 102 may be formed on a substrate. A preliminary mask pattern 104 may be formed on the sidewall of the first mold mask pattern 102. The preliminary mask pattern 104 may have a spacer shape. Figure 7 As shown, the first mold mask pattern 102 may be removed to form preliminary mask patterns 104 spaced apart from each other.

[0122] In some embodiments, the preliminary mask pattern 104 may be formed by a patterning process including a single photo process and a single etching process. In some embodiments, the preliminary mask pattern 104 may be formed by a four-time patterning process in which a double patterning process is performed twice.

[0123] The preliminary mask pattern 104 may be designed in various shapes to form an active pattern having a target shape.

[0124] FIG. 8A to FIG. 8G Figure 2 shows a plan view of various types of initial mask patterns. FIG. 8A to FIG. 8G In FIG. 1 , the dotted line indicates the portion used for cutting.

[0125] In some embodiments, Fig. 8A As shown, each of the preliminary mask patterns 104 may have a portion extending in the third direction and a bent portion bent in a fourth direction perpendicular to the third direction. Each of the preliminary mask patterns 104 may extend so that the portion extending in the third direction and the bent portion bent in the fourth direction may be repeatedly and alternately arranged. The bent portion bent in the fourth direction of the preliminary mask pattern 104 may correspond to a cutting portion in a subsequent process.

[0126] In some embodiments, Figure 8B and Figure 8C As shown, the preliminary mask pattern 104 may have a portion extending in the third direction and a bent portion bent in the first direction. The preliminary mask pattern 104 may extend so that the portion extending in the third direction and the bent portion bent in the first direction may be repeatedly and alternately arranged. The bent portion of the preliminary mask pattern 104 bent in the first direction may correspond to a cutting portion in a subsequent process.

[0127] In some embodiments, Fig.8D As shown, the preliminary mask pattern 104 may have a portion extending in the third direction and a protruding portion protruding from one side of the portion extending in the third direction. The protruding portion may be regularly and repeatedly disposed.

[0128] In some embodiments, Fig. 8E and Figure 7 As shown, the preliminary mask pattern 104 may include a portion extending in the third direction and a portion extending in the first direction. Both sides of the portion extending in the third direction may be bent. The portion extending in the first direction may correspond to a cutting portion in a subsequent process.

[0129] In some embodiments, Fig.8F As shown, each of the preliminary mask patterns may have a straight line shape extending in the third direction.

[0130] In some embodiments, Figure 8GAs shown, the initial mask pattern includes a portion extending in the first direction and a portion extending in the second direction. The initial mask pattern 104 can be extended so that the portion extending in the first direction and the portion extending in the second direction can be repeatedly and alternately arranged. Some of the portions extending in the first direction may correspond to the cutting portions in the subsequent process.

[0131] In the following, you can use Figure 7 The initial mask pattern 104 shown in FIG. 1 is used as an example to describe the process. However, even if the initial mask pattern 104 having a different shape may be used, the subsequent processes may be performed in the same manner.

[0132] Reference Figures 9 to 11 , the preliminary mask pattern 104 may be etched in the second direction to cut the preliminary mask pattern 104, thereby forming a mask pattern. The etched portion (ie, the cutting portion 10) may have a line shape extending in the second direction.

[0133] The substrate 100 may be etched using the mask pattern as an etching mask to form an active pattern 110. Specifically, the initial mask pattern 104 may be etched in the second direction, and the initial mask pattern 104 may be separated to form a mask pattern. The active pattern 110 may be formed using the mask pattern as an etching mask. Therefore, the active pattern 110 having a high arrangement density may be formed by the following process. In addition, a device isolation trench 112 may be formed between the active patterns 110.

[0134] In some embodiments, the substrate 100 may be etched using the preliminary mask pattern 104 as an etching mask to form a preliminary active pattern. Thereafter, the preliminary active pattern may be etched in the second direction, and thus, the preliminary active pattern may be separated to form an active pattern 110.

[0135] The active pattern 110 may have a target shape. The active pattern 110 may not be limited to Fig. 9 For example, the active pattern may have the shape and arrangement shown in FIG. 5A to FIG. 5H Any of the shapes and arrangements shown in .

[0136] Through the above process, the active patterns 110 having the third direction as the longitudinal direction may be formed. The active patterns 110 arranged side by side in the first direction may form active rows R. In addition, the active patterns 110 arranged side by side in the second direction perpendicular to the first direction may form active columns C. Therefore, the active rows R and the active columns C may form an active array.

[0137] The same active columns C may be repeatedly arranged in the first direction. In some embodiments, adjacent active columns C may be symmetrically arranged about a straight line extending in the second direction. The active patterns 110 included in the active columns C may be arranged along the second direction.

[0138] At least a portion of the active pattern 110 included in the even-numbered active rows R may be disposed between adjacent active patterns 110 included in the odd-numbered active rows R adjacent to the even-numbered active rows R.

[0139] Thereafter, a device isolation pattern 114 may be formed to fill the device isolation trench 112. The device isolation pattern 114 may include an insulating material, for example, silicon oxide.

[0140] The process for forming the device isolation pattern 114 may include forming an insulating layer on the active pattern 110 to fill the device isolation trench 112, and planarizing the insulating layer to expose the upper surface of the active pattern 110. The planarization process may include a chemical mechanical polishing process.

[0141] Reference Figure 12 to Figure 14 , the central portions of the active pattern 110 and the device isolation pattern 114 may be partially etched to form a first recess 120 extending in the first direction. One active pattern 110 may include one first recess 120. Therefore, one active pattern 110 may be divided by the first recess 120 into a first portion P1 corresponding to a portion above the first recess 120 in a plan view and a second portion P2 corresponding to a portion below the first recess 120 in a plan view. In the active pattern 110, a portion adjacent to a first sidewall of the first recess 120 may be the first portion P1, and a portion adjacent to a second sidewall of the first recess 120 may be the second portion P2.

[0142] Each of the first concave portions 120 may extend in the first direction to intersect central portions of the plurality of active patterns 110 included in the same active row R. The first concave portions 120 may be spaced apart in the second direction.

[0143] In some embodiments, distances d1 between adjacent first recesses 120 in the second direction may be substantially equal to each other. In this case, since the arrangement density of the first recesses 120 is uniform, the first recesses 120 may be easily formed.

[0144] In some embodiments, an upper surface of the device isolation pattern 114 exposed by the bottom of the first recess 120 may be lower than an upper surface of the active pattern 110 exposed by the bottom of the first recess 120. Thus, an upper portion (e.g., an upper sidewall and an upper surface) of the active pattern 110 disposed above an upper surface of the device isolation pattern 114 may be exposed in the first recess 120. Thus, an upper portion of the active pattern 110 exposed by the first recess 120 may be used as an active fin for forming a fin field effect transistor.

[0145] Thereafter, a gate structure 130 may be formed in the first recess 120 .

[0146] Specifically, a gate insulating layer may be conformally formed on the bottom and sidewalls of the first recess 120. A first gate electrode layer may be formed on the gate insulating layer, and an upper portion of the first gate electrode layer may be removed to form a first gate pattern 124 in a lower portion of the first recess 120. A second gate electrode layer may be formed on the first gate pattern 124 and the gate insulating layer, and then an upper portion of the second gate electrode layer may be removed to form a second gate pattern 126 in the first recess 120. A gate mask layer may be formed on the gate insulating layer and the second gate pattern 126. The gate mask layer may be planarized until the upper surfaces of the active pattern 110 and the device isolation pattern 114 may be exposed to form a gate structure 130 in the first recess 120. The gate structure 130 may include a stacked gate insulating pattern 122, a first gate pattern 124, a second gate pattern 126, and a gate mask 128.

[0147] The gate structure 130 may extend in the first direction, and a plurality of gate structures may be spaced apart from each other in the second direction.

[0148] In some embodiments, a gate insulating pattern 122 may be formed on an upper surface and a sidewall of the active pattern 110 in the first recess 120. Thus, the gate structure 130 may function as a gate of a fin field effect transistor.

[0149] Reference Fig.15 and Fig.16 , a cleaning process may be performed to remove the natural oxide layer on the surface of the active pattern 110 adjacent to both sides of the gate structure 130. When the cleaning process is performed, the upper portions of the device isolation pattern 114 and the gate insulation pattern 122 may be removed. Therefore, the active pattern 110 may protrude from the device isolation pattern 114, and the upper surface and upper sidewall of the active pattern 110 may be exposed. Therefore, the exposed area of ​​the active pattern 110 may be increased.

[0150] Thereafter, a first conductive layer 140 may be formed to cover the device isolation pattern 114, the gate structure 130, and the active pattern 110. The first conductive layer 140 may directly contact the active pattern 110 adjacent to both sides of the gate structure 130.

[0151] The first conductive layer 140 may include polysilicon doped with impurities. The impurities may include N-type impurities. The impurities may diffuse into the active pattern 110 to form first and second impurity regions at the active pattern 110 adjacent to both sides of the gate structure 130.

[0152] Reference Figures 17 to 19 An etching mask may be formed on the first conductive layer 140 to selectively expose a central portion of the active pattern 110. The etching mask may have a line shape extending in the first direction while covering at least the first portion P1 and the second portion P2 of the active pattern 110.

[0153] In some embodiments, the exposed portion of the etch mask can overlap the gate mask 128 of the gate structure 130 .

[0154] A portion of the first conductive layer 140 may be etched using the etching mask to form a first opening 142 that exposes an upper portion of the gate mask 128 of the gate structure 130 and extends in the first direction at the center of the active pattern 110. In the etching process, an upper portion of the gate mask 128 may be partially removed.

[0155] By forming the first opening 142, the first conductive layer 140 may be transformed into first conductive patterns 140a extending in the first direction. Each of the first conductive patterns 140a may extend in the first direction and may contact the first portion P1 and the second portion P2 of the active pattern 110. The first conductive patterns 140a may be spaced apart from each other in the second direction. In some embodiments, the distances between adjacent first conductive patterns 140a in the second direction may be substantially equal to each other.

[0156] Thereafter, a first insulating layer may be formed on the first conductive pattern 140a and the gate mask 128 to fill the first opening 142. The first insulating layer may be planarized until the upper surface of the first conductive pattern 140a is exposed to form a first insulating pattern 144 filling the first opening 142. The first insulating pattern 144 may include the same material as that of the gate mask 128. Thus, the gate mask 128 and the first insulating pattern 144 may be merged into one layer. The first insulating pattern 144 may include silicon nitride.

[0157] Reference Fig. 20 and Fig.21 A first buffer layer 150 may be formed on the first conductive pattern 140a and the first insulating pattern 144. The first buffer layer 150 may cover the first conductive pattern 140a and the first insulating pattern 144. A second buffer layer 152 may be formed on the first buffer layer 150.

[0158] The first buffer layer 150 and the second buffer layer 152 may include an insulating material. The first buffer layer 150 may include a material having a high etching selectivity relative to a material of the second buffer layer 152. In some embodiments, the first buffer layer 150 may include silicon oxide, and the second buffer layer 152 may include silicon nitride. The second buffer layer 152 may be formed to have a thickness greater than that of the first buffer layer 150.

[0159] An etch mask 154 having a liner shape extending in the second direction may be formed on the second buffer layer 152 to cover the second portion P2 of the active pattern 110 . The etch mask 154 may expose the first portion P1 of the active pattern 110 and a portion of the gate structure 130 .

[0160] Reference Figure 22 to Figure 25 The second buffer layer 152, the first buffer layer 150, the first conductive pattern 140a, and the first insulating pattern 144 may be etched using the etching mask 154. Subsequently, the device isolation pattern 114, the active pattern 110, and the upper portion of the gate mask 128 may be etched to form a second opening 156.

[0161] The second opening 156 may extend in the second direction while exposing the first portion P1 of each of the active patterns 110. The first portion P1 of the active pattern 110, the device isolation pattern 114, and the gate mask 128 may be exposed by the bottom of the second opening 156. The upper surface of the first portion P1 of the active pattern 110 exposed by the bottom of the second opening 156 may be lower than the upper surface of the second portion P2 of the active pattern 110.

[0162] The first conductive pattern 140a may be patterned to form first contact plugs 146 located at both sides of the second opening 156. In addition, the first buffer layer 150 and the second buffer layer 152 may be patterned to form first buffer layer patterns 150a and second buffer layer patterns 152a, respectively.

[0163] The first contact plugs 146 may have an isolated shape and may respectively contact the second portions P2 of the active patterns 110. That is, the first contact plugs 146 may be formed by cutting the first conductive pattern 140a in the second direction and thus may have an isolated shape. The first insulating pattern 144 may be maintained between the first contact plugs 146 in the second direction.

[0164] The first buffer layer pattern 150 a and the second buffer layer pattern 152 a may extend in the second direction. The first buffer layer pattern 150 a and the second buffer layer pattern 152 a may cover the first contact plug 146 and the first insulation pattern 144 .

[0165] In some embodiments, the device isolation pattern 114, the active pattern 110, and the gate mask 128 may be etched at substantially the same etching rate. Fig.23 and Fig.24 As shown, an upper surface of the first portion P1 of the active pattern 110 exposed by the bottom of the second opening 156 and an upper surface of the gate mask 128 exposed by the bottom of the second opening 156 may be substantially coplanar with each other.

[0166] In some embodiments, the gate mask 128 may be etched at a lower etching rate than the device isolation pattern 114 and the active pattern 110. In this case, Fig.25As shown, the first portion P1 of the active pattern 110 exposed by the bottom of the second opening 156 may be lower than the upper surface of the gate mask 128 exposed by the bottom of the second opening 156. The gate mask 128 exposed by the bottom of the second opening 156 may protrude from the first portion P1 of the active pattern 110 exposed by the bottom of the second opening 156.

[0167] Reference Figure 26 to Figure 29 , an insulating spacer layer may be conformally formed on surfaces of the second buffer layer pattern 152a and the second opening 156. The insulating spacer layer may include silicon oxide.

[0168] The insulating spacer layer may be anisotropically etched to form an insulating spacer 160 on the sidewall of the second opening 156. The insulating spacer 160 may be formed on the first contact plug 146, the device isolation pattern 114, and the first and second buffer layer patterns 150a and 152a corresponding to the sidewall of the second opening 156. When the insulating spacer 160 is formed, the inner width of the second opening 156 may be reduced. The first portion P1 of the active pattern 110 and the gate mask 128 may be exposed through the bottom of the second opening 156.

[0169] A first silicon layer may be formed on at least the first portion P1 of the active pattern 110 exposed by the bottom of the second opening 156 .

[0170] The first silicon layer may be formed in order to increase a silicon area contacting the first metal layer in a subsequent heat treatment process for silicidation. However, in some embodiments, the process of forming the first silicon layer may be omitted.

[0171] A first metal layer may be formed on the first silicon layer, and a heat treatment process may be performed to form a first metal silicide pattern 162 at least on the active pattern 110 in the second opening 156. The first metal silicide pattern 162 may be formed by reacting the first silicon layer and the first metal layer with each other. In some embodiments, during the process of forming the first metal silicide pattern 162, all of the first silicon layer may react to leave the first metal silicide pattern 162 only on the active pattern 110.

[0172] In some embodiments, the first silicon layer may be formed by a selective epitaxial growth process. Fig. 27 and Fig.28 As shown, the first silicon layer may be formed only on the exposed first portion P1 of the active pattern 110. Therefore, the first metal silicide pattern 162 may be formed only on the exposed first portion P1 of the active pattern 110. Therefore, the first metal silicide patterns 162 in the second opening 156 may be spaced apart from each other in the second direction.

[0173] In some embodiments, a first silicon layer may be formed on the first portion P1 of the active pattern 110 and the upper surface of the gate mask 128 adjacent thereto. The first silicon layer may be formed by depositing a polysilicon layer and etching back the polysilicon layer. The first silicon layer may be formed on the entire bottom of the second opening 156. Fig.29 As shown, a first metal silicide pattern 162 may be formed on the exposed first portion P1 of the active pattern 110 and the upper surface of the gate mask 128 adjacent thereto. Therefore, the first metal silicide pattern 162 formed in the second opening 156 may extend in the second direction.

[0174] Hereinafter, a process of forming the first metal silicide pattern 162 only on the exposed first portion P1 of the active pattern 110 will be described. However, the first metal silicide pattern may not be limited thereto, and the first metal silicide pattern may be formed on the exposed first portion P1 of the active pattern 110 and on the upper surface of the gate mask 128 adjacent thereto. In this case, the same subsequent processes may be performed.

[0175] Reference Figure 30 to Figure 32 A second conductive layer may be formed on the first metal silicide pattern 162, the gate mask 128, the second buffer layer pattern 152a, and the insulating spacer 160 to fill the second opening 156. The second conductive layer may be etched back so that the second conductive layer may remain only inside the second opening 156 to form a bit line pattern 164.

[0176] In some embodiments, the bit line pattern 164 may include a metal pattern. In some embodiments, the bit line pattern 164 may have a structure in which a barrier metal pattern and a metal pattern are stacked.

[0177] In some embodiments, an uppermost surface of the bit line pattern 164 may be lower than an upper surface of the first contact plug 146 .

[0178] The bit line pattern 164 may extend in the second direction and may be electrically connected to the first portion P1 of the active pattern 110 in the second opening 156. The bit line pattern 164 may be formed by a damascene process. Therefore, compared with forming the bit line pattern in an embossed process, patterning defects of the bit line pattern 164 may be reduced. In addition, even if the line width of the bit line pattern is reduced, patterning defects of the bit line pattern 164 may be reduced.

[0179] A second insulating layer may be formed on the bit line pattern 164, the second buffer layer pattern 152a, and the insulating spacer 160 to fill the second opening 156. The second insulating layer may include silicon oxide. Thereafter, the second insulating layer may be planarized until the second insulating layer remains only inside the second opening 156 to form a second insulating pattern 166 filling the second opening 156. The planarization process may include an etch-back or chemical mechanical polishing process. After the planarization process, the upper surfaces of the second insulating pattern 166, the insulating spacer 160, and the second buffer layer pattern 152a may be exposed.

[0180] Through the above processes, a bit line structure 168 including a first metal silicide pattern 162 , a bit line pattern 164 , and a second insulation pattern 166 may be formed.

[0181] In some embodiments, the bit line structure 168 contacting the first portion P1 of the active pattern 110 may include stacked first metal silicide pattern 162, bit line pattern 164, and second insulation pattern 166. The bit line structure 168 contacting the gate mask 128 may include stacked bit line pattern 164 and second insulation pattern 166.

[0182] In some embodiments, Fig.29 The structure shown is subjected to a planarization process. In this case, Fig.33 As shown, the bit line structure 168 contacting the first portion P1 of the active pattern 110 and the upper surface of the gate mask 128 may include a first metal silicide pattern 162 , a bit line pattern 164 , and a second insulating pattern 166 that are stacked.

[0183] In some embodiments, Fig.34 As shown, the gate mask 128 exposed by the bottom of the second opening 156 may protrude from the first portion P1 of the active pattern 110 exposed by the bottom of the second opening 156. In this case, the first metal silicide pattern 162 may be formed only in the gap between the gate masks 128. That is, the first metal silicide pattern 162 may be spaced apart in the second direction and may be isolated by the gate mask 128 having the protrusion.

[0184] like Fig.35 As shown, when the process of forming the first metal silicide pattern 162 is performed, the first silicon layer may not be completely reacted, and a portion of the first silicon layer may remain. In this case, a stack of the silicon pattern 161 and the first metal silicide pattern 162 may be formed under the bit line pattern 164. The bit line structure 168 contacting the first portion P1 of the active pattern 110 and the upper surface of the gate mask 128 may include the stacked silicon pattern 161, the first metal silicide pattern 162, the bit line pattern 164, and the second insulating pattern 166.

[0185] Reference Figure 36 to Figure 38 A first mold layer 170 may be formed on the second insulating pattern 166, the second buffer layer pattern 152a, the first insulating pattern 144, the insulating spacer 160, and the first contact plug 146. The first mold layer 170 may include an insulating material having an etching selectivity with respect to silicon oxide. The first mold layer 170 may include silicon nitride, SiOCN, or SiOC.

[0186] The first mold layer 170 may serve as a molding member for forming a second contact structure electrically connected to the first contact plug 146 .

[0187] A portion of the first mold layer 170 may be etched, and the first and second buffer layer patterns 150a and 152a, the second insulating pattern 166, and the insulating spacer 160 under the first mold layer 170 may be etched to form a second contact hole 172 exposing a portion of an upper surface of the first contact plug 146. In some embodiments, an upper portion of the first contact plug 146 may also be partially etched by the etching process.

[0188] A portion of the upper surface of one first contact plug 146 may be exposed by the bottom of one second contact hole 172 .

[0189] In some embodiments, the plurality of second contact holes 172 may be arranged in a honeycomb structure disposed at each vertex of the connected hexagons and at the central portion of each of the hexagons. Fig.39 , wherein the plurality of second contact holes 172 form a hexagonal lattice, and the second contact holes 172 are located at the vertices and the center of each connected hexagon in the lattice.

[0190] A second silicon layer may be formed on the first mold layer 170 to fill the second contact hole 172, and the second silicon layer may be planarized until an upper surface of the first mold layer 170 is exposed to form a second preliminary silicon pattern 174 in the second contact hole 172. The planarization process may include an etch-back process or a chemical mechanical polishing process.

[0191] In some embodiments, the second preliminary silicon pattern 174 may include polysilicon doped with impurities. In some embodiments, after forming the second silicon layer, a heat treatment process for removing the voids may be further performed. The heat treatment process may include laser annealing.

[0192] Reference Figure 39 to Figure 41 , the second preliminary silicon pattern 174 may be etched back to form a second silicon pattern 174 a in a lower portion of the second contact hole 172 .

[0193] A second metal layer may be formed on the second silicon pattern 174a, and a thermal treatment process may be performed to form a second metal silicide pattern 175 on the second silicon pattern 174a. The second metal silicide pattern 175 may be formed by reacting the second silicon pattern 174a and the second metal layer with each other.

[0194] An inner spacer 176 including an insulating material may be formed on a sidewall of the second contact hole 172 .

[0195] Thereafter, a third metal layer may be formed on the second metal silicide pattern 175 and the first mold layer 170 to fill the second contact hole 172. The third metal layer may be planarized until the upper surface of the first mold layer 170 is exposed to form a second contact plug 178 filling the second contact hole 172.

[0196] Thus, the second contact plug 178 may be electrically connected to the second portion P2 of the active pattern 110 via the second metal silicide pattern 175, the second silicon pattern 174a, and the first contact plug 146. A stacked structure including the second silicon pattern 174a, the second metal silicide pattern 175, and the second contact plug 178 and contacting the second portion P2 of the active pattern 110 may be referred to as a second contact structure 180.

[0197] In some embodiments, the plurality of second contact plugs 178 may be arranged in a honeycomb structure provided at each vertex of connected hexagons and at a central portion of each of the hexagons.

[0198] Reference Fig.42 and Fig.43 , an etch stop layer 182 may be formed on the second contact plug 178 and the first mold layer 170. The etch stop layer 182 may include silicon nitride.

[0199] A capacitor 190 may be formed on the second contact plug 178. The capacitor 190 may include a lower electrode 184, a dielectric layer 186, and an upper electrode 188. The lower electrode 184 may pass through the etch stop layer 182 and may contact the second contact plug 178. A plurality of lower electrodes 184 may be arranged in a honeycomb structure, for example, as shown in FIG. Fig.51 In some embodiments, the lower electrode 184 may have a pillar or cylindrical shape.

[0200] Through the above process, reference Figures 1 to 4 A semiconductor device is described.

[0201] Fig.44A and Fig.44B is a cross-sectional view for illustrating an example of a semiconductor device.

[0202] Fig.44A Including along Figure 2A cross-sectional view taken along line AA', and Fig.44B Included are cross-sectional views taken along line CC' and line DD'.

[0203] Fig.44A and Fig.44B The semiconductor device shown in FIG. Figures 2 to 4 The described semiconductor devices are substantially the same except that the first contact plug may not be formed on the second portion P2 of the active pattern 110. Therefore, redundant descriptions are omitted.

[0204] Reference Fig.44A and Fig.44B , the second contact structure 180 may contact the second portion P2 of the active pattern 110 .

[0205] In some embodiments, the second contact structure 180 may be offset relative to the second portion P2 of the active pattern 110 and may contact a portion of the second portion P2 of the active pattern 110. For example, the center of the bottom of the second contact structure 180 may not coincide with the center of the upper surface of the second portion P2 of the active pattern 110. A plurality of second contact structures 180 may be arranged in a honeycomb structure.

[0206] The bottom of the second contact structure 180 may contact the second portion P2 of the active pattern 110, the first and second buffer layer patterns 150a and 152a, and the insulating spacer 160 adjacent thereto.

[0207] In some embodiments, the second contact structure 180 may include a second silicon pattern 174a doped with impurities, a second metal silicide pattern 175, and a second contact plug 178. The stack structure of the second contact structure 180 may be similar to that of the reference Figures 2 to 4 Same as those described.

[0208] The capacitor 190 may be formed on the second contact structure 180. The lower electrode 184 of the capacitor 190 may be electrically connected to the second portion P2 of the active pattern 110 via the second contact structure 180.

[0209] Fig.45 and Fig.46 is a cross-sectional view for illustrating an example of a method of manufacturing a semiconductor device. Fig.45 and Fig.46 Each of the Figure 2 Cross-sectional views taken along lines AA', CC' and DD'.

[0210] In addition to omitting the process of forming the first contact plug, the manufacturing Fig.44A and Fig.44BThe semiconductor device method shown in the Figure 6 to Figure 43 The method described is the same.

[0211] Reference Fig.45 , the reference can be performed in the same way Figures 6 to 14 Thereafter, a first buffer layer and a second buffer layer may be formed to cover the active pattern 110 , the device isolation pattern 114 , and the gate structure 130 .

[0212] An etch mask having a liner shape extending in the second direction and covering the second portion P2 of the active pattern 110 may be formed on the second buffer layer. The etch mask may expose the first portion P1 of the active pattern 110 and a portion of the gate structure 130.

[0213] The first and second buffer layers, the upper portion of the first portion P1 of the active pattern 110, and the upper portion of the gate mask 128 may be etched to form a second opening 156. The first and second buffer layers may be transformed into first and second buffer layer patterns 150a and 152a through the second opening 156. The first and second buffer layer patterns 150a and 152a may extend in the second direction while covering the second portion P2 of the active pattern 110.

[0214] The second opening 156 may extend in the second direction while exposing the first portion P1 of the active pattern 110. The first portion P1 of the active pattern 110, the device isolation pattern 114, and the gate mask 128 may be exposed through the bottom of the second opening 156. An upper surface of the first portion P1 of the active pattern 110 exposed by the bottom of the second opening 156 may be lower than an upper surface of the second portion P2 of the active pattern 110.

[0215] In some embodiments, the device isolation pattern 114, the active pattern 110, and the gate mask 128 may be etched at substantially the same etching rate. Fig.45 As shown, an upper surface of the first portion P1 of the active pattern 110 exposed by the bottom of the second opening 156 and an upper surface of the gate mask 128 exposed by the bottom of the second opening 156 may be coplanar with each other.

[0216] In some embodiments, the gate mask 128 may be etched to have a lower etching rate than the etching rates of the device isolation pattern 114 and the active pattern 110. In this case, as shown in FIG. Fig.46 As shown, the first portion P1 of the active pattern 110 exposed by the bottom of the second opening 156 may be lower than the upper surface of the gate mask 128 exposed by the bottom of the second opening 156. The gate mask 128 exposed by the bottom of the second opening 156 may protrude from the first portion P1 of the active pattern 110 exposed by the bottom of the second opening 156.

[0217] After that, you can execute the reference Figure 26 to Figure 43 The process is described to manufacture a semiconductor device including the gate mask 128 protruding from the first portion P1 of the active pattern 110 .

[0218] The semiconductor device may not include the first contact plug, which simplifies the structure of the semiconductor device and thus simplifies the manufacturing process of the semiconductor device.

[0219] Fig.47 is a plan view showing an example of a semiconductor device. Fig.48A and Fig.48B is a cross-sectional view illustrating an example of a semiconductor device.

[0220] Fig.47 Only some components of the semiconductor device are shown. Fig.48A Including along Fig.47 A cross-sectional view taken along line AA', and Fig.48B Including along Fig.47 A cross-sectional view taken along line CC' and line DD'.

[0221] In addition to the second contact structure and the landing pad pattern, Fig.47 , Fig.48A and Fig.48B The semiconductor device shown in FIG. Fig.44A and Fig.44B The semiconductor devices described are substantially the same, and therefore, redundant descriptions may be omitted.

[0222] Reference Fig.47 , Fig.48A and Fig.48B , the second contact structure 180 may contact the second portion P2 of the active pattern 110 .

[0223] In some embodiments, the second contact structure 180 may be precisely aligned with the upper surface of the second portion P2 of the active pattern 110. The bottom of the second contact structure 180 may contact the entire upper surface of the second portion P2 of the active pattern 110.

[0224] The bottom of the second contact structure 180 may contact the second portion P2 of the active pattern 110 and the insulating spacer 160 adjacent thereto.

[0225] In some embodiments, the second contact structure 180 may include a second silicon pattern 174a doped with impurities, a second metal silicide pattern 175, and a second contact plug 178 that are stacked. The stacked structure of the second contact structure 180 may be similar to that of the reference Figures 2 to 4 Same as those described.

[0226] A landing pad pattern 192 may be formed on the second contact structure 180. The landing pad pattern 192 may include a metal, for example, tungsten.

[0227] The landing pad pattern 192 may not be offset relative to the upper surface of the second contact structure 180, but may contact at least a portion of the upper surface of the second contact structure 180. A plurality of landing pad patterns 192 may be arranged in a honeycomb structure. The bottom of the landing pad pattern 192 may contact the upper surfaces of the second contact structure 180 and the second insulation pattern 166.

[0228] The third opening 191 may be formed between the landing pad patterns 192. A portion of the second contact structure 180 may be exposed by a lower sidewall of the third opening 191. A bottom of the third opening 191 may be lower than an uppermost surface of the second contact structure 180. That is, a portion of the second contact structure 180 exposed by the third opening 191 may have a concave shape.

[0229] An uppermost surface of the second contact structure 180 may be higher than an uppermost surface of the bit line structure 168 .

[0230] A third insulating pattern 194 may be formed in the third opening 191. The third insulating pattern 194 may include silicon nitride.

[0231] Upper surfaces of the landing pad pattern 192 and the third insulation pattern 194 may be coplanar with each other and may be substantially flat.

[0232] The etch stop layer 182 may be on the landing pad pattern 192 and the third insulating pattern 194. The capacitor 190 may pass through the etch stop layer 182 and may contact the landing pad pattern 192. The lower electrode 184 of the capacitor 190 may pass through the etch stop layer 182 and may contact the landing pad pattern 192. Therefore, the lower electrode 184 of the capacitor 190 may be electrically connected to the second portion P2 of the active pattern 110 via the landing pad pattern 192 and the second contact structure 180.

[0233] Fig.49A , Fig.49B , Fig.50A and Fig.50B is a cross-sectional view for illustrating an example of a method of manufacturing a semiconductor device.

[0234] Fig.49A and Fig.50A is along Fig.47 A cross-sectional view taken along line AA' in FIG. Fig.49B and Fig.50B It is a cross-sectional view along the line CC' and the line DD'.

[0235] The method of manufacturing a semiconductor device may be similar to that described with reference to FIG. 1 except for the process for forming the second contact plug and the landing pad pattern. Fig.45 The described methods of manufacturing semiconductor devices are basically the same.

[0236] Reference Fig.49A and Fig.49B , the reference can be performed in the same way Figures 6 to 14 Describe the process.

[0237] Thereafter, first and second buffer layers and an etching mask may be formed to cover the active pattern 110, the device isolation pattern 114, and the gate structure 130. The first and second buffer layers and an upper portion of the gate mask may be etched using the etching mask to form a second opening. The second opening may extend in the second direction while exposing the first portion P1 of the active pattern 110.

[0238] Then, you can execute the reference Figure 26 to Figure 35 Describe the process.

[0239] Thereafter, a first mold layer 170 may be formed on the second insulating pattern 166 , the second buffer layer pattern 152 a , and the insulating spacer 160 .

[0240] A portion of the first mold layer 170 may be etched, and the first and second buffer layer patterns 150a and 152a under the first mold layer 170, an upper portion of the second portion P2 of the active pattern 110, and the insulating spacer 160 may be etched to form a second contact hole. The second portion P2 of the active pattern 110 and the insulating spacer 160 adjacent thereto may be exposed through the bottom of the second contact hole. Fig.39 The second contact hole 172 may be aligned with respect to the second portion P2 of the active pattern 110. For example, the second contact hole 172 overlaps the second portion P2 of the active pattern 110 in a plan view.

[0241] An inner spacer 176 may be formed on the sidewall of the second contact hole. A second silicon pattern 174a, a second metal silicide pattern 175, and a second contact plug 178 may be formed on the second portion P2 of the active pattern 110 in the second contact hole. Upper surfaces of the second contact plug 178 and the first mold layer 170 may be coplanar with each other and may be substantially flat.

[0242] Reference Fig.50A and 50B , a third conductive layer may be formed on the second contact plug 178 and the first mold layer 170. The third conductive layer may include a metal, for example, tungsten.

[0243] The third conductive layer, the second contact plug 178 under the third conductive layer, the inner spacer 176, and the first mold layer 170 may be etched to form a landing pad pattern 192 and a third opening 191. The landing pad pattern 192 may be formed by etching the third conductive layer, and may contact a portion of an upper surface of the second contact plug 178. The third opening 191 may be formed between the landing pad patterns 192.

[0244] The bottom of the third opening 191 may be lower than the uppermost surface of the second contact plug 178 .

[0245] In some embodiments, the plurality of landing pad patterns 192 may be arranged in a honeycomb structure.

[0246] Thereafter, a third insulation pattern 194 may be formed to fill the third opening 191 .

[0247] Subsequently, an etch stop layer 182 may be formed on the landing pad pattern 192 and the third insulating pattern 194. The capacitor 190 may be formed through the etch stop layer 182 and may be electrically connected to the upper surface of the landing pad pattern 192. Thus, the Fig.47 , Fig.48A and Fig.48B The semiconductor device shown in .

[0248] Since the semiconductor device further includes the landing pad pattern, a process margin (eg, alignment margin) for forming a capacitor may be increased.

[0249] Fig.51 , Fig.52 and Fig.53 are a plan view and a cross-sectional view for illustrating an example of a semiconductor device.

[0250] Fig.51 Only some components of the semiconductor device are shown. Fig.52 Including along Fig.51 A cross-sectional view taken along lines AA' and BB'. Fig.53 Including along Fig.51 A cross-sectional view taken along lines CC' and D-D'.

[0251] Figure 51 to Figure 53 The semiconductor device shown is similar to the Figures 2 to 4 The semiconductor device described is substantially the same except that the semiconductor device may not include the second contact structure. Therefore, redundant description may be omitted.

[0252] Reference Figure 51 to Figure 53 The etch stop layer 182 may cover upper surfaces of the insulating spacer 160 , the second buffer layer pattern 152 a , and the second insulating pattern 166 .

[0253] A lower electrode 184 of the capacitor 190 may pass through the etch stop layer 182 and may contact the first contact plug 146 .

[0254] In some embodiments, the first contact plug 146 may include a metal silicide pattern 146 a and a metal pattern 146 b .

[0255] The lower electrode 184 may contact a portion of an upper surface of the first contact plug 146. The lower electrode 184 may be electrically connected to the second portion P2 of the active pattern 110 via the first contact plug 146.

[0256] The center of the bottom of the lower electrode 184 may not be aligned with the center of the upper surface of the first contact plug 146. The center of the bottom of the lower electrode 184 and the center of the upper surface of the first contact plug 146 may not be aligned with each other. The lower electrode 184 may contact a portion of the upper surface of the first contact plug 146.

[0257] In some embodiments, the bottom of the lower electrode 184 may contact the first contact plug 146, the first and second buffer layer patterns 150a and 152a, the insulating spacer 160 adjacent thereto, and the second insulating pattern 166. The bottom of the lower electrode 184 may be lower than the uppermost surface of the first contact plug 146.

[0258] The plurality of lower electrodes 184 may be arranged in a honeycomb structure. A dielectric layer 186 and an upper electrode 188 may be on the lower electrodes 184. Therefore, the capacitor 190 may directly contact the first contact plug 146.

[0259] Hereinafter, a method of manufacturing a semiconductor device may be briefly described.

[0260] First, the executable reference Figure 6 to Figure 32 The process described above may be repeated, and an etch stop layer may then be formed to cover upper surfaces of the insulating spacers 160, the second buffer layer pattern 152a, and the second insulating pattern 166. The capacitor 190 may be formed on the first contact plug 146 through the etch stop layer 181.

[0261] The semiconductor device may not include the second contact structure and the landing pad pattern. Therefore, the semiconductor device may be manufactured through the process.

[0262] Fig.54 and Fig.55 is a cross-sectional view for illustrating an example of a semiconductor device.

[0263] Fig.54 Including along Figure 1 A cross-sectional view taken along lines AA' and BB'. Fig.55 Including along Figure 2 A cross-sectional view taken along lines CC' and D-D'.

[0264] Fig.54 and Fig.55 The semiconductor device shown in FIG. Figures 2 to 4 Those described are similar, except that the semiconductor device may not include the second contact structure and the first and second buffer layer patterns, and may further include a landing pad pattern. Therefore, redundant descriptions may be omitted.

[0265] Reference Fig.54 and Fig.55 , a landing pad pattern 192 contacting the first contact plug 146 may be on upper surfaces of the insulating spacer 160 , the first contact plug 146 , and the second insulating pattern 166 .

[0266] The first buffer layer pattern and the second buffer layer pattern may not be on the first contact plug 146. In some embodiments, the first contact plug 146 may include a metal silicide pattern 146a and a metal pattern 146b.

[0267] The landing pad pattern 192 may not be precisely aligned with the upper surface of the first contact plug 146, but may contact a portion of the upper surface of the first contact plug 146. A plurality of landing pad patterns 192 may be arranged in a honeycomb structure. The bottom of the landing pad pattern 192 may contact the upper surfaces of the first contact plug 146, the insulating spacer 160, and the second insulating pattern 166.

[0268] The third opening 191 may be formed between the landing pad patterns 192, and the first contact plug 146 may be exposed through a lower portion of the third opening 191. The bottom of the third opening 191 may be lower than the uppermost surface of the first contact plug 146. That is, the upper surface of the first contact plug 146 exposed by the third opening 191 may have a concave shape.

[0269] The third insulating pattern 194 may be in the third opening 191. The third insulating pattern 194 may include silicon nitride.

[0270] Upper surfaces of the landing pad pattern 192 and the third insulation pattern 194 may be coplanar with each other and may be substantially flat.

[0271] The etch stop layer 182 may be on the landing pad pattern 192 and the third insulating pattern 194. The capacitor 190 may pass through the etch stop layer 182, and may contact an upper surface of the landing pad pattern 192.

[0272] Hereinafter, a method of manufacturing a semiconductor device may be briefly described.

[0273] First, the executable reference Figure 6 to Figure 32 However, when executing the Figure 30 to Figure 32During the process described, the first and second buffer layer patterns 150a and 152a may be completely removed by the planarization process. Therefore, after the planarization process, upper surfaces of the second insulating pattern 166, the insulating spacer 160, the first contact plug 146, and the first insulating pattern 144 may be exposed.

[0274] Thereafter, a third conductive layer may be formed on the second insulating pattern 166 , the insulating spacer 160 , the first contact plug 146 , and the first insulating pattern 144 .

[0275] The third conductive layer, the first contact plugs 146 thereunder, the insulating spacers 160, and the second insulating patterns 166 may be etched to form landing pad patterns 192 contacting upper surfaces of the first contact plugs 146. Third openings 191 may be formed between the landing pad patterns 192.

[0276] The bottom of the third opening 191 may be lower than the uppermost surface of the first contact plug 146 .

[0277] Thereafter, a third insulation pattern 194 may be formed to fill the third opening 191 .

[0278] Subsequently, an etch stop layer 182 may be formed on the landing pad pattern 192 and the third insulating pattern 194. The capacitor 190 may be formed through the etch stop layer 182, and the capacitor 190 may be electrically connected to the upper surface of the landing pad pattern 192. Thus, a Fig.54 and Fig.55 The semiconductor device shown. Although the present disclosure contains many specific implementation details, these should not be construed as limitations on the scope of what may be claimed. Certain features described in the present disclosure in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented in multiple implementations individually or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations and even initially claimed as such, one or more features from a combination may be removed from the combination in some cases, and the combination may be directed to sub-combinations or variations of sub-combinations.

[0279] The above is an explanation of various examples and should not be interpreted as limiting them. Although some example embodiments have been described, it will be readily understood by those skilled in the art that many modifications may be made in the example embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all of these modifications are intended to be included within the scope defined by the claims. In the claims, the device-plus-function statement is intended to cover the structure that performs the function described herein, and not only covers structural equivalents but also covers equivalent structures. Therefore, it should be understood that the foregoing is an explanation of various example embodiments and should not be interpreted as being limited to the specific example embodiments disclosed, and modifications to the disclosed example embodiments and other example embodiments are intended to be included within the scope of the appended claims. In addition, the example embodiments do not have to be mutually exclusive. For example, some example embodiments may include one or more features described with reference to one or more figures, and may also include one or more other features described with reference to one or more other figures.

Claims

1. A semiconductor device comprising: Active array, wherein a plurality of active patterns are arranged on a substrate; a gate structure extending in a first direction parallel to an upper surface of the substrate and intersecting central portions of the plurality of active patterns; a bit line structure contacting a first portion of the plurality of active patterns adjacent to a first sidewall of the gate structure, the bit line structure extending in a second direction parallel to an upper surface of the substrate and perpendicular to the first direction; and a capacitor electrically connected to a second portion of each of the plurality of active patterns adjacent to the second sidewall of the gate structure, wherein, in a plan view, an upper end portion of each of the plurality of active patterns and a lower end portion of the plurality of active patterns are arranged to be spaced apart in a third direction intersecting the first direction at an oblique angle, and Wherein, active patterns arranged side by side in the second direction define active columns.

2. The semiconductor device according to claim 1, wherein: In a plan view, the sidewall of each of the multiple active patterns has one of a straight line shape extending in the third direction, a curved shape extending in the third direction, and a shape having an upper portion and a lower portion extending in the second direction and a middle portion between the upper portion and the lower portion and extending in the first direction.

3. The semiconductor device according to claim 1, wherein: The third direction corresponds to a direction along which each of the plurality of active patterns extends.

4. The semiconductor device according to claim 1, wherein: In a plan view, a plurality of active patterns arranged side by side in the first direction define an active row, Wherein, at least a portion of the plurality of active patterns included in the even-numbered active rows is disposed between adjacent active patterns included in the odd-numbered active rows.

5. The semiconductor device according to claim 1, wherein: The gate structure is located in a first recess on the plurality of active patterns.

6. The semiconductor device according to claim 1, wherein: An upper surface of the first portion of the plurality of active patterns is lower than an upper surface of the second portion of the plurality of active patterns.

7. The semiconductor device according to claim 1, wherein: An insulating spacer extends in the second direction and is defined between sidewalls of the second portions of the plurality of active patterns and sidewalls of the bit line structure.

8. The semiconductor device according to claim 1, wherein: The bit line structure includes a bit line pattern and a first insulating pattern, the bit line pattern including a conductive material.

9. The semiconductor device according to claim 1, further comprising: a first contact plug having an isolated shape and contacting an upper surface of the second portion of each of the plurality of active patterns; as well as a second contact structure that contacts at least a portion of an upper surface of the first contact plug, and Wherein, the capacitor contacts the second contact structure.

10. The semiconductor device according to claim 9, wherein: The plurality of second contact structures are arranged in a honeycomb structure provided at each vertex of the connected hexagons and at the center of each of the hexagons.

11. The semiconductor device according to claim 9, wherein: An uppermost surface of the first contact plug is lower than an uppermost surface of the bit line structure.

12. The semiconductor device according to claim 9, further comprising a second insulating pattern located between the first contact plugs in the second direction, and in, The first contact plug and the second insulation pattern are aligned with the second direction.

13. The semiconductor device according to claim 1, further comprising: a contact plug contacting an upper surface of the second portion of the plurality of active patterns, an upper portion of the contact plug including a recessed portion; a landing pad pattern contacting at least a portion of an upper surface of the contact plug; as well as A third insulating pattern fills the openings between the plurality of landing pad patterns and contacts the recessed portion.

14. The semiconductor device of claim 1 , further comprising a first contact plug having an isolated shape and contacting an upper surface of the second portion of each of the plurality of active patterns, and in, The capacitor contacts at least a portion of an upper surface of the first contact plug.

15. A semiconductor device comprising: Active array, wherein a plurality of active patterns are arranged on a substrate; a gate structure extending in a first direction parallel to an upper surface of the substrate and intersecting a central portion of the plurality of active patterns, wherein each of the plurality of active patterns is divided into a first portion and a second portion by the gate structure; a bit line structure, i) which contacts the first portion of the plurality of active patterns, ii) which extends in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction, and iii) which includes a bit line pattern, the bit line pattern including a conductive material stacked on a first insulating pattern; and capacitors electrically connected to the second portions of the plurality of active patterns, respectively, wherein, in a plan view, an upper end portion of each of the plurality of active patterns and a lower end portion of each of the plurality of active patterns are arranged to be spaced apart in a third direction intersecting the first direction at an oblique angle, and Wherein, an upper surface of the first portion of each of the plurality of active patterns is lower than an upper surface of the second portion of the plurality of active patterns.

16. The semiconductor device according to claim 15, wherein: The active patterns arranged side by side in the second direction define active columns, and the active patterns arranged side by side in the first direction define active rows, and The first portion of the active pattern included in the active column is arranged along the second direction, and the central portion of the active pattern included in the active row is arranged along the first direction.

17. The semiconductor device according to claim 15, wherein: In a plan view, a plurality of active columns are repeatedly arranged in the first direction.

18. The semiconductor device of claim 15 , wherein, in a plan view, the sidewall of each of the plurality of active patterns has one of a straight line shape extending in the third direction, a curved shape extending in the third direction, and a shape having an upper portion and a lower portion extending in the second direction and a middle portion between the upper portion and the lower portion and extending in the first direction.

19. The semiconductor device according to claim 15, further comprising: a first contact plug having an isolated shape and contacting an upper surface of the second portion of each of the plurality of active patterns; as well as A second contact structure contacts at least a portion of an upper surface of the first contact plug, wherein the capacitor contacts the second contact structure.

20. A semiconductor device comprising: Active array, wherein a plurality of active patterns are arranged on a substrate; a gate structure extending in a first direction parallel to an upper surface of the substrate and intersecting a central portion of the plurality of active patterns, wherein each of the plurality of active patterns is divided into a first portion and a second portion by the gate structure; a bit line structure, i) which contacts the first portion of the plurality of active patterns, ii) which extends in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction, and iii) which includes a stacked bit line pattern having a conductive material and a first insulating pattern; and an insulating spacer disposed between sidewalls of the second portion of the plurality of active patterns and sidewalls of the bit line structure and extending in the second direction; first contact plugs respectively contacting upper surfaces of the second portions of the plurality of active patterns, each of the first contact plugs having an isolated shape; a second insulating pattern between the first contact plugs in the second direction; and A capacitor is electrically connected to each of the first contact plugs.

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