Semiconductor device with peripheral contact plug

Abstract

An example semiconductor device includes a substrate including a cell array region and a connection region; a peripheral circuit layer; a bit line disposed on the peripheral circuit layer in the cell array region; a first upper interconnect portion disposed in the connection region, at the same height with respect to the substrate as the bit line; at least one lower interconnect layer disposed between the peripheral circuit layer and the bit line and between the peripheral circuit layer and the first upper interconnect portion; a bit line insulating layer surrounding the bit line in the cell array region and the first upper interconnection portion in the connection region; an upper structure disposed on the bit line and the first upper interconnect portion; an information storage structure disposed on the upper structure in the cell array region; and a lower contact plug electrically connected to the at least one lower interconnect layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0087018 filed on July 5, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor device having a peripheral contact plug. Background Art

[0004] As the demand for high performance, high speed and / or multifunctionality of semiconductor devices increases, the integration of semiconductor devices has increased. When manufacturing semiconductor devices with fine patterns corresponding to the high integration trend of semiconductor devices, it is necessary to realize patterns with fine width or fine distance. Summary of the invention

[0005] The present disclosure relates to a semiconductor device including a semiconductor device having a lower interconnection layer and an upper interconnection layer arranged on a peripheral circuit layer, and a lower contact plug connected to the lower interconnection layer.

[0006] In general, according to some aspects, a semiconductor device includes: a substrate including a cell array region and a connection region; a peripheral circuit layer disposed on the substrate and including circuit elements; a bit line disposed on the peripheral circuit layer in the cell array region; a first upper interconnection portion disposed at the same level as the bit line in the connection region; at least one lower interconnection layer disposed between the peripheral circuit layer and the bit line and between the peripheral circuit layer and the first upper interconnection portion; a bit line insulating layer surrounding the bit line in the cell array region and surrounding the first upper interconnection portion in the connection region; an upper structure disposed on the bit line and the first upper interconnection portion and including an upper insulating structure; an information storage structure disposed on the upper structure in the cell array region;

[0007] and a lower contact plug electrically connected to at least one lower interconnection layer through the bit line insulating layer in the connection region.

[0008] Generally speaking, according to some other aspects, a semiconductor device includes: a substrate including a cell array area and a connection area; a peripheral circuit layer, which is arranged on the substrate and includes circuit elements; a bit line, which is arranged on the peripheral circuit layer in the cell array area; a first upper interconnection portion, which is arranged at the same horizontal height as the bit line in the connection area; a lower interconnection layer, which is arranged between the peripheral circuit layer and the bit line and between the peripheral circuit layer and the first upper interconnection portion, the lower interconnection layer including a lower interconnection portion; a bit line insulation layer, which surrounds the bit line in the cell array area and surrounds the first upper interconnection portion in the connection area; an upper structure, which is arranged on the bit line and the first upper interconnection portion and includes an upper insulation structure; an information storage structure, which is arranged on the upper structure in the cell array area; an upper interlayer insulation layer, which covers the information storage structure in the cell array area and covers the upper insulation structure in the connection area; a lower contact plug, which extends in a vertical direction from an upper surface of the upper interlayer insulation layer in the connection area, passes through the bit line insulation layer, and contacts the lower interconnection portion; and a first upper contact plug, which extends in a vertical direction from an upper surface of the upper interlayer insulation layer and contacts the first upper interconnection portion.

[0009] In general, according to some other aspects, a semiconductor device includes: a substrate including a cell array region and a connection region; a peripheral circuit layer disposed on the substrate and including circuit elements; a first lower interconnect layer disposed on the peripheral circuit layer and including a first lower interconnect portion; a second lower interconnect layer disposed on the first lower interconnect layer and including a second lower interconnect portion; a bit line disposed on the second lower interconnect layer in the cell array region; a first upper interconnect portion disposed at the same level as the bit line in the connection region; a bit line insulating layer surrounding the bit line in the cell array region and surrounding the connection region; a first upper interconnection portion in the connection area; an upper structure, which is arranged on the bit line and the first upper interconnection portion and includes a landing pad and an upper insulating structure surrounding the landing pad; a second upper interconnection portion, which is arranged at the same level as the landing pad in the connection area; an information storage structure, which is arranged on the upper structure in the cell array area; an upper interlayer insulating layer, which covers the information storage structure in the cell array area and covers the upper insulating structure in the connection area; and a first lower contact plug, which passes through the upper interlayer insulating layer, the upper insulating structure and the bit line insulating layer and contacts the first lower interconnection portion in the connection area. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0011] Figure 1 is a plan view of a semiconductor device according to example embodiments.

[0012] Figure 2A yes Figure 1An example vertical cross-sectional view of a semiconductor device is shown taken along line II'.

[0013] Figure 2B yes Figure 1 An example vertical cross-sectional view of a semiconductor device is shown taken along line II-II'.

[0014] Figure 3 yes Figure 2A An example enlarged view of a portion of a semiconductor device is shown.

[0015] Figure 4A and Figure 4B is a vertical cross-sectional view of a semiconductor device according to example embodiments.

[0016] Figure 5A and Figure 5B is a vertical cross-sectional view of a semiconductor device according to example embodiments.

[0017] Figure 6 yes Figure 5A An example enlarged view of a portion of a semiconductor device is shown.

[0018] Fig. 7A and Figure 7B is a vertical cross-sectional view of a semiconductor device according to example embodiments.

[0019] Figure 8 yes Fig. 7A An example enlarged view of a portion of a semiconductor device is shown.

[0020] Fig. 9 is a vertical cross-sectional view of a semiconductor device according to example embodiments.

[0021] FIG. 10A to FIG. 15B are vertical cross-sectional views illustrating a series of processes of a method of manufacturing a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0022] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0023] Figure 1 is a plan view of a semiconductor device according to example embodiments. Figure 2A yes Figure 1 The semiconductor device shown is a vertical cross-sectional view taken along line II'. Figure 2B yes Figure 1 The semiconductor device shown is a vertical cross-sectional view taken along line II-II'.

[0024] Reference Figures 1 to 2B, a semiconductor device 1 according to example embodiments includes a lower structure LS, a bit line 50 , an upper structure US, an information storage structure 87 , an upper interlayer insulating layer 90 , a cell contact plug CPC, and a peripheral contact plug CPP.

[0025] The lower structure LS may include a peripheral circuit layer PS, a first lower interconnect layer LL1, and a second lower interconnect layer LL2. The peripheral circuit layer PS may include a circuit element TR disposed on a substrate 3. The circuit element TR may include a word line driver, a sense amplifier, a row decoder, a column decoder, and a control circuit. The substrate 3 may include a cell array area MCA and a connection area EA.

[0026] The substrate 3 may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the Group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate 3 may include a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial layer.

[0027] The circuit element TR may be disposed in the cell array area MCA and the connection area EA. The circuit element TR may include a peripheral transistor. For example, the peripheral transistor may include a gate structure 12 disposed on a peripheral active area 9a defined by a device isolation area 9b in the substrate 3 and a peripheral source / drain area 15 disposed in the peripheral active area 9a disposed on both sides of the gate structure 12.

[0028] The gate structure 12 may include a peripheral gate electrode 12b and a peripheral gate dielectric layer 12a between the peripheral gate electrode 12b and the peripheral active region 9a. The peripheral gate electrode 12b may include at least two conductive layers, for example, a first conductive layer 12b1 and a second conductive layer 12b2 on the first conductive layer 12b1.

[0029] The peripheral circuit layer PS may further include a peripheral plug 18, a peripheral interconnection 21, a first peripheral insulating layer 24, and a second peripheral insulating layer 27. The peripheral plug 18 may be connected to the peripheral source / drain region 15 and may extend vertically, and the peripheral interconnection 21 may be disposed on the peripheral plug 18. The peripheral interconnection 21 may be electrically connected to the circuit element TR through the peripheral plug 18. The first peripheral insulating layer 24 may surround the side surface of the peripheral gate electrode 12b and the side surface of the peripheral plug 18. The second peripheral insulating layer 27 may be disposed on the first peripheral insulating layer 24 and may surround the peripheral plug 18 and the peripheral interconnection 21. The upper surface of the second peripheral insulating layer 27 may be coplanar with the upper surface of the peripheral interconnection 21.

[0030] The first lower interconnection layer LL1 may be disposed on the peripheral circuit layer PS. In the cell array area MCA, the first lower interconnection layer LL1 may include a first lower interconnection portion 30 and a first lower plug 33. The first lower plug 33 may extend vertically and be connected to the corresponding peripheral interconnection portion 21. The first lower interconnection portion 30 may extend in the horizontal direction, and at least one of the first lower interconnection portions 30 may be electrically connected to the corresponding circuit element TR through the corresponding first lower plug 33. In the connection area EA, the first lower interconnection layer LL1 may include a first lower interconnection portion 30p and a first lower plug 33p. The first lower plug 33p may be connected to the corresponding peripheral interconnection portion 21, and the first lower interconnection portion 30p may be electrically connected to the corresponding circuit element TR through the first lower plug 33p. The first lower interconnection layer LL1 may include a first lower insulating layer 36 surrounding the first lower interconnections 30 and 30p and the first lower plugs 33 and 33p. The first lower insulating layer 36 may include silicon oxide, silicon nitride, silicon oxynitride, a low-κ dielectric, or a combination thereof.

[0031] The second lower interconnection layer LL2 may be disposed on the first lower interconnection layer LL1. In the cell array area MCA, the second lower interconnection layer LL2 may include a second lower interconnection portion 40 and a second lower plug 43. In the connection area EA, the second lower interconnection layer LL2 may include a second lower interconnection portion 40p and a second lower plug 43p. The second lower interconnection layer LL2 may include a second lower insulating layer 46 surrounding the second lower interconnections 40 and 40p and the second lower plugs 43 and 43p. The second lower interconnection layer LL2 may have a structure that is the same as or similar to that of the first lower interconnection layer LL1. The second lower interconnection layer LL2 may be electrically connected to the peripheral circuit layer PS through the first lower interconnection layer LL1. At least one of the first lower interconnections 30p may be electrically connected to at least one of the second lower interconnections 40p through the corresponding second lower plug 43p.

[0032] In some embodiments, the first lower interconnection 30p, the first lower plug 33p, the second lower interconnection 40p, and the second lower plug 43p may include a metal layer and a barrier layer covering the side surface and the lower surface of the metal layer. The barrier layer may include at least one of TiN, TaN, WN, TiSiN, TaSiN, and RuTiN, and the metal layer may include a metal material such as W or Mo.

[0033] The bit line 50 may be disposed on the second lower interconnect layer LL2 in the cell array area MCA. The bit line 50 may extend in the first horizontal direction X and may be spaced apart from each other in the second horizontal direction Y. The first horizontal direction X and the second horizontal direction Y may be perpendicular to each other. The semiconductor device 1 may further include a cell connection plug 53 disposed below the bit line 50 and a bit line insulating layer 56 surrounding the bit line 50 and the cell connection plug 53. The bit line 50 may be electrically connected to the second lower interconnect layer LL2 through the cell connection plug 53. The bit line 50 may include doped polysilicon, metal, conductive metal nitride, metal-semiconductor compound, metal compound, conductive metal oxide, graphene, carbon nanotube, or a combination thereof.

[0034] Although not shown, the semiconductor device 1 in the cell array area MCA may further include shielding patterns extending in the first horizontal direction X and spaced apart from each other in the second horizontal direction Y. The shielding patterns may be alternately arranged with the bit lines 50 in the second horizontal direction Y. The shielding patterns may reduce capacitance between the bit lines 50.

[0035] The semiconductor device 1 may further include a first upper interconnection portion 50p and a first peripheral plug 53p disposed in the connection area EA. The first upper interconnection portion 50p may be electrically connected to the second lower interconnection layer LL2 through the first peripheral plug 53p. The bit line insulating layer 56 may extend into the connection area EA to surround the first upper interconnection portion 50p and the first peripheral plug 53p. The first upper interconnection portion 50p may be disposed at the same level as the level of the bit line 50, and the first peripheral plug 53p may be disposed at the same level as the level of the cell connection plug 53. The first upper interconnection portion 50p may include the same material as the bit line 50, and the first peripheral plug 53p may include the same material as the cell connection plug 53. The bit line insulating layer 56 may include silicon oxide, silicon nitride, silicon oxynitride, a low-κ dielectric, or a combination thereof.

[0036] In some embodiments, the bit line 50, the cell connection plug 53, the first upper interconnection portion 50p, and the first peripheral plug 53p may include a metal layer and a barrier layer covering the side surface and the lower surface of the metal layer. The barrier layer may include at least one of TiN, TaN, WN, TiSiN, TaSiN, and RuTiN, and the metal layer may include a metal material such as W or Mo.

[0037] The upper structure US may be disposed on the bit line 50 in the cell array area MCA. The upper structure US may include a channel structure 73, a word line 79, an upper insulating structure 84, a second upper interconnection portion 81p, and a second peripheral plug 83p.

[0038] The channel structure 73 may include a horizontal portion 73L contacting and electrically connected to the bit line 50 and first and second vertical channel portions 73S1 and 73S2 extending from both sides of the horizontal portion 73L in the first horizontal direction X in the vertical direction Z. The vertical direction Z may be a direction perpendicular to the upper surface of the substrate 3 .

[0039] The channel structure 73 may be formed of a semiconductor material such as silicon. The channel structure 73 may be formed of single crystal silicon or polycrystalline silicon. However, the channel structure 73 is not limited to semiconductor materials such as silicon, but may be formed of other semiconductor materials that may be used as a channel region of a transistor. For example, the channel structure 73 may include an oxide semiconductor layer or a two-dimensional material layer that may be used as a channel region of a transistor.

[0040] The oxide semiconductor layer may be indium gallium zinc oxide (IGZO). However, example embodiments are not limited thereto. For example, the oxide semiconductor layer may include indium tungsten oxide (IWO), indium tin gallium oxide (ITGO), indium aluminum zinc oxide (IAGO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), ZnO, indium gallium silicon oxide (IGSO), indium oxide (InO), tin oxide (SnO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), indium zinc oxide (InZnO), indium gallium At least one of zinc oxide (InGaZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), zinc tin oxide (ZnSnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and indium gallium silicon oxide (InGaSiO).

[0041] The two-dimensional material layer may include at least one of a transition metal dichalcogenide (TMD) material layer, a black phosphorus material layer, and a hexagonal boron nitride (hBN) material layer that may have semiconductor properties. For example, the two-dimensional material layer may include BiOSe, Cr1, WSe, etc. that may form a two-dimensional material. 2 、MoS 2 , TaS, WS, SnSe, ReS, β-SnTe, MnO, AsS, P (black), InSe, h-BN, GaSe, GaN, SrTiO, Mxene and Janus 2D materials.

[0042] Each of the word lines 79 may extend in the second horizontal direction Y. A pair of word lines 79a and 79b of the word lines 79 may vertically overlap the horizontal portion 73L of the channel structure 73 and may be disposed between the first vertical channel portion 73S1 and the second vertical channel portion 73S2 of the channel structure 73. The pair of word lines 79a and 79b may include a first word line 79a facing the first vertical channel portion 73S1 and a second word line 79b facing the second vertical channel portion 73S2.

[0043] The upper structure US may further include a dielectric structure 76 between the word line 79 and the channel structure 73. The dielectric structure 76 may include a first dielectric structure 76a that may be disposed between the first word line 79a and the first vertical channel portion 73S1 and between the first word line 79a and the horizontal portion 73L, and a second dielectric structure 76b that may be disposed between the second word line 79b and the second vertical channel portion 73S2 and between the second word line 79b and the horizontal portion 73L.

[0044] In an example, each of the dielectric structures 76 may be a tunnel dielectric layer that does not include an information storage layer. For example, each of the dielectric structures 76 may include at least one of silicon oxide and a high-κ dielectric. The high-κ dielectric may include a metal oxide or a metal oxynitride. For example, the high-κ dielectric may be composed of HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO 2 、Al 2 O 3 Each of the dielectric structures 76 may be formed of a single layer or multiple layers of the above materials.

[0045] In another example, each of the dielectric structures 76 may include an information storage layer and a dielectric layer. For example, each of the dielectric structures 76 may include a ferroelectric layer that may have polarization characteristics according to an electric field and may have a dipole-induced residual polarization even in the absence of an external electric field. The polarization state in the ferroelectric layer may be used to record data. Therefore, each of the dielectric structures 76 may include a ferroelectric layer that may be referred to as an information storage layer. The ferroelectric layer that may be an information storage layer may include an Hf-based compound, a Zr-based compound, and / or an Hf-Zr-based compound. For example, the Hf-based compound may be a HfO-based ferroelectric material, the Zr-based compound may include a ZrO-based ferroelectric material, and the Hf-Zr-based compound may include a hafnium zirconium oxide (HZO)-based ferroelectric material. The ferroelectric layer that may be an information storage layer may include a ferroelectric material doped with impurities (e.g., at least one of C, Si, Mg, Al, Y, N, Ge, Sn, Gd, La, Sc, and Sr). For example, the ferroelectric layer that may be the information storage layer may be HfO doped with at least one of impurities C, Si, Mg, Al, Y, N, Ge, Sn, Gd, La, Sc, and Sr. 2 、ZrO 2 and HzrO to form a material of at least one.

[0046] In the dielectric structure 76 , the information storage layer is not limited to the above-mentioned types of materials, and may include a material capable of storing information.

[0047] The upper structure US may further include a landing pad 81 electrically connected to and contacting the first vertical channel portion 73S1 and the second vertical channel portion 73S2 on the channel structure 73. The landing pad 81 may be formed of a conductive material.

[0048] The upper insulating structure 84 may be disposed on the bit line 50 in the cell array area MCA. The upper insulating structure 84 may be disposed on the first upper interconnection portion 50p and the bit line insulating layer 56 in the connection area EA. The upper insulating structure 84 may cover the side surface of the structure including the channel structure 73, the word line 79, and the landing pad 81.

[0049] The second upper interconnect portion 81p may be disposed at the same level as that of the landing pad 81 in the cell array area MCA. For example, the upper surface of the second upper interconnect portion 81p may be located at the same level as that of the upper surface of the landing pad 81. The second peripheral plug 83p may extend in the vertical direction Z and may connect one of the second upper interconnect portions 81p to one of the first upper interconnect portions 50p. The second upper interconnect portion 81p may include the same material as that of the landing pad 81. The upper insulating structure 84 may surround the side surfaces of the second upper interconnect portion 81p and the second peripheral plug 83p in the connection area EA. The upper insulating structure 84 may include silicon oxide, silicon nitride, silicon oxynitride, a low-κ dielectric, or a combination thereof. For example, the upper insulating structure 84 may include silicon oxide.

[0050] The information storage structure 87 may be disposed on the upper structure US in the cell array area MCA. The information storage structure 87 may include a first electrode 88a electrically connected to and contacting the landing pad 81, a second electrode 88c on the first electrode 88a, and a dielectric layer 88b between the first electrode 88a and the second electrode 88c.

[0051] In an example, the information storage structure 87 may be a capacitor storing information in a DRAM. For example, the dielectric layer 88b of the information storage structure 87 may be a capacitor dielectric layer of the DRAM, and the dielectric layer 87b may include a high-κ dielectric layer, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0052] In another example, the information storage structure 87 may be a structure for storing information of a memory different from a DRAM. For example, the information storage structure 87 may be a capacitor of a ferroelectric memory (FeRAM). For example, the dielectric layer 88b may be a ferroelectric layer capable of recording data using a polarization state. In another example, the dielectric layer 88b may include a lower dielectric layer and a ferroelectric layer on the lower dielectric layer. Here, the lower dielectric layer may include at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-κ dielectric.

[0053] In some embodiments, when dielectric structure 76 includes an information storage layer, information storage structure 87 may be omitted.

[0054] The upper interlayer insulating layer 90 may cover the information storage structure 87 in the cell array area MCA and may cover the second upper interconnection portion 81p in the connection area EA. The upper interlayer insulating layer 90 may include silicon oxide, silicon nitride, silicon oxynitride, a low-κ dielectric, or a combination thereof. For example, the upper interlayer insulating layer 90 may include silicon oxide.

[0055] Figure 3 yes Figure 2A An example enlarged view of a portion of a semiconductor device is shown.

[0056] Reference Figure 2A , Figure 2B and Figure 3 , the cell contact plug CPC extends in the vertical direction (Z) in the cell array area (MCA) to pass through the upper interlayer insulating layer 90 and contact the information storage structure 87. For example, the cell contact plug CPC contacts the second electrode 88c.

[0057] The peripheral contact plug CPP is disposed in the connection area EA. In some embodiments, the peripheral contact plug CPP includes a first lower contact plug CPL1, a second lower contact plug CPL2, a first upper contact plug CPU1, and a second upper contact plug CPU2.

[0058] The first lower contact plug CPL1 may be connected to the first lower interconnection portion 30p. For example, the first lower contact plug CPL1 may extend in the vertical direction Z and pass through the upper interlayer insulating layer 90, the bit line insulating layer 56, and the second lower insulating layer 46, and may contact the first lower interconnection portion 30p. The first lower contact plug CPL1 may be electrically connected to at least one of the first lower interconnection portions 30p.

[0059] The second lower contact plug CPL2 may be connected to the second lower interconnection portion 40p. For example, the second lower contact plug CPL2 may extend in the vertical direction Z to pass through the upper interlayer insulating layer 90 and the bit line insulating layer 56, and may contact the second lower interconnection portion 40p. The second lower contact plug CPL2 may be electrically connected to at least one of the second lower interconnections 40p. The height of each of the first lower contact plug CPL1 and the second lower contact plug CPL2 may be greater than the sum of the height of the upper structure US and the height of the information storage structure 87.

[0060] The first upper contact plug CPU1 may be connected to the first upper interconnection portion 50p. For example, the first upper contact plug CPU1 may extend in the vertical direction Z to pass through the upper interlayer insulating layer 90 and the bit line insulating layer 56, and may contact the first upper interconnection portion 50p. The first upper contact plug CPU1 may be electrically connected to at least one of the first upper interconnection portions 50p. The height of the first upper contact plug CPU1 may be higher than the height of the upper structure US.

[0061] The second upper contact plug CPU2 may be connected to the second upper interconnection portion 81p. For example, the second upper contact plug CPU2 may extend in the vertical direction Z to pass through the upper interlayer insulating layer 90 and contact the second upper interconnection portion 81p. The second upper contact plug CPU2 may be electrically connected to at least one of the second upper interconnection portions 81p.

[0062] In some embodiments, the cell contact plug CPC and the peripheral contact plug CPP are formed simultaneously and may include the same material as each other. For example, the cell contact plug CPC, the first lower contact plug CPL1, the second lower contact plug CPL2, the first upper contact plug CPU1, and the second upper contact plug CPU2 may each include a metal layer 93 and a barrier layer 96 covering the lower surface and the side surface of the metal layer 93. The metal layer 93 may include a conductive material such as tungsten, and the barrier layer 96 may include a conductive material such as TiN.

[0063] The upper surfaces of the cell contact plug CPC, the first lower contact plug CPL1, the second lower contact plug CPL2, the first upper contact plug CPU1, and the second upper contact plug CPU2 may be coplanar with the upper interlayer insulating layer 90. The first lower contact plug CPL1, the second lower contact plug CPL2, the first upper contact plug CPU1, and the second upper contact plug CPU2 may each extend from the upper surface of the upper interlayer insulating layer 90 in the vertical direction Z, the first lower contact plug CPL1 may have a maximum height, and the second upper contact plug CPU2 may have a minimum height. The cell contact plug CPC, the first lower contact plug CPL1, the second lower contact plug CPL2, the first upper contact plug CPU1, and the second upper contact plug CPU2 may have a wedge shape whose horizontal width decreases downward.

[0064] A back-end BEOL interconnection structure (not shown) may be disposed on the upper interlayer insulating layer 90, and some of the cell contact plugs CPC, the first lower contact plugs CPL1, the second lower contact plugs CPL2, the first upper contact plugs CPU1, and the second upper contact plugs CPU2 may be electrically connected to each other through the BEOL interconnection structure.

[0065] In some embodiments, Figure 2A As shown, the peripheral contact plug CPP contacting the interconnection parts 30p, 40p, 50p and 81p arranged on different layers is arranged in the connection area EA. Since a plurality of interconnection layers are arranged in the connection area EA, various interconnection structures can be realized and the degree of freedom of design can be increased. Therefore, the area of ​​the connection area EA can be reduced, and the size of the semiconductor device 1 can be reduced.

[0066] In some embodiments, the horizontal widths of the upper surfaces of the peripheral contact plugs CPP are the same as each other. In addition, the lower horizontal widths of the peripheral contact plugs CPP may be different from each other. Here, the 'lower horizontal width' may refer to the horizontal width of the peripheral contact plugs CPP on the upper surfaces of the corresponding interconnection portions 30p, 40p, 50p, and 81p. The peripheral contact plugs CPP may have a smaller lower horizontal width as their height increases. Figure 3As shown, the second upper contact plug CPU2, the first upper contact plug CPU1, the second lower contact plug CPL2 and the first lower contact plug CPL1 have lower horizontal widths W1, W2, W3 and W4, respectively, and the lower horizontal widths W1, W2, W3 and W4 of the second upper contact plug CPU2, the first upper contact plug CPU1, the second lower contact plug CPL2 and the first lower contact plug CPL1 may decrease sequentially (W1>W2>W3>W4).

[0067] In some embodiments, the depths to which the peripheral contact plugs CPP are respectively inserted into the corresponding interconnection portions 30p, 40p, 50p, and 81p are different from each other. For example, the second upper contact plug CPU2 may be inserted into the second upper interconnection portion 81p to a depth D1, the first upper contact plug CPU1 may be inserted into the first upper interconnection portion 50p to a depth D2, the second lower contact plug CPL2 may be inserted into the second lower interconnection portion 40p to a depth D3, and the first lower contact plug CPL1 may be inserted into the first lower interconnection portion 30p to a depth D4. The depths D1, D2, D3, and D4 inserted into the interconnection portions may decrease in order (D1>D2>D3>D4).

[0068] Figure 2A The arrangement structure and number of the lower interconnection layers LL1 and LL2 and the peripheral contact plugs CPP shown are examples and are not limited thereto. In some embodiments, one or three or more lower interconnection layers are arranged.

[0069] Figure 4A and 4B is a vertical cross-sectional view of a semiconductor device according to example embodiments.

[0070] Reference Figure 4A and 4B , the semiconductor device 1a includes a peripheral contact plug CPP extending from the upper surface of the upper interlayer insulating layer 90. In some embodiments, the semiconductor device 1a further includes an insulating pattern 81a disposed between the second upper interconnection portions 81p. The insulating pattern 81a is also disposed between the upper insulating structure 84 and the upper interlayer insulating layer 90. The upper surface of the insulating pattern 81a is coplanar with the upper surface of the second upper interconnection portion 81p. In some embodiments, the insulating pattern 81a extends downward more than the second upper interconnection portion 81p. The insulating pattern 81a is also disposed between the landing pads 81.

[0071] In some embodiments, the insulating pattern 81a includes a material different from that of the upper insulating structure 84 and the upper interlayer insulating layer 90. The insulating pattern 81a may include silicon boron nitride (SiBN), silicon carbon nitride (SiCN), silicon oxide (SiO 2 ), silicon nitride (SiN), or a combination thereof. For example, the insulating pattern 81a may include silicon nitride.

[0072] In some embodiments, the peripheral contact plug CPP includes a portion in which the slope of the side surface changes. For example, the first lower contact plug CPL1 may include an overlapping portion OL overlapping the insulating pattern 81a in the horizontal direction. The slope of the side surface of the first lower contact plug CPL1 in the overlapping portion OL may be different from the slope of the side surface of the first lower contact plug CPL1 in a portion horizontally overlapping the upper insulating structure 84 and the upper interlayer insulating layer 90. For example, the slope in the portion overlapping the upper insulating structure 84 and the upper interlayer insulating layer 90 in the horizontal direction may be steeper than the slope in the overlapping portion OL.

[0073] Similarly, slopes of the second lower contact plug CPL2 and the first upper contact plug CPU1 may be changed in a portion overlapping the insulating pattern 81 a .

[0074] Figure 5A and Figure 5B is a vertical cross-sectional view of a semiconductor device according to example embodiments. Figure 6 yes Figure 5A An enlarged view of a portion of a semiconductor device is shown.

[0075] Reference Figure 5A , Figure 5B and Figure 6 , the semiconductor device 1b includes a peripheral contact plug CPP extending from the upper surface of the upper interlayer insulating layer 90. In some embodiments, the semiconductor device 1b further includes a lower etch stop layer 53b, a capping layer 50b, and an upper etch stop layer 81b. The lower etch stop layer 53b covers the second lower interconnection portion 40p and the second lower insulating layer 46 and is disposed below the bit line insulating layer 56. The capping layer 50b covers the upper surfaces of the bit line 50 and the first upper interconnection portion 50p. The upper etch stop layer 81b covers the upper surfaces of the landing pad 81 and the second upper interconnection portion 81p and extends in the horizontal direction.

[0076] In some embodiments, the lower etch stop layer 53b, the capping layer 50b, and the upper etch stop layer 81b include materials different from those of the upper insulating structure 84 and the upper interlayer insulating layer 90. The lower etch stop layer 53b and the upper etch stop layer 81b may include silicon boron nitride (SiBN), silicon carbon nitride (SiCN), silicon nitride, or a combination thereof. The capping layer 50b may include silicon nitride.

[0077] In some embodiments, the peripheral contact plug CPP includes a portion in which a slope of a side surface changes. The slopes of the first lower contact plug CPL1 and the second lower contact plug CPL2 may change in portions overlapping the lower etch stop layer 53b and the upper etch stop layer 81b in the horizontal direction, respectively. For example, the first lower contact plug CPL1 may include a first overlapping portion OLa horizontally overlapping the lower etch stop layer 53b and a second overlapping portion OLb horizontally overlapping the upper etch stop layer 81b. The slope of the side surface of the first lower contact plug CPL1 in the first overlapping portion OLa and the second overlapping portion OLb may be different from the slope of the side surface of the first lower contact plug CPL1 in a portion horizontally overlapping the upper insulating structure 84 and the upper interlayer insulating layer 90.

[0078] The slope of the first upper contact plug CPU1 may vary in a portion horizontally overlapping the capping layer 50b and the upper etch stop layer 81b. The slope of the second upper contact plug CPU2 may vary in a portion horizontally overlapping the upper etch stop layer 81b.

[0079] Fig. 7A and 7B is a vertical cross-sectional view of a semiconductor device according to example embodiments. Figure 8 yes Fig. 7A An enlarged view of a portion of a semiconductor device is shown.

[0080] Reference Fig. 7A , Figure 7B and Figure 8 , the semiconductor device 1c includes a peripheral contact plug CPP extending from the upper surface of the upper interlayer insulating layer 90. In some embodiments, the first lower insulating layer 36 of the first lower interconnection layer LL1 includes a first material layer 36a covering the side surface of the first lower plug 33p and a second material layer 36b covering the side surface of the first lower interconnection portion 30p. The second lower insulating layer 46 includes a first material layer 46a covering the side surface of the second lower plug 43p and a second material layer 46b covering the side surface of the second lower interconnection portion 40p.

[0081] The first material layers 36a and 46a include a material different from that of the second material layers 36b and 46b. For example, the first material layers 36a and 46a include SiCOH, SiBN, SiCN, SiN, or a combination thereof, and the second material layers 36b and 46b include silicon oxide.

[0082] In some embodiments, the first lower contact plug CPL1 includes a portion in which a slope of a side surface varies. For example, the first lower contact plug CPL1 may include an overlapping portion OL overlapping the first material layer 46a in the horizontal direction. The slope of the side surface of the first lower contact plug CPL1 in the overlapping portion OL may be different from the slope of the side surface in a portion of the first lower contact plug CPL1 overlapping the second material layer 46b in the horizontal direction. For example, the slope in the portion overlapping the second material layer 46b in the horizontal direction may be steeper than the slope in the overlapping portion OL.

[0083] Fig. 9 is a vertical cross-sectional view of a semiconductor device according to example embodiments.

[0084] Reference Fig. 9 , the semiconductor device 1d includes a peripheral contact plug CPP extending from the upper surface of the upper interlayer insulating layer 90. In some embodiments, the horizontal widths of the upper surfaces of the peripheral contact plugs CPP are different from each other. For example, the horizontal width of the upper surface of the peripheral contact plug CPP increases as its height increases. The horizontal width of the upper surface of the second upper contact plug CPU2 may be the smallest, and the horizontal width of the upper surface of the first lower contact plug CPL1 may be the largest.

[0085] FIG. 10A to FIG. 15B is a vertical cross-sectional view showing a series of processes of a method for manufacturing a semiconductor device according to an example embodiment. Specifically, Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A and Fig.15A is a vertical cross-sectional view showing the connection area EA and corresponds to Figure 2A . Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B and Fig. 15B is a vertical cross-sectional view showing the cell array area MCA and corresponds to Figure 2B .

[0086] Reference Fig. 10A and Fig. 10B , forming a peripheral circuit layer PS. Figure 2A and Figure 2B As described above, the peripheral circuit layer PS includes a substrate 3, a circuit element TR on the substrate 3, a peripheral interconnection portion 21 electrically connected to the circuit element TR, a first peripheral insulating layer 24 surrounding the side surface of the peripheral plug 18 and the side surface of the circuit element TR, and a second peripheral insulating layer 27 surrounding the peripheral interconnection portion 21 and the peripheral plug 18.

[0087] Reference Fig.11A and Fig. 11B , forming a first lower interconnection layer LL1 and a second lower interconnection layer LL2 on the peripheral circuit layer PS. The step of forming the first lower interconnection layer LL1 includes: forming an insulating material on the peripheral circuit layer PS; patterning the insulating material to form an opening; depositing a conductive material in the opening; and patterning the conductive material. Figure 2A and Figure 2B , the first lower interconnection layer LL1 includes first lower interconnection parts 30 and 30 p , first lower plugs 33 and 33 p , and a first lower insulating layer 36 .

[0088] The second lower interconnection layer LL2 is formed on the first lower interconnection layer LL1 and is formed by a method that is the same as or similar to the method of forming the first lower interconnection layer LL1. Figure 2A and Figure 2B , the second lower interconnection layer LL2 includes second lower interconnection parts 40 and 40 p , second lower plugs 43 and 43 p , and a second lower insulating layer 46 .

[0089] Reference Fig. 12A and Fig. 12B , a bit line 50, a cell connection plug 53, and a bit line insulating layer 56 are formed in the cell array area MCA. The cell connection plug 53 may be formed by forming a conductive material on the second lower interconnect layer LL2 and patterning the conductive material. The bit line 50 may be formed on the cell connection plug 53 and may extend in the first horizontal direction X.

[0090] In the connection area EA, a first upper interconnection portion 50p and a first peripheral plug 53p may be formed on the second lower interconnection layer LL2. The first upper interconnection portion 50p and the first peripheral plug 53p may be formed simultaneously with the bit line 50 and the cell connection plug 53 and may be formed of the same material as the bit line 50 and the cell connection plug 53.

[0091] Reference Fig.13A and Fig. 13B , an upper structure US is formed on the bit line 50 and the bit line insulating layer 56 in the cell array area MCA. Figure 2B As shown, the upper structure US includes a channel structure 73, a dielectric structure 76, a word line 79, a landing pad 81 and an upper insulating structure 84. However, the shape of the upper structure US is not limited to Figure 2B Rather, the example embodiments shown may be modified variously.

[0092] In the connection area EA, a second upper interconnection portion 81p and a second peripheral plug 83p may be formed on the first upper interconnection portion 50p and the bit line insulating layer 56. In some embodiments, the second upper interconnection portion 81p and the second peripheral plug 83p are formed simultaneously with the landing pad 81 and may include the same material as the landing pad 81. An upper insulating structure 84 may surround the second upper interconnection portion 81p and the second peripheral plug 83p.

[0093] Reference Fig.14A and Fig. 14B , an information storage structure 87 is formed on the upper structure US in the cell array area MCA. Figure 2A and Figure 2B , the information storage structure 87 includes a first electrode 88a electrically connected to and contacting the landing pad 81, a second electrode 88c on the first electrode 88a, and a dielectric layer 88b between the first electrode 88a and the second electrode 88c.

[0094] The upper interlayer insulating layer 90 may be formed to cover the information storage structure 87 in the cell array area MCA. The upper interlayer insulating layer 90 may cover the second upper interconnection portion 81p in the connection area EA.

[0095] Reference Fig.15A and Fig. 15B , a cell contact hole HC is formed in the cell array area MCA, and a second upper contact hole H1, a first upper contact hole H2, a second lower contact hole H3, and a first lower contact hole H4 are formed in the connection area EA. The cell contact hole HC, the second upper contact hole H1, the first upper contact hole H2, the second lower contact hole H3, and the first lower contact hole H4 expose the upper surface of the second electrode 88c, the second upper interconnection portion 81p, the first upper interconnection portion 50p, the second lower interconnection portion 40p, and the upper surface of the first lower interconnection portion 30p, respectively.

[0096] The cell contact hole HC, the second upper contact hole H1, the first upper contact hole H2, the second lower contact hole H3, and the first lower contact hole H4 may be simultaneously formed by performing an anisotropic etching process. In some embodiments, the horizontal widths at the upper ends of the cell contact hole HC, the second upper contact hole H1, the first upper contact hole H2, the second lower contact hole H3, and the first lower contact hole H4 are the same as each other, but are not limited thereto.

[0097] Return to reference Figure 2A and Figure 2B, a barrier layer 96 is conformally formed in the cell contact hole HC, the second upper contact hole H1, the first upper contact hole H2, the second lower contact hole H3 and the first lower contact hole H4, and the barrier layer 96 is filled with a metal layer 93 to form each of the cell contact plug CPC, the second upper contact plug CPU2, the first upper contact plug CPU1, the second lower contact plug CPL2 and the first lower contact plug CPL1.

[0098] The cell contact plug CPC, the second upper contact plug CPU2, the first upper contact plug CPU1, the second lower contact plug CPL2 and the first lower contact plug CPL1 may extend from the upper surface of the upper interlayer insulating layer 90 to contact the second electrode 88c, the second upper interconnection portion 81p, the first upper interconnection portion 50p, the second lower interconnection portion 40p and the first lower interconnection portion 30p, respectively.

[0099] According to an example embodiment of the concept described herein, a peripheral contact plug that contacts interconnection portions arranged on different layers is arranged. Since the plurality of interconnection layers are arranged in a connection region, each interconnection structure is implemented and the degree of freedom of design is increased. Therefore, the area of ​​the connection region is reduced and the size of the semiconductor device is reduced.

[0100] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of any invention or on the scope of what may be claimed, but rather as descriptions of features that may be specific to a particular embodiment of a particular invention. Certain features described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented individually in multiple embodiments, or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations, and even initially claimed as such, in some cases, one or more features from the claimed combination may be removed from the combination, and the claimed combination may point to a sub-combination or a variation of a sub-combination.

[0101] While example embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined in the appended claims.

Claims

1. A semiconductor device comprising: A substrate including a cell array region and a connection region; A peripheral circuit layer, which is disposed on the substrate, and includes circuit elements; A bit line disposed on the peripheral circuit layer in the cell array region; a first upper interconnection portion disposed on the connection region of the substrate, wherein the first upper interconnection portion and the bit line are located at the same height relative to the substrate; at least one lower interconnect layer disposed between the peripheral circuit layer and the bit line and between the peripheral circuit layer and the first upper interconnect portion; a bit line insulating layer surrounding the bit line in the cell array region and surrounding the first upper interconnection portion in the connection region; an upper structure disposed on the bit line and the first upper interconnection portion, the upper structure comprising an upper insulating structure; an information storage structure disposed on the upper structure in the cell array region; as well as A plurality of lower contact plugs are electrically connected to the at least one lower interconnection layer through the bit line insulating layer, and the plurality of lower contact plugs are disposed in the connection region.

2. The semiconductor device according to claim 1, wherein The plurality of lower contact plugs pass through the upper insulating structure.

3. The semiconductor device according to claim 1, comprising: an upper interlayer insulating layer covering the information storage structure in the cell array region and covering the upper insulating structure in the connection region, Wherein, the plurality of lower contact plugs pass through the upper interlayer insulating layer.

4. The semiconductor device according to claim 1, wherein The at least one lower interconnect layer includes a first lower interconnect layer and a second lower interconnect layer, the second lower interconnect layer being disposed on the first lower interconnect layer, The first lower interconnect layer includes a plurality of first lower interconnect parts, The second lower interconnect layer includes a plurality of second lower interconnect portions, and The plurality of lower contact plugs includes a first lower contact plug that passes through the second lower interconnection layer and contacts one first lower interconnection portion among the plurality of first lower interconnection portions.

5. The semiconductor device according to claim 4, wherein: At least one of the plurality of first lower interconnections is electrically connected to at least one of the plurality of second lower interconnections, and one or more of the plurality of first lower interconnections is electrically connected to the first lower contact plug.

6. The semiconductor device according to claim 4, wherein: The plurality of lower contact plugs include a second lower contact plug contacting one second lower interconnection portion among the plurality of second lower interconnection portions.

7. The semiconductor device according to claim 6, wherein: A width of an upper surface of the first lower contact plug is greater than a width of an upper surface of the second lower contact plug.

8. The semiconductor device according to claim 6, wherein: A width of an upper surface of the first lower contact plug is equal to a width of an upper surface of the second lower contact plug.

9. The semiconductor device according to claim 8, wherein: The lower width of the first lower contact plug is smaller than the lower width of the second lower contact plug, the lower width of the first lower contact plug being the width of the first lower contact plug located on the upper surface of the first lower interconnection portion, and the lower width of the second lower contact plug being the width of the second lower contact plug located on the upper surface of the second lower interconnection portion.

10. The semiconductor device according to claim 8, wherein A depth to which the first lower contact plug extends into the first lower interconnection portion is smaller than a depth to which the second lower contact plug extends into the second lower interconnection portion.

11. The semiconductor device according to claim 4, comprising: an insulating pattern disposed on the upper insulating structure, the insulating pattern comprising a material different from that of the upper insulating structure, A slope of a side surface of the first lower contact plug in a portion where the first lower contact plug overlaps the insulating pattern in a horizontal direction is different from a slope of a side surface of the first lower contact plug in a portion where the first lower contact plug overlaps the upper insulating structure in the horizontal direction.

12. The semiconductor device according to claim 4, further comprising: a lower etch stop layer disposed below the bit line insulating layer; as well as an upper etch stop layer disposed on the upper structure, The slope of the side surface of the first lower contact plug changes in a portion overlapping with the lower etch stop layer in the horizontal direction, and the slope of the side surface of the first lower contact plug changes in a portion overlapping with the upper etch stop layer in the horizontal direction.

13. The semiconductor device according to claim 4, wherein: The second lower interconnection layer includes a first material layer and a second material layer, the second material layer includes a material different from that of the first material layer and covers a plurality of side surfaces of the plurality of second lower interconnection parts, and A slope of a side surface of the first lower contact plug in a portion overlapping the first material layer in a horizontal direction is different from a slope of a side surface of the first lower contact plug in a portion overlapping the second material layer in the horizontal direction.

14. A semiconductor device comprising: A substrate including a cell array region and a connection region; A peripheral circuit layer, which is disposed on the substrate, and includes circuit elements; A bit line disposed on the peripheral circuit layer in the cell array region; a first upper interconnection portion disposed on the connection region of the substrate, wherein the first upper interconnection portion and the bit line are located at the same height relative to the substrate; a lower interconnect layer disposed between the peripheral circuit layer and the bit line and between the peripheral circuit layer and the first upper interconnect portion, the lower interconnect layer including a lower interconnect portion; a bit line insulating layer surrounding the bit line in the cell array region and surrounding the first upper interconnection portion in the connection region; an upper structure disposed on the bit line and the first upper interconnection portion, the upper structure comprising an upper insulating structure; an information storage structure disposed on the upper structure in the cell array region; an upper interlayer insulating layer covering the information storage structure in the cell array region and covering the upper insulating structure in the connection region; a lower contact plug extending in a vertical direction from an upper surface of the upper interlayer insulating layer in the connection region, passing through the bit line insulating layer, and contacting the lower interconnection portion; as well as A first upper contact plug extends from the upper surface of the upper interlayer insulating layer in the vertical direction and contacts the first upper interconnection portion.

15. The semiconductor device according to claim 14, wherein: A width of an upper surface of the lower contact plug is equal to a width of an upper surface of the first upper contact plug.

16. The semiconductor device according to claim 15, wherein: The lower width of the lower contact plug is smaller than the lower width of the first upper contact plug, the lower width of the lower contact plug being the width of the lower contact plug on the upper surface of the lower interconnection portion, and the lower width of the first upper contact plug being the width of the first upper contact plug on the upper surface of the first upper interconnection portion.

17. The semiconductor device according to claim 14, wherein: The first upper contact plug passes through the upper insulating structure and the upper interlayer insulating layer.

18. The semiconductor device according to claim 14, wherein: A height of the first upper contact plug is greater than a height of the upper structure.

19. A semiconductor device comprising: A substrate including a cell array region and a connection region; A peripheral circuit layer, which is disposed on the substrate, and includes circuit elements; A first lower interconnect layer, which is disposed on the peripheral circuit layer, the first lower interconnect layer comprising a first lower interconnect portion; a second lower interconnect layer disposed on the first lower interconnect layer, the second lower interconnect layer comprising a second lower interconnect portion; a bit line disposed on the second lower interconnect layer in the cell array region; a first upper interconnection portion disposed on the connection region of the substrate, wherein the first upper interconnection portion and the bit line are located at the same height relative to the substrate; a bit line insulating layer surrounding the bit line in the cell array region and surrounding the first upper interconnection portion in the connection region; an upper structure disposed on the bit line and the first upper interconnection portion, the upper structure comprising a landing pad and an upper insulating structure surrounding the landing pad; a second upper interconnect portion disposed on the connection region of the substrate, wherein the second upper interconnect portion is located at the same height as the landing pad relative to the substrate; an information storage structure disposed on the upper structure in the cell array region; an upper interlayer insulating layer covering the information storage structure in the cell array region and covering the upper insulating structure in the connection region; as well as A first lower contact plug passes through the upper interlayer insulating layer, the upper insulating structure, and the bit line insulating layer, the first lower contact plug contacts the first lower interconnection portion in the connection region.

20. The semiconductor device according to claim 19, comprising: A first upper contact plug passes through the upper interlayer insulating layer and the upper insulating structure, the first upper contact plug contacts the first upper interconnection portion in the connection region.

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