Semiconductor device

Abstract

A semiconductor device is provided. An integrated circuit memory device (e.g., a DRAM) includes a substrate having a bit line thereon; and an electrically insulating region having a first opening therein exposing a first portion of the bit line. A first semiconductor active layer is provided that forms a layer along opposing first and second sidewalls of the first opening and an exposed first portion of the bit line, such that a direct electrical connection is provided between the exposed first portion of the bit line and a portion of the first semiconductor active layer extending between the first and second sidewalls of the first opening. A first word line is provided on a first portion of the first semiconductor active layer extending opposite the first sidewall of the first opening, and a second word line is provided on a second portion of the first semiconductor active layer extending opposite the second sidewall of the first opening.

Description

Technical Field

[0001] The inventive concept relates to semiconductor devices, and more particularly, to integrated circuit memory devices. Background Art

[0002] As semiconductor devices continue to shrink in size, the size of dynamic random access memory (DRAM) devices is also decreasing. In DRAM devices having a 1T-1C structure in which one capacitor is connected to one transistor, there is a problem that leakage current through the channel region generally increases as the device becomes smaller. In order to reduce the leakage current, vertical channel transistors using oxide semiconductor materials as the channel layer have been proposed. Summary of the invention

[0003] The inventive concept provides a semiconductor device, such as a DRAM device, having excellent electrical performance.

[0004] According to one aspect of the inventive concept, a semiconductor device is provided, the semiconductor device comprising: a bit line extending in a first horizontal direction on a substrate; and a mold structure disposed on the bit line and comprising a mold opening extending in a second horizontal direction perpendicular to the first horizontal direction. The mold structure may include: a mold insulating layer; a cover insulating layer disposed on the mold insulating layer; and an interface insulating layer disposed on an upper surface of the cover insulating layer and on at least a portion of a sidewall of the cover insulating layer. An active semiconductor layer is also provided, and the active semiconductor layer comprises: a first portion disposed on an inner wall of the mold opening of the mold structure and extending in a vertical direction perpendicular to the upper surface of the substrate; and a second portion connected to a bottom of the first portion and extending in the first horizontal direction. In some embodiments, the second portion is disposed on an upper surface of the bit line, and the first portion comprises a first sidewall in contact with a sidewall of the mold opening and a second sidewall extending opposite to the first sidewall. A word line is also provided, and the word line is disposed on the second sidewall of the active semiconductor layer and extends in the second horizontal direction. A gate insulating layer is provided between the active semiconductor layer and the word line, and a landing pad extending on an upper surface of the first portion of the active semiconductor layer is provided.

[0005] According to a further embodiment, a semiconductor device is provided, the semiconductor device comprising: a bit line extending in a first horizontal direction on a substrate; a molding structure, the molding structure being disposed on the bit line and comprising a molding opening extending in a second horizontal direction perpendicular to the first horizontal direction, wherein the molding structure comprises: a molding insulating layer; a covering insulating layer disposed on the molding insulating layer; and an interface insulating layer disposed on an upper surface of the covering insulating layer and on at least a portion of a sidewall of the covering insulating layer. An active semiconductor layer is provided, the active semiconductor layer comprising: a first portion disposed on an inner wall of the molding opening of the molding structure and extending in a vertical direction perpendicular to the upper surface of the substrate; and a second portion connected to a bottom of the first portion and extending in the first horizontal direction. In some embodiments, the second portion is disposed on an upper surface of the bit line, and the first portion comprises a first sidewall in contact with a sidewall of the molding opening and a second sidewall opposite to the first sidewall. A word line is provided, the word line being disposed on the second sidewall of the active semiconductor layer and extending in the second horizontal direction. A gate insulating layer is provided, the gate insulating layer being disposed between the active semiconductor layer and the word line. A landing pad is provided, the landing pad being connected to an upper surface of the first portion of the active semiconductor layer. In some embodiments, the landing pad may include: an upper portion, the upper portion being disposed on an upper surface of the molding structure; and a bottom portion, the bottom portion being connected to the upper portion and disposed in a landing pad recess space, and a bottom surface of the bottom portion of the landing pad may be disposed at the same level as a bottom surface of the interface insulating layer.

[0006] According to another aspect of the present invention, there is provided a semiconductor device, comprising: a bit line extending in a first horizontal direction on a substrate; a mold structure, the mold structure being disposed on the bit line and comprising a mold opening extending in a second horizontal direction perpendicular to the first horizontal direction, the mold structure comprising: a mold insulating layer; a cover insulating layer, the cover insulating layer being disposed on the mold insulating layer; and an interface insulating layer, the interface insulating layer being disposed on an upper surface of the cover insulating layer and on at least a portion of a sidewall of the cover insulating layer; an active semiconductor layer, the active semiconductor layer comprising: a first portion, the first portion being disposed on an inner wall of the mold opening of the mold structure and extending in a vertical direction perpendicular to the upper surface of the substrate; and a second portion, the second portion being connected to a bottom of the first portion and extending in the first horizontal direction, wherein the second portion is disposed on an upper surface of the bit line and the first portion comprises a mold opening extending in a second horizontal direction perpendicular to the first horizontal direction. a first side wall contacting the side wall of the opening and a second side wall opposite to the first side wall, and the active semiconductor layer has an upper surface arranged at a horizontal height lower than the upper surface of the mold structure; a word line, the word line is arranged on the second side wall of the active semiconductor layer and extends in the second horizontal direction; a gate insulating layer, the gate insulating layer is arranged between the active semiconductor layer and the word line; a buried insulating layer, the buried insulating layer is arranged on the side wall of the word line and fills the mold opening; a landing pad, the landing pad is connected to the upper surface of the first part of the active semiconductor layer, the landing pad includes an upper portion arranged on the upper surface of the mold structure and a bottom connected to the upper portion and arranged in a recessed space of the landing pad; and a storage node, the storage node is connected to the landing pad, wherein the interface insulating layer extends from the upper surface of the cover insulating layer to the side wall of the cover insulating layer arranged in the recessed space of the landing pad.

[0007] According to yet another embodiment of the present invention, an integrated circuit memory device is provided, the integrated circuit memory device comprising: a substrate having a bit line (BL) thereon; and an electrically insulating region having a first opening therein exposing a first portion of the bit line. A first semiconductor active layer is also provided, the first semiconductor active layer forming a layer (line) along the first and second sidewalls opposite to each other of the first opening and the exposed first portion of the bit line, so that a direct electrical connection is provided between the exposed first portion of the bit line and the portion of the first semiconductor active layer extending between the first sidewall and the second sidewall of the first opening. A first word line is provided on a first portion of the first semiconductor active layer extending relative to the first sidewall of the first opening, and a second word line is provided on a second portion of the first semiconductor active layer extending relative to the second sidewall of the first opening. Advantageously, the portion of the first word line extending relative to the first portion of the first semiconductor active layer is used as a gate electrode of an access transistor of a first memory cell, and the portion of the second word line extending relative to the second portion of the first semiconductor active layer is used as a gate electrode of an access transistor of a second memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a layout diagram showing a semiconductor device according to an embodiment;

[0010] Figure 2 yes Figure 1 an enlarged layout diagram of a portion of a cell array region;

[0011] Figure 3 It is along Figure 2 A cross-sectional view taken along line A1-A1';

[0012] Figure 4 It is along Figure 2 A cross-sectional view taken along line A2-A2';

[0013] Figure 5 yes Figure 3 A magnified view of a portion of CX1;

[0014] Figure 6 and Figure 7 is a cross-sectional view showing a semiconductor device according to an embodiment;

[0015] Figure 8 yes Figure 6 A magnified view of a portion of CX1;

[0016] Fig. 9 is a cross-sectional view showing a semiconductor device according to an embodiment;

[0017] Fig.10 yes Fig. 9 A magnified view of a portion of CX1;

[0018] Fig.11 is a cross-sectional view showing a semiconductor device according to an embodiment; and

[0019] FIG. 12A to FIG. 23 is a schematic diagram showing a method of manufacturing a semiconductor device according to an embodiment, wherein Fig. 12A , Fig.13A , Fig.14 , Fig.15A , Fig.16A , Figures 17 to 21A , Fig. 22 and Fig.23 It is along Figure 2 A cross-sectional view taken along line A1-A1', Fig. 15B , Fig. 16B and Fig. 21B It is along Figure 2 A cross-sectional view taken along line A2-A2', and Fig. 12B , Fig. 13B , Fig. 15C and Fig. 16C yes Fig. 12A , Fig.13A , Fig.15A and Fig.16A A top view of FIG. 12A to FIG. 23 In, with Figures 1 to 11 The same reference numerals as in the drawings indicate the same components. DETAILED DESCRIPTION

[0020] Figure 1 is a layout diagram showing a semiconductor device 100 according to an embodiment, and Figure 2 yes Figure 1 FIG. 1 is an enlarged layout diagram of a portion of the cell array area MCA. Figure 3 It is along Figure 2 A cross-sectional view taken along line A1-A1', Figure 4 It is along Figure 2 A cross-sectional view taken along line A2-A2', and Figure 5 yes Figure 3 A magnified view of a portion of the CX1.

[0021] refer to Figures 1 to 5, the semiconductor device 100 may include a substrate 110, which includes a cell array area MCA and a peripheral circuit area PCA. In some embodiments, the cell array area MCA may be a memory cell area of ​​a dynamic random access memory (DRAM) device, and the peripheral circuit area PCA may be a core area or a peripheral circuit area of ​​the DRAM device. For example, the peripheral circuit area PCA may include a peripheral circuit transistor (not shown) for transmitting signals and / or power to a memory cell array included in the cell array area MCA. In an embodiment, the peripheral circuit transistor (not shown) may form various circuits such as a command decoder, control logic, an address buffer, a row decoder, a column decoder, a sense amplifier, and a data input / output circuit.

[0022] like Figure 2 As shown, in the cell array area MCA of the substrate 110, a plurality of word lines WL extending in a first horizontal direction X and a plurality of bit lines BL extending in a second horizontal direction Y may be arranged. A plurality of cell transistors CTR may be arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL. A plurality of storage nodes 180 may be arranged on each cell transistor CTR.

[0023] The plurality of word lines WL may include first word lines WL1 and second word lines WL2 alternately arranged in the second horizontal direction Y, and the plurality of cell transistors CTR may include first cell transistors CTR1 and second cell transistors CTR2 alternately arranged in the second horizontal direction Y. The first cell transistor CTR1 may be disposed adjacent to the first word line WL1, and the second cell transistor CTR2 may be disposed adjacent to the second word line WL2.

[0024] The first cell transistor CTR1 and the second cell transistor CTR2 may have mirror-symmetric structures with respect to a center line extending in the first horizontal direction X between the first cell transistor CTR1 and the second cell transistor CTR2.

[0025] like Figure 3 As shown, the lower insulating layer 112 may be disposed on the substrate 110. The substrate 110 may include silicon, such as single crystal silicon, polycrystalline silicon, or amorphous silicon. In some other embodiments, the substrate 110 may include at least one selected from Ge, SiGe, SiC, GaAs, InAs, and InP. In some embodiments, the substrate 110 may include a conductive region, such as a well doped with impurities or a structure doped with impurities. The lower insulating layer 112 may include an oxide film, a nitride film, or a combination thereof.

[0026] In some embodiments, a peripheral circuit structure may be disposed on the substrate 110, and a lower insulating layer 112 may be disposed to cover the peripheral circuit structure. The peripheral circuit structure may include, but is not limited to, a sense amplifier electrically connected to the bit line BL and / or a sub-word line driver electrically connected to the word line WL.

[0027] The bit line BL extending in the second horizontal direction Y may be disposed on the lower insulating layer 112. In an embodiment, the bit line BL may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof. The bit line isolation insulating layer 122 extending in the second horizontal direction Y may be disposed on the sidewall of the bit line BL. For example, the bit line isolation insulating layer 122 may fill the space between two adjacent bit lines BL and may be formed at the same height as the bit line BL.

[0028] The mold structure 130 may be disposed on the bit line BL and the bit line isolation insulating layer 122. The mold structure 130 may include an etch stop layer 132, a mold insulation layer 134, a capping insulation layer 136, and an interface insulation layer 138. In some embodiments, the etch stop layer 132 may have a relatively small thickness and be disposed on upper surfaces of the bit line BL and the bit line isolation insulating layer 122. The etch stop layer 132 may include silicon nitride.

[0029] In some embodiments, the mold insulation layer 134 may be disposed on the etch stop layer 132. The mold insulation layer 134 may be formed to have a relatively large height. In embodiments, the mold insulation layer 134 may include silicon oxide.

[0030] In an embodiment, the capping insulating layer 136 may be disposed on an upper surface of the mold insulating layer 134. The capping insulating layer 136 may include a material having an etch selectivity with respect to a material of the mold insulating layer 134. In an embodiment, the capping insulating layer 136 may include silicon nitride.

[0031] In an embodiment, the interface insulating layer 138 may be disposed on an upper surface of the capping insulating layer 136 and on a portion of a sidewall of the capping insulating layer 136. In some embodiments, the interface insulating layer 138 may include silicon oxynitride or silicon oxide. In some embodiments, the interface insulating layer 138 may include a material layer formed by oxidizing a portion of the capping insulating layer 136 as a result of performing an oxygen annealing process on the upper surface of the capping insulating layer 136.

[0032] In an embodiment, the interface insulating layer 138 disposed on the sidewall of the capping insulating layer 136 may have a first thickness t11, and the interface insulating layer 138 disposed on the upper surface of the capping insulating layer 136 may have a second thickness t12. In an embodiment, the first thickness t11 and the second thickness t12 may be in a range from about several angstroms to about tens of angstroms. In some embodiments, the first thickness t11 may be substantially equal to the second thickness t12. In some embodiments, the first thickness t11 may be less than the second thickness t12.

[0033] In an embodiment, the mold structure 130 may include a plurality of mold openings 130H. The plurality of mold openings 130H may extend in the first horizontal direction X, and the upper surface of the bit line BL may be exposed at the bottom of each of the plurality of mold openings 130H. For example, the plurality of mold openings 130H may include a first sidewall 130H1 and a second sidewall 130H2, and the first sidewall 130H1 and the second sidewall 130H2 may be spaced apart from each other and extend in the first horizontal direction X.

[0034] A plurality of active semiconductor layers 140 may be disposed on the inner walls of the plurality of mold openings 130H. Each of the plurality of active semiconductor layers 140 may include a first portion 140P1 and a second portion 140P2. The first portion 140P1 may refer to a portion extending in the vertical direction Z on the first sidewall 130H1 and the second sidewall 130H2 of the mold opening 130H. The second portion 140P2 may refer to a portion disposed at the bottom of the mold opening 130H, disposed on the bit line BL and in contact with the upper surface of the bit line BL. For example, each of the plurality of active semiconductor layers 140 may have a U-shaped vertical cross section.

[0035] The first portion 140P1 of the active semiconductor layer 140 disposed adjacent to the first sidewall 130H1 of the mold opening 130H may be used as a vertical channel layer of the first cell transistor CTR1, and the first portion 140P1 of the active semiconductor layer 140 disposed adjacent to the second sidewall 130H2 of the mold opening 130H may be used as a vertical channel layer of the second cell transistor CTR2. Therefore, within one mold opening 130H, the first cell transistor CTR1 and the second cell transistor CTR2 may be arranged in shapes that are mirror-symmetrical to each other.

[0036] The first portion 140P1 of the plurality of active semiconductor layers 140 may include a first sidewall S11 and a second sidewall S12 opposite to each other, and the first sidewall S11 may be in contact with the mold insulating layer 134. In an embodiment, each of the plurality of active semiconductor layers 140 may have an upper surface disposed at a level lower than that of the upper surface of the mold structure 130 and disposed at the same level as the bottom surface of the cover insulating layer 136. In some embodiments, each of the plurality of active semiconductor layers 140 may have an upper surface disposed at a level lower than that of the bottom surface of the cover insulating layer 136.

[0037] In an embodiment, the plurality of active semiconductor layers 140 may include an oxide semiconductor material. For example, the plurality of active semiconductor layers 140 may include indium gallium zinc oxide (InGaZnO). x Ga y Zn z O), indium tungsten oxide (In x WyO), indium tin gallium oxide (In x Sn y Ga z O), indium aluminum zinc oxide (In x Al y Zn z O), indium gallium oxide (In x Ga y O), indium tin zinc oxide (In x Sn y Zn z O), Indium Gallium Silicon Oxide (In x Ga y Si z O), indium zinc oxide (In x Zn y O), indium oxide (In x O) and magnesium aluminum zinc oxide (Mg x Al y Zn z O), zinc tin oxide (Zn x Sn y O), zirconium zinc tin oxide (Zr x Zn y Sn z O), gallium zinc tin oxide (Ga x Zn y Sn z O), aluminum zinc tin oxide (Al x Zn y Sn z O) and tin oxide (Sn xIn some embodiments, in addition to the above materials, the plurality of active semiconductor layers 140 may include an oxide semiconductor material having a band gap energy greater than that of silicon.

[0038] The gate insulating layer 150 may be disposed on the second sidewalls S12 of the plurality of active semiconductor layers 140. For example, the gate insulating layer 150 may be conformally arranged on the upper surfaces of the second sidewalls S12 of the first portion 140P1 and the second portion 140P2 of the plurality of active semiconductor layers 140.

[0039] In some embodiments, the gate insulating layer 150 may have an upper surface disposed at a higher level than an upper surface of the active semiconductor layer 140. The gate insulating layer 150 may have an upper surface disposed at the same level as an upper surface of the capping insulating layer 136. In other embodiments, the gate insulating layer 150 may include at least one selected from a high-k dielectric material having a higher dielectric constant than silicon oxide and a ferroelectric material. In some embodiments, the gate insulating layer 150 may include at least one material selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminate (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanate (BaSrTiO), barium titanate (BaTiO), lead zirconate titanate (PbZrTiO), strontium bismuth tantalate (SrTaBiO), bismuth iron oxide (BiFeO), strontium titanate (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), or lead tantalum scandium oxide (PbTaScO).

[0040] The word line WL may be disposed on the upper surface of the second sidewall S12 and the second portion 140P2 of the first portion 140P1 of the plurality of active semiconductor layers 140, such that the gate insulating layer 150 is disposed between the word line WL and the second sidewall S12. In an embodiment, the word line WL may have an L-shaped vertical cross-section. In an embodiment, the bit line BL may include Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof.

[0041] The first insulating pad 162 and the second insulating pad 164 may be disposed on the sidewalls of the two word lines WL spaced apart from each other within the mold opening 130H, and a buried insulating layer 166 filling a space between the two word lines WL spaced apart from each other may be disposed on the first insulating pad 162 and the second insulating pad 164. For example, the first insulating pad 162 and the second insulating pad 164 may include silicon nitride, and the buried insulating layer 166 may include silicon oxide.

[0042] The landing pad 170 may be disposed on the upper surfaces of the mold structure 130 and the buried insulating layer 166. The landing pad 170 may include an upper portion 170U and a bottom portion 170B, and the upper portion 170U of the landing pad 170 may be disposed on the upper surfaces of the mold structure 130 and the buried insulating layer 166, and the bottom portion 170B of the landing pad 170 may be disposed inside the landing pad recess space 170R.

[0043] For example, the landing pad recess space 170R may be defined on the upper surface of the first portion 140P1 of the active semiconductor layer 140, between the first sidewall 130H1 and the second sidewall 130H2 of the mold opening 130H and the gate insulating layer 150. The bottom 170B of the landing pad 170 may be disposed between the gate insulating layer 150 and the interface insulating layer 138 within the landing pad recess space 170R. The bottom surface of the bottom 170B of the landing pad 170 may contact the upper surface of the first portion 140P1 of the active semiconductor layer 140. The bottom surface of the bottom 170B of the landing pad 170 may be disposed at the same level as the bottom surface of the cover insulating layer 136 and the bottom surface of the interface insulating layer 138.

[0044] In some embodiments, the landing pad 170 may have a T-shaped vertical cross-section, and a width of an upper portion 170U of the landing pad 170 may be greater than a width of a bottom portion 170B of the landing pad 170. In embodiments, the landing pad 170 may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof.

[0045] In other embodiments, the interface insulating layer 138 may be disposed to cover the sidewalls of the cover insulating layer 136 within the landing pad recess space 170R, and thus, the bottom 170B of the landing pad 170 and the cover insulating layer 136 may not contact each other. Figure 5 As shown, the entire sidewall of the capping insulating layer 136 facing the bottom 170B of the landing pad 170 may be covered by the interface insulating layer 138 .

[0046] In the manufacturing process according to the embodiment, a recess process may be performed on the upper side of the first portion 140P1 of the active semiconductor layer 140 disposed between the mold structure 130 and the buried insulating layer 166, thereby reducing the height of the first portion 140P1 of the active semiconductor layer 140 and forming the landing pad recess space 170R. Then, by performing an oxygen annealing process on the upper surface of the first portion 140P1 of the active semiconductor layer 140 exposed through the landing pad recess space 170R, oxygen vacancies included in the active semiconductor layer 140 may be passivated, thereby adjusting the carrier concentration of the active semiconductor layer 140. Due to the oxygen annealing process performed on the upper surface of the capping insulating layer 136 exposed on the inner wall of the landing pad recess space 170R, the interface insulating layer 138 may be formed on the sidewall and upper surface of the capping insulating layer 136.

[0047] A landing pad isolation insulating layer 172 covering the landing pad 170 may be disposed on the upper surfaces of the mold structure 130 and the buried insulating layer 166. The landing pad isolation insulating layer 172 may fill the space between adjacent landing pads 170 and cover the upper surfaces of the landing pads 170, and the landing pad isolation insulating layer 172 may have an upper surface disposed at a higher level than the upper surfaces of the landing pads 170. In other embodiments, the landing pad isolation insulating layer 172 may have an upper surface disposed at the same level as the upper surfaces of the landing pads 170.

[0048] The storage node 180 may be disposed on the landing pad isolation insulating layer 172. In some embodiments, the storage node 180 may be a capacitor type (e.g., for a DRAM memory cell) and may include, for example, a lower electrode 182, a capacitor dielectric layer 184, and an upper electrode 186. The lower electrode 182 may be disposed on the upper surface of the landing pad 170 and may extend in the vertical direction Z. The capacitor dielectric layer 184 may be disposed on the sidewalls of the lower electrode 182, and the upper electrode 186 may be located on the capacitor dielectric layer 184.

[0049] According to the above-described embodiment, an oxygen annealing process may be performed through the upper surface of the active semiconductor layer 140 exposed in the landing pad recess space 170R, and thus, the carrier concentration of the active semiconductor layer 140 may be adjusted, and thus, the semiconductor device 100 may have excellent electrical properties.

[0050] Figure 6 and Figure 7 is a cross-sectional view showing a semiconductor device 100A according to an embodiment, and Figure 8 yes Figure 6 An enlarged view of a portion of CX1. Figures 6 to 8 In, with Figures 1 to 5 The same reference numerals in the drawings represent the same components. Figures 6 to 8 , the upper surface of the active semiconductor layer 140 may be disposed at a higher level than the upper surface of the mold insulating layer 134. For example, the upper surface of the active semiconductor layer 140 may be higher than the bottom surface of the cover insulating layer 136, and may be disposed at a lower level than the upper surface of the cover insulating layer 136. The landing pad 170A may include an upper portion 170U and a bottom portion 170B, and the bottom portion 170B of the landing pad 170A may be disposed inside the landing pad recess space 170R.

[0051] In some embodiments, the interface insulating layer 138 may be disposed to cover a portion of the sidewall of the cover insulating layer 136 within the landing pad recess space 170R, and, for example, a lower portion of the sidewall of the cover insulating layer 136 may not be covered by the interface insulating layer 138 and may be in contact with an upper side of the first portion 140P1 of the active semiconductor layer 140. An upper side of the sidewall of the cover insulating layer 136 may be covered by the interface insulating layer 138 and thus may not be in contact with the bottom 170B of the landing pad 170A.

[0052] In the manufacturing process according to the embodiment, a recess process may be performed on the upper side of the first portion 140P1 of the active semiconductor layer 140 disposed between the mold structure 130 and the buried insulating layer 166, thereby reducing the height of the first portion 140P1 of the active semiconductor layer 140 and forming a landing pad recess space 170R. Here, the etching amount in the recess process may be adjusted so that the upper surface of the active semiconductor layer 140 is at a lower level than the upper surface of the capping insulating layer 136 and at a higher level than the upper surface of the mold insulating layer 134.

[0053] Then, by performing an oxygen annealing process on the upper surface of the first portion 140P1 of the active semiconductor layer 140 exposed through the landing pad recess space 170R, oxygen vacancies included in the active semiconductor layer 140 may be passivated, thereby adjusting the carrier concentration of the active semiconductor layer 140. Here, since the oxygen annealing process is performed on a portion of the upper surface and the sidewall of the capping insulating layer 136 exposed at the inner wall of the landing pad recess space 170R, a portion of the capping insulating layer 136 may be oxidized to form the interface insulating layer 138.

[0054] Sidewalls of the interface insulating layer 138 exposed in the landing pad recess space 170R may be aligned with lower sidewalls of the cover insulating layer 136 , and a bottom surface of the interface insulating layer 138 may be disposed at a higher vertical level than a bottom surface of the cover insulating layer 136 .

[0055] Fig. 9 is a cross-sectional view of a semiconductor device 100B according to an embodiment, and Fig.10 yes Fig. 9An enlarged view of a portion of CX1. Fig. 9 and Fig.10 In, with Figures 1 to 8 The same reference numerals in the drawings represent the same components. Fig. 9 and Fig.10 , the gate insulating layer 150 and the word line WL may have an L-shaped vertical cross-section, and the second insulating pad 164 may cover the sidewalls of the word line WL and the gate insulating layer 150 , and extend downward so as to extend to the upper surface of the second portion 140P2 of the active semiconductor layer 140 .

[0056] According to the embodiment, the active semiconductor layer 140 within one mold opening 130H constitutes the first cell transistor CTR1 (see Figure 2 ) can be connected to the active semiconductor layer 140 constituting the second cell transistor CTR2 (see Figure 2 ), and a portion of the gate insulating layer 150 constituting the first cell transistor CTR1 within one mold opening 130H may be disposed to be separated from a portion of the gate insulating layer 150 constituting the second cell transistor CTR2. In addition, within one mold opening 130H, a portion of the gate insulating layer 150 constituting the first cell transistor CTR1 may have a mirror-symmetrical shape with respect to a portion of the gate insulating layer 150 constituting the second cell transistor CTR2.

[0057] Fig.11 is a cross-sectional view showing a semiconductor device 100C according to an embodiment. Fig.11 In, with Figures 1 to 10 The same reference numerals in the drawings represent the same components. Fig.11 , the word line WL may have a vertical cross-section of a rectangular shape, and the upper width and the lower width of the word line WL may be substantially the same. Figures 1 to 5 The described second insulating liner 164 may be omitted, and the buried insulating layer 166 may be disposed on the sidewall and upper surface of the first insulating liner 162 .

[0058] FIG. 12A to FIG. 23 is a schematic diagram showing a method of manufacturing a semiconductor device 100 according to an embodiment, wherein Fig. 12A , Fig.13A , Fig.14 , Fig.15A , Fig.16A , Figures 17 to 21A , Fig. 22 and Fig.23 It is along Figure 2 A cross-sectional view taken along line A1-A1', Fig. 15B , Fig. 16B and Fig. 21B It is along Figure 2 A cross-sectional view taken along line A2-A2', and Fig. 12B , Fig. 13B , Fig. 15C and Fig. 16C yes Fig. 12A , Fig.13A , Fig.15A and Fig.16A A top view of the FIG. 12A to FIG. 23 In, with Figures 1 to 11 The same reference numerals in the drawings represent the same components.

[0059] refer to Fig. 12A and Fig. 12B , a lower insulating layer 112 is formed on the substrate 110. Thereafter, a bit line isolation insulating layer 122 may be formed on the lower insulating layer 112 to fill spaces between the plurality of bit lines BL extending in the second horizontal direction Y.

[0060] In some embodiments, a bit line isolation insulating layer 122 can be formed on the lower insulating layer 112, and a mask pattern (not shown) can be used to pattern the bit line isolation insulating layer 122 to form a bit line forming space (not shown), and a conductive layer is formed in the bit line forming space, and the upper side of the conductive layer can be removed to expose the upper surface of the bit line isolation insulating layer 122, thereby forming a plurality of bit lines BL.

[0061] refer to Fig.13A and Fig. 13B , a mold stack 130S may be formed on the plurality of bit lines BL and the bit line isolation insulating layer 122. As shown, this mold stack 130S may include an etch stop layer 132, a mold insulating layer 134, and a capping insulating layer 136. For example, the etch stop layer 132 may be formed using silicon nitride, the mold insulating layer 134 may be formed using silicon oxide, and the capping insulating layer 136 may be formed using silicon nitride.

[0062] Then, a mask pattern (not shown) may be formed on the mold stack 130S, and a plurality of mold openings 130H may be formed using the mask pattern as an etching mask. The upper surface of the bit line BL and the upper surface of the bit line isolation insulating layer 122 may be exposed at the bottom of the plurality of mold openings 130H. The plurality of mold openings 130H may be arranged to extend in the first horizontal direction X, and each of the plurality of mold openings 130H may include a first sidewall 130H1 and a second sidewall 130H2 extending in the first horizontal direction X and opposite to each other.

[0063] refer to Fig.14, a primary active semiconductor layer 140P may be formed on the mold stack 130S to conformally cover the inner wall of the mold opening 130H. This primary active semiconductor layer 140P may be formed using an oxide semiconductor material. For example, the primary active semiconductor layer 140P may include indium gallium zinc oxide (InGaZnO). x Ga y Zn z O), indium tungsten oxide (In x W y O), indium tin gallium oxide (In x Sn y Ga z O), indium aluminum zinc oxide (In x Al y Zn z O), indium gallium oxide (In x Ga y O), indium tin zinc oxide (In x Sn y Zn z O), Indium Gallium Silicon Oxide (In x Ga y Si z O), indium zinc oxide (In x Zn y O), indium oxide (In x O) and magnesium aluminum zinc oxide (Mg x Al y Zn z O), zinc tin oxide (Zn x Sn y O), zirconium zinc tin oxide (Zr x Zn y Sn z O), gallium zinc tin oxide (Ga x Zn y Sn z O), aluminum zinc tin oxide (Al x Zn y Sn z O) and tin oxide (Sn x In some embodiments, the preliminary active semiconductor layer 140P may be formed using at least one of a chemical vapor deposition (CVD) process, a low pressure CVD process, a plasma enhanced CVD process, a metal organic CVD (MOCVD) process, and an atomic layer deposition process.

[0064] refer to FIG. 15A to FIG. 15C , a first mask layer 210 may be formed on the preliminary active semiconductor layer 140P. The first mask layer 210 may be formed to have a thickness thick enough to completely fill the mold opening 130H.

[0065] Thereafter, a mask pattern (not shown) may be formed on the first mask layer 210, and a portion of the preliminary active semiconductor layer 140P may be removed using the mask pattern and the first mask layer 210 as an etching mask. For example, the mask pattern may have a linear shape extending in the first horizontal direction X, and thus, the preliminary active semiconductor layer 140P may also remain on the inner wall of the mold opening 130H and the upper surface of the mold stack 130P to extend in the first horizontal direction X. Also, as a portion of the preliminary active semiconductor layer 140P is removed, the upper surface of the bit line isolation insulating layer 122 may be exposed to the bottom of the mold opening 130H again.

[0066] refer to FIG. 16A to FIG. 16C , the first mask layer 210 may be removed. Then, a second mask layer 220 may be formed on the molding stack 130S and the preliminary active semiconductor layer 140P. The second mask layer 220 may be formed to have a thickness sufficient to completely fill the molding opening 130H, and thus the upper surface of the preliminary active semiconductor layer 140P disposed on the upper surface of the molding stack 130S may be covered by the second mask layer 220.

[0067] Thereafter, a planarization process may be performed on the upper side of the second mask layer 220 to remove a portion of the preliminary active semiconductor layer 140P disposed on the upper surface of the mold stack 130S (e.g., the cover insulating layer 136) and leave the preliminary active semiconductor layer 140P on the inner wall of the mold opening 130H. In order to dispose one active semiconductor layer 140 in a portion where one mold opening 130H and one bit line BL intersect each other as a portion of the preliminary active semiconductor layer 140P disposed on the upper surface of the mold stack 130S (e.g., the cover insulating layer 136) is removed, a plurality of active semiconductor layers 140 spaced apart from each other in the first horizontal direction X and the second horizontal direction Y may be defined.

[0068] The active semiconductor layer 140 may include a first portion 140P1 disposed on the first and second sidewalls 130H1 and 130H2 of the mold opening 130H and a second portion 140P2 disposed on the bottom of the mold opening 130H and continuously connected to the first portion 140P1. The active semiconductor layer 140 may have a U-shaped vertical cross-section.

[0069] refer to Fig.17, the second mask layer 220 may be removed. Then, a gate insulating layer 150 may be formed on the plurality of active semiconductor layers 140. In some embodiments, the gate insulating layer 150 may include at least one selected from a high-k dielectric material having a higher dielectric constant than silicon oxide and a ferroelectric material. In some embodiments, the gate insulating layer 150 may include at least one material selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminate (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanate (BaSrTiO), barium titanate (BaTiO), lead zirconate titanate (PbZrTiO), strontium bismuth tantalate (SrTaBiO), bismuth iron oxide (BiFeO), strontium titanate (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), or lead tantalum scandium oxide (PbTaScO).

[0070] A word line metal layer WLP may be formed on the gate insulating layer 150. In some cases, this word line metal layer WLP may be formed using Ti, TiN, Ta, TaN, Mo, Ru, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof.

[0071] refer to Fig.18 , a first insulating liner 162 may be formed on the word line metal layer WLP, and an anisotropic etching process may be performed on the word line metal layer WLP and the first insulating liner 162 to remove a portion of the word line metal layer WLP disposed on the bottom of the mold opening 130H and leave the word line WL on the first sidewall 130H1 and the second sidewall 130H2 of the mold opening 130H. In addition, a portion of the word line metal layer WLP disposed on the upper surface of the mold stack 130P may also be removed by the anisotropic etching process. After the anisotropic etching process, two word lines WL may be arranged to be spaced apart from each other and respectively disposed on the first sidewall 130H1 and the second sidewall 130H2 of the plurality of mold openings 130H.

[0072] refer to Fig.19 , a second insulating liner 164 and a buried insulating layer 166 may be formed in the mold opening 130H. The second insulating liner 164 may be disposed on the upper surface of the active semiconductor layer 140 disposed at the bottom of the mold opening 130H, for example, on the second portion 140P2 of the active semiconductor layer 140. The buried insulating layer 166 may fill the mold opening 130H on the second insulating liner 164.

[0073] In an embodiment, the buried insulating layer 166 may have an upper surface disposed at the same horizontal height as the upper surface of the molded stack 130S, and the upper surface of the first portion 140P1 of the active semiconductor layer 140 and the upper surface of the gate insulating layer 150 may also be disposed at the same horizontal height as the upper surface of the molded stack 130S.

[0074] refer to Fig. 20 , a portion of the upper side of the active semiconductor layer 140 may be removed by an etch-back process to form a landing pad recess space 170R. The landing pad recess space 170R may refer to a space between the upper surface of the active semiconductor layer 140 and the upper sides of the molding stack 130S and the buried insulating layer 166. The upper surface of the active semiconductor layer 140 may be disposed at the bottom of the landing pad recess space 170R.

[0075] In an embodiment, the landing pad recess space 170R may be formed to a depth exposing a sidewall of the capping insulating layer 136 , and an upper surface of the first portion 140P1 of the active semiconductor layer 140 may be disposed at the same level as a bottom surface of the capping insulating layer 136 .

[0076] refer to Fig.21A and Fig. 21B , an oxygen annealing process P200 may be performed through the upper surface of the active semiconductor layer 140 exposed in the landing pad recess space 170R. In some cases, this oxygen annealing process P200 may include exposing the upper surface of the active semiconductor layer 140 to an oxygen-containing atmosphere. For example, the oxygen annealing process P200 may include supplying at least one of oxygen, atmospheric gas, ozone, or oxygen plasma to the active semiconductor layer 140 so that oxygen atoms may pass through the upper surface of the active semiconductor layer 140 exposed in the landing pad recess space 170R.

[0077] In an embodiment, the oxygen annealing process P200 may be performed at atmospheric pressure or elevated pressure. In some embodiments, the oxygen annealing process P200 may be performed sequentially under vacuum and atmospheric pressure. In an embodiment, the oxygen annealing process P200 may be performed at room temperature or elevated temperature. In an embodiment, the oxygen annealing process P200 may be performed for about several minutes to about several hours.

[0078] In embodiments, by performing the oxygen annealing process P200 , oxygen atoms may penetrate and / or diffuse into the active semiconductor layer 140 , and oxygen vacancies included within the active semiconductor layer 140 may be passivated, and carrier concentration of the active semiconductor layer 140 may be adjusted.

[0079] In an embodiment, since the oxygen annealing process P200 is performed through the upper surface of the active semiconductor layer 140 exposed in the landing pad recess space 170R, a sufficient amount of oxygen atoms may be supplied into the active semiconductor layer 140 .

[0080] In an embodiment, due to the oxygen annealing process performed on the upper surface of the capping insulating layer 136 exposed at the inner wall of the landing pad recess space 170R, a portion of the capping insulating layer 136 may be oxidized to form an interface insulating layer 138. The interface insulating layer 138 may be formed on the entire upper surface of the capping insulating layer 136 exposed during the oxygen annealing process P200. Additionally, during the oxygen annealing process P200, the interface insulating layer 138 may be formed on the sidewall of the capping insulating layer 136 exposed within the landing pad recess space 170R.

[0081] In an embodiment, the interface insulating layer 138 formed on the sidewall of the capping insulating layer 136 may have a first thickness t11 (see Figure 5 ), and the interface insulating layer 138 formed on the upper surface of the capping insulating layer 136 may have a second thickness t12 (see Figure 5 ). In an embodiment, the first thickness t11 and the second thickness t12 may be in a range from about several angstroms to about tens of angstroms. In some embodiments, the first thickness t11 may be substantially equal to the second thickness t12. In some embodiments, the first thickness t11 may be less than the second thickness t12. Here, a structure in which the etch stop layer 132, the mold insulating layer 134, the capping insulating layer 136, and the interface insulating layer 138 are sequentially disposed is referred to as a mold structure 130.

[0082] refer to Fig. 22 , a landing pad 170 may be formed on the mold structure 130 and the buried insulating layer 166. The landing pad 170 may fill the landing pad recess space 170R and may contact the upper surface of the first portion 140P1 of the active semiconductor layer 140. In some cases, the landing pad 170 may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, polysilicon, or a combination thereof. Also, in some embodiments, before forming the landing pad 170 in the landing pad recess space 170R, a contact region may also be formed by implanting impurity ions into the upper surface of the first portion 140P1 of the active semiconductor layer 140 exposed in the landing pad recess space 170R.

[0083] refer to Fig.23, a landing pad isolation insulating layer 172 covering the landing pad 170 may be formed on the mold structure 130 and the buried insulating layer 166. The landing pad isolation insulating layer 172 may be formed using silicon nitride. Then, a lower electrode 182, a capacitor dielectric layer 184, and an upper electrode 186 may be sequentially formed on the landing pad 170 and the landing pad isolation insulating layer 172.

[0084] The semiconductor device 100 may be completely formed by performing the above-mentioned processes. In addition, by performing the oxygen annealing process P200, oxygen atoms may be penetrated and / or diffused into the active semiconductor layer 140, and thus oxygen vacancies within the active semiconductor layer 140 may be passivated, or the carrier concentration of the active semiconductor layer 140 may be adjusted. Therefore, the semiconductor device 100 may have excellent electrical properties.

[0085] In other embodiments, in reference Fig. 20 In the described process, the landing pad recess space 170R may be formed to a depth that exposes only the upper portion of the sidewall of the capping insulating layer 136, and the upper surface of the first portion 140P1 of the active semiconductor layer 140A (see Figure 6 ) may be disposed at a level higher than the bottom surface of the cover insulating layer 136. In this case, when the oxygen annealing process P200 is performed in the process described with reference to FIG. 21, the interface insulating layer 138 may be formed only on the upper portion of the sidewall of the cover insulating layer 136 exposed by the landing pad recess space 170R. The lower portion of the sidewall of the cover insulating layer 136 may be covered by the active semiconductor layer 140A and may not be exposed to the oxygen atmosphere, and the interface insulating layer 138 may not be formed on the lower portion of the sidewall of the cover insulating layer 136. In this case, the reference may be manufactured. Figures 6 to 8 A semiconductor device 100A is described.

[0086] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: a bit line extending in a first horizontal direction on an underlying substrate; a molding structure extending on the bit line and having therein a molding opening extending in a second horizontal direction perpendicular to the first horizontal direction, the molding structure comprising a molding insulating layer, a capping insulating layer extending on the molding insulating layer, and an interface insulating layer extending on an upper surface of the capping insulating layer and on at least a portion of a sidewall of the capping insulating layer; An active semiconductor layer, the active semiconductor layer comprising: a first portion on an inner wall of the mold opening in the mold structure and extending in a vertical direction perpendicular to an upper surface of the substrate, the first portion having a first sidewall in contact with a sidewall of the mold opening and a second sidewall extending opposite to the first sidewall; and a second portion connected to a bottom portion of the first portion and extending in the first horizontal direction on an upper surface of the bit line; a word line on the second sidewall of the active semiconductor layer and extending in the second horizontal direction; and A gate insulating layer extends between the active semiconductor layer and the word line.

2. The device according to claim 1, further comprising: a landing pad extending over an upper surface of the first portion of the active semiconductor layer; wherein the interface insulating layer extends between the landing pad and the cover insulating layer; and Wherein, the landing pad does not contact the covering insulating layer.

3. The device according to claim 1, wherein The active semiconductor layer has a U-shaped vertical cross-section; and wherein the word line has an L-shaped vertical cross-section.

4. The device according to claim 1, further comprising: a landing pad extending over an upper surface of the first portion of the active semiconductor layer; Wherein, the landing pad comprises an upper portion and a bottom portion; wherein the bottom of the landing pad extends in a landing pad recessed space, the landing pad recessed space being defined between the molding structure and the gate insulating layer on the upper surface of the active semiconductor layer; and Wherein, the upper portion of the landing pad is disposed on an upper surface of the molding structure.

5. The device according to claim 4, wherein The upper portion of the landing pad has a first width in the first horizontal direction; wherein the bottom portion of the landing pad has a second width in the first horizontal direction that is smaller than the first width.

6. The device according to claim 4, wherein the interface insulating layer extending from the upper surface of the cover insulating layer to the sidewall of the cover insulating layer extending in the landing pad recess space; And, wherein a portion of the interface insulating layer extending on the sidewall of the cover insulating layer contacts the landing pad.

7. The device according to claim 6, wherein The first portion of the active semiconductor layer has an upper surface disposed at a level that is the same as or lower than a bottom surface of the covering insulating layer; and wherein the sidewall of the covering insulating layer extending in the landing pad recess space is completely covered by the interface insulating layer.

8. The device according to claim 6, in, The first portion of the active semiconductor layer has an upper surface disposed at a higher level than a bottom surface of the capping insulating layer; wherein an upper side of the sidewall of the cover insulating layer extending in the landing pad recess space is covered by the interface insulating layer; and Wherein, a lower side of the sidewall of the cover insulating layer contacts a sidewall of the first portion of the active semiconductor layer.

9. The device according to claim 4, further comprising: a buried insulating layer extending on the sidewalls of the word line and filling the mold opening; and Wherein, a portion of the bottom surface of the upper portion of the landing pad is disposed on an upper surface of the buried insulating layer.

10. The device according to claim 1, wherein A bottom surface of the landing pad is disposed at the same level as a bottom surface of the interface insulating layer.

11. The device according to claim 1, wherein The interface insulating layer includes at least one of silicon oxynitride and silicon oxide.

12. The device according to claim 1, wherein The active semiconductor layer includes at least one of indium gallium zinc oxide, indium tungsten oxide, indium tin gallium oxide, indium aluminum zinc oxide, indium gallium oxide, indium tin zinc oxide, indium gallium silicon oxide, indium zinc oxide, indium oxide, magnesium aluminum zinc oxide, zinc tin oxide, zirconium zinc tin oxide, gallium zinc tin oxide, aluminum zinc tin oxide and tin oxide.

13. A semiconductor device, comprising: a bit line extending in a first direction on an underlying substrate; a mold structure having therein a mold opening extending in a second direction perpendicular to the first direction, the mold structure extending over the bit line and comprising a mold insulating layer, a cover insulating layer on the mold insulating layer, and an interface insulating layer on an upper surface of the cover insulating layer and on at least a portion of a sidewall of the cover insulating layer; an active semiconductor layer, the active semiconductor layer comprising a first portion and a second portion, the first portion extending on an inner wall of the mold opening in the mold structure and extending in a vertical direction perpendicular to the upper surface of the substrate, the second portion connected to a bottom of the first portion and extending in the first direction, wherein the first portion comprises a first sidewall contacting a sidewall of the mold opening and a second sidewall extending opposite to the first sidewall; a word line extending on the second sidewall of the active semiconductor layer and extending in the second direction; a gate insulating layer extending between the active semiconductor layer and the word line; and a landing pad electrically connected to an upper surface of the first portion of the active semiconductor layer, the landing pad comprising an upper portion extending on an upper surface of the molding structure and a bottom portion connected to the upper portion and extending in a landing pad recessed space; wherein a bottom surface of the bottom portion of the landing pad extends at the same level as a bottom surface of the interface insulating layer; and Wherein, the second portion extends on the upper surface of the bit line.

14. The device according to claim 13, wherein The interface insulating layer extends from the upper surface of the cover insulating layer to the side wall of the cover insulating layer disposed in the recessed space of the landing pad; and wherein a portion of the interface insulating layer disposed on the side wall of the cover insulating layer contacts the bottom of the landing pad.

15. The device according to claim 14, wherein The interface insulating layer extends between the bottom of the landing pad and the cover insulating layer; and wherein the bottom of the landing pad does not contact the cover insulating layer.

16. The device according to claim 13, wherein The first portion of the active semiconductor layer has an upper surface disposed at a level that is the same as or lower than the bottom surface of the covering insulating layer; and wherein the sidewall of the covering insulating layer disposed in the landing pad recess space is completely covered by the interface insulating layer.

17. The device according to claim 13, further comprising: a buried insulating layer extending on the sidewalls of the word line and filling the mold opening; and wherein a portion of a bottom surface of the upper portion of the landing pad extends over an upper surface of the buried insulating layer.

18. The device according to claim 13, wherein The interface insulating layer comprises silicon oxynitride or silicon oxide, and The capping insulating layer includes silicon nitride.

19. A semiconductor device, comprising: a bit line extending in a first horizontal direction on the substrate; a molding structure extending on the bit line and having a molding opening therein, the molding opening extending in a second horizontal direction perpendicular to the first horizontal direction, the molding structure comprising a molding insulating layer, a cover insulating layer disposed on the molding insulating layer, and an interface insulating layer disposed on an upper surface of the cover insulating layer and on at least a portion of a sidewall of the cover insulating layer; an active semiconductor layer, the active semiconductor layer comprising a first portion and a second portion, the first portion being disposed on an inner wall of the mold opening of the mold structure and extending in a vertical direction perpendicular to an upper surface of the substrate, the second portion being connected to a bottom of the first portion and extending in the first horizontal direction, wherein the second portion extends on an upper surface of the bit line, and the first portion comprises a first sidewall contacting a sidewall of the mold opening and a second sidewall opposite to the first sidewall, and wherein the active semiconductor layer has an upper surface extending at a lower level than an upper surface of the mold structure; a word line extending on the second sidewall of the active semiconductor layer and extending in the second horizontal direction; a gate insulating layer, the gate insulating layer being disposed between the active semiconductor layer and the word line; a buried insulating layer extending on the sidewalls of the word line and filling the mold opening; a landing pad electrically connected to an upper surface of the first portion of the active semiconductor layer, the landing pad comprising an upper portion disposed on the upper surface of the molding structure and a bottom portion connected to the upper portion and disposed in a landing pad recess space; and a storage node connected to the landing pad, The interface insulating layer extends from the upper surface of the cover insulating layer to the sidewall of the cover insulating layer extending in the landing pad recess space.

20. The semiconductor device according to claim 19, in, the first portion of the active semiconductor layer having an upper surface disposed at the same level as or lower than a bottom surface of the cover insulating layer; wherein the sidewall of the cover insulating layer disposed in the recessed space of the landing pad is completely covered by the interface insulating layer; and The interface insulating layer extends between the bottom of the landing pad and the cover insulating layer, and the bottom of the landing pad does not contact the cover insulating layer.

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