Display panel, manufacturing method and display device

Abstract

The application discloses a display panel, a manufacturing method and a display device. The display panel comprises a substrate, an active layer arranged on the substrate, a gate insulating assembly arranged on the active layer, an interlayer dielectric layer arranged on the gate insulating assembly, a first via penetrating the gate insulating assembly to expose the active layer, a first metal layer arranged on the interlayer dielectric layer and deposited in the first via, a first planar layer covering the first metal layer and the interlayer dielectric layer and arranged with a second via to expose the first metal layer, a second metal layer arranged on the first planar layer and deposited in the second via, an electrode insulating assembly arranged on the second metal layer, a second planar layer arranged on the electrode insulating assembly and arranged with a third via penetrating the electrode insulating assembly to expose the second metal layer, and a pixel anode layer arranged on the second planar layer and deposited in the third via. The application directly connects the pixel anode layer and the second metal layer through the via, thereby avoiding the problem that the contact impedance is increased due to the connection between the pixel anode layer and the electrode wiring.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel, a manufacturing method and a display device. BACKGROUND

[0002] At present, a larger screen ratio has become one of the future development trends, that is, a full-screen technology; to realize a full-screen, a camera under panel (CUP) technology is one of the key factors. At present, a mainstream technology is to use a transparent PI (organic material, flexible panel substrate) plus a transparent electrode trace to improve light transmittance, so that imaging effect is optimized; the transparent electrode trace is used to realize TFT (Thin Film Transistor) driving of a CUP area pixel in an AA (Active Area) area; a disadvantage is that an Anode (pixel anode layer) in the AA area is connected to a lower SD (Source / Drain) metal through two layers of transparent electrodes ITO (Indium Tin Oxide) (Fig 1); since the ITO metal itself is unstable and has a large resistance value, contact impedance between the Anode and the SD is increased, which affects EL luminous efficiency and display effect. SUMMARY

[0003] Embodiments of the present application provide a display panel, a manufacturing method and a display device; a pixel anode layer and a second metal layer are directly connected through a second planar layer and an electrode insulation combination, so that the problem of increased contact impedance caused by the connection of the Anode and the ITO is avoided.

[0004] In a first aspect, embodiments of the present application provide a display panel, comprising:

[0005] a substrate;

[0006] an active layer, disposed on the substrate;

[0007] a gate insulation combination, disposed on the active layer and the substrate;

[0008] an interlayer dielectric layer, disposed on the gate insulation combination, the interlayer dielectric layer is provided with a first via, and the first via penetrates the gate insulation combination to expose a part of the active layer;

[0009] a first metal layer, disposed on the interlayer dielectric layer, and the first metal layer is deposited in the first via and in contact with the active layer;

[0010] a first planar layer, covering the first metal layer and the interlayer dielectric layer, the first planar layer is provided with a second via, and the second via exposes a part of the first metal layer;

[0011] a second metal layer disposed on the first planar layer, the second metal layer being deposited in the second via in contact with the first metal layer;

[0012] an electrode insulation assembly disposed on the second metal layer and the first planar layer;

[0013] a second planar layer disposed on the electrode insulation assembly, the second planar layer being provided with a third via, the third via penetrating the electrode insulation assembly to expose a portion of the second metal layer;

[0014] a pixel anode layer disposed on the second planar layer, the pixel anode layer being deposited in the third via in contact with the second metal layer.

[0015] In some embodiments, the gate insulation assembly comprises:

[0016] a first gate insulation layer covering the active layer and the substrate;

[0017] a first gate layer disposed on the first gate insulation layer;

[0018] a second gate insulation layer covering the first gate layer and the first gate insulation layer;

[0019] a second gate layer disposed on the first gate insulation layer;

[0020] the interlayer dielectric layer covering the second gate layer and the second gate insulation layer, the first via penetrating the first gate insulation layer and the second gate insulation layer to expose a portion of the active layer.

[0021] In some embodiments, the active layer comprises a channel region and conductor regions disposed on both sides of the channel region, the first gate layer being disposed opposite to the channel region, the first metal layer being in contact with the conductor regions on both sides.

[0022] In some embodiments, the electrode insulation assembly comprises:

[0023] a first electrode insulation layer covering the second metal layer and the first planar layer;

[0024] a first electrode layer disposed on the first electrode insulation layer;

[0025] a second electrode insulation layer covering the first electrode layer and the first electrode insulation layer, the second electrode insulation layer being provided with a fourth via, the fourth via penetrating the first electrode layer and the first electrode insulation layer to expose a portion of the second metal layer.

[0026] a second electrode layer disposed on the first electrode insulating layer, and the second electrode layer is deposited in the fourth via to contact the second metal layer;

[0027] the second planar layer covers the second electrode layer and the second electrode insulating layer, and the third via penetrates the first electrode insulating layer and the second electrode insulating layer to expose a part of the second metal layer.

[0028] In some embodiments, the display panel further comprises:

[0029] a pixel definition layer covering the second planar layer and the pixel anode layer, and the pixel definition layer is provided with a fifth via, and the fifth via exposes a part of the pixel anode layer;

[0030] a support layer disposed on the pixel definition layer.

[0031] In some embodiments, the substrate comprises:

[0032] a substrate layer;

[0033] a buffer layer disposed on the substrate layer, and the active layer and the gate insulating combination are disposed on the buffer layer.

[0034] In a second aspect, the present application provides a display panel manufacturing method, comprising:

[0035] providing a substrate, and an active layer is prepared on the substrate;

[0036] preparing a gate insulating combination on the substrate and the active layer;

[0037] depositing an interlayer dielectric layer on the gate insulating combination, and etching a first via on the interlayer dielectric layer, and the first via penetrates the gate insulating combination to expose a part of the active layer;

[0038] depositing a first metal layer on the interlayer dielectric layer, and the first metal layer is deposited in the first via to contact the active layer;

[0039] depositing a first planar layer on the first metal layer and the interlayer dielectric layer, and etching a second via on the first planar layer, and the second via exposes a part of the first metal layer;

[0040] depositing a second metal layer on the first planar layer, and the second metal layer is deposited in the second via to contact the first metal layer;

[0041] preparing an electrode insulating combination on the second metal layer and the first planar layer;

[0042] depositing a second planar layer over the electrode insulation combination and etching a third via through the electrode insulation combination exposing a portion of the second metal layer;

[0043] depositing a pixel anode layer over the second planar layer and the pixel anode layer is deposited in contact with the second metal layer in the third via.

[0044] In one embodiment, the preparing an electrode insulation combination over the second metal layer and the first planar layer comprises:

[0045] depositing a first electrode insulation layer over the second metal layer and the first planar layer;

[0046] depositing a first electrode layer over the first electrode insulation layer;

[0047] depositing a second electrode insulation layer over the first electrode layer and the first electrode insulation layer and etching a fourth via through the first electrode layer and the first electrode insulation layer exposing a portion of the second metal layer;

[0048] depositing a second electrode layer over the second electrode insulation layer, the second electrode layer is deposited in contact with the second metal layer in the fourth via.

[0049] In one embodiment, further comprising:

[0050] depositing a pixel definition layer over the second planar layer and the pixel anode layer and etching a fifth via through the pixel definition layer exposing a portion of the pixel anode layer;

[0051] preparing a support layer over the pixel definition layer.

[0052] In one embodiment, the preparing a gate insulation combination over the substrate and the active layer comprises:

[0053] depositing a first gate insulation layer over the active layer and the substrate;

[0054] depositing a metal as a first gate layer over the first gate insulation layer and etching a pattern;

[0055] depositing a second gate insulation layer over the first gate layer and the first gate insulation layer;

[0056] depositing a metal as a second gate layer over the first gate insulation layer and etching a pattern.

[0057] In a third aspect, the present application provides a display device, comprising the display panel according to any one of the above.

[0058] The display panel, the manufacturing method and the display device provided by the embodiments of the present application connect the pixel anode layer and the second metal layer through direct hole connection of the second planar layer and the electrode insulation combination, thereby avoiding the problem of increased contact impedance caused by connection of the Anode and the ITO. BRIEF DESCRIPTION OF DRAWINGS

[0059] The technical solutions and other beneficial effects of the present application will be apparent from the following detailed description of the specific embodiments of the present application, combined with the accompanying drawings.

[0060] Figure 1 is a structural cross-sectional schematic diagram of a display panel in an embodiment of the present application;

[0061] Figure 2 is a structural cross-sectional schematic diagram of a display panel in another embodiment of the present application;

[0062] Figure 3 is a structural cross-sectional schematic diagram of a display panel in another embodiment of the present application;

[0063] Figure 4 is a structural cross-sectional schematic diagram of a display panel in another embodiment of the present application;

[0064] Figure 5 is a structural cross-sectional schematic diagram of a display panel in another embodiment of the present application.

[0065] LIST OF ELEMENTS IN THE DRAWINGS

[0066] 1, substrate; 11, substrate layer; 12, buffer layer; 2, active layer; 21, channel region; 22, conductor region; 3, gate insulation combination; 31, first gate insulation layer; 32, first gate layer; 33, second gate insulation layer; 34, second gate layer; 4, interlayer dielectric layer; 41, first via hole; 5, first metal layer; 6, first planar layer; 61, second via hole; 7, second metal layer; 8, electrode insulation combination; 81, first electrode insulation layer; 82, first electrode layer; 83, second electrode insulation layer; 831, fourth via hole; 84, second electrode layer; 9, second planar layer; 91, third via hole; 10, pixel anode layer; 110, pixel definition layer; 111, fifth via hole; 120, support layer. DETAILED DESCRIPTION

[0067] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0068] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0069] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0070] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0071] The following disclosure provides many different embodiments, or examples, for implementing different structures of the present application. For the purpose of simplification, the components and arrangements of the specific examples are described in the following. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application can repeatedly refer to the reference numerals and / or reference letters in different examples, and such repetition is for the purpose of simplification and clarity, which does not indicate the relationship between the various embodiments and / or arrangements discussed. In addition, the present application provides examples of various specific processes and materials, but those skilled in the art can realize the application of other processes and / or the use of other materials.

[0072] Please refer to Figure 1 The display panel provided by the embodiments of the present application comprises, in sequence, a substrate 1, an active layer 2, a gate insulation combination 3, an inter-layer dielectric layer 4, a first metal layer 5, a first planar layer 6, a second metal layer 7, an electrode insulation combination 8, a second planar layer 9, and a pixel anode layer 10.

[0073] The active layer 2 is arranged on the substrate 1, but the active layer 2 only occupies part of the area of the substrate 1, so the gate insulation combination 3 is prepared on the side of the active layer 2 away from the substrate 1, and the gate insulation combination 3 covers both the substrate 1 and the active layer 2. The gate insulation combination 3 comprises at least one gate layer and one gate insulation layer.

[0074] The inter-layer dielectric layer 4 is arranged on the gate insulation combination 3, so the inter-layer dielectric layer 4 (ILD) is deposited on the side of the gate insulation combination 3 away from the substrate 1. In order to communicate with the outside and drive, the active layer 2 needs to be connected with the outside, so the inter-layer dielectric layer 4 is provided with a first via hole 41, which penetrates the gate insulation combination 3 to expose a part of the active layer 2, so that the active layer 2 is connected with other metal electrodes. The first metal layer 5 (SD1) is arranged on the inter-layer dielectric layer 4, so the first metal layer 5 is deposited on the side of the inter-layer dielectric layer 4 away from the substrate 1, and the first metal layer 5 is deposited in the first via hole 41 to contact the active layer 2. The first metal layer 5 is a TFT device Source Drain metal layer, which is used to make a data line, a VddLine and an STV signal line.

[0075] The first metal layer 5 only occupies part of the area of the interlayer dielectric layer 4, so a first planarization layer 6 (PLN1) is deposited on the side of the first metal layer 5 and the interlayer dielectric layer 4 away from the substrate 1, the first planarization layer 6 covers both the first metal layer 5 and the interlayer dielectric layer 4, and the first planarization layer 6 is a medium layer between the SD1 and the SD2, which planarizes the surface of the SD1. In addition, in order to communicate data and drive, the first metal layer 5 needs to be connected to the outside, so the first planarization layer 6 is provided with a second via hole 61, which exposes part of the first metal layer 5 so that the first metal layer 5 is connected to other metal electrodes.

[0076] The second metal layer 7 (SD2) is provided on the first planarization layer 6, so a second metal layer 7 is deposited on the side of the first planarization layer 6 away from the substrate 1, and the second metal layer 7 is deposited in the second via hole 61 to contact the first metal layer 5, and the second metal layer 7 is made into a mesh structure to make the uniformity better. The second metal layer 7 is electrically connected to the first metal layer 5 through the second via hole 61 to form a double-layer wiring structure, and after any one of the first metal layer 5 and the second metal layer 7 is broken, the other metal layer can still maintain signal transmission, which reduces the risk of signal transmission caused by long-term bending and breakage, and improves the yield of the display panel.

[0077] The second metal layer 7 only occupies part of the area of the first planarization layer 6, so an electrode insulation combination 8 is prepared on the side of the second metal layer 7 away from the substrate 1, and the electrode insulation combination 8 covers both the second metal layer 7 and the first planarization layer 6. The electrode insulation combination 8 at least includes an electrode layer and an electrode insulation layer.

[0078] A second planarization layer 9 (PLN2) is provided on the electrode insulation combination 8, so a second planarization layer 9 is deposited on the side of the electrode insulation combination 8 away from the substrate 1, and the second planarization layer 9 is a medium layer between the SD2 and the Anode, which planarizes the surface of the SD2. In addition, in order to communicate data and drive, the second metal layer 7 needs to be connected to the outside, so the second planarization layer 9 is provided with a third via hole 91, which penetrates the electrode insulation combination 8 to expose part of the second metal layer 7, so that the second metal layer 7 is connected to other metal electrodes. A pixel anode layer 10 (Anode) is provided on the second planarization layer 9, so the pixel anode layer 10 is deposited on the second planarization layer 9, and the pixel anode layer 10 is deposited in the third via hole 91 to contact the second metal layer 7, the pixel anode layer 10 makes anode wiring, and the pixel anode layer 10 contacts the second metal layer 7 through the third via hole 91 to make the driving signal connected.

[0079] In this embodiment, the pixel anode layer 10 and the second metal layer 7 are connected directly through the opening in the second planar layer 9 and the electrode insulation combination 8, thereby avoiding the problem of increased contact impedance caused by the connection of the anode and the ITO, and improving the luminous efficiency without affecting the transparent electrode wiring. The area of the SD2 Pad can be increased to facilitate the lapping of the pixel anode layer 10.

[0080] In one embodiment, the gate insulation combination 3 includes a first gate insulation layer 31 (Gate Insulator 1, GI1), a first gate layer 32 (Gate Metal 1, GE1), a second gate insulation layer 33 (Gate Insulator 2, GI2), and a second gate layer 34 (Gate Metal 2, GE2). The first gate layer 32 is used as the gate for the switching of the TFT device, and is also used as the wiring for the Scan and EM signals. The second gate layer 34 is arranged opposite to the first gate layer 32 to form a capacitor, and is also used as the wiring for the Vi signal.

[0081] In this embodiment, the active layer 2 only occupies part of the area of the substrate 1, and therefore the first gate insulation layer 31 is prepared on the side of the active layer 2 away from the substrate 1, covering both the substrate 1 and the active layer 2. A layer of metal is deposited on the first gate insulation layer 31 as the first gate layer 32, and a pattern is etched out.

[0082] The first gate layer 32 only occupies part of the area of the first gate insulation layer 31, and therefore the second gate insulation layer 33 is prepared on the side of the first gate layer 32 away from the substrate 1, covering both the first gate insulation layer 31 and the first gate layer 32. A layer of metal is deposited on the second gate insulation layer 33 as the second gate layer 34, and a pattern is etched out.

[0083] The second gate layer 34 only occupies part of the area of the second gate insulation layer 33, and therefore the interlayer dielectric layer 4 is prepared on the side of the second gate layer 34 away from the substrate 1, covering both the second gate insulation layer 33 and the second gate layer 34. The first via hole 41 on the interlayer dielectric layer 4 penetrates the first gate insulation layer 31 and the second gate insulation layer 33 to expose a part of the active layer 2, so that the active layer 2 is in communication with the first metal layer 5.

[0084] In one embodiment, the active layer 2 includes a channel region 21 and conductor regions 22 arranged on both sides of the channel region 21. The first gate layer 32 is arranged opposite to the channel region 21, and the second gate layer 34 is arranged opposite to the first gate layer 32, so that the channel region 21, the first gate layer 32, and the second gate layer 34 are arranged in sequence. The first via hole 41 is arranged above each of the conductor regions 22, and the first metal layer 5 is deposited in the first via hole 41 to contact the conductor regions 22, so as to realize signal transmission.

[0085] In one embodiment, the electrode insulation assembly 8 comprises a first electrode insulation layer 81 (PV1), a first electrode layer 82 (ITO1), a second electrode insulation layer 83 (PV2), and a second electrode layer 84 (ITO2). The first electrode insulation layer 81 is an insulation layer between the second metal layer 7 and the first electrode layer 82, and the second electrode insulation layer 83 is an insulation layer between the first electrode layer 82 and the second electrode layer 84. The first electrode insulation layer 81 and the second electrode insulation layer 83 can be a non-metallic film or an organic film, including but not limited to one of PMDS, PEN, PI, PEI, PET, PPS materials. However, since the organic film will reduce the transmittance of visible light, a non-metallic film layer with high transmittance is usually used to make the first electrode insulation layer 81. The first electrode layer 82 and the second electrode layer 84 are transparent electrodes used as CUP area wiring. The transparent electrode material can use any one of ITO, IGZO, IZO, IGZTO, which is not specifically limited in the embodiment.

[0086] The second metal layer 7 only occupies part of the area of the first flat layer 6, so the first electrode insulation layer 81 is deposited on the side of the second metal layer 7 away from the substrate 1, and the first electrode insulation layer 81 covers both the second metal layer 7 and the first flat layer 6. Figure 2 As shown, the first electrode layer 82 is deposited on the first electrode insulation layer 81. Similarly, Figure 3 As shown, since the first electrode layer 82 only occupies part of the area of the first electrode insulation layer 81, the second electrode insulation layer 83 is deposited on the side of the first electrode layer 82 away from the substrate 1, and the second electrode insulation layer 83 covers both the first electrode layer 82 and the first electrode insulation layer 81. Then, the fourth via hole 831 on the second electrode insulation layer 83 is used to etch the first electrode insulation layer 81 and the first electrode layer 82 by exposure and etching technology, and the fourth via hole 831 exposes part of the second metal layer 7. That is, the first electrode insulation layer 81 does not need to be designed in a pattern, and the fourth via hole 831 can be made by using the second electrode insulation layer 83 in the later process, so as to achieve the purpose of saving light exposure. Figure 4 As shown, the second electrode layer 84 is deposited on the second electrode insulation layer 83, and the second electrode layer 84 is deposited in the fourth via hole 831. The second electrode layer 84 is in contact with both the second metal layer 7 and the first electrode layer 82, that is, the fourth via hole 831 is used to connect the second metal layer 7 with the transparent electrodes of the first electrode layer 82 and the second electrode layer 84.

[0087] In addition, as shown, Figure 5As shown, the second planar layer 9 is disposed on the electrode-insulating combination 8, i.e. the second planar layer 9 is disposed on the second electrode layer 84, since the second electrode layer 84 only occupies a part of the second electrode-insulating layer 83, the second planar layer 9 is deposited on the side of the second electrode layer 84 away from the substrate 1, and the second planar layer 9 covers both the second electrode layer 84 and the second electrode-insulating layer 83. The second planar layer 9 is provided with a third via hole 91, and the third via hole 91 penetrates the first electrode-insulating layer 81 and the second electrode-insulating layer 83 to expose a part of the second metal layer 7, and the pixel anode layer 10 is deposited in the third via hole 91 in communication with the second metal layer 7.

[0088] In this embodiment, instead of opening a hole in the first electrode-insulating layer 81, a fourth via hole 831 is directly opened in the second electrode-insulating layer 83 to penetrate the first electrode layer 82 and the first electrode-insulating layer 81, so as to realize the connection between the second metal layer 7 and the first electrode layer 82 and the second electrode layer 84, simplify the process steps, and improve the production rhythm. At the same time, a third via hole 91 is opened in the second electrode-insulating layer 83 to penetrate the first electrode-insulating layer 81 and the second electrode-insulating layer 83, so as to realize the connection between the second metal layer 7 and the pixel anode layer 10. The third via hole 91 and the fourth via hole 831 do not interfere with each other, and at the same time, in order to realize that both of the two via holes opened in the second electrode-insulating layer 83 are in communication with the second metal layer 7, the area of the second metal layer 7 can be increased as needed.

[0089] In one embodiment, the display panel further comprises a pixel definition layer 110 (Pixel Define Layer, PDL) and a support layer 120 (Photo Spacer, PS). Since the pixel anode layer 10 only occupies a part of the second planar layer 9, the pixel definition layer 110 is deposited on the side of the pixel anode layer 10 away from the substrate 1, and the second electrode-insulating layer 83 covers both the pixel anode layer 10 and the second planar layer 9. In addition, a fifth via hole 111 is etched on the pixel definition layer 110, and the fifth via hole 111 exposes a part of the pixel anode layer 10 so as to realize the connection between the pixel anode layer 10 and other electrodes. The support layer 120 is also provided on the pixel definition layer 110, and the support layer 120 is patterned from the reserved area of the pixel definition layer 110. In addition, the pixel definition layer 110 and the support layer 120 can be manufactured in one layer by using a Halftone process.

[0090] In one embodiment, the substrate 1 comprises a substrate layer 11 and a buffer layer 12 (Buffer), and the substrate layer 11 is a flexible panel substrate which can be an organic material PI (Polyimide, polyimide) and the like, and the present embodiment is not limited in particular. The buffer layer 12 is disposed on the substrate layer 11, and the active layer 2 and the gate-insulating combination 3 are disposed on the buffer layer 12.

[0091] In this embodiment, the pixel anode layer 10 and the second metal layer 7 are connected by directly opening holes in the second planar layer 9 and the electrode insulation combination 8, thereby avoiding the problem of increased contact impedance caused by the connection of the anode and the ITO, improving the luminous efficiency without affecting the transparent electrode wiring. In addition, there is no need to open holes in the first electrode insulation layer 81, but to directly open the fourth via hole 831 on the second electrode insulation layer 83 to penetrate the first electrode layer 82 and the first electrode insulation layer 81, to realize the connection of the second metal layer 7 and the first electrode layer 82 and the second electrode layer 84, simplify the process steps, and improve the production rhythm.

[0092] Please refer to Figures 1 to 5 The embodiment of the present application provides a display panel manufacturing method, which comprises the following steps:

[0093] Providing a substrate 1, wherein an active layer 2 is prepared on the substrate 1;

[0094] A gate insulation combination 3 is prepared on the substrate 1 and the active layer 2;

[0095] A layer interlayer dielectric layer 4 is deposited on the gate insulation combination 3, and a first via hole 41 is etched on the layer interlayer dielectric layer 4, wherein the first via hole 41 penetrates the gate insulation combination 3 to expose a part of the active layer 2;

[0096] A first metal layer 5 is deposited on the layer interlayer dielectric layer 4, and the first metal layer 5 is deposited in contact with the active layer 2 in the first via hole 41;

[0097] A first planar layer 6 is deposited on the first metal layer 5 and the layer interlayer dielectric layer 4, and a second via hole 61 is etched on the first planar layer 6, wherein the second via hole 61 exposes a part of the first metal layer 5;

[0098] A second metal layer 7 is deposited on the first planar layer 6, and the second metal layer 7 is deposited in contact with the first metal layer 5 in the second via hole 61;

[0099] An electrode insulation combination 8 is prepared on the second metal layer 7 and the first planar layer 6;

[0100] A second planar layer 9 is deposited on the electrode insulation combination 8, and a third via hole 91 is etched on the second planar layer 9, wherein the third via hole 91 penetrates the electrode insulation combination 8 to expose a part of the second metal layer 7;

[0101] A pixel anode layer 10 is deposited on the second planar layer 9, and the pixel anode layer 10 is deposited in contact with the second metal layer 7 in the third via hole 91.

[0102] In one embodiment, the preparing the electrode insulation combination 8 on the second metal layer 7 and the first flat layer 6 comprises:

[0103] depositing a first electrode insulation layer 81 on the second metal layer 7 and the first flat layer 6;

[0104] depositing a first electrode layer 82 on the first electrode insulation layer 81;

[0105] depositing a second electrode insulation layer 83 on the first electrode layer 82 and the first electrode insulation layer 81, and etching a fourth via hole 831 in the second electrode insulation layer 83, the fourth via hole 831 penetrating the first electrode layer 82 and the first electrode insulation layer 81 to expose a part of the second metal layer 7;

[0106] depositing a second electrode layer 84 on the second electrode insulation layer 83, the second electrode layer 84 being deposited in contact with the second metal layer 7 in the fourth via hole 831.

[0107] In one embodiment, the preparing the electrode insulation combination 8 on the second metal layer 7 and the first flat layer 6 further comprises:

[0108] depositing a pixel definition layer 110 on the second flat layer 9 and the pixel anode layer 10, and etching a fifth via hole 111 in the pixel definition layer 110, the fifth via hole 111 exposing a part of the pixel anode layer 10;

[0109] preparing a support layer 120 on the pixel definition layer 110.

[0110] In one embodiment, the preparing the gate insulation combination 3 on the substrate 1 and the active layer 2 comprises:

[0111] depositing a first gate insulation layer 31 on the active layer 2 and the substrate 1;

[0112] depositing a metal as a first gate layer 32 on the first gate insulation layer 31, and etching a pattern;

[0113] depositing a second gate insulation layer 33 on the first gate layer 32 and the first gate insulation layer 31;

[0114] depositing a metal as a second gate layer 34 on the first gate insulation layer 31, and etching a pattern.

[0115] Embodiments of the present application provide a display device, which comprises the display panel described in any of the above embodiments.

[0116] In the above embodiments, the description of each embodiment focuses on different aspects, and the parts not described in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0117] Any combination of the technical features in the above embodiments can be made. For the sake of brevity, not all possible combinations are described, however, it is understood that the scope of the present specification includes all possible combinations.

[0118] The display panel, manufacturing method and display device provided by the embodiments of the present application are described in detail above, and the principles and implementation manners of the present application are described by applying specific examples. The above embodiment descriptions are only used to help understand the method of the present application and its core idea. Meanwhile, for those skilled in the art, the specific implementation manners and application ranges can be changed according to the idea of the present application. In conclusion, the content of the present specification should not be understood as a limitation of the present application.

Claims

1. A display panel, characterized in that, include: substrate; An active layer is disposed on the substrate; A gate insulating assembly is disposed on the active layer and the substrate; An interlayer dielectric layer is disposed on the gate insulating assembly, the interlayer dielectric layer having a first via, and the first via penetrating the gate insulating assembly to expose a portion of the active layer; A first metal layer is disposed on the interlayer dielectric layer, and the first metal layer is deposited in the first via and contacts the active layer; A first planarization layer covers the first metal layer and the interlayer dielectric layer, and the first planarization layer has a second via, wherein the second via exposes a portion of the first metal layer; A second metal layer is disposed on the first planarization layer, and the second metal layer is deposited in the second via and contacts the first metal layer; An electrode insulating assembly is disposed on the second metal layer and the first planarization layer; A second planarization layer is disposed on the electrode insulation assembly, the second planarization layer having a third via, and the third via penetrating the electrode insulation assembly to expose a portion of the second metal layer; A pixel anode layer is disposed on the second planarization layer, and the pixel anode layer is deposited in the third via and contacts the second metal layer; The electrode insulation assembly includes: A first electrode insulating layer covers the second metal layer and the first planarization layer; The first electrode layer is disposed on the first electrode insulating layer; A second electrode insulating layer covers the first electrode layer and the first electrode insulating layer. The second electrode insulating layer is provided with a fourth via, and the fourth via penetrates the first electrode layer and the first electrode insulating layer to expose a portion of the second metal layer. The second electrode layer is disposed on the second electrode insulating layer, and the second electrode layer is deposited in the fourth via and contacts the second metal layer; The second planarization layer covers the first electrode layer, the first electrode insulating layer, the second electrode layer, and the second electrode insulating layer, and the third via penetrates the first electrode insulating layer and the second electrode insulating layer to expose a portion of the second metal layer; The first electrode layer and the second electrode layer are any one of ITO, IGZO, IZO, and IGZTO, and the first electrode layer and the second electrode layer are provided in the under-display camera area.

2. The display panel as described in claim 1, characterized in that, The first electrode insulating layer and the second electrode insulating layer comprise non-metallic films or organic films.

3. The display panel as described in claim 1, characterized in that, The first electrode layer and the second electrode layer are used as traces in the under-display camera area.

4. The display panel as described in claim 1, characterized in that, The area of ​​the second metal layer is larger than the area of ​​the first metal layer that is in contact with the second metal layer.

5. The display panel as described in claim 1, characterized in that, The gate insulation assembly includes: A first gate insulating layer covers the active layer and the substrate; The first gate layer is disposed on the first gate insulating layer; A second gate insulating layer, wherein the second gate insulating layer covers the first gate layer and the first gate insulating layer; The second gate layer is disposed on the first gate insulating layer; The interlayer dielectric layer covers the second gate layer and the second gate insulating layer, and the first via penetrates the first gate insulating layer and the second gate insulating layer to expose a portion of the active layer.

6. A method for manufacturing a display panel, characterized in that, include: A substrate is provided, and an active layer is formed on the substrate; A gate insulating assembly is fabricated on the substrate and the active layer; An interlayer dielectric layer is deposited on the gate insulating assembly, and a first via is etched on the interlayer dielectric layer, the first via penetrating the gate insulating assembly to expose a portion of the active layer; A first metal layer is deposited on the interlayer dielectric layer, and the first metal layer is deposited in the first via in contact with the active layer; A first planarization layer is deposited on the first metal layer and the interlayer dielectric layer, and a second via is etched on the first planarization layer, the second via exposing a portion of the first metal layer; A second metal layer is deposited on the first planarization layer, and the second metal layer is deposited in the second via in contact with the first metal layer; An electrode insulating assembly is fabricated on the second metal layer and the first planarization layer; A second planarization layer is deposited on the electrode insulating assembly, and a third via is etched on the second planarization layer, the third via penetrating the electrode insulating assembly to expose a portion of the second metal layer; A pixel anode layer is deposited on the second planarization layer, and the pixel anode layer is deposited in the third via in contact with the second metal layer; The fabrication of the electrode insulating assembly on the second metal layer and the first planarization layer specifically includes: A first electrode insulating layer is deposited on the second metal layer and the first planarization layer; A first electrode layer is deposited on the first electrode insulating layer; The step of fabricating an electrode insulating assembly on the second metal layer and the first planarization layer further includes: A second electrode insulating layer is deposited on the first electrode layer and the first electrode insulating layer, and a fourth via is etched on the second electrode insulating layer, the fourth via penetrating the first electrode layer and the first electrode insulating layer to expose a portion of the second metal layer; A second electrode layer is deposited on the second electrode insulating layer. The second electrode layer is deposited in the fourth via and contacts the second metal layer. The first electrode layer and the second electrode layer are provided in the under-display camera area.

7. A display device, characterized in that, The display device includes a display panel as described in any one of claims 1-5.

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