Wafer hotspot fixed layout cues through machine learning

Abstract

A system includes a machine learning model configured to: receive an input layout file including a portion of an integrated circuit layout having previously identified wafer hotspots; matching the previously identified wafer hotspot to one of a plurality of wafer hotspot type categories; and outputting a suggested layout modification associated with the matched wafer hotspot type category.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Non-Provisional Application No. 18 / 355,331, filed on July 19, 2023, in the U.S. Patent and Trademark Office, entitled “WAFER HOTSPOT-FIXING LAYOUT HINTS BY MACHINE LEARNING,” and is hereby incorporated by reference in its entirety for all purposes, which application claims priority to U.S. Provisional Application No. 63 / 419,872, filed on October 27, 2022. Background Art

[0003] Integrated circuit manufacturing involves a variety of detailed processes, including lithography and etching. As integrated circuit feature sizes decrease, integrated circuit layouts also shrink. Due to limitations in lithography and etching, defects may occur during the manufacture of integrated circuit dies on semiconductor wafers. For example, such manufacturing defects may include broken wires, shorts between adjacent wires, incompletely opened holes, and other similar defects. Such defects that are not caused by random processing variations between dies are referred to herein as "wafer hot spots."

[0004] Wafer hot spots can cause failed operation of an integrated circuit die and therefore must be corrected. Once a wafer hot spot has been identified, the traditional solution for an experienced layout engineer is to determine a suggested layout modification for eliminating the wafer hot spot and then run a simulation to verify that the suggested layout modification is satisfactory. This process is typically repeated through several time-consuming trial-and-error iterations before a corrected layout without wafer hot spots is obtained.

[0005] In addition to being very time consuming, this conventional technique requires a layout engineer to have a great deal of experience to successfully resolve wafer hot spots. As a result, less experienced layout engineers are often unable to correct wafer hot spots. Thus, fixing wafer hot spots presents many challenges. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Like numbered elements refer to common parts in different figures.

[0007] Figure 1 is a simplified diagram of an embodiment of a system for providing suggested layout modifications for eliminating previously identified wafer hot spots.

[0008] Figures 2A1 to 2E1 An example input layout file is depicted that depicts a portion of an integrated circuit layout that includes a previously identified wafer hotspot.

[0009] Figures 2A2 to 2E2 Depicted are the corresponding Figures 2A1 to 2E1The modified layout of the input layout file.

[0010] Figure 3A Depicted is a simplified block diagram of a training system for generating a trained machine learning model.

[0011] Figure 3B Depicted for use Figure 3A A simplified block diagram of a matching system for trained machine learning models.

[0012] Figure 4 is a simplified diagram of another embodiment of a system for providing suggested layout modifications for eliminating previously identified wafer hot spots.

[0013] FIG. 5A1 to FIG. 5C1 An example input layout file is depicted that depicts a portion of an integrated circuit layout that includes a previously identified wafer hotspot.

[0014] FIG. 5A2 to FIG. 5C2 Depicted are the corresponding FIG. 5A1 to FIG. 5C1 The modified layout of the input layout file.

[0015] Fig. 6A Depicted is a simplified block diagram of a training system for generating a trained machine learning model.

[0016] Figure 6B Depicted for use Fig. 6A A simplified block diagram of a matching system for trained machine learning models.

[0017] Figure 7 Depicted is an example graphical user interface that facilitates the training and implementation of a machine learning model for providing suggested layout modifications for eliminating previously identified wafer hotspots in an integrated circuit layout. DETAILED DESCRIPTION

[0018] Techniques are described for a machine learning system configured to: receive an input layout file including a portion of an integrated circuit layout having a previously identified wafer hotspot; match the previously identified wafer hotspot to one of a plurality of wafer hotspot type categories; and output a suggested layout modification associated with the matched wafer hotspot type category.

[0019] Without wishing to be bound by any particular theory, it is believed that such machine learning systems can facilitate the correction of wafer hot spots. Without wishing to be bound by any particular theory, it is believed that such machine learning systems can enable less experienced layout engineers to correct wafer hot spots more easily and quickly.

[0020] Figure 11 is a simplified diagram of an embodiment of a system 100 for providing suggested layout modifications for eliminating previously identified wafer hot spots. In one embodiment, the system 100 includes a machine learning model 102 configured to receive one or more input layout files 104 (e.g., input layout files 104-1, 104-2, ..., 104-m) and output a corresponding category indicator 106 for each input layout file 104. In one embodiment, the machine learning model 102 can be implemented on a computing device such as a computer, workstation, tablet computer, smart phone, or other similar computing device.

[0021] In one embodiment, each input layout file 104 depicts a portion of an integrated circuit layout that includes previously identified wafer hotspots. For example, a simulation tool or other technique may be used to identify wafer hotspots in a layout.

[0022] In one embodiment, the input layout file 104 includes a graphic design system (GDS) data file. GDS is a binary file format that represents layout data in a hierarchical format. The GDS file includes a pattern layout design. Those of ordinary skill in the art will appreciate that the input layout file 104 may include data in other file formats.

[0023] In one embodiment, the machine learning model 102 is an artificial neural network configured to analyze visual images. In one embodiment, the machine learning model 102 is a convolutional neural network.

[0024] In one embodiment, each input layout file 104 includes a hotspot tag 108 that specifies a wafer hotspot previously identified in the input layout file 104. For example, Figure 2A1 An example input layout file 104a is depicted that depicts a portion of an integrated circuit layout that includes a previously identified wafer hotspot. The example input layout file 104a includes a hotspot label 108a that specifies the previously identified wafer hotspot in the input layout file 104a. Figure 2A1 In the example depicted in , the hotspot label 108a is a shaded object, but other types of labels may be used.

[0025] Similarly, Figure 2B1 An example input layout file 104b is depicted that depicts a portion of an integrated circuit layout that includes a previously identified wafer hotspot. The example input layout file 104b includes a hotspot label 108b that specifies the previously identified wafer hotspot in the input layout file 104b.

[0026] same, Figures 2C1 to 2E1Example input layout files 104c-104e are depicted, respectively, where each input layout file depicts a portion of an integrated circuit layout including a previously identified wafer hotspot. The example input layout files 104c-104e include hotspot labels 108c-108e, respectively, which specify the previously identified wafer hotspots in the input layout files 104c-104e, respectively.

[0027] Reference again Figure 1 In one embodiment, the machine learning model 102 is an artificial neural network that is trained to receive an input layout file 104 and match previously identified wafer hotspots in the input layout file 104 to one of N wafer hotspot type categories. In one embodiment, each category has a corresponding category indicator 106 (e.g., one or more numbers, letters, symbols, or other similar indicia). For simplicity, the remainder of the description will use the phrase "matching category indicator 106" to refer to matching the category of a previously identified wafer hotspot.

[0028] In one embodiment, each category indicator 106 has an associated textual description of a suggested layout modification for eliminating the matching previously identified wafer hotspot from the layout. In one embodiment, the machine learning model 102 outputs the matching category indicators 106. In one embodiment, the machine learning model 102 additionally or alternatively outputs the textual description associated with the matching category indicators 106.

[0029] For example, a first category (category 1) may be associated with a suggested layout modification "create a fork," a second category (category 2) may be associated with a suggested layout modification "move the double crank and add an H-shape," a third category (category 3) may be associated with a suggested layout modification "create an H-shape," a fourth category (category 4) may be associated with a suggested layout modification "add a horizontal line to the edge," and so on, up to an Nth category (category N), which may be associated with a suggested layout modification "remove the small crank." In an embodiment, N may be 16 or some other number of wafer hotspot categories.

[0030] In an embodiment, each associated text description of a suggested layout modification is intended to facilitate elimination of a matching previously identified wafer hotspot. For example, a layout engineer may use the described suggested layout modification as a guide for modifying a layout to eliminate a previously identified wafer hotspot.

[0031] For example, Figure 2A1 The input layout file 104a includes a previously identified wafer hotspot specified by a hotspot label 108a. The previously identified wafer hotspot matches category 1, which has an associated text description of a suggested layout modification "create fork". Figure 2A2Depicted is a modified layout 200a, which is an example of the result of applying a suggested layout modification "Create Fork" to the input layout file 104a.

[0032] Figure 2B1 The input layout file 104b includes a previously identified wafer hotspot specified by a hotspot label 108b. The previously identified wafer hotspot matches category 2, which has an associated text description of the suggested layout modification "double crank move and add H-shape". Figure 2B2 Depicted is a modified layout 200b, which is an example of the result of applying the suggested layout modification "double crank move and add H-shape" to the input layout file 104b.

[0033] Fig.2C1 The input layout file 104c includes a previously identified wafer hotspot specified by a hotspot label 108c. The previously identified wafer hotspot matches category 3, which has an associated text description of a suggested layout modification "create an H-shape". Figure 2C2 Depicted is a modified layout 200c, which is an example of the result of applying the suggested layout modification "Create H-Shape" to the input layout file 104c.

[0034] Figure 2D1 The input layout file 104d includes a previously identified wafer hotspot specified by a hotspot label 108d. The previously identified wafer hotspot matches category 4, which has an associated text description of a suggested layout modification "add horizontal line to edge". Figure 2D2 Depicted is a modified layout 200d, which is an example of the result of applying the suggested layout modification "add horizontal line at margin" to the input layout file 104d.

[0035] Fig.2E1 The input layout file 104e includes a previously identified wafer hotspot specified by a hotspot label 108e. The previously identified wafer hotspot matches category N, which has an associated text description of a suggested layout modification "remove the small crank." Figure 2E2 Depicted is a modified layout 200e, which is an example of the result of applying the suggested layout modification "Remove Crank" to the input layout file 104e.

[0036] Reference again Figure 1 In one embodiment, the machine learning model 102 is trained to match previously identified wafer hotspots in one or more training input images to one of N wafer hotspot categories. Figure 3AA simplified block diagram of a training system 300a for training a machine learning model 102 to perform such matching is depicted. One of ordinary skill in the art will appreciate that some or all of the elements of the training system 300a may be implemented on a computing device such as a computer, workstation, tablet computer, smart phone, or other similar computing device.

[0037] In the illustrated embodiment, the training system 300a includes a first set of training layout files 304a and a second set of training layout files 304b. In one embodiment, the first set of training layout files 304a and the second set of training layout files 304b each include one or more input files, which may include GDS data.

[0038] In one embodiment, each input file in the first set of training layout files 304a has a corresponding input file in the second set of training layout files 304b. In one embodiment, the corresponding input files are related to the same portion of the integrated circuit layout, but the input files in the first set of training layout files 304a include wafer hotspots, while the corresponding input files in the second set of training layout files 304b do not include wafer hotspots. In other words, the input files in the second set of training layout files 304b include data related to a "corrected" version of the corresponding input files in the first set of training layout files 304a.

[0039] In one embodiment, input files from the first set of training layout files 304a are processed by a hotspot marking block 306, which is configured to specify wafer hotspots in each input layout file of the first set of training layout files 304a. In one embodiment, data output from the hotspot marking block 306 is input to an image generation block 310a, and data output from the second set of training layout files 304b is input to an image generation block 310b. In one embodiment, the image generation block 310a and the image generation block 310b are each configured to generate images in TIFF, BMP, JPG, JPEG, or PNG format, although other formats may be used.

[0040] In one embodiment, the outputs of image generation block 310a and image generation block 310b are corresponding images depicting the same portion of the integrated circuit layout, but the images output from image generation block 310a each include wafer hotspots, while the corresponding images output from image generation block 310b do not include wafer hotspots.

[0041] In one embodiment, the images from the image generation block 310a and the image generation block 310b are input to a convolutional neural network (CNN) training block 312, which is configured to generate a trained CNN model 314 from the received input image data. As is known in the art, convolutional neural networks are a type of artificial neural network most commonly applied to analyze visual images. In one embodiment, the CNN training block 312 is configured to generate a trained CNN model 314, which can be used to match previously identified wafer hot spots to one of the N wafer hot spot categories.

[0042] In one embodiment, the trained CNN model 314 can then be deployed to input a layout file (e.g., Figure 1 The previously identified wafer hotspots on the input layout file 104) are matched to one of the N wafer hotspot categories. Figure 3B Depicted is a simplified block diagram of a matching system 300b for performing such matching using a trained CNN model 314. One of ordinary skill in the art will appreciate that some or all of the elements of the matching system 300b may be implemented on a computing device such as a computer, workstation, tablet computer, smart phone, or other similar computing device.

[0043] Specifically, the matching system 300b includes Figure 3A The hotspot marking block 306, the image generation block 310a and the trained CNN model 314. In one embodiment, the input layout file 304c includes previously identified wafer hotspots and is input to the matching system 300b, which matches the previously identified wafer hotspots to one of the N wafer hotspot categories, as described above.

[0044] Figure 4 4 is a simplified diagram of an embodiment of a system 400 for providing suggested layout modifications for eliminating previously identified wafer hot spots. In one embodiment, the system 400 includes a machine learning model 402 configured to receive one or more input layout files 404 (e.g., input layout files 404-1, 404-2, ..., 404-j) and output a corresponding output image file 406 (e.g., output image files 406-1, 406-2, ..., 406-j) for each input image 404. In one embodiment, the machine learning model 402 can be implemented on a computing device such as a computer, workstation, tablet computer, smart phone, or other similar computing device.

[0045] In one embodiment, each input layout file 404 depicts a portion of the integrated circuit layout including a previously identified wafer hotspot. For example, a simulation tool or other technique may be used to identify wafer hotspots in the layout. In one embodiment, each output image file 406 depicts the same portion of the integrated circuit layout as depicted in the corresponding input layout file 404, but includes suggested changes to the integrated circuit layout to eliminate the previously identified wafer hotspot.

[0046] In one embodiment, the input layout file 404 includes a GDS data file. One of ordinary skill in the art will appreciate that the input layout file 404 may include data in other file formats.

[0047] In one embodiment, the machine learning model 402 is an image-to-image translation predictor, which is a type of artificial neural network configured to analyze visual images to perform pixel-by-pixel predictions. In the remaining description, the machine learning model 402 will also be referred to as the image-to-image translation predictor 402.

[0048] In one embodiment, image-to-image translation is the process of transforming an image from one domain to another, where the goal is to learn the mapping between the input image and the output image. This task has typically been performed using a training set of aligned image pairs.

[0049] In one embodiment, each input layout file 404 includes a hotspot tag 408 that specifies a wafer hotspot previously identified in the input layout file 404. For example, Figure 5A1 An example input layout file 404a is depicted that depicts a portion of an integrated circuit layout that includes a previously identified wafer hotspot. The example input layout file 404a includes a hotspot label 408a that specifies the previously identified wafer hotspot in the input layout file 404a. Figure 5A1 In the example depicted in , the hotspot label 408a is a shaded object, but other types of labels may be used.

[0050] Similarly, Figure 5B1 An example input layout file 404b is depicted that depicts a portion of an integrated circuit layout that includes a previously identified wafer hotspot. The example input layout file 404b includes a hotspot label 408b that specifies the previously identified wafer hotspot in the input layout file 404b.

[0051] same, Fig.5C1 An example input layout file 404b is depicted, depicting a portion of an integrated circuit layout including a previously identified wafer hotspot. An example input layout file 404c includes a hotspot label 408c that specifies a previously identified wafer hotspot in the input layout file 404c.

[0052] Reference again Figure 4 In one embodiment, the image-to-image translation predictor 402 is an artificial neural network that is trained to receive an input layout file 404, match previously identified wafer hotspots 408 in the input layout file 404 to the corrected layout portion, and generate a corresponding output image file 406 that depicts the same portion of the integrated circuit layout as depicted in the corresponding input layout file 404, but with suggested changes to the integrated circuit layout to eliminate the previously identified wafer hotspot. For example, a layout engineer can use the corresponding output image 406 as a guide for modifying the layout to eliminate the previously identified wafer hotspot.

[0053] For example, Figure 5A1 The input layout file 404a includes previously identified wafer hot spots specified by hot spot labels 408a. In one embodiment, the image-to-image translation predictor 402 receives the input layout file 404a, matches the previously identified wafer hot spots 408a to the corrected layout portion, and generates a corresponding output image file 406a ( Figure 5A2 ), which output image file depicts the same portion of the integrated circuit layout as depicted in the corresponding input layout file 404a, but with suggested changes to the integrated circuit layout to eliminate the previously identified wafer hotspots.

[0054] In another example, Figure 5B1 The input layout file 404b includes previously identified wafer hot spots specified by hot spot labels 408b. In one embodiment, the image-to-image translation predictor 402 receives the input layout file 404b, matches the previously identified wafer hot spots 408b to the corrected layout portion, and generates a corresponding output image file 406b ( Figure 5B2 ), which output image file depicts the same portion of the integrated circuit layout as depicted in the corresponding input layout file 404b, but with suggested changes to the integrated circuit layout to eliminate the previously identified wafer hotspots.

[0055] In yet another example, Fig.5C1 The input layout file 404c includes previously identified wafer hot spots specified by hot spot labels 408c. In one embodiment, the image-to-image translation predictor 402 receives the input layout file 404c, matches the previously identified wafer hot spots 408c to the corrected layout portion, and generates a corresponding output image file 406c ( Fig.5C2 ), which output image file depicts the same portion of the integrated circuit layout as depicted in the corresponding input layout file 404c, but with suggested changes to the integrated circuit layout to eliminate the previously identified wafer hotspots.

[0056] Reference again Figure 4In one embodiment, the image-to-image translation predictor 402 is trained to learn the mapping between input images and output images for eliminating previously identified wafer hot spots. Fig. 6A A simplified block diagram of a training system 600a for training the image-to-image translation predictor 402 to perform such a mapping is depicted. One of ordinary skill in the art will appreciate that some or all of the elements of the training system 600a may be implemented on a computing device such as a computer, workstation, tablet computer, smart phone, or other similar computing device.

[0057] In the illustrated embodiment, the training system 600a includes a first set of training layout files 604a and a second set of training layout files 604b. In one embodiment, the first set of training layout files 604a and the second set of training layout files 604b each include one or more input files, which may include GDS data.

[0058] In one embodiment, each input file in the first set of training layout files 604a has a corresponding input file in the second set of training layout files 604b. In one embodiment, the corresponding input files are related to the same portion of the integrated circuit layout, but the input files in the first set of training layout files 604a include wafer hotspots, while the corresponding input files in the second set of training layout files 604b do not include wafer hotspots. In other words, the input files in the second set of training layout files 604b include data related to a "corrected" version of the corresponding input files in the first set of training layout files 604a.

[0059] In one embodiment, the input files from the first set of training layout files 604a are processed by a hotspot marking block 606, which is configured to specify wafer hotspots in each input file of the first set of training layout files 604a. In one embodiment, the data output from the hotspot marking block 606 is input to an image generation block 610a, and the data output from the second set of training layout files 604b is input to an image generation block 610b. In one embodiment, the image generation block 610a and the image generation block 610b are each configured to generate images in TIFF, BMP, JPG, JPEG, or PNG format, although other formats may be used.

[0060] In one embodiment, the outputs of image generation block 610a and image generation block 610b are corresponding images depicting the same portion of the integrated circuit layout, but the images output from image generation block 610a both include wafer hotspots, while the corresponding images output from image generation block 610b do not include wafer hotspots.

[0061] In one embodiment, the images from the image generation block 610a and the image generation block 610b are input to an image merging block 612 configured to merge the input images together. The merged image file is input to an image training block 614 configured to generate a trained image model 616 from the received merged input image data. In one embodiment, the image training block 614 is configured to generate a trained image model 616 that can be used to match previously identified wafer hot spots to the corrected layout portions and generate a corresponding output image file with suggested changes to the integrated circuit layout to eliminate the previously identified wafer hot spots.

[0062] In one embodiment, the trained image model 616 can then be deployed to match the input layout file (e.g., Figure 4 The integrated circuit layout is configured to identify previously identified wafer hotspots on an input layout file 404 of the integrated circuit and generate a corresponding output image file with suggested changes to the integrated circuit layout to eliminate the previously identified wafer hotspots. Figure 6B A simplified block diagram of a matching system 600b for performing such matching using a trained image model 616 is depicted.

[0063] Specifically, the matching system 600b includes Fig. 6A The hotspot marking block 606, the image generation block 610a, and the trained image model 616. In one embodiment, the input layout file 604c includes previously identified wafer hotspots and is input to the matching system 600b, which matches the previously identified wafer hotspots and generates a corresponding output image file with suggested changes to the integrated circuit layout to eliminate the previously identified wafer hotspots, as described above. It will be understood by those of ordinary skill in the art that some or all of the elements of the matching system 600b can be implemented on a computing device such as a computer, workstation, tablet computer, smart phone, or other similar computing device.

[0064] The above-described example system may be implemented and include a graphical user interface (GUI) to facilitate training and implementation of a machine learning model for providing suggested layout modifications to eliminate previously identified wafer hotspots in an integrated circuit layout. Figure 7 An example of such a machine learning graphical user interface 700 is depicted. In one embodiment, the machine learning graphical user interface 700 includes a plurality of tabs 702 for implementing an example workflow for training a machine learning model, such as described above and in Figure 3A and Fig. 6A The example training system depicted in FIG. 1 and the example workflow for implementing a trained machine learning model, such as described above and in Figure 3B and Figure 6BThe example implementation system depicted in FIG.

[0065] For example, the first tab 702a (labeled as "hotspot tab") includes FIG. 3A to FIG. 3B The hotspot marker block 306 and FIG. 6A to FIG. 6B The second tab 702b (labeled "Image with Hotspots") includes various user settings related to the hotspot marking block 606 in FIG. FIG. 3A to FIG. 3B The image generation block 310a and FIG. 6A to FIG. 6B The third tab 702c (labeled "Image without hot spots") includes various user settings related to the image generation block 610a in FIG. Figure 3A The image generation block 310b and Fig. 6A The fourth tab 702d (labeled "Merge Image") includes various user settings related to the image generation block 610b in FIG. Fig. 6A The fifth tab (labeled “CNN Prediction”) includes various user settings related to the image merging block 612 in FIG. Figure 3A CNN training block 312 and Figure 3B The sixth tab (labeled "Image Prediction") includes various user settings related to hotspot matching in Fig. 6A The image training block 614 and Figure 6B Various user settings related to hotspot image prediction in .

[0066] Those skilled in the art will appreciate that other user interfaces may be used, that a graphical user interface having more or fewer than six tabs may be used, and that a graphical user interface including the Figure 7 The tabs are depicted in the different tabs of the graphical user interface.

[0067] One embodiment includes a system comprising a machine learning model configured to: receive an input layout file including a portion of an integrated circuit layout having a previously identified wafer hotspot; match the previously identified wafer hotspot to one of a plurality of wafer hotspot type categories; and output a suggested layout modification associated with the matched wafer hotspot type category.

[0068] One embodiment includes an apparatus comprising: a first block configured to specify a previously identified wafer hotspot in an input layout file including a portion of an integrated circuit layout, a second block configured to convert information from the input layout file to generate an image of the portion of the integrated circuit layout having the previously identified wafer hotspot, and a third block including a machine learning model configured to match the previously identified wafer hotspot to one of a plurality of wafer hotspot type categories.

[0069] One embodiment includes an apparatus comprising: a first block configured to specify a previously identified wafer hotspot in an input layout file including a portion of an integrated circuit layout, a second block configured to convert information from the input layout file to generate an image of the portion of the integrated circuit layout having the previously identified wafer hotspot, and a third block including an image-to-image translation predictor configured to match the previously identified wafer hotspot to a corrected portion of the integrated circuit layout.

[0070] For the purposes of this document, each process associated with the disclosed technology can be performed serially and by one or more computing devices. Each step in the process can be performed by the same or different computing device as the computing device used in other steps, and each step does not have to be performed by a single computing device.

[0071] For the purposes of this document, references in the specification to "one embodiment," "one embodiment," "some embodiments," or "another embodiment" may be used to describe different embodiments and are not necessarily referring to the same embodiment.

[0072] For the purposes of this document, a connection may be a direct connection or an indirect connection (eg, through another part).

[0073] For the purposes of this document, the term "group" of objects may refer to a "group" of one or more objects.

[0074] Although the subject matter has been described in language specific to structural features and / or methodological acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. A system, comprising: A machine learning system, the machine learning system being configured to: receiving an input layout file including a portion of an integrated circuit layout including a previously identified wafer hotspot; matching the previously identified wafer hotspot to one of a plurality of wafer hotspot type categories; as well as Suggested layout modifications associated with the matching wafer hotspot type categories are output. 2 . The system of claim 1 , wherein the image file includes a tag specifying the previously identified wafer hotspot.

3. The system of claim 1, wherein the image file comprises a graphic design system data file. 4 . The system of claim 1 , wherein each of the wafer hotspot type categories includes a respective category indicator. 5 . The system of claim 1 , wherein each of the wafer hotspot type categories includes a corresponding text description of the suggested layout modification.

6. The system of claim 1, wherein the machine learning system comprises a convolutional neural network.

7. The system of claim 1, wherein the machine learning system comprises an image-to-image translation predictor.

8. The system of claim 1, wherein the output comprises text.

9. The system of claim 1, wherein the output comprises an image.

10. The system of claim 1, wherein the machine learning system comprises a machine learning model trained to match previously identified wafer hotspots to one of N wafer hotspot categories.

11. The system of claim 1 , further comprising a graphical user interface configured to facilitate training and implementation of the machine learning system.

12. A device, comprising: a first block configured to specify a previously identified wafer hotspot in an input layout file comprising a portion of an integrated circuit layout; a second block configured to convert information from the input layout file to generate an image of the portion of the integrated circuit layout having the previously identified wafer hotspots; and A third block includes a machine learning model configured to match the previously identified wafer hotspot to one of a plurality of wafer hotspot type categories.

13. The apparatus of claim 12, wherein the input layout file comprises a graphic design system data file.

14. The apparatus of claim 12, wherein the image comprises TIFF, BMP, JPG, JPEG, or PNG data.

15. The apparatus of claim 12, wherein each of the wafer hotspot type categories includes a corresponding text description of the suggested layout modification.

16. The apparatus of claim 12, wherein the third block is configured to output a text description of the suggested layout modification.

17. The apparatus of claim 12, wherein the machine learning model comprises a convolutional neural network.

18. A device, comprising: a first block configured to specify a previously identified wafer hotspot in an input layout file comprising a portion of an integrated circuit layout; a second block configured to convert information from the input layout file to generate an image of the portion of the integrated circuit layout having the previously identified wafer hotspots; and A third block includes an image-to-image translation predictor configured to match the previously identified wafer hotspot to a corrected portion of the integrated circuit layout.

19. The apparatus of claim 18, wherein the third block is further configured to generate an output image file depicting the same portion of the integrated circuit layout as the portion depicted in the input layout file, but with suggested changes to eliminate the previously identified wafer hotspot.

20. The apparatus of claim 18, wherein the input layout file comprises a graphic design system data file.

Images