A chip testing method, system, medium and device

Abstract

The present invention discloses a chip testing method, system, medium and equipment, and relates to the field of chip testing electrical digital data processing technology. The method comprises the following steps: judging whether to perform aging test or repair on the chip according to the first performance comparison and analysis result of the chip; judging and determining the chip aging test process or repair according to the second performance comparison and analysis result of the chip; judging and determining the chip aging test result level according to the third performance comparison and analysis result of the chip. The present invention performs performance evaluation analysis, stability analysis evaluation and comprehensive test analysis evaluation on the dynamic random access memory chip respectively, and comprehensively judges the chip aging test result level according to the comparative analysis of the analysis and evaluation results and the corresponding threshold value, thereby achieving the effect of improving the accuracy of the dynamic random access memory chip aging test evaluation and judgment, and solving the problem of insufficient accuracy of the dynamic random access memory chip aging test evaluation and judgment in the prior art.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing electronic digital data processing, and in particular to a chip testing method, system, medium and equipment. Background Art

[0002] With the continuous advancement of information technology, the chip industry has broad prospects for development. In the future, with the application of emerging technologies such as artificial intelligence, the Internet of Things, and 5G, the performance requirements for chips will become higher and higher, which will put higher requirements on chip testing technology and equipment. Therefore, the development prospects of chip testing methods, systems, media, and equipment are also very broad.

[0003] Existing chip testing methods include analog testing, digital testing, mixed signal testing, etc. These testing methods and systems can ensure the quality of the chip by comprehensively testing the function, performance, reliability, etc. of the chip.

[0004] For example, the DRAM chip aging test equipment, method, computer equipment and storage medium announced in the invention patent with announcement number: CN111209152B include: an aging cabinet that provides environmental temperature control, a communication control module that connects to and controls the aging cabinet, and a test board for placing the tested DRAM chip. The test board includes an SSD master control module for testing the DRAM chip. The SSD master control module connects multiple DRAM chips for testing through a high-speed DRAM interface.

[0005] For example, the chip aging performance modeling method, system, device and storage medium announced in the invention patent with announcement number: CN112651210B include: performing accelerated testing on the target circuit module that affects chip performance to obtain test results; establishing a first functional relationship between the first performance parameter of the target circuit module and the time according to the test results; establishing a second functional relationship between the first performance parameter of the target circuit module and the second performance parameter of the chip when the chip is not aged; and establishing an aging performance model of the second performance parameter of the chip that changes with time according to the first functional relationship and the second functional relationship.

[0006] However, in the process of implementing the technical solution of the invention in the embodiments of the present application, the present application found that the above technology has at least the following technical problems:

[0007] In the prior art, the main problem with dynamic random access memory chips of major computer brands that are returned for after-sales repair is memory errors. The return rate is highest at the beginning because the internal structure of the chip is not yet stable in the early stage of chip aging; when the internal structure of the chip tends to be stable, it gradually becomes lower with use. During the aging test, the internal parameters of the chip are constantly changing, and there is a problem of insufficient accuracy in the evaluation and judgment of the dynamic random access memory chip aging test. Summary of the invention

[0008] The embodiments of the present application solve the problem of insufficient accuracy in evaluating and judging aging tests of dynamic random access memory chips in the prior art by providing a chip testing method, system, medium and device, thereby achieving the purpose of improving the accuracy of evaluating and judging aging tests of dynamic random access memory chips.

[0009] The embodiment of the present application provides a chip testing method, comprising the following steps: performing performance evaluation and analysis on a chip after initial activation to obtain a first chip evaluation and analysis result, comparing and analyzing the first chip evaluation and analysis result with a corresponding preset chip first evaluation and analysis threshold to obtain a first chip performance comparison and analysis result, and judging whether to perform an aging test or repair on the chip based on the first chip performance comparison and analysis result; performing stability analysis and evaluation on the chip undergoing the aging test to obtain a second chip evaluation and analysis result, comparing and analyzing the second chip evaluation and analysis result with a corresponding preset chip second evaluation and analysis threshold to obtain a second chip performance comparison and analysis result, and judging whether to perform an aging test or repair on the chip based on the second chip performance comparison and analysis result; performing comprehensive test analysis and evaluation on the chip to obtain a third chip evaluation and analysis result, comparing and analyzing the third chip evaluation and analysis result with a corresponding preset chip third evaluation and analysis threshold, and judging and determining the chip aging test result level based on the third chip performance comparison and analysis result.

[0010] Furthermore, the specific process of obtaining the first chip evaluation and analysis result is: collecting chip performance parameters of the dynamic random access memory chip after the initial activation through an electronic measuring instrument, and extracting the chip performance standard parameters of the dynamic random access memory chip from the dynamic random access memory chip database; obtaining the first chip evaluation and analysis result by analyzing and evaluating the chip performance parameters of the dynamic random access memory chip after the initial activation and the chip performance standard parameters of the dynamic random access memory chip; the first chip evaluation and analysis result is the chip activation performance negative evaluation index, and the chip activation performance negative evaluation index is used to represent the chip basic performance level after the dynamic random access memory chip is activated.

[0011] Furthermore, the specific process of obtaining the first chip performance comparison analysis result is: if the chip first evaluation analysis result is greater than the preset chip first evaluation analysis threshold, the corresponding chip is judged to be a defective product and the defective product is returned for repair; if the chip first evaluation analysis result is not greater than the preset chip first evaluation analysis threshold, the corresponding chip is judged to be a qualified product and the qualified product is subjected to aging test.

[0012] Furthermore, the specific process of obtaining the second evaluation and analysis result of the chip is: collecting chip performance parameters of the dynamic random access memory chip after the aging test through an electronic measuring instrument, and extracting the chip aging test performance standard parameters of the dynamic random access memory chip from the dynamic random access memory chip database; obtaining the chip aging stability negative evaluation integral value at different chip aging stability timing time points by analyzing and evaluating the chip performance parameters after the aging test of the dynamic random access memory chip and the chip aging test performance standard parameters of the dynamic random access memory chip; obtaining the second evaluation and analysis result of the chip according to the chip aging stability negative evaluation integral value; the second evaluation and analysis result of the chip is the chip aging stability evaluation index, and the chip aging stability evaluation index is used to represent the chip performance stability level during the aging process of the dynamic random access memory chip.

[0013] Furthermore, the specific process of obtaining the chip second performance comparison and analysis result is as follows: if the chip second performance comparison and analysis result is greater than a preset chip second evaluation and analysis threshold, the corresponding chip is judged to be a defective product, and the corresponding chip continues to be aged. After the unqualified chip is aged for a preset observation time, the chip second performance comparison and analysis result is compared with the preset chip second evaluation and analysis threshold again. If the corresponding chip second performance comparison and analysis result is still greater than the corresponding preset chip second evaluation and analysis threshold, the corresponding chip is judged to be a defective product, and the defective product is returned for repair; if the chip second performance comparison and analysis result is not greater than the preset chip second evaluation and analysis threshold, the corresponding chip is judged to be a qualified and stable product; the qualified and stable chip continues to be aged, and the chip second performance comparison and analysis result is compared with the preset chip second evaluation at each chip aging stability timing time point within the preset observation time of the qualified chip aging. Comparative analysis of the analysis threshold; if the corresponding chip second performance comparative analysis result at each chip aging stability timing time point within the preset observation time of qualified chip aging, is still not greater than the corresponding preset chip second evaluation analysis threshold, the corresponding chip is judged to be a first-level qualified and stable product, and the aging test is stopped; if the corresponding chip second performance comparative analysis result at any chip aging stability timing time point within the preset observation time of qualified chip aging, is greater than the corresponding preset chip second evaluation analysis threshold, the corresponding chip is judged to be an unqualified aging product, and the aging test is continued; after the unqualified chip has aged for the preset observation time, the chip second performance comparative analysis result and the preset chip second evaluation analysis threshold are compared and analyzed again on the unqualified aging product. If the corresponding chip second performance comparative analysis result is still greater than the corresponding preset chip second evaluation analysis threshold, the corresponding chip is judged to be an unqualified product, and the unqualified product is returned for repair.

[0014] Furthermore, the specific process of obtaining the third chip evaluation analysis result is: comprehensively analyzing the first chip performance comparison analysis result and the second chip performance comparison analysis result through an analysis formula to obtain the third chip evaluation analysis result. The specific analysis formula is as follows:

[0015] ;

[0016] Indicates the comprehensive fluctuation index of chip aging, which is the result of the third chip evaluation analysis; Indicates The chip aging stability evaluation index at each chip aging stability timing time point; Represents the negative evaluation index of chip activation performance; represents a natural constant, is the preset chip aging stability evaluation index weight factor obtained from the database, is the preset chip activation performance negative evaluation index weight factor obtained from the database, Indicates the number of the chip aging stability timing time point, , Indicates the total number of chip aging stability timing time points.

[0017] Furthermore, the specific process of determining the chip aging test result level based on the chip third performance comparison analysis result is as follows: the repaired chip is subjected to performance evaluation analysis and stability analysis again after the repair, and the corresponding chip first evaluation analysis result and chip second evaluation analysis result are obtained. If the chip first evaluation analysis result is greater than the preset chip first evaluation analysis threshold or the chip second evaluation analysis result is greater than the preset chip second evaluation analysis threshold, the chip aging test result level of the corresponding chip is set to a defective product; a first-level qualified and stable product is subjected to a comprehensive test analysis and evaluation. If the chip third evaluation analysis result of the first-level qualified and stable product is greater than the corresponding preset chip third evaluation analysis threshold, the chip aging test result level of the corresponding chip is still set to a first-level qualified and stable product; if the chip third evaluation analysis result of the first-level qualified and stable product is not greater than the corresponding preset chip third evaluation analysis threshold, the chip aging test result level of the corresponding chip is set to a second-level qualified and stable product.

[0018] The embodiment of the present application provides a chip testing system, including a chip performance evaluation and analysis module, a chip aging test evaluation and analysis module and a chip aging test level analysis and judgment module; the chip performance evaluation and analysis module is used to perform performance evaluation and analysis on the chip after initial activation to obtain a first chip evaluation and analysis result, compare and analyze the first chip evaluation and analysis result with a corresponding preset chip first evaluation and analysis threshold value to obtain a first chip performance comparison and analysis result, and determine whether to perform aging test or rework on the chip according to the first chip performance comparison and analysis result; the chip aging test evaluation and analysis module is used to perform stability analysis and evaluation on the chip to be tested for aging to obtain a second chip evaluation and analysis result, compare and analyze the second chip evaluation and analysis result with a corresponding preset chip second evaluation and analysis threshold value to obtain a second chip performance comparison and analysis result, and determine the chip aging test process or rework according to the second chip performance comparison and analysis result; the chip aging test level analysis and judgment module is used to perform comprehensive test analysis and evaluation on the chip to obtain a third chip evaluation and analysis result, compare and analyze the third chip evaluation and analysis result with a corresponding preset chip third evaluation and analysis threshold value, and determine the chip aging test result level according to the third chip performance comparison and analysis result.

[0019] An embodiment of the present application provides a computer-readable storage medium for storing a program, wherein the program implements a chip testing method when executed by a processor.

[0020] An embodiment of the present application provides an electronic device, including: automatic testing equipment and chip high-efficiency aging testing equipment; wherein the automatic testing equipment is used to perform performance evaluation and analysis on a chip after initial activation, to perform stability analysis and evaluation on a chip undergoing an aging test, and to perform comprehensive test analysis and evaluation on the chip; and the chip high-efficiency aging testing equipment is used to perform an aging test on the chip.

[0021] One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:

[0022] 1. By performing performance evaluation analysis, stability analysis evaluation and comprehensive test analysis evaluation on the dynamic random access memory chip respectively, the chip aging test result level is comprehensively judged based on the comparative analysis of the analysis evaluation results and the corresponding thresholds, thereby achieving the effect of improving the accuracy of the dynamic random access memory chip aging test evaluation and judgment, and solving the problem of insufficient accuracy of the dynamic random access memory chip aging test evaluation and judgment in the prior art.

[0023] 2. By comparing and analyzing the chip first evaluation analysis results with the corresponding preset chip first evaluation analysis thresholds, the chip first performance comparison analysis results are obtained, so that only chips that meet the first evaluation analysis results are subjected to aging testing, saving test time and avoiding defective products from entering the next step of the process and causing more serious consequences, thereby achieving the improvement of the overall efficiency of dynamic random access memory chip aging testing.

[0024] 3. Determine the chip aging test process or rework through the comparative analysis results of the chip's second performance, more accurately evaluate the chip's performance stability under long-term use, and ensure that only stable chips can be considered qualified products. Through grading evaluation, product quality can be more finely controlled, thereby achieving the accuracy of dynamic random access memory chip aging test grading. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A flowchart of a chip testing method provided in an embodiment of the present application;

[0026] Figure 2 A schematic diagram of a negative evaluation index function image of chip activation performance provided in an embodiment of the present application;

[0027] Figure 3 A schematic diagram of the structure of a chip testing system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The embodiments of the present application provide a chip testing method, system, medium and device to solve the problem of insufficient accuracy in the evaluation and judgment of aging test of dynamic random access memory chips in the prior art. By comparing the evaluation results with the corresponding thresholds and comprehensively judging the chip aging test result level, the accuracy of the evaluation and judgment of aging test of dynamic random access memory chips is improved.

[0029] The technical solution in the embodiment of the present application is to solve the above-mentioned problem of insufficient accuracy in the evaluation and judgment of the aging test of the dynamic random access memory chip. The overall idea is as follows:

[0030] By performing performance evaluation analysis, stability analysis evaluation and comprehensive test analysis evaluation on the dynamic random access memory chip respectively, the chip aging test result level is comprehensively judged based on the comparative analysis of the analysis evaluation results with the corresponding thresholds, thereby achieving the effect of improving the accuracy of the dynamic random access memory chip aging test evaluation judgment.

[0031] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0032] like Figure 1As shown, it is a flow chart of the chip testing method provided in an embodiment of the present application. The method is applied to a chip testing system, and the method includes the following steps: performing performance evaluation and analysis on the chip after initial activation to obtain a first evaluation and analysis result of the chip, comparing and analyzing the first evaluation and analysis result of the chip with the corresponding preset first evaluation and analysis threshold of the chip to obtain a first performance comparison and analysis result of the chip, and judging whether to perform an aging test or repair on the chip according to the first performance comparison and analysis result of the chip; performing stability analysis and evaluation on the chip undergoing the aging test to obtain a second evaluation and analysis result of the chip, comparing and analyzing the second evaluation and analysis result of the chip with the corresponding preset second evaluation and analysis threshold of the chip to obtain a second performance comparison and analysis result of the chip, and judging whether to perform an aging test or repair on the chip according to the second performance comparison and analysis result of the chip; performing comprehensive test analysis and evaluation on the chip to obtain a third evaluation and analysis result of the chip, comparing and analyzing the third evaluation and analysis result of the chip with the corresponding preset third evaluation and analysis threshold of the chip, and judging whether to determine the chip aging test result level according to the third performance comparison and analysis result of the chip.

[0033] Furthermore, the specific process of obtaining the first evaluation and analysis result of the chip is as follows: collecting chip performance parameters of the dynamic random access memory chip after the initial activation through electronic measuring instruments, and extracting the chip performance standard parameters of the dynamic random access memory chip from the dynamic random access memory chip database; obtaining the first evaluation and analysis result of the chip by analyzing and evaluating the chip performance parameters of the dynamic random access memory chip after the initial activation and the chip performance standard parameters of the dynamic random access memory chip; the first evaluation and analysis result of the chip is the chip activation performance negative evaluation index, and the chip activation performance negative evaluation index is used to represent the basic performance level of the chip after the dynamic random access memory chip is activated.

[0034] In this embodiment, the electronic measuring instrument includes a frequency meter, a signal generator, a logic analyzer and an oscilloscope;

[0035] The negative evaluation index of chip activation performance is obtained through analysis. The specific analysis formula is as follows:

[0036] ;

[0037] Set chip activation performance monitoring points and number them in sequence. Indicates the number of the chip activation performance monitoring point. , Indicates the total number of chip activation performance monitoring points.

[0038] Represents the negative evaluation index of chip activation performance.

[0039] Indicates The tRAS value of the dynamic random access memory chip of each chip activation performance monitoring point, in nanoseconds; Indicates The DRAM chip preset standard tRAS value of each chip activation performance monitoring point is in nanoseconds.

[0040] tRAS (Row Active Time): It indicates the time from the start of a new read / write operation of the chip memory to the start of the next same read / write operation, that is, the time from the start of a chip memory request to the start of the next request, including the chip memory row activation time and the chip memory row recovery time.

[0041] Indicates The tRCD value of the dynamic random access memory chip of each chip activation performance monitoring point, in nanoseconds; Indicates The DRAM chip preset standard tRCD value of each chip activation performance monitoring point is in nanoseconds.

[0042] tRCD (Row to Column Delay): Indicates how long it takes to read or write data after a memory row of the chip memory is activated, that is, the time interval from chip memory row activation to chip memory column selection.

[0043] Indicates The tRP value of the dynamic random access memory chip for each chip activation performance monitoring point, in nanoseconds; Indicates The DRAM chip preset standard tRP value of each chip activation performance monitoring point is in nanoseconds.

[0044] tRP (Row Precharge Time): Indicates the time required for the chip memory to end a read / write operation and set the row to an invalid state, that is, the time between the chip memory ending the current read / write operation and starting a new read / write operation.

[0045] Through memory testing programs or professional memory testing tools, such as memtest86+ software, a series of tests can be performed on the chip memory, and the measurement results of various chip parameters including tRAS, tRCD and tRP can be provided; or the chip output waveform can be analyzed through a logic analyzer to obtain the measurement results of various chip parameters including tRAS, tRCD and tRP.

[0046] According to JEDEC standards and / or factory design specifications (the test is set to the median of the normal distribution) and / or according to customer preset parameters (customer-specified test requirements, tighten the test standard for a certain parameter to obtain the preset standard tRAS value of the dynamic random access memory chip, the preset standard tRCD value of the dynamic random access memory chip, and the preset standard tRP value of the dynamic random access memory chip.

[0047] like Figure 2 As shown, it is a schematic diagram of the negative evaluation index function of chip activation performance provided in an embodiment of the present application; if the tRP value of the dynamic random access memory chip is used as the dependent variable, if the negative evaluation index of chip activation performance is used as the independent variable;

[0048] Among them, the function curve middle, ,express and , function curve Indicates when and Schematic diagram of the negative evaluation exponential function curve of the chip activation performance at .

[0049] Function Curve middle, ,express and , function curve Indicates when and Schematic diagram of the negative evaluation exponential function curve of the chip activation performance at .

[0050] Function Curve middle, ,express and , function curve Indicates when and Schematic diagram of the negative evaluation exponential function curve of the chip activation performance at .

[0051] As can be seen from the figure, when The value of is the same as When the values ​​are different, The larger the value, that is, the larger the preset standard tRP value of the dynamic random access memory chip, which means that the preset standard tRP value of the dynamic random access memory chip is set more loosely, the slower the growth trend of the chip activation performance negative evaluation index is, and the smaller the chip activation performance negative evaluation index corresponding to the same dynamic random access memory chip tRP value is.

[0052] As can be seen from the figure, when The value of is the same as When the values ​​are different, The larger the value is, the higher the relative ratio of the dynamic random access memory chip tRAS value and the dynamic random access memory chip tRCD value to the corresponding preset values, that is, the lower the degree to which the dynamic random access memory chip tRAS value and the dynamic random access memory chip tRCD value meet the corresponding preset values, the larger the starting value of the chip activation performance negative evaluation index is, and the larger the chip activation performance negative evaluation index corresponding to the same dynamic random access memory chip tRP value is.

[0053] Comprehensively evaluate and analyze the above parameters. When the performance parameters of the dynamic random access memory chip meet or even exceed the corresponding performance parameter requirements, the negative evaluation index of the chip activation performance is smaller. Conversely, when the performance parameters of the dynamic random access memory chip do not meet or are far less than the corresponding performance parameter requirements, the negative evaluation index of the chip activation performance is larger. The performance parameters of the dynamic random access memory chip will fluctuate during the initial activation of the chip and the subsequent aging process, but can still be used as quantitative evaluation indicators for subsequent judgment of the chip performance level.

[0054] Furthermore, the specific process of obtaining the first chip performance comparison analysis result is: if the chip first evaluation analysis result is greater than the preset chip first evaluation analysis threshold, the corresponding chip is judged to be a defective product and the defective product is returned for repair; if the chip first evaluation analysis result is not greater than the preset chip first evaluation analysis threshold, the corresponding chip is judged to be a qualified product and the qualified product is subjected to aging test.

[0055] In this embodiment, the dynamic random access memory chip can be aged after being activated. The preset chip first evaluation and analysis threshold is a preset threshold obtained from a database.

[0056] Furthermore, the specific process of obtaining the second evaluation and analysis result of the chip is as follows: collecting chip performance parameters of the dynamic random access memory chip after the aging test through an electronic measuring instrument, and extracting the chip aging test performance standard parameters of the dynamic random access memory chip from the dynamic random access memory chip database; obtaining the chip aging stability negative evaluation integral value at different chip aging stability timing time points by analyzing and evaluating the chip performance parameters after the aging test of the dynamic random access memory chip and the chip aging test performance standard parameters of the dynamic random access memory chip; obtaining the second evaluation and analysis result of the chip according to the chip aging stability negative evaluation integral value; the second evaluation and analysis result of the chip is the chip aging stability evaluation index; the chip aging stability evaluation index is used to indicate the chip performance stability level during the aging process of the dynamic random access memory chip; the chip aging stability negative evaluation integral value is used to indicate the chip performance negative impact level during the aging process of the dynamic random access memory chip.

[0057] In this embodiment, in the early stage of aging of the dynamic random access memory chip, the internal structure of the chip is not yet stable, and the fluctuation index value is relatively high, which is regarded as a high-speed change phenomenon inside the dynamic random access memory chip;

[0058] When the internal structure of the dynamic random access memory chip tends to be stable, its chip aging stability evaluation index will be equal to 0 or close to 0; the chip aging stability evaluation index is obtained through an analysis formula, and the specific analysis formula is as follows:

[0059] ;

[0060] ;

[0061] Set the chip aging stability timing time points, and number the chip aging stability timing time points in sequence. Indicates the chip aging stability timing time point in minutes.

[0062] Indicates the number of the chip aging stability timing time point, , Indicates the total number of chip aging stability timing time points.

[0063] Indicates Chip aging stability timing time point, Indicates Chip aging stability timing time point, Indicates A chip aging stability timing time point.

[0064] Set chip aging stability monitoring points and number them in sequence. Indicates the number of the chip aging stability monitoring point, , Indicates the total number of chip aging stability monitoring points. The chip aging stability monitoring points are monitoring points of different storage areas or different storage particles in the dynamic random access memory chip.

[0065] Indicates The chip aging stability timing time point is The chip aging stability negative evaluation integral value between the chip aging stability timing time points.

[0066] Indicates The chip aging stability evaluation index at each chip aging stability timing time point.

[0067] Indicates the upper limit of the preset chip aging stability integral range.

[0068] Indicates The tCL value of the dynamic random access memory chip at each chip aging stability monitoring point, in nanoseconds.

[0069] Indicates tSU-D value of the dynamic random access memory chip for each chip activation performance monitoring point, in nanoseconds.

[0070] Indicates tWR value of the DRAM chip with each chip activating a performance monitoring point, in nanoseconds.

[0071] Indicates tDRT value of the dynamic random access memory chip when the chip activates the performance monitoring point, in nanoseconds. Indicates The DRAM chip preset standard tDRT value of each chip activation performance monitoring point is in nanoseconds.

[0072] tCL (Column Latency) refers to the time from column selection to data transmission completion of a dynamic random access memory chip, that is, the column access time.

[0073] tSU-D (Data Setup Time before Deassertion of OE) data setup time refers to the time it takes to stabilize the data in the internal circuit of the chip before writing data into the dynamic random access memory chip, by pulling down the chip's output enable signal (OE) to a level that prohibits outputting data, and then pulling up the OE signal after the new data on the data line is stable.

[0074] tWR (Write Recovery Time): Indicates how long it takes for the dynamic random access memory chip to be ready to receive the next write operation after writing data.

[0075] tDRT (Data Retention Time): Indicates the time that data is retained in the dynamic random access memory chip after the memory power is turned off.

[0076] Automated test equipment (ATE) can be used to test dynamic random access memory chips and obtain performance parameters including tCL, tSU-D, tWR, and tDRT.

[0077] When a dynamic random access memory chip is aged, its internal performance parameters fluctuate greatly. After a period of time, its internal structure becomes stable. If only the instantaneous value of its internal performance is judged, it is easy to misjudge the actual state of the chip's aging stability. The comprehensive negative performance integral level within two adjacent chip aging stability timing time points should be evaluated to make the aging stability evaluation of the dynamic random access memory chip more accurate.

[0078] Furthermore, the specific process of obtaining the chip second performance comparison analysis result is as follows: if the chip second performance comparison analysis result is greater than the preset chip second evaluation analysis threshold, the corresponding chip is judged to be a defective product, the corresponding chip is continued to be aged, and after the unqualified chip is aged for a preset observation time, the chip second performance comparison analysis result is compared with the preset chip second evaluation analysis threshold again; if the corresponding chip second performance comparison analysis result is still greater than the corresponding preset chip second evaluation analysis threshold, the corresponding chip is judged to be a defective product, and the defective product is returned for repair; if the chip second performance comparison analysis result is not greater than the preset chip second evaluation analysis threshold, the corresponding chip is judged to be a qualified and stable product; the qualified and stable chip is continued to be aged, and the chip second performance comparison analysis result is compared with the preset chip second evaluation analysis threshold again at each chip aging stability timing time point within the preset observation time of qualified chip aging. If the corresponding chip second performance comparison analysis result at each chip aging stability timing time point within the preset observation time of qualified chip aging is still not greater than the corresponding preset chip second evaluation analysis threshold, the corresponding chip is judged to be a first-level qualified stable product, and the aging test is stopped; if the corresponding chip second performance comparison analysis result at any chip aging stability timing time point within the preset observation time of qualified chip aging is greater than the corresponding preset chip second evaluation analysis threshold, the corresponding chip is judged to be an unqualified aging product, and the aging test is continued; after the unqualified chip has aged for the preset observation time, the chip second performance comparison analysis result and the preset chip second evaluation analysis threshold are compared and analyzed on the unqualified aging product again. If the corresponding chip second performance comparison analysis result is still greater than the corresponding preset chip second evaluation analysis threshold, the corresponding chip is judged to be an unqualified product, and the unqualified product is returned for repair.

[0079] In this embodiment, the preset chip second evaluation analysis threshold, the preset aging observation time of unqualified chips, and the preset aging observation time of qualified chips can all be obtained from the database.

[0080] In a specific real-time example, the natural aging time of a dynamic random access memory chip enters the stable operation period after 3-6 months. If the memory accelerated aging technology equivalent to 30-50 times is used, a 3-6-day aging test can achieve a 3-6-month natural aging effect, and the preset observation time for qualified chip aging can be set to 3 days.

[0081] Furthermore, the specific process of obtaining the third chip evaluation analysis result is: comprehensively analyzing the first chip performance comparison analysis result and the second chip performance comparison analysis result through an analysis formula to obtain the third chip evaluation analysis result. The specific analysis formula is as follows:

[0082] ;

[0083] Indicates the comprehensive fluctuation index of chip aging, which is the result of the third chip evaluation analysis; Indicates The chip aging stability evaluation index at each chip aging stability timing time point; Represents the negative evaluation index of chip activation performance; represents a natural constant, is the preset chip aging stability evaluation index weight factor obtained from the database, is the preset chip activation performance negative evaluation index weight factor obtained from the database, , Indicates the number of the chip aging stability timing time point, , Indicates the total number of chip aging stability timing time points.

[0084] In a specific embodiment, a mapping set is established through the relationship between the chip aging stability evaluation index and the chip aging comprehensive volatility index in the historical index data, and the real-time chip activation performance negative evaluation index is input into the pre-set mapping set to obtain the corresponding chip aging stability evaluation index weight factor.

[0085] In a specific embodiment, a mapping set is established through the relationship between the chip activation performance negative evaluation index and the chip aging comprehensive fluctuation index in the historical index data, and the real-time chip activation performance negative evaluation index is input into the pre-set mapping set to obtain the corresponding chip activation performance negative evaluation index weight factor.

[0086] The chip aging comprehensive fluctuation index data example table is shown in Table 1.

[0087] Table 1 Example of chip aging comprehensive fluctuation index data

[0088]

[0089] The chip aging stability evaluation index in Table 1 is a single example value at the chip aging stability timing time point. According to the different preset chip first evaluation analysis thresholds in practice, if the chip activation performance negative evaluation index fails to pass the comparative analysis with the corresponding preset chip first evaluation analysis threshold, the chip aging stability evaluation index cannot be further evaluated. When the chip aging stability evaluation index passes the comparative analysis with the preset chip second evaluation analysis threshold in practice, the corresponding chip can be judged as a qualified product. However, according to the actual business standard setting, by adjusting the preset weight factor, the final chip aging comprehensive fluctuation index and the preset chip third evaluation analysis threshold comparative analysis results are in line with the expected business classification requirements, thereby improving the accuracy of dynamic random access memory chip aging test classification.

[0090] Furthermore, the specific process of determining the chip aging test result level according to the chip third performance comparison analysis result is as follows: the repaired chip is subjected to performance evaluation analysis and stability analysis again after the repair, and the corresponding chip first evaluation analysis result and chip second evaluation analysis result are obtained. If the chip first evaluation analysis result is greater than the preset chip first evaluation analysis threshold or the chip second evaluation analysis result is greater than the preset chip second evaluation analysis threshold, the chip aging test result level of the corresponding chip is set to defective product; a first-level qualified and stable product is subjected to comprehensive test analysis and evaluation. If the chip third evaluation analysis result of the first-level qualified and stable product is greater than the corresponding preset chip third evaluation analysis threshold, the chip aging test result level of the corresponding chip is still set to the first-level qualified and stable product; if the chip third evaluation analysis result of the first-level qualified and stable product is not greater than the corresponding preset chip third evaluation analysis threshold, the chip aging test result level of the corresponding chip is set to the second-level qualified and stable product.

[0091] In summary, the specific process of obtaining the chip aging test result hierarchy is also the chip aging test quality grading method. By comparing the evaluation analysis at three different levels with the corresponding preset evaluation thresholds, it is helpful to discover potential quality problems at an early stage, so as to take measures to repair or eliminate them. At the same time, the chips can be accurately divided into different levels. According to actual business requirements, the corresponding preset thresholds can be adjusted to better control the quality and classification of products. The re-grading of qualified products makes the first-level qualified and stable products and the second-level qualified and stable products applicable to a wider range of businesses. Through multi-dimensional performance analysis, the stability and reliability of product quality are ensured, while improving production efficiency and market competitiveness.

[0092] like Figure 3As shown, it is a structural schematic diagram of the chip testing system provided in the embodiment of the present application. The chip testing system provided in the embodiment of the present application includes: a chip performance evaluation and analysis module, a chip aging test evaluation and analysis module and a chip aging test level analysis and judgment module; the chip performance evaluation and analysis module is used to perform performance evaluation and analysis on the chip after the initial activation, obtain the first chip evaluation and analysis result, compare and analyze the first chip evaluation and analysis result with the corresponding preset chip first evaluation and analysis threshold value, obtain the first chip performance comparison and analysis result, and judge whether to perform aging test or rework on the chip according to the first chip performance comparison and analysis result; the chip aging test evaluation and analysis module is used to perform stability analysis and evaluation on the chip under aging test, obtain the second chip evaluation and analysis result, compare and analyze the second chip evaluation and analysis result with the corresponding preset chip second evaluation and analysis threshold value, obtain the second chip performance comparison and analysis result, and determine the chip aging test process or rework according to the second chip performance comparison and analysis result; the chip aging test level analysis and judgment module is used to perform comprehensive test analysis and evaluation on the chip, obtain the third chip evaluation and analysis result, compare and analyze the third chip evaluation and analysis result with the corresponding preset chip third evaluation and analysis threshold value, and determine the chip aging test result level according to the third chip performance comparison and analysis result.

[0093] An embodiment of the present application also provides a computer-readable storage medium for storing a program, which implements a chip testing method when the program is executed by a processor.

[0094] An embodiment of the present application provides an electronic device, including: automatic testing equipment and chip high-efficiency aging testing equipment; wherein the automatic testing equipment is used to perform performance evaluation and analysis on the chip after initial activation, to perform stability analysis and evaluation on the chip undergoing aging test, and to perform comprehensive test analysis and evaluation on the chip; the chip high-efficiency aging testing equipment is used to perform aging test on the chip.

[0095] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0096] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A system that specifies the functions of a box or multiple boxes.

[0097] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction system, which is implemented in the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0098] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0099] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0100] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A chip testing method, characterized in that: The following steps are involved: Performing performance evaluation and analysis on the chip after initial activation to obtain a first evaluation and analysis result of the chip, comparing and analyzing the first evaluation and analysis result of the chip with a corresponding preset first evaluation and analysis threshold of the chip to obtain a first performance comparison and analysis result of the chip, and judging whether to perform an aging test or return the chip for repair according to the first performance comparison and analysis result of the chip; Perform stability analysis and evaluation on the chip undergoing the aging test to obtain a second chip evaluation analysis result, compare and analyze the second chip evaluation analysis result with the corresponding preset chip second evaluation analysis threshold to obtain a second chip performance comparison analysis result, and determine the chip aging test process or rework based on the second chip performance comparison analysis result; Perform comprehensive test analysis and evaluation on the chip to obtain the third evaluation analysis result of the chip, compare and analyze the third evaluation analysis result of the chip with the corresponding preset third evaluation analysis threshold of the chip, and determine the chip aging test result level according to the third performance comparison analysis result of the chip; The specific process of obtaining the third chip evaluation analysis result is as follows: The chip first performance comparison analysis results and the chip second performance comparison analysis results are comprehensively analyzed through an analysis formula to obtain the chip third evaluation analysis results. The specific analysis formula is as follows: ； It indicates the comprehensive fluctuation index of chip aging, which is the result of the third chip evaluation analysis. Indicates The chip aging stability evaluation index at each chip aging stability timing time point; Represents the negative evaluation index of chip activation performance; represents a natural constant, is the preset chip aging stability evaluation index weight factor obtained from the database, is the preset chip activation performance negative evaluation index weight factor obtained from the database, Indicates the number of the chip aging stability timing time point, , Indicates the total number of chip aging stability timing time points.

2. The chip testing method according to claim 1, characterized in that: The specific process of obtaining the first chip evaluation and analysis result is as follows: Collect chip performance parameters of the dynamic random access memory chip after initial activation by an electronic measuring instrument, and extract chip performance standard parameters of the dynamic random access memory chip from a dynamic random access memory chip database; Obtaining a first chip evaluation analysis result by analyzing and evaluating chip performance parameters of the dynamic random access memory chip after initial activation and chip performance standard parameters of the dynamic random access memory chip; The first chip evaluation analysis result is a chip activation performance negative evaluation index, and the chip activation performance negative evaluation index is used to indicate a basic chip performance level after the dynamic random access memory chip is activated.

3. The chip testing method according to claim 1, characterized in that: The specific process of obtaining the first chip performance comparison analysis result is as follows: If the chip first evaluation analysis result is greater than the preset chip first evaluation analysis threshold, the corresponding chip is judged to be a defective product and the defective product is returned for repair; If the chip first evaluation analysis result is not greater than the preset chip first evaluation analysis threshold, the corresponding chip is judged to be a qualified product, and the qualified product is subjected to an aging test.

4. The chip testing method according to claim 1, characterized in that: The specific process of obtaining the second chip evaluation and analysis result is as follows: Collect chip performance parameters of the dynamic random access memory chip after aging test by electronic measuring instruments, and extract chip aging test performance standard parameters of the dynamic random access memory chip from a dynamic random access memory chip database; By analyzing and evaluating the chip performance parameters after the aging test of the dynamic random access memory chip and the chip aging test performance standard parameters of the dynamic random access memory chip, the negative evaluation integral value of the chip aging stability at different chip aging stability timing time points is obtained; The second chip evaluation analysis result is obtained according to the chip aging stability negative evaluation integral value analysis; The second chip evaluation and analysis result is the chip aging stability evaluation index, which is used to indicate the chip performance stability level during the aging process of the dynamic random access memory chip.

5. The chip testing method according to claim 1, characterized in that: The specific process of obtaining the second chip performance comparison analysis result is as follows: If the chip second performance comparison analysis result is greater than the preset chip second evaluation analysis threshold, the corresponding chip is judged to be a defective product, and the corresponding chip is further aged. After the preset observation time of aging of the unqualified chip, the chip second performance comparison analysis result is again compared and analyzed with the preset chip second evaluation analysis threshold. If the corresponding chip second performance comparison analysis result is still greater than the corresponding preset chip second evaluation analysis threshold, the corresponding chip is judged to be a defective product and the defective product is returned for repair. If the chip second performance comparison analysis result is not greater than the preset chip second evaluation analysis threshold, the corresponding chip is judged to be a qualified and stable product. The qualified stable chips are further aged, and at each chip aging stability timing time point within the preset observation time of the qualified chip aging, the chip second performance comparison analysis result is again compared and analyzed with the preset chip second evaluation analysis threshold; If the corresponding chip second performance comparison analysis result at each chip aging stability timing time point within the preset observation time of qualified chip aging is still not greater than the corresponding preset chip second evaluation analysis threshold, the corresponding chip is judged to be a first-level qualified stable product, and the aging test is stopped; If the corresponding chip second performance comparison analysis result at any chip aging stability timing time point within the preset observation time of qualified chip aging is greater than the corresponding preset chip second evaluation analysis threshold, the corresponding chip is judged as an unqualified aging product and the aging test is continued; After the unqualified chip is aged for a preset observation time, the chip second performance comparison analysis results of the unqualified aged product are compared and analyzed again with the preset chip second evaluation analysis threshold. If the corresponding chip second performance comparison analysis result is still greater than the corresponding preset chip second evaluation analysis threshold, the corresponding chip is judged to be an unqualified product and the unqualified product is returned for repair.

6. The chip testing method according to claim 1, characterized in that: The specific process of determining the chip aging test result level according to the chip third performance comparison analysis result is as follows: After the repair, the chip is subjected to performance evaluation and stability analysis again to obtain the corresponding chip first evaluation analysis result and chip second evaluation analysis result. If the chip first evaluation analysis result is greater than the preset chip first evaluation analysis threshold or the chip second evaluation analysis result is greater than the preset chip second evaluation analysis threshold, the chip aging test result level of the corresponding chip is set to defective; Perform comprehensive test analysis and evaluation on the first-level qualified and stable products. If the chip third evaluation analysis result of the first-level qualified and stable products is greater than the corresponding preset chip third evaluation analysis threshold, the chip aging test result level of the corresponding chip is still set to the first-level qualified and stable products; If the third evaluation analysis result of the chip of the first-level qualified and stable product is not greater than the corresponding preset chip third evaluation analysis threshold, the chip aging test result level of the corresponding chip is set to the second-level qualified and stable product.

7. A chip testing system, characterized in that: The chip testing system comprises: a chip performance evaluation and analysis module, a chip aging test evaluation and analysis module and a chip aging test level analysis and judgment module; The chip performance evaluation and analysis module is used to perform performance evaluation and analysis on the chip after initial activation to obtain a first chip evaluation and analysis result, compare and analyze the first chip evaluation and analysis result with a corresponding preset chip first evaluation and analysis threshold to obtain a first chip performance comparison and analysis result, and determine whether to perform an aging test or return the chip for repair based on the first chip performance comparison and analysis result; The chip aging test evaluation and analysis module is used to perform stability analysis and evaluation on the chip under aging test, obtain a second chip evaluation and analysis result, compare and analyze the second chip evaluation and analysis result with the corresponding preset chip second evaluation and analysis threshold, obtain a second chip performance comparison and analysis result, and determine the chip aging test process or rework according to the second chip performance comparison and analysis result; The chip aging test level analysis and judgment module is used to perform comprehensive test analysis and evaluation on the chip, obtain the chip third evaluation analysis result, compare and analyze the chip third evaluation analysis result with the corresponding preset chip third evaluation analysis threshold, and determine the chip aging test result level based on the chip third performance comparison analysis result.

8. A computer-readable storage medium for storing a program, characterized in that: When the program is executed by a processor, the chip testing method as described in any one of claims 1 to 6 is implemented.

9. An electronic device, characterized in that: The electronic device implements the chip testing method as claimed in any one of claims 1 to 6, comprising: automatic testing equipment and chip high-efficiency aging testing equipment; The automatic test equipment is used to perform performance evaluation and analysis on the chip after initial activation, stability analysis and evaluation on the chip during aging test, and comprehensive test and analysis and evaluation on the chip; The chip high-efficiency aging test equipment is used for performing aging test on chips.

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