Bandgap reference circuit, chip and electronic device

Abstract

The embodiment of the application provides a band gap reference circuit, a chip and an electronic device, the band gap reference circuit comprises: a voltage output module, a switched capacitor module and an integration module, the voltage output module is used for outputting a first voltage and a second voltage, the first voltage and the second voltage are negatively related to an absolute temperature, and a first voltage difference between the first voltage and the second voltage is positively related to the absolute temperature; the switched capacitor module is used for outputting a first temperature coefficient voltage and a first temperature coefficient charge according to the first voltage and the second voltage; and the integration module is used for outputting a reference voltage irrelevant to the absolute temperature according to the first temperature coefficient voltage and the first temperature coefficient charge. The application outputs the reference voltage in the mode of accessing the negative temperature coefficient voltage and integrating the positive temperature coefficient charge, can reduce the influence of the offset voltage of the first operational amplifier on the reference voltage, and finally is beneficial to improving the precision of the band gap reference voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a bandgap reference circuit, a chip and an electronic device. BACKGROUND

[0002] A bandgap reference circuit (BGR) can output a reference voltage that is substantially independent of power supply voltage, process and temperature. Based on its unique advantages, the circuit is widely used in various systems (such as voltage regulators, analog-to-digital converters, data acquisition systems, digital-to-analog converters, MCUs) to provide a stable reference voltage for the system.

[0003] In related technologies, the bandgap reference circuit usually uses the virtual short and virtual open characteristics of the operational amplifier to clamp and output the reference voltage. However, due to the asymmetry of the internal components of the operational amplifier, the deviation of the manufacturing process and the influence of the external environment, the operational amplifier usually has a deviation voltage. The deviation voltage causes the operational amplifier to not accurately clamp the phase node potential to be equal, which leads to the problem of decreased accuracy of the reference voltage output by the bandgap reference circuit. SUMMARY

[0004] In view of the above problems, the embodiments of the present application provide a bandgap reference circuit, a chip and an electronic device to solve the above technical problems.

[0005] In a first aspect, the embodiments of the present application provide a bandgap reference circuit, comprising:

[0006] A voltage output module, the voltage output module comprising a first operational amplifier, the voltage output module being configured to output a first voltage and a second voltage, the first voltage and the second voltage being negatively related to absolute temperature, and a first voltage difference between the first voltage and the second voltage being positively related to absolute temperature;

[0007] A switched capacitor module, the switched capacitor module being configured to output a first temperature coefficient voltage and a first temperature coefficient charge according to the first voltage and the second voltage;

[0008] An integration module, the integration module being configured to access the first temperature coefficient voltage and integrate the first temperature coefficient charge, so as to output a reference voltage independent of absolute temperature according to the first temperature coefficient voltage and the first temperature coefficient charge;

[0009] Wherein, the first temperature coefficient voltage is negatively related to absolute temperature, the first temperature coefficient charge is positively related to absolute temperature, and the first temperature coefficient charge is generated based on the first voltage difference.

[0010] In a second aspect, the embodiments of the present application further provide a chip comprising the above bandgap reference circuit.

[0011] In a third aspect, the embodiments of the present application further provide an electronic device comprising the chip or the bandgap reference circuit.

[0012] The first voltage and the second voltage are output by the voltage output module, the first voltage and the second voltage are negatively related to the absolute temperature, and the first voltage difference between the first voltage and the second voltage is positively related to the absolute temperature, so that the switched capacitor module can output a first temperature coefficient voltage (for example, the first voltage or the second voltage) negatively related to the absolute temperature according to the first voltage and the second voltage, and output a first temperature coefficient charge positively related to the absolute temperature according to the first voltage difference between the first voltage and the second voltage. After the first temperature coefficient voltage is input into the integration module and the first temperature coefficient charge is integrated, the integration module can output a reference voltage independent of the absolute temperature.

[0013] That is, the present application outputs the reference voltage by inputting the negative temperature coefficient voltage and integrating the positive temperature coefficient charge. Compared with the conventional way of outputting the reference voltage by superimposing the negative temperature coefficient voltage and the positive temperature coefficient voltage, the first temperature coefficient charge integrated by the present application is independent of the offset voltage of the first operational amplifier, so that the influence of the offset voltage of the first operational amplifier on the reference voltage can be reduced, and ultimately the precision of the bandgap reference voltage can be improved.

[0014] These aspects or other aspects of the present application will be more apparent in the following description of the embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative effort.

[0016] Figure 1 A schematic diagram of a bandgap reference circuit in the related art is shown.

[0017] Figure 2 Another schematic diagram of a bandgap reference circuit in the related art is shown.

[0018] Figure 3 A schematic diagram of a bandgap reference circuit in the embodiments of the present application is shown.

[0019] Figure 4 A schematic diagram of a voltage output module in the embodiments of the present application is shown.

[0020] Figure 5 Another schematic diagram of a bandgap reference circuit in the embodiments of the present application is shown.

[0021] Figure 6 A working schematic diagram of the bandgap reference circuit in the embodiment of the present application is shown.

[0022] Figure 7 Another schematic diagram of the bandgap reference circuit in the embodiment of the present application is shown.

[0023] Figure 8 Another schematic diagram of the bandgap reference circuit in the embodiment of the present application is shown.

[0024] Figure 9 Another schematic diagram of the bandgap reference circuit in the embodiment of the present application is shown.

[0025] Figure 10 Another schematic diagram of the bandgap reference circuit in the embodiment of the present application is shown.

[0026] Figure 11 Another schematic diagram of the bandgap reference circuit in the embodiment of the present application is shown.

[0027] wherein 10 is a voltage output module, 20 is a switched capacitor module, and 30 is an integration module;

[0028] a reference voltage VBG, a first voltage VBE1, a second voltage VBE2, a first temperature coefficient voltage VBE, and a first temperature coefficient charge Q0;

[0029] a first operational amplifier AMP1, a second operational amplifier AMP2, an integration capacitor CI, an integration switch SI, a first sampling capacitor Cs1, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a first capacitor C1, a second sampling capacitor Cs2, a second capacitor C2, a fifth switch S5, a sixth switch S6, a seventh switch S7, and an eighth switch S8. DETAILED DESCRIPTION

[0030] The embodiments of the present application will be described in detail below with reference to the drawings, in which the same or similar components have the same reference numerals throughout. The embodiments described below are exemplary only, and are not intended to limit the present application.

[0031] In order to make the technical personnel in the technical field better understand the scheme of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0032] It should be noted that, in the embodiments of the present application, in this paper, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or sequence between the entities or operations.

[0033] Moreover, the terms "comprise", "contain" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. Without more limitations, the element defined by the sentence "comprises a" does not exclude the presence of another identical element in the process, method, article or equipment comprising the element.

[0034] In the description of the embodiments of the present application, the words "example" or "for example" are used to represent example, illustration or description. Any embodiment or design scheme described as "example" or "for example" in the embodiments of the present application is not interpreted as more preferred or having more advantages than another embodiment or design scheme. The words "example" or "for example" are intended to present relative concepts in a clear manner.

[0035] In addition, "multiple" in the embodiments of the present application means two or more, and therefore "multiple" in the embodiments of the present application can also be understood as "at least two". "At least one" can be understood as one or more, for example, as one, two or more. For example, including at least one means including one, two or more, and does not limit which ones are included, for example, including at least one of A, B and C, and the included can be A, B, C, A and B, A and C, B and C, or A and B and C.

[0036] It should be noted that, in the embodiments of the present application, the "and / or" describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which means that there are three cases of A alone, A and B together, and B alone. In addition, the character " / ", if not specially stated, generally represents a "or" relationship between the associated objects before and after.

[0037] It should be noted that, in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical elements can be direct or indirect connection between the two electrical elements. For example, A and B are connected, which can be direct connection between A and B, or indirect connection between A and B through one or more other electrical elements.

[0038] The first pole / first end of each transistor in the embodiments of the present application is one of the source and the drain, and the second pole / second end of each transistor is the other of the source and the drain. Since the source and the drain of a transistor can be symmetrical in structure, the source and the drain of a transistor can be indistinguishable in structure, that is, the first pole / first end and the second pole / second end of a transistor in the embodiments of the present application can be indistinguishable in structure. For example, when a transistor is a P-type transistor, the first pole / first end of the transistor is the source, and the second pole / second end of the transistor is the drain; for example, when a transistor is an N-type transistor, the first pole / first end of the transistor is the drain, and the second pole / second end of the transistor is the source.

[0039] In the circuit structure provided by the embodiments of the present application, the nodes such as the first node and the second node do not represent actual components, but represent the convergence points of relevant couplings in a circuit diagram, that is, these nodes are nodes equivalent to the convergence points of relevant couplings in a circuit diagram.

[0040] The bandgap reference circuit can output a reference voltage that is substantially independent of power supply voltage, process and temperature. For reference, see Figure 1 , Figure 1 A schematic diagram of a bandgap reference circuit in the related art is shown, wherein the bandgap reference circuit includes transistors M1, M2 and M3, an operational amplifier OP1, resistors R1-R2, a transistor QP, a transistor QN and a transistor QM that are current mirrors of each other.

[0041] During the operation of the bandgap reference circuit, the bases of the transistors QP, QN and QM are respectively shorted to the collectors thereof, and the base-emitter voltages of the relevant transistors are negative temperature coefficient voltages and satisfy the following relationship:

[0042]

[0043] wherein k is the Boltzmann constant, T is the absolute temperature, q is the unit charge, I C is the collector current, and I S is the reverse saturation current of the transistor.

[0044] The reverse saturation current I S is proportional to the emitter area of the transistor. Assuming that the sizes of the transistors M1, M2 and M3 are the same (that is, the collector currents flowing through the transistors are equal), and the ratio of the emitter areas of the transistors QP and QN is 1:N, and the ratio of the emitter areas of the transistors QP and QM is 1:1, the base-emitter voltage of the transistor QP, the base-emitter voltage of the transistor QN and the base-emitter voltage of the transistor QM can be respectively calculated according to the following formulas:

[0045]

[0046] Due to the virtual short and virtual open characteristics of the operational amplifier OP1, the voltage at node N is equal to the voltage at node P without considering the offset voltage of the operational amplifier OP1, and thus the current flowing through the resistor R1 (i.e. the IPTAT current flowing through the resistor R2) is: PTAT

[0047]

[0048] It can be seen that k, q, lnN, and R1 in the above equation are constants, and thus the current flowing through the resistor R1 is a positive temperature coefficient current, and VBE2-VBE1 is also a positive temperature coefficient voltage.

[0049] Therefore, based on the voltage division of the resistor R2 and the voltage division of the transistor QM, the reference voltage Vref output by the final node O is:

[0050] Vref = VBE3 + (VBE2-VBE1)R2 / R1

[0051] In the above equation, VBE3 is a negative temperature coefficient voltage, and VBE2-VBE1 is a positive temperature coefficient voltage, and thus by changing the ratio of R2 / R1, a reference voltage Vref independent of absolute temperature can be output under the superposition of the negative temperature coefficient voltage and the positive temperature coefficient voltage.

[0052] However, referring to Figure 2 Since there is actually an offset voltage Vos of the operational amplifier OP1, the voltage at node N is not absolutely equal to the voltage at node P, and at this time the current flowing through the resistor R1 (i.e. the IPTAT current flowing through the resistor R2) is actually:

[0053] I R1 = (VBE2-VBE1+Vos) / R1

[0054] where Vos is the offset voltage of the operational amplifier OP1.

[0055] Therefore, the reference voltage Vref output by the final node O is actually:

[0056] Vref = VBE3 + (VBE2-VBE1+Vos)R2 / R1

[0057] Since R2 / R1 is usually 8.2 or 5, according to the above equation, it can be seen that the offset voltage Vos of the operational amplifier OP1 is amplified by 8.2 times or 5 times, which leads to the problem of degradation of the precision of the reference voltage Vref output by the bandgap reference circuit.

[0058] ​To this end, the application provides a bandgap reference circuit, a chip and an electronic device, which are described in detail below.

[0059] First, referring to Figure 3 , Figure 3 A schematic diagram of a bandgap reference circuit in an embodiment of the application is shown, wherein the bandgap reference circuit comprises a voltage output module 10, a switched capacitor module 20 and an integration module 30.

[0060] Specifically, the voltage output module 10 comprises a first operational amplifier AMP1, and the voltage output module 10 can output a first voltage VBE1 and a second voltage VBE2 under voltage clamping of the first operational amplifier AMP1, the first voltage VBE1 and the second voltage VBE2 are negatively related to absolute temperature, and a first voltage difference between the first voltage VBE1 and the second voltage VBE2 is positively related to absolute temperature, that is, the first voltage VBE1 and the second voltage VBE2 are negative temperature coefficient voltages, and the first voltage difference is a positive temperature coefficient voltage.

[0061] As an example, referring to Figure 4 , Figure 4 A schematic diagram of the voltage output module 10 in an embodiment of the application is shown, wherein the voltage output module 10 comprises a first operational amplifier AMP1, PMOS tubes MP1 and MP2 which are current mirrors, a transistor Q1, a transistor Q2 and a resistor R1, the first operational amplifier AMP1 has an offset voltage Vos1, during the working process of the voltage output module 10, the collectors of the transistor Q1 and the transistor Q2 output the first voltage VBE1 and the second voltage VBE2 respectively, and the first voltage VBE1 and the second voltage VBE2 satisfy the following relationship respectively:

[0062]

[0063] Wherein, k is the Boltzmann constant, T is the absolute temperature, q is the unit charge, I C is the collector current of the transistor Q1 and the transistor Q2, I S is the reverse saturation current of the transistor Q2, and m is the ratio between the emitter area of the transistor Q1 and the emitter area of the transistor Q2.

[0064] Since the reverse saturation current of the transistor decreases when the temperature rises, and the reverse saturation current of the transistor increases when the temperature decreases, the first voltage VBE1 and the second voltage VBE2 are negatively related to absolute temperature, that is, the first voltage VBE1 and the second voltage VBE2 are negative temperature coefficient voltages.

[0065] Meanwhile, due to the virtual short and virtual open characteristics of the first operational amplifier AMP1, in the case of considering the offset voltage of the operational amplifier OP1, the first voltage difference between the first voltage VBE1 and the second voltage VBE2 satisfies the following relationship:

[0066] △VBE = (VBE2-VBE1) = kT / q*lnm

[0067] Since the ratio m between the emitter area of the transistor Q1 and the emitter area of the transistor Q2 is a fixed value, lnm is a constant term, and the first voltage difference between the first voltage VBE1 and the second voltage VBE2 is positively correlated with the absolute temperature, that is, the first voltage difference is a positive temperature coefficient voltage.

[0068] It can be understood that the above-mentioned embodiments are only exemplary embodiments of the voltage output module 10 of the present application, and should not be understood as limiting the voltage output module 10 of the present application. Those skilled in the art can make equivalent modifications and designs to the voltage output module 10 under the guidance of the present application, for example, replacing the transistor Q1 and / or the transistor Q2 with a diode having a PN junction; for example, using a more complex current mirror structure (such as a low-voltage common-source common-gate current source or a wide-swing common-source common-gate current mirror, etc.) to replace the PMOS transistor MP1 and the PMOS transistor MP2 in Figure 4 .

[0069] The switched capacitor module 20 can output a first temperature coefficient voltage VBE and a first temperature coefficient charge Q0 according to the first voltage VBE1 and the second voltage VBE2, the first temperature coefficient voltage VBE is negatively correlated with the absolute temperature, the first temperature coefficient charge Q0 is generated based on the first voltage difference, and the first temperature coefficient charge Q0 is positively correlated with the absolute temperature, that is, the first temperature coefficient voltage VBE is a negative temperature coefficient voltage, and the first temperature coefficient charge Q0 is a positive temperature coefficient charge, so that the integration module 30 outputs a reference voltage VBG independent of the absolute temperature according to the first temperature coefficient voltage VBE and the first temperature coefficient charge Q0.

[0070] In some embodiments of the present application, the first temperature coefficient voltage VBE can be any one of the first voltage VBE1 and the second voltage VBE2. Since the first voltage VBE1 and the second voltage VBE2 are negative temperature coefficient voltages, the switched capacitor module 20 can directly input the first voltage VBE1 or the second voltage VBE2 as the first temperature coefficient voltage VBE to the integration module 30. In some embodiments of the present application, the switched capacitor module 20 can make equivalent changes (such as voltage reduction according to resistance voltage division) to the first voltage VBE1 or the second voltage VBE2, and then output the first temperature coefficient voltage VBE negatively correlated with the absolute temperature to the integration module 30.

[0071] In some embodiments of the present application, the switched capacitor module 20 can output the first temperature coefficient charge Q0 according to the first voltage difference between the first voltage VBE1 and the second voltage VBE2, and since the first voltage difference between the first voltage VBE1 and the second voltage VBE2 is a positive temperature coefficient voltage, the switched capacitor module 20 can output the first temperature coefficient charge Q0 positively related to absolute temperature to the integration module 30. In some embodiments of the present application, the switched capacitor module 20 can make equivalent changes to the first voltage VBE1 or the second voltage VBE2, and since the first voltage difference between the first voltage VBE1 and the second voltage VBE2 is a positive temperature coefficient voltage, the equivalent changes will still result in a positive temperature coefficient voltage, so the switched capacitor module 20 can output the first temperature coefficient charge Q0 positively related to absolute temperature to the integration module 30 according to the voltage difference corresponding to the changes.

[0072] The integration module 30 is configured to access the first temperature coefficient voltage VBE and integrate the first temperature coefficient charge Q0, so as to output a reference voltage VBG independent of absolute temperature according to the first temperature coefficient voltage VBE and the first temperature coefficient charge Q0. For example, taking the case where the switched capacitor module 20 outputs the first temperature coefficient charge Q0 according to the first voltage difference between the first voltage VBE1 and the second voltage VBE2, the positive temperature coefficient voltage V+ converted by the integration module 30 when integrating the first temperature coefficient charge Q0 is:

[0073] V+ = (VBE2 - VBE1) * k

[0074] wherein k is a coefficient.

[0075] At the same time, since the integration module 30 also accesses the first temperature coefficient voltage VBE negatively related to absolute temperature, the reference voltage VBG output by the integration module 30 can satisfy the following relationship:

[0076] VBG = VBE + (VBE2 - VBE1) * k

[0077] It can be seen that VBE is a negative temperature coefficient voltage, and VBE2 - VBE1 is a positive temperature coefficient voltage, so by changing the value of the coefficient k, the positive and negative temperature coefficient voltages can be offset, and finally the reference voltage VBG independent of absolute temperature can be output.

[0078] It should be noted that the offset voltage Vos1 of the first operational amplifier AMP1 will only affect the first voltage VBE1, the second voltage VBE2 and the current flowing through the resistor R1, but will not affect the size of the first voltage difference between the first voltage VBE1 and the second voltage VBE2. For example, in the case where the first voltage VBE1 is 0.7 V, the second voltage VBE2 is 1.2 V, and the offset voltage Vos1 of the first operational amplifier AMP1 is 0.1 V, the first voltage VBE1 will be 0.6 V, the second voltage VBE2 will be 1.1 V, and the first voltage difference between the first voltage VBE1 and the second voltage VBE2 will be 0.5 V. Figure 4In the case where the offset voltage Vos1 of the first operational amplifier AMP1 is not considered, the current flowing through the resistor R1 (i.e. the collector current of the transistors Q1, Q2) is:

[0079] I1= (VBE2-VBE1) / R1

[0080] The first voltage VBE1 and the second voltage VBE2 are respectively:

[0081]

[0082] Suppose the voltage difference between the first voltage VBE1 and the second voltage VBE2, and the offset voltage Vos1 of the first operational amplifier AMP1 are:

[0083] VBE2-VBE1= 54mv

[0084] Vos1= (VBE2-VBE1) / 4 = 13.5mv

[0085] Then, in the case where the offset voltage Vos1 of the first operational amplifier AMP1 is considered, the current flowing through the resistor R1 (i.e. the collector current of the transistors Q1, Q2) is:

[0086] I2= (VBE2-VBE1+Vos1) / R1 = 1.25 (VBE2-VBE1) / R1 = 1.25 I1

[0087] The first voltage VBE1 and the second voltage VBE2 are respectively:

[0088]

[0089] Therefore, the first voltage difference between the first voltage VBE1 and the second voltage VBE2 is:

[0090]

[0091] After simplifying the above formula, the first voltage difference between the first voltage VBE1 and the second voltage VBE2 satisfies the following relationship:

[0092]

[0093] Meanwhile, the voltage variation caused by the offset voltage of the first operational amplifier AMP1 affecting the first voltage VBE1 and the second voltage VBE2 is:

[0094]

[0095] It can be seen that the first voltage difference between the first voltage VBE1 and the second voltage VBE2 is not affected by the offset voltage Vos1 of the first operational amplifier AMP1, and thus the first temperature coefficient charge generated based on the first voltage difference is also irrelevant to the offset voltage Vos1 of the first operational amplifier AMP1. Since the voltage variation caused by the offset voltage of the first operational amplifier AMP1 to the first voltage VBE1 and the second voltage VBE2 is 5.8 mv, according to the reference voltage VBG calculation formula VBG = VBE + (VBE2-VBE1)*k, it can be known that the variation of the reference voltage VBG caused by the offset voltage Vos1 of the first operational amplifier AMP1 is about 5.8 mv, which is 8.2 times (i.e. 13.5 mv*8.2 = 110.7 mv) or 5 times (13.5 mv*5 = 67.5 mv) larger than the phenomenon in the prior art that the offset voltage Vos1 of the first operational amplifier AMP1 is amplified. The application reduces the influence of the offset voltage Vos1 of the first operational amplifier AMP1 on the reference voltage VBG, which is finally beneficial to improve the accuracy of the reference voltage VBG.

[0096] In some embodiments of the application, reference is made to Figure 5 , Figure 5 Another schematic diagram of the bandgap reference circuit in the embodiments of the application is shown, wherein the integration module 30 includes a second operational amplifier AMP2, an integration capacitor CI, and an integration switch SI; the first end of the integration capacitor CI is connected with the first input end of the second operational amplifier AMP2, and the second end of the integration capacitor CI is connected with the output end of the second operational amplifier AMP2; the first end of the integration switch SI is connected with the first input end of the second operational amplifier AMP2, and the second end of the integration switch SI is connected with the output end of the second operational amplifier AMP2.

[0097] It should be noted that the first input end of the second operational amplifier AMP2 is configured to receive the first temperature coefficient charge Q0, and the second input end of the second operational amplifier AMP2 is configured to access the first temperature coefficient voltage VBE. When the integration module 30 accesses the first temperature coefficient voltage VBE and integrates the first temperature coefficient charge Q0, the integration switch SI is in an open state, and after the integration capacitor CI integrates the first temperature coefficient charge Q0, the voltage difference across the integration capacitor CI is:

[0098] AVCI = Q0 / CI = (VBE2-VBE1)*k

[0099] Due to the virtual short and virtual open characteristics of the second operational amplifier AMP2, the voltage at the first input end of the second operational amplifier AMP2 is the first temperature coefficient voltage VBE, and thus the reference voltage at the output end of the second operational amplifier AMP2 is:

[0100] VBG = VBE + (VBE2-VBE1) * k

[0101] It can be seen that after the integral module 30 accesses the first temperature coefficient voltage VBE and charges the first temperature coefficient charge Q0, the integral module 30 can output the reference voltage VBG irrelevant to the absolute temperature.

[0102] In some embodiments, continuing to refer to Figure 5 The switch SIB that is reciprocal to the switch state of the integral switch SI and the voltage stabilizing capacitor CO can also be set at the output end of the second operational amplifier AMP2, that is, the switch SI is closed and the switch SIB is opened in the sampling working state, and the switch SI is opened and the switch SIB is closed in the integral working state, so as to output the stable reference voltage VBG through the voltage stabilizing capacitor CO in the integral working state.

[0103] In some embodiments of the present application, the first temperature coefficient charge Q0 is irrelevant to the offset voltage Vos2 of the second operational amplifier AMP2, that is, the first temperature coefficient charge Q0 is not affected by the offset voltage Vos2 of the second operational amplifier AMP2, so as to reduce the influence of the offset voltage Vos2 of the second operational amplifier AMP2 on the reference voltage VBG.

[0104] For example, referring to Figure 6 , Figure 6 A working schematic diagram of the bandgap reference circuit in the embodiments of the present application is shown, and the switch capacitor module 20 has a sampling working state and an integral working state; in the sampling working state, the switch capacitor module 20 charges and accumulates the first charge based on the first voltage VBE1 and the offset voltage Vos2 of the second operational amplifier AMP2, and at this time, the charge amount of the first charge is:

[0105] Q1 = (VBE1-Vos2) * Cs

[0106] Wherein, Cs is the capacitor corresponding to the first charge accumulated by the switch capacitor module 20.

[0107] And in the integral working state, the switch capacitor module 20 charges and accumulates the second charge based on the second voltage VBE2 and the offset voltage Vos2 of the second operational amplifier AMP2, and at this time, the charge amount of the second charge is:

[0108] Q2 = (VBE2-Vos2) * Cs

[0109] Therefore, when the switch capacitor module 20 is switched from the sampling working state to the integral working state, the charge output by the switch capacitor module 20 is:

[0110] Q0 = Q2-Q1 = (VBE2-Vos2-VBE1+Vos2) * Cs = (VBE2-VBE1) * Cs

[0111] It can be seen that when the switched capacitor module 20 is switched from the sampling working state to the integration working state, the switched capacitor module 20 can output the first temperature coefficient charge Q0 irrelevant to the offset voltage Vos2 of the second operational amplifier AMP2 according to the reduced charge amount.

[0112] As an example, refer to Figure 7 , Figure 7 Another schematic diagram of the bandgap reference circuit in the embodiment of the application is shown, wherein the switched capacitor module 20 includes a first sampling capacitor Cs1, a first switch S1 and a second switch S2; the first end of the first sampling capacitor Cs1 is connected with the ground end, and the second end of the first sampling capacitor Cs1 is connected with the first input end of the second operational amplifier AMP2; the first end of the first switch S1 is used to access the first voltage VBE1, and the second end of the first switch S1 is connected with the second input end of the second operational amplifier AMP2; the first end of the second switch S2 is used to access the second voltage VBE2, and the second end of the second switch S2 is connected with the second input end of the second operational amplifier AMP2.

[0113] It should be noted that in the sampling working state of the switched capacitor module 20, the first switch S1 and the integration switch SI are closed, and the second switch S2 is disconnected. Due to the virtual short and virtual open characteristics of the second operational amplifier AMP2 and the existence of the offset voltage Vos2 of the second operational amplifier AMP2, the voltage at the second input end of the second operational amplifier AMP2 is VBE1, and the voltage at the first input end of the second operational amplifier AMP2 is VBE1+Vos2. Therefore, the first charge accumulated by the first sampling capacitor Cs1 is:

[0114] Q1=(VBE1-Vos2)*Cs1

[0115] And in the integration working state of the switched capacitor module 20, the first switch S1 and the integration switch SI are disconnected, and the second switch S2 is disconnected. Due to the virtual short and virtual open characteristics of the second operational amplifier AMP2 and the existence of the offset voltage Vos2 of the second operational amplifier AMP2, the voltage at the second input end of the second operational amplifier AMP2 is VBE2, and the voltage at the first input end of the second operational amplifier AMP2 is VBE2+Vos2. Therefore, the second charge accumulated by the first sampling capacitor Cs1 is:

[0116] Q2=(VBE2-Vos2)*Cs1

[0117] Then after the switched capacitor module is switched to the integration working state, the first temperature coefficient charge Q0 output by the first sampling capacitor Cs1 is:

[0118] Q0=Q2-Q1=(VBE2-VBE1)*Cs1

[0119] It can be seen that the first temperature coefficient charge Q0 is irrelevant to the offset voltage Vos2 of the second operational amplifier AMP2, and thus the influence of the offset voltage Vos2 of the second operational amplifier AMP2 on the reference voltage VBG can be reduced.

[0120] It should be noted that in the related art, the reference voltage VBG satisfies the formula:

[0121] VBG = VBE3 + (VBE2 - VBE1 + Vos1)R2 / R1

[0122] Generally, the ratio of R2 / R1 is 8.2 or 5, that is, the offset voltage Vos1 of the first operational amplifier AMP1 is amplified by 8.2 times or 5 times.

[0123] In the above embodiment, it is assumed that the voltage difference between the first voltage VBE1 and the second voltage VBE2, the offset voltage Vos1 of the first operational amplifier AMP1 and the offset voltage Vos2 of the second operational amplifier AMP2 are equal and satisfy the following formula:

[0124] VBE2 - VBE1 = 54 mv

[0125] Vos2 = Vos1 = (VBE2 - VBE1) / 4 = 13.5 mv

[0126] The current flowing through the resistor R1 (i.e., the collector current of the transistors Q1 and Q2) is actually:

[0127] I2 = (VBE2 - VBE1 + Vos1) / R1 = 1.25(VBE2 - VBE1) / R1 = 1.25I1

[0128] Therefore, the offset voltage Vos1 of the first operational amplifier AMP1 causes the size of the second voltage VBE2 to change by:

[0129]

[0130] Therefore, the reference voltage VBG output by the above embodiment is actually:

[0131] VBG = VBE2 +△VBE2 + Vos2 + (VBE2 - VBE1)*Cs / CI

[0132] According to the above formula, it can be seen that the variation of the reference voltage VBG caused by the offset voltage Vos1 of the first operational amplifier AMP1 and the offset voltage Vos2 of the second operational amplifier AMP2 is 13.5mv+5.8mv=18.3mv, which is 8.2 times (i.e. 13.5mv*8.2=110.7mv) or 5 times (13.5mv*5=67.5mv) of the offset voltage Vos1 of the first operational amplifier AMP1 in the prior art. Although the second operational amplifier of the integration module 30 has the offset voltage Vos, the above embodiment can significantly reduce the influence of the offset voltage of the operational amplifier on the reference voltage VBG, thereby improving the accuracy of the reference voltage VBG.

[0133] In some embodiments of the present application, the first temperature coefficient charge Q0 is irrelevant to the offset voltage Vos2 of the second operational amplifier AMP2, and the first end voltage of the integration capacitor CI is irrelevant to the offset voltage Vos2 of the second operational amplifier AMP2, that is, the reference voltage VBG calculation formula can be changed to:

[0134] VBG=VBE2+△VBE2+(VBE2-VBE1)*Cs / CI

[0135] Wherein, △VBE2 is the variation of the second voltage VBE2 caused by the offset voltage Vos1 of the first operational amplifier AMP1, and the offset voltage Vos2 of the second operational amplifier AMP2 has no influence on the reference voltage VBG, thereby being beneficial to completely eliminating the influence of the offset voltage Vos2 of the second operational amplifier AMP2.

[0136] As an example, refer to Figure 8 , Figure 8Another schematic diagram of the bandgap reference circuit in the embodiments of the present application is shown, wherein the switched capacitor module 20 comprises a first sampling capacitor Cs1, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5 and a first capacitor C1; a first end of the first switch S1 is used to access a first voltage VBE1, a second end of the first switch S1 is connected with a first end of the first sampling capacitor Cs1; a second end of the first sampling capacitor Cs1 is connected with a first end of the first capacitor C1, a second end of the first capacitor C1 is connected with a first input end of a second operational amplifier AMP2; a first end of the second switch S2 is connected with the first end of the first sampling capacitor Cs1, a second end of the second switch S2 is connected with a ground end; a first end of the third switch S3 is connected with a second end of the first sampling capacitor Cs1, a second end of the third switch S3 is connected with the ground end; a first end of the fourth switch S4 is used to access a second voltage VBE2, a second end of the fourth switch S4 is connected with a second input end of the second operational amplifier AMP2; a first end of the fifth switch S5 is connected with the second input end of the second operational amplifier AMP2, a second end of the fifth switch S5 is connected with the ground end.

[0137] It should be noted that, in the sampling working state of the switched capacitor module 20, the integral switch SI, the second switch S2, the third switch S3 and the fifth switch S5 are closed, the first switch S1 and the fourth switch S4 are disconnected, at this time, the charge quantity accumulated by the first sampling capacitor Cs1 is zero, and the charge quantity accumulated by the first capacitor C1 is:

[0138] Qc1=Vos2*C1

[0139] And in the integral working state of the switched capacitor module 20, the integral switch SI, the second switch S2, the third switch S3 and the fifth switch S5 are disconnected, the first switch S1 and the fourth switch S4 are closed, due to the virtual short and virtual open characteristics of the second operational amplifier AMP2, the first input end voltage of the second operational amplifier AMP2 is: VBE2+Vos2, at the same time, the charge quantity of the first capacitor C1 remains unchanged (that is, the voltage difference across the first capacitor C1 remains unchanged), therefore, the voltage of the first node m1 (that is, the voltage of the first end of the integral capacitor CI) satisfies the following relationship:

[0140] VBE2+Vos2-Vm1=Vos2

[0141] Wherein, Vm1 is the voltage of the first node m1.

[0142] That is, the voltage of the first node m1 is the second voltage VBE2, therefore, the charge quantity accumulated by the first sampling capacitor Cs1 is:

[0143] Qcs1=(VBE2-VBE1)*Cs1

[0144] Therefore, the voltage difference generated by the integral capacitor CI accumulating charges in the integral working state of the switched capacitor module 20 is:

[0145] VCI = (VBE2-VBE1) * Cs1 / CI

[0146] In combination with the voltage of the first node m1, the reference voltage VBG output by the second operational amplifier AMP2 satisfies the following relationship:

[0147] VBG = VBE2 + (VBE2-VBE1) * Cs1 / CI

[0148] As can be seen, in the above embodiment, the offset voltage Vos2 of the second operational amplifier AMP2 is fixed at the first capacitor C1. Not only is the charge output by the first sampling capacitor Cs1 (i.e., the first temperature coefficient charge Q0) independent of the offset voltage Vos2 of the second operational amplifier AMP2, but also the voltage of the first node m1 (i.e., the first end voltage of the integral capacitor CI) is independent of the offset voltage Vos2 of the second operational amplifier AMP2, thereby completely eliminating the influence of the offset voltage of the second operational amplifier AMP2. In contrast to the conventional technology, the offset voltage Vos1 of the first operational amplifier AMP1 is amplified by 8.2 times (i.e., 13.5mv * 8.2 = 110.7mv) or 5 times (13.5mv * 5 = 67.5mv). At this time, only the offset voltage Vos1 of the first operational amplifier AMP1 causes the change of the reference voltage VBG (i.e., 5.8mv). As can be seen, the above embodiment further reduces the influence of the offset voltage of the operational amplifier on the reference voltage VBG.

[0149] As another example, refer to Figure 9 , Figure 9Another schematic diagram of the bandgap reference circuit in the embodiments of the present application is shown, wherein the switched capacitor module 20 comprises a first sampling capacitor Cs1, a first capacitor C1, a first switch S1, a second switch S2, a third switch S3, a second sampling capacitor Cs2, a second capacitor C2, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, and an eighth switch S8; a first end of the first switch S1 is used to access a first input voltage, and a second end of the first switch S1 is connected with a first end of the first sampling capacitor Cs1; a second end of the first sampling capacitor Cs1 is connected with a first end of the first capacitor C1, and a second end of the first capacitor C1 is connected with a first input end of the second operational amplifier AMP2; a first end of the second switch S2 is connected with the first end of the first sampling capacitor Cs1, and a second end of the second switch S2 is connected with a ground end; a first end of the third switch S3 is connected with a second end of the first sampling capacitor Cs1, and a second end of the third switch S3 is connected with the ground end; a first end of the fourth switch S4 is used to access a second voltage VBE2, a second end of the fourth switch S4 is connected with a first end of the second sampling capacitor Cs2, and a second end of the second sampling capacitor Cs2 is connected with a second input end of the second operational amplifier AMP2; a first end of the fifth switch S5 is connected with the first end of the second sampling capacitor Cs2, and a second end of the fifth switch S5 is connected with the ground end; a first end of the sixth switch S6 is connected with a second end of the second sampling capacitor Cs2, and a second end of the sixth switch S6 is connected with the ground end; a first end of the seventh switch S7 is used to access the second voltage VBE2, a second end of the seventh switch S7 is connected with a first end of the second capacitor C2, and a second end of the second capacitor C2 is connected with the second input end of the second operational amplifier AMP2; a first end of the eighth switch S8 is connected with the first end of the second capacitor C2, and a second end of the eighth switch S8 is connected with the ground end.

[0150] It should be noted that, in the sampling working state of the switched capacitor module 20, the integration switch SI, the second switch S2, the third switch S3, the fourth switch S4, the sixth switch S6, and the eighth switch S8 are closed, and the first switch S1, the fifth switch S5, and the seventh switch S7 are disconnected, at this time, the charge amounts accumulated by the first sampling capacitor Cs1 and the second capacitor C2 are zero, and the charge amounts accumulated by the first capacitor C1 and the second sampling capacitor Cs2 are respectively:

[0151] Qc1 = Vos2 * C1

[0152] Qcs2 = VBE2 * Cs2

[0153] And in the integration working state of the switched capacitor module 20, the integration switch SI, the second switch S2, the third switch S3, the fourth switch S4, the sixth switch S6, and the eighth switch S8 are disconnected, and the first switch S1, the fifth switch S5, and the seventh switch S7 are closed, according to the charge conservation, the voltage of the second node m2 satisfies the following relationship:

[0154] Vm2*Cs2+(Vm2-VBE2)*C2=-VBE2*Cs2

[0155] That is, the voltage of the second node m2 is:

[0156] Vm2=VBE2*(C2-Cs2) / (C2+Cs2)

[0157] Due to the virtual short and virtual open characteristics of the second operational amplifier AMP2, the voltage of the first input terminal of the second operational amplifier AMP2 is Vm2+Vos2, and the charge amount of the first capacitor CI remains unchanged (that is, the voltage difference across the first capacitor CI remains unchanged), so the voltage of the first node m1 satisfies the following relationship:

[0158] Vm2+Vos2-Vm1=Vos2

[0159] Therefore, the voltage of the first node m1 is:

[0160] Vm1=Vm2=VBE2*(C2-Cs2) / (C2+Cs2)

[0161] The first input voltage VIN is generated based on the first voltage VBE1, and since the first input voltage VIN and the first voltage VBE1 satisfy the first ratio, the difference between the capacitance values of the second sampling capacitor Cs2 and the second capacitor C2 satisfies the second ratio relative to the sum of the capacitance values of the second sampling capacitor Cs2 and the second capacitor C2, and the first ratio is equal to the second ratio, that is, the first input voltage VIN and the first voltage VBE1 satisfy the following relationship:

[0162] VIN / VBE1=(C2-Cs2) / (C2+Cs2)

[0163] That is, the first input voltage is VIN=(C2-Cs2) / (C2+Cs2)*VBE1, and in combination with the voltage of the first node m1, the charge amount accumulated by the first sampling capacitor Cs1 in the integration working state of the switched capacitor module 20 is:

[0164] Qcs1=(VIN-Vm1)*Cs1=(C2-Cs2) / (C2+Cs2)*(VBE2-VBE1)*Cs1

[0165] Therefore, the reference voltage VBG output by the second operational amplifier AMP2 satisfies the following relationship:

[0166] VBG=(C2-Cs2) / (C2+Cs2)*[VBE2+(VBE2-VBE1)*Cs1 / CI]

[0167] It can be seen that in the above formula, (C2-Cs2) / (C2+Cs2) is a constant term, so by changing C2, Cs2, the size of the reference voltage VBG can be changed, and by changing the ratio of Cs1 / CI, the positive and negative temperature coefficient voltages can be offset to each other and the reference voltage VBG independent of absolute temperature can be output. In addition, in the above embodiment, the offset voltage Vos2 of the second operational amplifier AMP2 is fixed to the first capacitor C1. Not only is the charge (i.e. the first temperature coefficient charge Q0) output by the first sampling capacitor Cs1 independent of the offset voltage Vos2 of the second operational amplifier AMP2, but also the voltage at the first node m1 (i.e. the voltage at the first end of the integration capacitor CI) is also independent of the offset voltage Vos2 of the second operational amplifier AMP2, thereby completely eliminating the influence of the offset voltage of the second operational amplifier AMP2.

[0168] It should be noted that in some embodiments of the present application, for example for embodiments requiring to provide a first input voltage VIN, the bandgap reference circuit of the present application can further include a voltage changing module 40 as shown in Figure 9 , the first input voltage VIN can be generated by the voltage changing module 40 according to the first voltage VBE1, and the voltage changing module 40 can include but is not limited to a resistance voltage dividing circuit, a BUCK voltage reducing circuit, etc. to generate a voltage signal, so as to generate a first input voltage VIN satisfying a first ratio with the first voltage VBE1.

[0169] As another example, referring to Figure 10 , Figure 10 shows another schematic diagram of the bandgap reference circuit in the embodiments of the present application, wherein the switched capacitor module 20 includes a first sampling capacitor Cs1, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a first capacitor C1, a fifth switch S5, and a sixth switch S6; the first end of the first switch S1 is used to access the first voltage VBE1, and the second end of the first switch S1 is connected with the first end of the first sampling capacitor Cs1; the second end of the first sampling capacitor Cs1 is connected with the first end of the second switch S2, the second end of the second switch S2 is connected with the first end of the first capacitor C1, and the second end of the first capacitor C1 is connected with the first input end of the second operational amplifier AMP2; the first end of the third switch S3 is connected with the second end of the first sampling capacitor Cs1, and the second end of the third switch S3 is connected with the ground; the first end of the fourth switch S4 is connected with the first end of the first sampling capacitor Cs1, and the second end of the fourth switch S4 is connected with the second end of the second switch S2; the first end of the fifth switch S5 is used to access the second voltage VBE2, and the second end of the fifth switch S5 is connected with the second input end of the second operational amplifier AMP2; the first end of the sixth switch S6 is connected with the second input end of the second operational amplifier AMP2, and the second end of the sixth switch S6 is connected with the ground.

[0170] It should be noted that in the sampling working state of the switched capacitor module 20, the integral switch SI, the first switch S1, the second switch S2, the third switch S3 and the sixth switch S6 are closed, and the fourth switch S4 and the fifth switch S5 are disconnected. At this time, the charge amounts accumulated by the first capacitor C1 and the first sampling capacitor Cs1 are respectively:

[0171] Qc1 = Vos2 * C1

[0172] Qcs1 = VBE1 * Cs2

[0173] In the integral working state of the switched capacitor module 20, the integral switch SI, the first switch S1, the second switch S2 and the sixth switch S6 are disconnected, and the third switch S3, the fourth switch S4 and the fifth switch S5 are closed. Due to the virtual short and virtual open characteristics of the second operational amplifier AMP2, the voltage at the first input end of the second operational amplifier AMP2 is Vm2 + Vos2, and the charge amount of the first capacitor C1 remains unchanged (i.e., the voltage difference across the first capacitor C1 remains unchanged). Therefore, the voltage at the first node m1 satisfies the following relationship:

[0174] VBE2 + Vos2 - Vm1 = Vos2

[0175] Therefore, the voltage at the first node m1 and the charge amount accumulated thereby are:

[0176] Vm1 = VBE2

[0177] Qcs1 = (VBE2 - VBE1) * Cs1

[0178] Therefore, the voltage difference generated by the integral capacitor CI accumulating charges in the integral working state of the switched capacitor module 20 is:

[0179] VCI = (VBE2 - VBE1) * Cs1 / CI

[0180] In combination with the voltage at the first node m1, the reference voltage VBG output by the second operational amplifier AMP2 satisfies the following relationship:

[0181] VBG = VBE2 + (VBE2 - VBE1) * Cs1 / CI

[0182] As can be seen, in the above embodiment, the offset voltage Vos2 of the second operational amplifier AMP2 is fixed at the first capacitor C1. Not only is the charge (i.e., the first temperature coefficient charge Q0) output by the first sampling capacitor Cs1 independent of the offset voltage Vos2 of the second operational amplifier AMP2, but also the voltage at the first node m1 (i.e., the voltage at the first end of the integral capacitor) is also independent of the offset voltage Vos2 of the second operational amplifier AMP2, thereby completely eliminating the influence of the offset voltage of the second operational amplifier AMP2.

[0183] As yet another example, see Figure 11 , Figure 11 Another schematic diagram of the bandgap reference circuit in the embodiments of the present application is shown, wherein the switched capacitor module 20 comprises a first sampling capacitor Cs1, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a first capacitor C1, a second sampling capacitor Cs2, a second capacitor C2, a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8, and a ninth switch S9; a first end of the first switch S1 is used to access a first input voltage, a second end of the first switch S1 is connected with a first end of the first sampling capacitor Cs1; a second end of the first sampling capacitor Cs1 is connected with a first end of the second switch S2, a second end of the second switch S2 is connected with a first end of the first capacitor C1, a second end of the first capacitor C1 is connected with a first input end of the second operational amplifier AMP2; a first end of the third switch S3 is connected with a second end of the first sampling capacitor Cs1, a second end of the third switch S3 is connected with a ground terminal; a first end of the fourth switch S4 is connected with the first end of the first sampling capacitor Cs1, a second end of the fourth switch S4 is connected with the second end of the second switch S2; a first end of the fifth switch S5 is used to access a second voltage VBE2, a second end of the fifth switch S5 is connected with a first end of the second sampling capacitor Cs2, a second end of the second sampling capacitor Cs2 is connected with a second input end of the second operational amplifier AMP2; a first end of the sixth switch S6 is connected with the first end of the second sampling capacitor Cs2, a second end of the sixth switch S6 is connected with the ground terminal; a first end of the seventh switch S7 is connected with the second end of the second sampling capacitor Cs2, a second end of the seventh switch S7 is connected with the ground terminal; a first end of the eighth switch S8 is used to access the second voltage VBE2, a second end of the eighth switch S8 is connected with a first end of the second capacitor C2, a second end of the second capacitor C2 is connected with the second input end of the second operational amplifier AMP2; a first end of the ninth switch S9 is connected with the first end of the second capacitor C2, a second end of the ninth switch S9 is connected with the ground terminal.

[0184] It should be noted that, in the sampling working state of the switched capacitor module 20, the integration switch SI, the first switch S1, the second switch S2, the third switch S3, the fifth switch S5, the seventh switch S7, and the ninth switch S9 are closed, and the fourth switch S4, the sixth switch S6, and the eighth switch S8 are disconnected, at this time, the charge amount of the second capacitor C2 is zero, and the charge amounts accumulated by the first capacitor C1, the first sampling capacitor Cs1, and the second sampling capacitor Cs2 are respectively:

[0185] Qc1 = Vos2 * C1

[0186] Qcs1 = VIN * C1

[0187] Qcs2 = VBE2 * Cs2

[0188] In the integration state of the switched-capacitor module 20, the integration switch SI, the first switch S1, the second switch S2, the fifth switch S5, the seventh switch S7 and the ninth switch S9 are open, and the third switch S3, the fourth switch S4, the sixth switch S6 and the eighth switch S8 are closed. According to the charge conservation, the voltage of the second node m2 satisfies the following relationship:

[0189] Vm2 * Cs2 + (Vm2 - VBE2) * C2 = -VBE2 * Cs2

[0190] That is, the voltage of the second node m2 is:

[0191] Vm2 = VBE2 * (C2 - Cs2) / (C2 + Cs2)

[0192] Due to the virtual short and virtual open characteristics of the second operational amplifier AMP2, the voltage of the first input terminal of the second operational amplifier AMP2 is Vm2 + Vos2, and the charge amount of the first capacitor C1 remains unchanged (that is, the voltage difference across the first capacitor C1 remains unchanged). Therefore, the voltage of the first node m1 satisfies the following relationship:

[0193] Vm2 + Vos2 - Vm1 = Vos2

[0194] Therefore, the voltage of the first node m1 is:

[0195] Vm1 = Vm2 = VBE2 * (C2 - Cs2) / (C2 + Cs2)

[0196] The first input voltage VIN is generated by the voltage changing module 40 according to the first voltage VBE1. Since the first input voltage VIN and the first voltage VBE1 satisfy a first ratio, the difference between the capacitance values of the second sampling capacitor Cs2 and the second capacitor C2 satisfies a second ratio with respect to the sum of the capacitance values of the second sampling capacitor Cs2 and the second capacitor C2, and the first ratio is equal to the second ratio, that is, the first input voltage VIN and the first voltage VBE1 satisfy the following relationship:

[0197] VIN / VBE1 = (C2 - Cs2) / (C2 + Cs2)

[0198] That is, the first input voltage is VIN = (C2 - Cs2) / (C2 + Cs2) * VBE1. In combination with the voltage of the first node m1, the charge amount accumulated by the first sampling capacitor Cs1 in the integration state of the switched-capacitor module 20 is:

[0199] Qcs1 = (VIN - Vm1) * Cs1 = (C2 - Cs2) / (C2 + Cs2) * (VBE2 - VBE1) * Cs1

[0200] Therefore, the reference voltage VBG output by the second operational amplifier AMP2 satisfies the following relationship:

[0201] VBG = (C2-Cs2) / (C2+Cs2)*[VBE2+(VBE2-VBE1)*Cs1 / CI]

[0202] As can be seen, in the above formula, (C2-Cs2) / (C2+Cs2) is a constant term, so by changing C2 and Cs2, the size of the reference voltage VBG can be changed, and by changing the ratio of Cs1 / CI, the positive and negative temperature coefficient voltages can be offset and the reference voltage VBG independent of absolute temperature can be output. In addition, in the above embodiment, the offset voltage Vos2 of the second operational amplifier AMP2 is fixed at the first capacitor C1, so that not only the charge (i.e. the first temperature coefficient charge Q0) output by the first sampling capacitor Cs1 is independent of the offset voltage Vos2 of the second operational amplifier AMP2, but also the voltage at the first node m1 (i.e. the voltage at the first end of the integration capacitor CI) is independent of the offset voltage Vos2 of the second operational amplifier AMP2, thereby completely eliminating the influence of the offset voltage of the second operational amplifier AMP2.

[0203] The chip provided by the embodiment of the present application comprises the bandgap reference circuit described above. The chip (IC) can be, but is not limited to, a SOC (System on Chip) chip, a SIP (system in package) chip. Since the chip of the present application is provided with the bandgap reference circuit described in the above embodiment, it has all the beneficial effects of the bandgap reference circuit described in the above embodiment, which will not be described here again.

[0204] The electronic device provided by the embodiment of the present application comprises a device main body and a chip as described above arranged in the device main body. The electronic device can be, but is not limited to, a body weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a human body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a vehicle charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a touch pen, a true wireless earphone, a car control panel, a car, a smart wearable device, a mobile terminal, a smart home device. The smart wearable device includes, but is not limited to, a smart watch, a smart bracelet, a cervical vertebra massage instrument. The mobile terminal includes, but is not limited to, a smart phone, a notebook computer, a tablet computer, a POS (point of sales terminal) machine. The smart home device includes, but is not limited to, a smart socket, a smart rice cooker, a smart sweeper, a smart lamp.

[0205] The above merely describes the preferred embodiments of the present application, and is not intended to limit the present application in any form. Although the present application has been disclosed with the preferred embodiments as above, it is not intended to limit the present application, and any person skilled in the art can make some more changes or modifications to the equivalent embodiments with the disclosed technical content, as long as the changes or modifications do not deviate from the technical solution of the present application. Any brief modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still falls within the scope of the technical solution of the present application.

Claims

1. A bandgap reference circuit, characterized in that, include: A voltage output module, comprising a first operational amplifier, is used to output a first voltage and a second voltage, wherein the first voltage and the second voltage are negatively correlated with absolute temperature, and the first voltage difference between the first voltage and the second voltage is positively correlated with absolute temperature. A switched capacitor module is configured to output a first temperature coefficient voltage and a first temperature coefficient charge based on the first voltage and the second voltage. An integration module is used to receive the first temperature coefficient voltage and integrate the first temperature coefficient charge to output a reference voltage based on the first temperature coefficient voltage and the first temperature coefficient charge. Wherein, the first temperature coefficient voltage is negatively correlated with the absolute temperature, the first temperature coefficient charge is positively correlated with the absolute temperature, and the first temperature coefficient charge is generated based on the first voltage difference; The integration module includes a second operational amplifier, an integration capacitor, and an integration switch; The first terminal of the integrating capacitor is connected to the first input terminal of the second operational amplifier, and the second terminal of the integrating capacitor is connected to the output terminal of the second operational amplifier. The first terminal of the integral switch is connected to the first input terminal of the second operational amplifier, and the second terminal of the integral switch is connected to the output terminal of the second operational amplifier. Wherein, the first input terminal of the second operational amplifier is configured to receive the first temperature coefficient charge, and the second input terminal of the second operational amplifier is configured to be connected to the first temperature coefficient voltage.

2. The bandgap reference circuit as described in claim 1, characterized in that, The first temperature coefficient charge is independent of the offset voltage of the second operational amplifier.

3. The bandgap reference circuit as described in claim 1 or 2, characterized in that, The switched capacitor module includes a first sampling capacitor, a first switch, and a second switch; The first end of the first sampling capacitor is connected to the ground terminal, and the second end of the first sampling capacitor is connected to the first input terminal of the second operational amplifier. The first terminal of the first switch is used to connect to the first voltage, and the second terminal of the first switch is connected to the second input terminal of the second operational amplifier; The first terminal of the second switch is used to connect to the second voltage, and the second terminal of the second switch is connected to the second input terminal of the second operational amplifier.

4. The bandgap reference circuit as described in claim 1, characterized in that, The first temperature coefficient charge is independent of the offset voltage of the second operational amplifier, and the voltage at the first terminal of the integrating capacitor is independent of the offset voltage of the second operational amplifier.

5. The bandgap reference circuit as described in claim 1 or 4, characterized in that, The switched capacitor module includes a first sampling capacitor, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, and a first capacitor; The first terminal of the first switch is used to connect to the first voltage, and the second terminal of the first switch is connected to the first terminal of the first sampling capacitor; The second end of the first sampling capacitor is connected to the first end of the first capacitor, and the second end of the first capacitor is connected to the first input end of the second operational amplifier. The first terminal of the second switch is connected to the first terminal of the first sampling capacitor, and the second terminal of the second switch is connected to the ground terminal. The first terminal of the third switch is connected to the second terminal of the first sampling capacitor, and the second terminal of the third switch is connected to the ground terminal. The first terminal of the fourth switch is used to connect to the second voltage, and the second terminal of the fourth switch is connected to the second input terminal of the second operational amplifier. The first terminal of the fifth switch is connected to the second input terminal of the second operational amplifier, and the second terminal of the fifth switch is connected to the ground terminal.

6. The bandgap reference circuit as described in claim 1 or 4, characterized in that, The switched capacitor module includes a first sampling capacitor, a first capacitor, a first switch, a second switch, a third switch, a second sampling capacitor, a second capacitor, a fourth switch, a fifth switch, a sixth switch, a seventh switch, and an eighth switch; The first terminal of the first switch is used to connect to the first input voltage, and the second terminal of the first switch is connected to the first terminal of the first sampling capacitor; The second end of the first sampling capacitor is connected to the first end of the first capacitor, and the second end of the first capacitor is connected to the first input end of the second operational amplifier. The first terminal of the second switch is connected to the first terminal of the first sampling capacitor, and the second terminal of the second switch is connected to the ground terminal. The first terminal of the third switch is connected to the second terminal of the first sampling capacitor, and the second terminal of the third switch is connected to the ground terminal. The first terminal of the fourth switch is used to connect to the second voltage, the second terminal of the fourth switch is connected to the first terminal of the second sampling capacitor, and the second terminal of the second sampling capacitor is connected to the second input terminal of the second operational amplifier. The first terminal of the fifth switch is connected to the first terminal of the second sampling capacitor, and the second terminal of the fifth switch is connected to the ground terminal. The first terminal of the sixth switch is connected to the second terminal of the second sampling capacitor, and the second terminal of the sixth switch is connected to the ground terminal; The first terminal of the seventh switch is used to connect to the second voltage, the second terminal of the seventh switch is connected to the first terminal of the second capacitor, and the second terminal of the second capacitor is connected to the second input terminal of the second operational amplifier. The first terminal of the eighth switch is connected to the first terminal of the second capacitor, and the second terminal of the eighth switch is connected to the ground terminal; Wherein, the first input voltage is generated based on the first voltage, the first input voltage and the first voltage satisfy a first ratio, the difference between the capacitance values ​​of the second sampling capacitor and the second capacitor satisfies a second ratio relative to the sum of the capacitance values ​​of the second sampling capacitor and the second capacitor, and the first ratio is equal to the second ratio.

7. The bandgap reference circuit as described in claim 1 or 4, characterized in that, The switched capacitor module includes a first sampling capacitor, a first switch, a second switch, a third switch, a fourth switch, a first capacitor, a fifth switch, and a sixth switch; The first terminal of the first switch is used to connect to the first voltage, and the second terminal of the first switch is connected to the first terminal of the first sampling capacitor; The second end of the first sampling capacitor is connected to the first end of the second switch, the second end of the second switch is connected to the first end of the first capacitor, and the second end of the first capacitor is connected to the first input end of the second operational amplifier. The first terminal of the third switch is connected to the second terminal of the first sampling capacitor, and the second terminal of the third switch is connected to the ground terminal. The first terminal of the fourth switch is connected to the first terminal of the first sampling capacitor, and the second terminal of the fourth switch is connected to the second terminal of the second switch. The first terminal of the fifth switch is used to connect to the second voltage, and the second terminal of the fifth switch is connected to the second input terminal of the second operational amplifier; The first terminal of the sixth switch is connected to the second input terminal of the second operational amplifier, and the second terminal of the sixth switch is connected to the ground terminal.

8. The bandgap reference circuit as described in claim 1 or 4, characterized in that, The switched capacitor module includes a first sampling capacitor, a first switch, a second switch, a third switch, a fourth switch, a first capacitor, a second sampling capacitor, a second capacitor, a fifth switch, a sixth switch, a seventh switch, an eighth switch, and a ninth switch; The first terminal of the first switch is used to connect to the first input voltage, and the second terminal of the first switch is connected to the first terminal of the first sampling capacitor; The second end of the first sampling capacitor is connected to the first end of the second switch, the second end of the second switch is connected to the first end of the first capacitor, and the second end of the first capacitor is connected to the first input end of the second operational amplifier. The first terminal of the third switch is connected to the second terminal of the first sampling capacitor, and the second terminal of the third switch is connected to the ground terminal. The first terminal of the fourth switch is connected to the first terminal of the first sampling capacitor, and the second terminal of the fourth switch is connected to the second terminal of the second switch. The first terminal of the fifth switch is used to connect to the second voltage, the second terminal of the fifth switch is connected to the first terminal of the second sampling capacitor, and the second terminal of the second sampling capacitor is connected to the second input terminal of the second operational amplifier. The first terminal of the sixth switch is connected to the first terminal of the second sampling capacitor, and the second terminal of the sixth switch is connected to the ground terminal; The first terminal of the seventh switch is connected to the second terminal of the second sampling capacitor, and the second terminal of the seventh switch is connected to the ground terminal; The first terminal of the eighth switch is used to connect to the second voltage, the second terminal of the eighth switch is connected to the first terminal of the second capacitor, and the second terminal of the second capacitor is connected to the second input terminal of the second operational amplifier. The first terminal of the ninth switch is connected to the first terminal of the second capacitor, and the second terminal of the ninth switch is connected to the ground terminal; Wherein, the first input voltage is generated based on the first voltage, the first input voltage and the first voltage satisfy a first ratio, the difference between the capacitance values ​​of the second sampling capacitor and the second capacitor satisfies a second ratio relative to the sum of the capacitance values ​​of the second sampling capacitor and the second capacitor, and the first ratio is equal to the second ratio.

9. A chip, characterized in that, Includes the bandgap reference circuit as described in any one of claims 1 to 8.

10. An electronic device, characterized in that, Includes the chip as described in claim 9.

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