Controller and system for processing interrupt requests

Abstract

The present application discloses a controller and a system for processing interrupt requests, belonging to the field of computer technology. The controller is used to: in response to detecting an interrupt request with an interrupt identifier, determine the target processor cluster corresponding to the interrupt request; determine the transmission path of the interrupt request, the transmission path including the target processor cluster and the first interrupt node; store the first identifier corresponding to the interrupt identifier in the first memory, the first memory is used for the first interrupt node to query the first memory according to the received interrupt identifier, obtain the first identifier corresponding to the interrupt identifier, and forward the interrupt request according to the first identifier, so that the target processor cluster processes the interrupt request. By configuring the first memory, the first interrupt node can quickly and flexibly route the interrupt request according to the first memory, thereby improving the processing efficiency of the interrupt request.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to a controller and a system for processing interrupt requests. Background Art

[0002] In the field of computer technology, interrupt mechanisms exist. When a peripheral device experiences an emergency event, it sends an interrupt request to a processor cluster. The processor cluster, in response to the interrupt request, interrupts other currently executing requests and prioritizes the interrupt request, thereby promptly resolving the emergency event in the peripheral device. This eliminates the need for the processor cluster to poll peripheral devices and other components for emergency events, improving the performance of the processor cluster. However, how to enable the processor cluster to handle interrupt requests flexibly and efficiently has become a significant issue. Summary of the Invention

[0003] The embodiments of the present application provide a controller and a system for processing interrupt requests, which can be used to enable a processor cluster to flexibly and efficiently process interrupt requests. The technical solution provided by the embodiments of the present application includes the following aspects.

[0004] In a first aspect, a controller is provided, configured to: in response to detecting an interrupt request, determine a target processor cluster corresponding to the interrupt request in one or more processor clusters included in an integrated circuit, the interrupt request having an interrupt identifier, the integrated circuit further comprising an interrupt circuit coupled to the one or more processor clusters, the interrupt circuit comprising a multi-level interrupt node; determine a transmission path for the interrupt request, the transmission path comprising the target processor cluster and a first interrupt node in the multi-level interrupt nodes; store a first identifier corresponding to the interrupt identifier in a first memory, the first memory being configured to query the first memory according to the interrupt identifier after receiving the interrupt request, to obtain the first identifier corresponding to the interrupt identifier, and perform any one of the following processes according to the first identifier: when the first identifier indicates a second interrupt node in the multi-level interrupt nodes, sending the interrupt request to the target processor cluster via the second interrupt node so that the target processor cluster processes the interrupt request; or, when the first identifier indicates the target processor cluster, sending the interrupt request directly to the target processor cluster so that the target processor cluster processes the interrupt request.

[0005] In an exemplary embodiment, the transmission path also includes a third interrupt node in the multi-level interrupt node, and the controller is further used to: store a second identifier corresponding to the interrupt identifier in a second memory, and the second memory is used for the third interrupt node to query the second memory according to the interrupt identifier after receiving the interrupt request, obtain the second identifier corresponding to the interrupt identifier, and send the interrupt request to the first interrupt node indicated by the second identifier.

[0006] In an exemplary embodiment, the controller is also used to: store a third identifier corresponding to the interrupt identifier in a third memory, the third memory is used by the third interrupt node to query the third memory according to the interrupt identifier to obtain the third identifier corresponding to the interrupt identifier, in response to the value of the third identifier indicating that the third interrupt node is authorized to send the interrupt request to the first interrupt node, query the second memory according to the interrupt identifier to obtain the second identifier corresponding to the interrupt identifier.

[0007] In an exemplary embodiment, the controller is also used to: store a fourth identifier corresponding to the second identifier in a fourth memory, and the fourth memory is used by the third interrupt node to query the fourth memory according to the second identifier to obtain the fourth identifier corresponding to the second identifier, and in response to the value of the fourth identifier indicating that the first interrupt node is authorized to receive the interrupt request, send the interrupt request to the first interrupt node.

[0008] In an exemplary embodiment, the controller is also used to: in response to the first interrupt node being in an abnormal state, determine that the value of the fourth identifier indicates that the first interrupt node is not authorized to receive the interrupt request; in response to the first interrupt node returning to a normal state within a first time, update the fourth memory so that the value of the fourth identifier indicates that the first interrupt node is authorized to receive the interrupt request; in response to the first interrupt node not returning to a normal state within the first time, update the second memory and the fourth memory to update the first interrupt node and the target processor cluster included in the transmission path.

[0009] In an exemplary embodiment, the controller is also used to: store a fifth identifier corresponding to the interrupt identifier in a fifth memory, and the fifth memory is used by the first interrupt node to query the fifth memory according to the interrupt identifier to obtain the fifth identifier corresponding to the interrupt identifier; wherein, in response to the value of the fifth identifier indicating that the first interrupt node is authorized to send the interrupt request to other interrupt nodes, the first identifier indicates the second interrupt node.

[0010] In an exemplary embodiment, the controller is also used to: store a sixth identifier corresponding to the first identifier in a sixth memory, the sixth memory is used by the first interrupt node to query the sixth memory according to the first identifier to obtain the sixth identifier corresponding to the first identifier, and in response to the value of the sixth identifier indicating that the second interrupt node is authorized to receive the interrupt request, send the interrupt request to the target processor cluster through the second interrupt node.

[0011] In an exemplary embodiment, the controller is also used to: in response to the second interrupt node being in an abnormal state, determine that the value of the sixth identifier indicates that the second interrupt node is not authorized to receive the interrupt request; in response to the second interrupt node returning to a normal state within a second time, update the sixth memory so that the value of the sixth identifier indicates that the second interrupt node is authorized to receive the interrupt request; in response to the second interrupt node not returning to a normal state within the second time, update the first memory and the sixth memory to update the second interrupt node and the target processor cluster included in the transmission path.

[0012] In an exemplary embodiment, the interrupt request is an MSI (message signaled interrupt) type interrupt request, and the controller is also used to: store a fifth identifier corresponding to the interrupt identifier in a fifth memory, and the fifth memory is used by the first interrupt node to query the fifth memory according to the interrupt identifier to obtain the fifth identifier corresponding to the interrupt identifier; wherein, in response to the value of the fifth identifier indicating that the first interrupt node is not authorized to send the interrupt request to the other interrupt nodes, the first identifier indicates the target processor cluster.

[0013] In an exemplary embodiment, the controller is used to: read a seventh memory to obtain topology information, where the topology information indicates a topological relationship between the multi-level interrupt node and the one or more processor clusters; and determine a transmission path for the interrupt request based on the topology information.

[0014] In a second aspect, a method for processing an interrupt request is provided, the method comprising:

[0015] In response to detecting an interrupt request, determining a target processor cluster corresponding to the interrupt request among one or more processor clusters included in an integrated circuit, wherein the interrupt request has an interrupt identifier, the integrated circuit further comprising an interrupt circuit coupled to the one or more processor clusters, the interrupt circuit comprising multiple levels of interrupt nodes;

[0016] Determining a transmission path of the interrupt request, the transmission path including the target processor cluster and a first interrupt node in the multi-level interrupt nodes;

[0017] A first identifier corresponding to the interrupt identifier is stored in a first memory. The first memory is used for the first interrupt node to query the first memory according to the interrupt identifier after receiving the interrupt request, obtain the first identifier corresponding to the interrupt identifier, and perform any one of the following processes according to the first identifier:

[0018] In a case where the first identifier indicates a second interrupt node in the multi-level interrupt nodes, sending the interrupt request to the target processor cluster through the second interrupt node, so that the target processor cluster processes the interrupt request;

[0019] Alternatively, when the first identifier indicates the target processor cluster, the interrupt request is directly sent to the target processor cluster, so that the target processor cluster processes the interrupt request.

[0020] In an exemplary embodiment, the transmission path also includes a third interrupt node in the multi-level interrupt node, and the method further includes: storing a second identifier corresponding to the interrupt identifier in a second memory, and the second memory is used for the third interrupt node to query the second memory according to the interrupt identifier after receiving the interrupt request, obtain the second identifier corresponding to the interrupt identifier, and send the interrupt request to the first interrupt node indicated by the second identifier.

[0021] In an exemplary embodiment, the method further includes: storing a third identifier corresponding to the interrupt identifier in a third memory, the third memory being used by the third interrupt node to query the third memory according to the interrupt identifier to obtain the third identifier corresponding to the interrupt identifier, and in response to the value of the third identifier indicating that the third interrupt node is authorized to send the interrupt request to the first interrupt node, querying the second memory according to the interrupt identifier to obtain the second identifier corresponding to the interrupt identifier.

[0022] In an exemplary embodiment, the method further includes: storing a fourth identifier corresponding to the second identifier in a fourth memory, the fourth memory being used by the third interrupt node to query the fourth memory based on the second identifier to obtain the fourth identifier corresponding to the second identifier, and in response to the value of the fourth identifier indicating that the first interrupt node is authorized to receive the interrupt request, sending the interrupt request to the first interrupt node.

[0023] In an exemplary embodiment, the method further includes: in response to the first interrupt node being in an abnormal state, determining that the value of the fourth identifier indicates that the first interrupt node is not authorized to receive the interrupt request; in response to the first interrupt node returning to a normal state within a first time, updating the fourth memory so that the value of the fourth identifier indicates that the first interrupt node is authorized to receive the interrupt request; in response to the first interrupt node not returning to a normal state within the first time, updating the second memory and the fourth memory to update the first interrupt node and the target processor cluster included in the transmission path.

[0024] In an exemplary embodiment, the method further includes: storing a fifth identifier corresponding to the interrupt identifier in a fifth memory, and the fifth memory is used by the first interrupt node to query the fifth memory according to the interrupt identifier to obtain the fifth identifier corresponding to the interrupt identifier; wherein, in response to the value of the fifth identifier indicating that the first interrupt node is authorized to send the interrupt request to other interrupt nodes, the first identifier indicates the second interrupt node.

[0025] In an exemplary embodiment, the method also includes: storing a sixth identifier corresponding to the first identifier in a sixth memory, the sixth memory being used by the first interrupt node to query the sixth memory based on the first identifier to obtain the sixth identifier corresponding to the first identifier, and in response to the value of the sixth identifier indicating that the second interrupt node is authorized to receive the interrupt request, sending the interrupt request to the target processor cluster through the second interrupt node.

[0026] In an exemplary embodiment, the method further includes: in response to the second interrupt node being in an abnormal state, determining that the value of the sixth identifier indicates that the second interrupt node is not authorized to receive the interrupt request; in response to the second interrupt node returning to a normal state within a second time, updating the sixth memory so that the value of the sixth identifier indicates that the second interrupt node is authorized to receive the interrupt request; in response to the second interrupt node not returning to a normal state within the second time, updating the first memory and the sixth memory to update the second interrupt node and the target processor cluster included in the transmission path.

[0027] In an exemplary embodiment, the interrupt request is an MSI type interrupt request, and the method further includes: storing a fifth identifier corresponding to the interrupt identifier in a fifth memory, and the fifth memory is used by the first interrupt node to query the fifth memory according to the interrupt identifier to obtain the fifth identifier corresponding to the interrupt identifier; wherein, in response to the value of the fifth identifier indicating that the first interrupt node is not authorized to send the interrupt request to the other interrupt nodes, the first identifier indicates the target processor cluster.

[0028] In an exemplary embodiment, determining the transmission path of the interrupt request includes: reading a seventh memory to obtain topology information, wherein the topology information indicates a topological relationship between the multi-level interrupt node and the one or more processor clusters; and determining the transmission path of the interrupt request based on the topology information.

[0029] According to a third aspect, a system for processing an interrupt request is provided. The system includes an integrated circuit and the controller provided by the first aspect or any exemplary embodiment of the first aspect.

[0030] The technical solutions provided by the embodiments of the present application bring at least the following technical effects.

[0031] In an embodiment of the present application, since the first memory is configured, the first interrupt node can quickly determine the first identifier by querying the first memory after receiving the interrupt request, thereby realizing fast, accurate and flexible routing of the interrupt request according to the first identifier. It only takes a short time for the target processor cluster to receive (directly receive, or receive through the second interrupt node) and process the interrupt request, thereby improving the processing efficiency of the interrupt request. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0033] Figure 1 This is a schematic diagram of the structure of an integrated circuit provided in an embodiment of the present application;

[0034] Figure 2 is a schematic structural diagram of another integrated circuit provided in an embodiment of the present application;

[0035] Figure 3 is a structural diagram of a seventh memory provided in an embodiment of the present application;

[0036] Figure 4This is a schematic diagram of an address value provided in an embodiment of the present application;

[0037] Figure 5 This is a schematic diagram of the structure of another integrated circuit provided in an embodiment of the present application;

[0038] Figure 6 This is a schematic diagram of the structure of another integrated circuit provided in an embodiment of the present application;

[0039] Figure 7 This is a schematic structural diagram of another integrated circuit provided in an embodiment of the present application;

[0040] Figure 8 This is a schematic diagram of the structure of another integrated circuit provided in an embodiment of the present application;

[0041] Figure 9 This is a schematic diagram of the structure of a multi-chip system provided in an embodiment of the present application;

[0042] Figure 10 This is a schematic diagram of a routing table provided in an embodiment of the present application;

[0043] Figure 11 This is a flowchart of a method for processing an interrupt request provided by an embodiment of the present application. DETAILED DESCRIPTION

[0044] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0045] The development of modern processors has brought about tremendous changes in various fields of human society. For example, modern processors have promoted the development of industrial automation, healthcare, scientific research, and entertainment. Among them, the processor is, for example, a CPU (central processing unit).

[0046] Modern processor instruction set architectures can be categorized as complex instruction sets (CIS) and RISC (reduced instruction set computer). Complex instruction sets, such as X86, offer a first-mover advantage. RISC, with its lower power consumption and higher frequency, has gradually replaced complex instruction sets in recent years. Examples of RISC include ARM (advanced RISC machine) and RISC-V, where the V stands for five.

[0047] Furthermore, with in-depth research into semiconductor processes and processor architectures, processor performance has also improved significantly, making it possible to design highly complex processor systems. Within such complex processor systems, peripheral devices can be configured based on actual needs to expand the functionality of the complex processor system. Peripheral devices can be connected to the processor, enabling users to access the complex processor system and utilize its additional features.

[0048] The interrupt system improves the processor's efficiency when handling interrupt requests from peripheral devices. When the interrupt system receives an interrupt request from a peripheral device, the processor interrupts the currently executing program and then selects the appropriate interrupt handler to respond and process the interrupt request based on the source of the interrupt request.

[0049] In the RISC-V architecture, traditional interrupt systems only support wired interrupt requests, such as those handled by the platform-level interrupt controller (PLIC). However, in complex processor systems, the number of peripheral devices sending wired interrupt requests (i.e., the source of interrupt requests) is large, as is the number of processors required to handle them. This complicates the layout and routing of the entire interrupt system, reducing its feasibility.

[0050] AIA (Advanced Interrupt Architecture) is a new interrupt system for the RISC-V architecture. AIA adds support for MSI-type interrupt requests. In other words, in AIA, wired interrupt requests are uniformly converted to MSI-type interrupt requests for easier processor processing. This conversion is accomplished by the Advanced Platform Level Interrupt Controller (APLIC).

[0051] However, when there are a large number of peripheral devices, the number of interrupt requests is also large. It takes a long time for APLIC to process a large number of interrupt requests. Therefore, after the peripheral device sends an interrupt request, the processor needs to wait a long time before receiving the interrupt request to be processed, which affects the efficiency of interrupt request processing. In addition, in multi-chip (die, also called bare die) scenarios, that is, in complex multi-core scenarios, the peripheral devices may be located in distant physical slots. The die that receives the interrupt request and the die where the processor used to process the interrupt request are located may be different dies. Therefore, it is necessary to implement interrupt request processing in such scenarios.

[0052] The embodiment of the present application provides an integrated circuit. Figure 1 As shown, the integrated circuit includes one or more processor clusters and an interrupt circuit coupled to the one or more processor clusters, wherein the interrupt circuit includes multiple levels of interrupt nodes.

[0053] Among them, multi-level interrupt nodes refer to at least two levels of interrupt nodes. The at least two levels of interrupt nodes include interrupt nodes for interrupt control. The interrupt nodes for interrupt control can have one level. The interrupt nodes for interrupt control are connected to the processor cluster. The interrupt nodes for interrupt control are, for example, APLIC. The at least two levels of interrupt nodes also include interrupt nodes for routing interrupt requests. The interrupt nodes for routing interrupt requests can have one or more levels. When there is one level of interrupt nodes for routing interrupt requests, the interrupt nodes for routing interrupt requests are connected to the interrupt nodes for interrupt control. When there are multiple levels of interrupt nodes for routing interrupt requests, the multiple levels of interrupt nodes for routing interrupt requests are connected in sequence, and one level of interrupt nodes for routing interrupt requests is connected to the interrupt nodes for interrupt control.

[0054] When a multi-level interrupt node includes two levels of interrupt nodes, the two levels of interrupt nodes are a first interrupt node and a second interrupt node. The first interrupt node is an interrupt node for routing interrupt requests. The first interrupt node includes a first memory. The second interrupt node is an interrupt node for performing interrupt control (for example, APLIC). The first interrupt node, the second interrupt node, and the processor cluster are connected in sequence. The transmission direction of the interrupt request is, for example, the first interrupt node, the second interrupt node, and the processor cluster. In the multi-level interrupt node, the second interrupt node is the next-level interrupt node of the first interrupt node.

[0055] When the multi-level interrupt node includes three-level interrupt nodes, the three-level interrupt nodes are the first interrupt node, the second interrupt node and the third interrupt node (also called the dispatcher). The first interrupt node and the third interrupt node are interrupt nodes for routing interrupt requests, and the second interrupt node is an interrupt node for performing interrupt control. Figure 2 As shown, the third interrupt node, the first interrupt node, the second interrupt node and the processor cluster are connected in sequence, and the transmission direction of the interrupt request is, for example, the third interrupt node, the first interrupt node, the second interrupt node and the processor cluster. In the multi-level interrupt node, the first interrupt node is the next-level interrupt node of the third interrupt node.

[0056] Of course, the multi-level interrupt nodes may also include a fourth interrupt node (for example, the third interrupt node is the next-level interrupt node of the fourth interrupt node), a fifth interrupt node (for example, the fourth interrupt node is the next-level interrupt node of the fifth interrupt node), and so on, according to actual needs. Examples are not given here one by one. The integrated circuit provided in the embodiment of the present application has a tree-like topology structure of multi-level interrupt nodes and processor clusters. This topology structure has low complexity, high scalability, and high robustness, which is conducive to hierarchical management and routing of interrupt requests, improves routing efficiency, and thus improves the processing efficiency of interrupt requests.

[0057] The aforementioned processor clusters can also be referred to as processor clusters or processor groups. A processor cluster includes a configurable cache and multiple processor cores, such as a level 3 (L3) cache. In one example, a processor cluster includes four cores and one L3 cache, meaning that four cores share one L3 cache. This combination of four cores and one L3 cache is called a CPU Cluster. If a CPU die includes 64 cores, this means the CPU die includes 16 CPU Clusters.

[0058] The embodiment of the present application provides a controller for controlling the integrated circuit and processing interrupt requests. For example, the controller may run an operating system to control the integrated circuit.

[0059] Among them, the controller is used to determine the target processor cluster corresponding to the interrupt request in one or more processor clusters included in the integrated circuit in response to detecting an interrupt request, and the interrupt request has an interrupt identifier; determine the transmission path of the interrupt request, and the transmission path includes the target processor cluster and the first interrupt node in the multi-level interrupt node; store the first identifier corresponding to the interrupt identifier in the first memory, and the first memory is used for the first interrupt node to query the first memory according to the interrupt identifier after receiving the interrupt request, obtain the first identifier corresponding to the interrupt identifier, and forward the interrupt request according to the first identifier so that the target processor cluster can process the interrupt request.

[0060] Among them, the peripheral device can generate an interrupt request when an emergency occurs, and the interrupt request is used to request to improve the emergency event that occurred in the peripheral device. For example, the embodiment of the present application obtains the interrupt request generated by the peripheral device through the HMI (hub management interface, HMI), and then performs address conversion on the interrupt request through the IOMMU (input / output memory management unit, input and output memory management unit), and sends the interrupt request after address conversion to the first interrupt node. The interrupt request received by the first interrupt node is the interrupt request after address conversion. Optionally, address conversion refers to converting a virtual address into a physical address.

[0061] In some embodiments, the peripheral device is a wired interrupt device that sends a wired interrupt request. For example, the IOMMU can send the wired interrupt request to the first interrupt node via the first line, where the interrupt identifier of the wired interrupt request is the line identifier of the first line.

[0062] In some other embodiments, the peripheral device is a PCI-E (Peripheral Component Interconnect Express) device, and the PCI-E device sends an MSI-type interrupt request. Exemplarily, the IOMMU sends the MSI-type interrupt request to the first interrupt node via a second line (different from the first line described above), and the MSI-type interrupt request has an interrupt identifier that is included in the MSI-type interrupt request.

[0063] Alternatively, an HMI for obtaining wired interrupt requests is also referred to as a wired HMI, and an HMI for obtaining MSI interrupt requests is also referred to as a PCI-E HMI. Wired HMI and PCI-E HMI may be collectively referred to as a device HMI.

[0064] It can be seen that no matter what type of interrupt request the first interrupt node receives, the interrupt request has an interrupt identifier, and the interrupt identifier corresponds to the interrupt request one-to-one. In addition, each peripheral device may also have a device identifier, and the device identifier corresponds to the peripheral device one-to-one.

[0065] In some embodiments, an interrupt request has a bound processor cluster (interrupt binding technology), and the controller uses the processor cluster bound to the interrupt request as the target processor cluster. For example, there is a correspondence between an interrupt identifier and a processor cluster. The controller queries the correspondence based on the interrupt identifier of the interrupt request to obtain the processor cluster corresponding to the interrupt identifier, and then uses the queried processor cluster as the target processor cluster.

[0066] In other embodiments, the controller determines a target processor cluster based on the load conditions of each processor cluster in the multiple processor clusters. The target processor cluster is, for example, a processor cluster with a lower load rate among the multiple processor clusters. A lower load rate may mean that the load rate is lower than a load rate threshold.

[0067] After determining the target processor cluster, a transmission path for the interrupt request can be determined. This transmission path is used to transmit the interrupt request from the interrupt request initiator (such as the aforementioned peripheral device) to the target processor cluster so that the target processor cluster can process the interrupt request. The transmission path includes the target processor cluster and the first interrupt node. In other words, after the interrupt request is sent by the initiator, it can be transmitted to the target processor cluster via the first interrupt node.

[0068] For example, the transmission path may include not only the target processor cluster and the first interrupt node, but also a third interrupt node. That is, after the interrupt request is sent by the initiator, it may first be transmitted to the first interrupt node via the third interrupt node, and then transmitted to the target processor cluster via the first interrupt node. Of course, the transmission path may also include the fourth and fifth interrupt nodes mentioned above, which will not be detailed here.

[0069] In an exemplary embodiment, the controller is configured to read the seventh memory to obtain topology information indicating a topological relationship between multi-level interrupt nodes and one or more processor clusters; and determine a transmission path for the interrupt request according to the topology information.

[0070] Optionally, the seventh memory is a read-only memory, such as a read-only register. In one example, the seventh memory includes: the number of third interrupt nodes, the number of first interrupt nodes corresponding to each third interrupt node, the number of second interrupt nodes corresponding to each first interrupt node, and reserved bits to reflect the above-mentioned topology information, so that the topology information can indicate the topological relationship between the multi-level interrupt nodes and one or more processor clusters, that is, indicate the topology of the above-mentioned integrated circuit.

[0071] See also Figure 3The seventh memory is represented by AIA number control (AIA_NUMCTRL) to control the number of nodes that each routing level can support. In one example, AIA_NUMCTRL is a 32-bit memory. Figure 3 As shown, the meaning of each bit in the 32-bit memory is as follows.

[0072] Bits 31 to 24 are reserved bits, and the values ​​of the reserved bits can all be 0.

[0073] Bits 23 to 16 are DP_NODENUM, which represents the number of third interrupt nodes Dispatcher that the integrated circuit can support. The number is 256, for example.

[0074] Bits 15 to 8 are AB_NODENUM, which represents the number of first interruption nodes Arbiter that each third interruption node Dispatcher can support. The number is 256, for example.

[0075] Bits 7 to 0 are AP_NODENUM, which represents the number of second interruption nodes that each first interruption node Arbiter can support. The number is 256, for example.

[0076] Optionally, the transmission path determined by the controller is in a first format, which is a format that the controller can recognize (or understand), and the transmission path includes the identifiers of each element present on the transmission path. The transmission path can also be abstracted into a second format, which is a format that the user can recognize. In one example, the controller can also recognize the second format. For example, the second format is the format of an interrupt routing address value (IRAV). In an embodiment of the present application, the first interrupt node, the third interrupt node, and the second interrupt node can respectively have address values, and the interrupt routing address value can reflect the various interrupt nodes included in the transmission path. An exemplary structure of the address value can be found in Figure 4 .

[0077] exist Figure 4 In the address value, there are 4 fields, namely LV.3, LV.2, LV.1 and LV.0 fields, and the levels of these four fields decrease in sequence. The 15th to 12th bits of the address value are the LV.3 field, the 11th to 8th bits are the LV.2 field, the 7th to 4th bits are the LV.1 field, and the 3rd to 0th bits are the LV.0 field. Each field represents a routing level. Figure 4In the example shown, each routing level can accommodate a maximum of 16 child nodes, where the nodes at the last level are called leaf nodes. For example, the routing level represented by LV.3 includes 1 child node (e.g., 1 Dispatcher, the fourth interrupt node), the routing level represented by LV.2 includes 1 child node (e.g., 1 Dispatcher, the third interrupt node), the routing level represented by LV.1 includes 16 child nodes (e.g., 16 Arbiters, the first interrupt node), and the routing level represented by LV.0 includes 16 leaf nodes (e.g., 16 second interrupt nodes). Therefore, the integrated circuit includes a total of 256 leaf nodes.

[0078] It should be understood that Figure 4 The situation shown is only an example. In the embodiment of the present application, the total number of fields and the number of bits occupied by the fields can be changed according to the number of leaf nodes to meet actual needs. In the embodiment of the present application, there is no binding relationship between the routing level and the first interruption node or the third interruption node. For example, if the second interruption node is LV.0, the first interruption node directly connected to the second interruption node can be LV.1, LV.2, etc., and the third interruption node connected to the first interruption node can be LV.2, LV.3, etc., and so on.

[0079] Next, combine Figures 5 to 8 Give examples to illustrate several topological structures of integrated circuits.

[0080] The first topology, see Figure 5 , Figure 5 A 4-layer tree topology is shown.

[0081] There is only one LV.3 and LV.2, which are node A (the fourth interrupt node Dispatcher) and node B (the third interrupt node Dispatcher). The interrupt routing address values ​​are 0.xxx and 0.0.xx respectively, where x means ignore, that is, the routing level of x does not need to be considered.

[0082] There are two nodes in LV.1 connected to LV.2 node B, namely node C0 and node C1 (both are first interruption nodes Arbiter), and the interruption routing address values ​​are 0.0.0.x and 0.0.1.x respectively.

[0083] There are four nodes in Level 0 connected to Level 1 node C0, namely leaf nodes D0, D1, D2, and D3 (all APLIC). The interrupt routing address values ​​are 0.0.0.0, 0.0.0.1, 0.0.0.2, and 0.0.0.3 respectively.

[0084] There are three nodes in Level 0 connected to Level 1 node C1: leaf nodes D4, D5, and D6 (all APLIC). The interrupt routing address values ​​are 0.0.1.0, 0.0.1.1, and 0.0.1.2, respectively.

[0085] The second topology, see Figure 6 , Figure 6 A 3-layer tree topology is shown.

[0086] LV.3 has only one node, namely node A (the third interrupt node Dispatcher), whose interrupt routing address value is 0.xxx.

[0087] There are two LV.2 nodes connected to LV.3 node A, namely node B0 and node B1 (both are first interruption nodes Arbiter), and the interruption routing address values ​​are 0.0.xx and 0.1.xx respectively.

[0088] There are four nodes in Level 0 directly connected to Level 2 node B0, namely leaf nodes D0, D1, D2, and D3 (all APLIC). The interrupt routing address values ​​are 0.0.x.0, 0.0.x.1, 0.0.x.2, and 0.0.x.3 respectively.

[0089] There is only one LV.0 node directly connected to LV.2 node B1, namely leaf node D4 (APLIC), with an interrupt routing address value of 0.1.x.0.

[0090] The third topology, see Figure 7 , Figure 7 A 2-layer tree topology is shown.

[0091] LV.3 has only one node, namely node A (the first interrupt node Arbiter), and the interrupt routing address value is 0.xxx.

[0092] There are four LV.0 nodes directly connected to LV.3 node A, namely leaf nodes D0, D1, D2, and D3 (all APLIC). The interrupt routing address values ​​are 0.xx0, 0.xx1, 0.xx2, and 0.xx3 respectively.

[0093] The fourth topology, see Figure 8 , Figure 8 A composite topology is shown.

[0094] LV.3 has only one node, namely node A (the fourth interrupt node Dispatcher for the branch of node B0, the third interrupt node Dispatcher for the branch of node B1, and the first interrupt node Arbiter for the branch of node D7), where the interrupt routing address value is 0.xxx.

[0095] There are two LV.2 nodes connected to LV.3 node A, namely node B0 (third interrupt node Dispatcher) and node B1 (first interrupt node Arbiter), with interrupt routing address values ​​of 0.0.xx and 0.1.xx respectively.

[0096] There are two nodes in LV.1 connected to LV.2 node B0, namely nodes C0 and C1 (both are first interruption nodes Arbiter). The interruption routing address values ​​are 0.0.0.x and 0.0.1.x respectively.

[0097] There are three nodes in Level 0 connected to Level 1 node C1: leaf nodes D0, D1, and D2 (all APLIC). The interrupt routing address values ​​are 0.0.0.0, 0.0.0.1, and 0.0.0.2, respectively.

[0098] There are two LV.0 nodes connected to LV.1 node C1, leaf nodes D3 and D4 (both APLIC). The interrupt routing address values ​​are 0.0.1.0 and 0.0.1.1 respectively.

[0099] There are two LV.0 nodes directly connected to LV.2 node B1: leaf nodes D5 and D6 (both APLIC). Their interrupt routing address values ​​are 0.1.x.0 and 0.1.x.1, respectively.

[0100] There is only one LV.0 node directly connected to LV.3 node A, namely leaf node D7 (APLIC). The interrupt routing address value is 0.xx0.

[0101] According to the above description, the first memory AB_INTPROUTE[x] is used by the first interrupt node to query the first memory AB_INTPROUTE[x] according to the interrupt identifier after receiving the interrupt request, obtain the first identifier corresponding to the interrupt identifier, and forward the interrupt request according to the first identifier so that the target processor cluster receives and processes the interrupt request.

[0102] Optionally, the first memory may include multiple sub-memories, and the x in AB_INTPROUTE[x] is used to distinguish different sub-memories. The reason is that the storage space of each sub-memory is limited. When the number of interrupt identifiers is large, the storage space of one sub-memory may not be able to accommodate the first identifiers corresponding to all interrupt identifiers. Therefore, the embodiment of the present application may adopt multiple sub-memories to accommodate the first identifiers corresponding to all interrupt identifiers. Regardless of how many sub-memories the first memory includes, the interrupt identifier and the first identifier are in a one-to-one correspondence, and different sub-memories are used to store the first identifiers corresponding to different interrupt identifiers. The other memories mentioned below may also include multiple sub-memories, which will not be described in detail in the embodiment of the present application.

[0103] Since the controller has determined the transmission path of the interrupt request in the integrated circuit, the memory used by each interrupt node (such as the first interrupt node and the third interrupt node, etc.) on the transmission path for routing the interrupt request can be configured, so that each interrupt node used to route the interrupt request can query the used memory after receiving the interrupt request to forward the interrupt request according to the transmission path, thereby ensuring that the target processor cluster can receive and process the interrupt request.

[0104] For example, the first interrupt node performs any of the following processes based on the first identifier: if the first identifier indicates the second interrupt node in the multi-level interrupt node, the first interrupt node sends an interrupt request to the target processor cluster through the second interrupt node, so that the target processor cluster processes the interrupt request; or if the first identifier indicates the target processor cluster, the first interrupt node directly sends the interrupt request to the target processor cluster, so that the target processor cluster processes the interrupt request. In other words, the first identifier satisfies any of the following conditions.

[0105] In the first condition, the first identifier indicates the target processor cluster. For this condition, the first identifier directly indicates the target processor cluster, so the first interrupt node can directly send an interrupt request to the target processor cluster. Directly sending an interrupt request to the target processor cluster means sending the interrupt request to the target processor cluster without passing through the second interrupt node. For example, this condition applies when the interrupt request is an MSI-type interrupt request.

[0106] In an exemplary embodiment, the controller is also used to: store a fifth identifier corresponding to the interrupt identifier in a fifth memory, the fifth memory is used by the first interrupt node to query the fifth memory according to the interrupt identifier to obtain the fifth identifier corresponding to the interrupt identifier, in response to the value of the fifth identifier indicating that the first interrupt node is not authorized to send an interrupt request to other interrupt nodes (for example, the second interrupt node at the next level), the first identifier indicates the target processor cluster.

[0107] Thus, the first interrupt node queries the second portion of the first memory based on the interrupt identifier, obtains the first identifier, and directly sends an interrupt request to the target processor cluster indicated by the first identifier. Because the value of the fifth identifier indicates that the first interrupt node is not authorized to send an interrupt request to the second interrupt node at the next level below the first interrupt node, the first interrupt node can directly send the interrupt request to the target processor cluster according to the above description.

[0108] For example, the controller may store a fifth identifier corresponding to the interrupt identifier in the fifth memory AB_INTPCTRL[x], and the fifth identifier indicates that an interrupt request is not allowed to be sent to the second interrupt node at the next level of the first interrupt node. For example, if the interrupt identifier is 1, the fifth identifier corresponding to the interrupt identifier 1 may be stored in the first bit group (corresponding to the interrupt identifier 1) included in the fifth memory. The controller may also store a first identifier in the second part of the first memory, and the first identifier indicates the target processor cluster for processing the interrupt request. For example, if the interrupt identifier is 1 and the target processor cluster is 1, the first identifier indicating the target processor cluster 1 is stored in the first bit group (corresponding to the interrupt identifier 1) included in the second part of the first memory.

[0109] The second condition is that the first identifier indicates a second interrupt node, the second interrupt node corresponds to the target processor cluster, and the transmission path also includes the second interrupt node. For this condition, the first identifier indicates the second interrupt node, so the first interrupt node can send an interrupt request to the second interrupt node. Accordingly, the second interrupt node forwards the interrupt request to the target processor cluster, thereby implementing the interrupt request to the target processor cluster through the second interrupt node. Exemplarily, this condition can be applicable to the case where the interrupt request is a wired type interrupt request, and can also be applicable to the case where the interrupt request is an MSI type interrupt request.

[0110] In an exemplary embodiment, the controller is also used to: store a fifth identifier corresponding to the interrupt identifier in a fifth memory, the fifth memory is used by the first interrupt node to query the fifth memory according to the interrupt identifier to obtain the fifth identifier corresponding to the interrupt identifier, and in response to the value of the fifth identifier indicating that the first interrupt node is authorized to send an interrupt request to other interrupt nodes (for example, the second interrupt node at the next level), the first identifier indicates the second interrupt node.

[0111] Thus, the first interrupt node queries the first portion of the first memory based on the interrupt identifier to obtain the first identifier, and then sends an interrupt request to the target processor cluster through the second interrupt node indicated by the first identifier. Because the value of the fifth identifier indicates that the first interrupt node is authorized to send an interrupt request to the second interrupt node at the next level, the first interrupt node can directly send the interrupt request to the second interrupt node in accordance with the above instructions, and the second interrupt node forwards the interrupt request to the target processor cluster.

[0112] If the interrupt request is a wired interrupt request, the second interrupt node converts the wired interrupt request into an MSI interrupt request and forwards the MSI interrupt request to the target processor cluster. Alternatively, if the interrupt request is an MIS interrupt request, the second interrupt node does not need to convert the MSI interrupt request and can transparently transmit the MSI interrupt request to the target processor cluster.

[0113] For example, the controller may store a fifth identifier corresponding to the interrupt identifier in the fifth memory AB_INTPCTRL[x], where the fifth identifier indicates that an interrupt request is allowed to be sent to the second interrupt node at the next level of the first interrupt node. For example, if the interrupt identifier is 1, the fifth identifier corresponding to the interrupt identifier 1 may be stored in the first bit group (corresponding to the interrupt identifier 1) included in the fifth memory. The controller may also store a first identifier corresponding to the interrupt identifier in the first part of the first memory, where the first identifier is used to indicate the second interrupt node at the next level of the first interrupt node. For example, if the interrupt identifier is 1 and the second interrupt node is the second interrupt node 1, the first identifier indicating the second interrupt node 1 is stored in the first bit group (corresponding to the interrupt identifier 1) included in the first part of the first memory.

[0114] In the first condition above, the first identifier (indicating the target processor cluster) is located in the second portion of the first memory. In the second condition here, the first identifier (indicating the second interrupt node) is located in the first portion of the first memory, because the two first identifiers indicate different elements. Optionally, the first portion and the second portion are different storage spaces in the same memory (i.e., the first memory), or the first portion and the second portion are different memories (i.e., the first memory includes different memories), which is not limited in this embodiment of the present application.

[0115] Exemplarily, the target processor cluster includes at least one processing core. The target processor cluster can process the interrupt request sent by the second interrupt node through a reference processing core in the at least one processing core to improve emergency events occurring in the peripheral device.

[0116] When the target processor cluster has only one processing core, that core serves as the reference core. If the target processor cluster has multiple processing cores, the reference core can be a controller-assigned core among the multiple cores. For example, when a PCI-E device initiates an interrupt request (wired or MSI), the hypervisor (a virtualization controller) assigns a reference core to the interrupt request based on the load of the processors in the multiple processor clusters.

[0117] Optionally, the second interrupt node corresponds to a reference register, which can also be configured by the controller. The reference register includes a processing core identifier corresponding to the interrupt identifier of the interrupt request. After the second interrupt node receives the interrupt request, it queries the reference register according to the interrupt identifier to obtain the processing core identifier corresponding to the interrupt identifier. The processing core indicated by the processing core identifier is the reference processing core used to process the interrupt request. The second interrupt node sends an interrupt request to the target processor cluster where the reference processing core is located, so that the reference processing core processes the interrupt request.

[0118] In an exemplary embodiment, the controller is also used to: store a sixth identifier corresponding to the first identifier in a sixth memory, the sixth memory is used by the first interrupt node to query the sixth memory according to the first identifier, obtain the sixth identifier corresponding to the first identifier, and in response to the value of the sixth identifier indicating that the second interrupt node is authorized to receive the interrupt request, send the interrupt request to the target processor cluster through the second interrupt node indicated by the first identifier.

[0119] For example, the first interrupt node also uses the sixth memory AB_APCTRL[x], and thus the controller may store a sixth identifier corresponding to the first identifier (used to indicate the second interrupt node) in the sixth memory, where the sixth identifier is used to indicate whether the second interrupt node is allowed to receive the interrupt request. For example, if the first identifier indicating the second interrupt node 1 is the first identifier 1, then the sixth identifier corresponding to the first identifier 1 is stored in the first bit group (corresponding to the first identifier 1) included in the sixth memory.

[0120] In an exemplary embodiment, the controller is also used to: in response to the second interrupt node being in an abnormal state, determine that the value of the sixth identifier indicates that the second interrupt node is not authorized to receive an interrupt request; in response to the second interrupt node returning to a normal state within a second time, update the sixth memory so that the value of the sixth identifier indicates that the second interrupt node is authorized to receive an interrupt request; in response to the second interrupt node not returning to a normal state within the second time, update the first memory and the sixth memory to update the second interrupt node and the target processor cluster included in the transmission path.

[0121] In response to the second interrupt node being in an abnormal state, for example, the occupancy rate of the target processor cluster corresponding to the second interrupt node is higher than a threshold, it is determined that the value of the sixth flag indicates that the second interrupt node is not authorized to receive the interrupt request. It should be understood that the value of the sixth flag can be switched according to actual conditions (whether the second interrupt node is in a normal state or an abnormal state), that is, the controller can modify the value of the sixth flag according to actual conditions.

[0122] For example, if the occupancy rate of the target processor cluster is lower than the threshold within the second time, the second interrupt node returns to normal state within the second time, thereby updating the sixth memory so that the value of the sixth flag indicates that the second interrupt node is authorized to receive interrupt requests.

[0123] For another example, if the occupancy rate of the target processor cluster does not fall below the threshold within the second time, and the second interrupt node does not return to normal within the second time, the processor cluster that processes the interrupt request can be updated from the target processor cluster to another processor cluster. The other processor cluster no longer corresponds to the second interrupt node that is not authorized to receive the interrupt request, but instead corresponds to another second interrupt node. Accordingly, the first memory (to indicate the other second interrupt node) and the sixth memory (to indicate whether the other second interrupt node is authorized to receive the interrupt request) need to be updated.

[0124] As previously mentioned, in addition to the first interrupt node, the integrated circuit may also include a third interrupt node. The controller may also configure the memory used by the third interrupt node. See the following description for details.

[0125] In an exemplary embodiment, the controller is also used to: store a second identifier corresponding to the interrupt identifier in a second memory, and the second memory is used for the third interrupt node to query the second memory according to the interrupt identifier after receiving the interrupt request, obtain the second identifier corresponding to the interrupt identifier, and send an interrupt request to the first interrupt node indicated by the second identifier.

[0126] For example, the third interrupt node uses the second memory DP_INTPROUTE[x], so the controller can store a second identifier corresponding to the interrupt identifier in the second memory. The second identifier is used to indicate the first interrupt node of the next level after the third interrupt node. For example, if the interrupt identifier is 1 and the first interrupt node of the next level is first interrupt node 1, the second identifier indicating first interrupt node 1 is stored in the first bit group (corresponding to interrupt identifier 1) included in the second memory.

[0127] In an exemplary embodiment, the controller is also used to: store a third identifier corresponding to the interrupt identifier in a third memory, the third memory is used for the third interrupt node to query the third memory according to the interrupt identifier to obtain the third identifier corresponding to the interrupt identifier, in response to the value of the third identifier indicating that the third interrupt node is authorized to send an interrupt request to the first interrupt node, query the second memory according to the interrupt identifier to obtain the second identifier corresponding to the interrupt identifier.

[0128] For example, the third interrupt node also uses the third memory DP_INTPCTRL[x], so the controller can store a third identifier corresponding to the interrupt identifier in the third memory, and the third identifier is used to indicate whether to allow an interrupt request to be sent to the first interrupt node at the next level of the third interrupt node. For example, if the interrupt identifier is 1, the third identifier corresponding to the interrupt identifier being 1 is stored in the first bit group (corresponding to the interrupt identifier 1) included in the third memory. The third identifier can be determined based on actual conditions and is not limited in this embodiment of the present application.

[0129] In an exemplary embodiment, the controller is also used to: store a fourth identifier corresponding to the second identifier in a fourth memory, the fourth memory is used by the third interrupt node to query the fourth memory according to the second identifier, obtain the fourth identifier corresponding to the second identifier, and in response to the value of the fourth identifier indicating that the first interrupt node is authorized to receive the interrupt request, send an interrupt request to the first interrupt node.

[0130] For example, the third interrupt node also uses the fourth memory DP_ABCTRL[x], and thus the controller may store a fourth identifier corresponding to the second identifier (used to indicate the first interrupt node) in the fourth memory, where the fourth identifier is used to indicate whether the first interrupt node is allowed to receive interrupt requests. For example, if the second identifier indicating the first interrupt node 1 is second identifier 1, then the fourth identifier corresponding to second identifier 1 is stored in the first bit group (corresponding to second identifier 1) included in the fourth memory.

[0131] In an exemplary embodiment, the controller is also used to: in response to the first interrupt node being in an abnormal state, determine that the value of the fourth identifier indicates that the first interrupt node is not authorized to receive an interrupt request; in response to the first interrupt node returning to a normal state within a first time, update the fourth memory so that the value of the fourth identifier indicates that the first interrupt node is authorized to receive an interrupt request; in response to the first interrupt node not returning to a normal state within the first time, update the second memory and the fourth memory to update the first interrupt node and the target processor cluster included in the transmission path.

[0132] In response to the first interrupt node being in an abnormal state, for example, the occupancy rate of the target processor cluster corresponding to the second interrupt node corresponding to the first interrupt node is higher than a threshold, it is determined that the value of the fourth identifier indicates that the first interrupt node is not authorized to receive the interrupt request. It should be understood that the value of the fourth identifier can be switched according to actual conditions (whether the first interrupt node is in a normal state or an abnormal state), that is, the controller can modify the value of the fourth identifier according to actual conditions.

[0133] For example, if the occupancy rate of the target processor cluster is lower than the threshold within the first time, the first interrupt node returns to normal state within the first time; or, if other processor clusters different from the target processor cluster are replaced within the first time, the target processor cluster and the other processor clusters correspond to different second interrupt nodes, but correspond to the same first interrupt node, then the first interrupt node also returns to normal state within the first time, and the fourth memory can be updated so that the value of the fourth identifier indicates that the first interrupt node is authorized to receive interrupt requests.

[0134] For another example, if the occupancy rate of the target processor cluster does not fall below a threshold within the first time, the processor cluster that processes the interrupt request may be updated from the target processor cluster to another processor cluster. The target processor cluster and the other processor cluster correspond to different second interrupt nodes, and the other processor cluster corresponds to a first interrupt node different from the first interrupt node. If the first interrupt node does not return to normal state within the first time, the second memory (to indicate the other first interrupt node) and the fourth memory (to indicate whether the other first interrupt node is authorized to receive the interrupt request) need to be updated accordingly.

[0135] Next, combine Figure 9 and Figure 10 The following examples illustrate the process of the controller configuring the memory and the process of the integrated circuit routing the interrupt request. Figure 9 This is an exemplary multi-DIE architecture that forms a SOC (system on chip). Figure 9 In the , there are four dies, namely IO DIE 0, IO DIE 1, CPU DIE 0, and CPU DIE 0. D2D represents the communication module between different DIEs.

[0136] IO DIE 0 and IO DIE 1 include the Device Hub and IOMMU, respectively. The functions of the Device Hub and IOMMU can be found in the above description and are not detailed here.

[0137] CPU DIE 1 includes LV.3, LV.2, and LV.0 nodes. LV.3 is node A, LV.2 is node B1, and LV.0 is node D5, D6, and D7.

[0138] CPU DIE 0 includes LV.2, LV.1, and LV.0 nodes. LV.2 is node B0, LV.1 is node C0 and C1, and LV.0 is node D0, D1, D2, D3, and D4.

[0139] See also Figure 10The peripheral device with device ID 0 sends interrupt request 0. The address value corresponding to interrupt request 0 is 0.0.0.0, indicating that the target processor cluster for interrupt request 0 is CPU Cluster 0. Based on this, the controller determines that the routing path corresponding to interrupt request 0 is node A, node B0, node C0, and node D0. Therefore, the controller configures the memory used by nodes A, B0, and C0 respectively, so that node A sends interrupt request 0 to node B0, node B0 sends interrupt request 0 to node C0, and node C0 sends interrupt request 0 to node D0. Interrupt request 0 can then be sent by node D0 to CPU Cluster 0, and CPU Cluster 0 processes it. In this case, cross-CPUDIE processing of interrupt request 0 is achieved, which is more flexible.

[0140] Continue to see Figure 10 The peripheral device with device ID m+1 sends interrupt request j. The address corresponding to interrupt request j is 0.1.x.1, which means that the target processor cluster corresponding to interrupt request j is CPU Cluster 6. Based on this, the controller determines that the routing path corresponding to interrupt request j is node A, node B1, and node D6. Therefore, the controller configures the memory used by nodes A and B1 respectively so that node A sends interrupt request j to node B1, and node B1 sends interrupt request j to node D6. Then, interrupt request j can be sent by node D6 to CPU Cluster 6, and CPU Cluster 6 processes interrupt request j.

[0141] To sum up, in the embodiment of the present application, since the first memory is configured, the first interrupt node can quickly determine the first identifier by querying the first memory after receiving the interrupt request, thereby realizing fast, accurate and flexible routing of the interrupt request according to the first identifier. It only takes a short time for the target processor cluster to receive (directly receive, or receive through the second interrupt node) and process the interrupt request, thereby improving the processing efficiency of the interrupt request.

[0142] The embodiment of the present application also provides a method for processing an interrupt request, which can be applied to the controller described above. Figure 11 As shown, the method includes the following steps.

[0143] Step 1101, in response to detecting an interrupt request, determining a target processor cluster corresponding to the interrupt request in one or more processor clusters included in an integrated circuit, the interrupt request having an interrupt identifier, the integrated circuit further comprising an interrupt circuit coupled to the one or more processor clusters, the interrupt circuit comprising multiple levels of interrupt nodes.

[0144] Step 1102 : Determine a transmission path of the interrupt request, where the transmission path includes a target processor cluster and a first interrupt node in a multi-level interrupt node.

[0145] In an exemplary embodiment, determining a transmission path of an interrupt request includes: reading a seventh memory to obtain topology information, where the topology information indicates a topological relationship between multi-level interrupt nodes and one or more processor clusters; and determining the transmission path of the interrupt request based on the topology information.

[0146] Step 1103, storing a first identifier corresponding to the interrupt identifier in a first memory, the first memory is used for the first interrupt node to query the first memory according to the interrupt identifier after receiving the interrupt request, to obtain the first identifier corresponding to the interrupt identifier, and to perform any of the following processes according to the first identifier: when the first identifier indicates the second interrupt node in the multi-level interrupt node, sending the interrupt request to the target processor cluster through the second interrupt node so that the target processor cluster processes the interrupt request; or, when the first identifier indicates the target processor cluster, sending the interrupt request directly to the target processor cluster so that the target processor cluster processes the interrupt request.

[0147] In response to detecting an interrupt request, determining a target processor cluster corresponding to the interrupt request among one or more processor clusters included in the integrated circuit, the interrupt request having an interrupt identifier, the integrated circuit further comprising an interrupt circuit coupled to the one or more processor clusters, the interrupt circuit comprising a plurality of levels of interrupt nodes;

[0148] Determining a transmission path of the interrupt request, the transmission path including a target processor cluster and a first interrupt node in a multi-level interrupt node;

[0149] A first identifier corresponding to the interrupt identifier is stored in the first memory. The first memory is used for the first interrupt node to query the first memory according to the interrupt identifier after receiving the interrupt request, obtain the first identifier corresponding to the interrupt identifier, and perform any one of the following processes according to the first identifier:

[0150] In a case where the first identifier indicates a second interrupt node in the multi-level interrupt node, sending an interrupt request to the target processor cluster through the second interrupt node, so that the target processor cluster processes the interrupt request;

[0151] Alternatively, when the first identifier indicates the target processor cluster, the interrupt request is directly sent to the target processor cluster so that the target processor cluster processes the interrupt request.

[0152] In an exemplary embodiment, the transmission path also includes a third interrupt node in the multi-level interrupt node, and the method also includes: storing a second identifier corresponding to the interrupt identifier in a second memory, and the second memory is used for the third interrupt node to query the second memory according to the interrupt identifier after receiving the interrupt request, obtain the second identifier corresponding to the interrupt identifier, and send an interrupt request to the first interrupt node indicated by the second identifier.

[0153] In an exemplary embodiment, the method further includes: storing a third identifier corresponding to the interrupt identifier in a third memory, the third memory being used by the third interrupt node to query the third memory according to the interrupt identifier to obtain the third identifier corresponding to the interrupt identifier, and in response to the value of the third identifier indicating that the third interrupt node is authorized to send an interrupt request to the first interrupt node, querying the second memory according to the interrupt identifier to obtain the second identifier corresponding to the interrupt identifier.

[0154] In an exemplary embodiment, the method also includes: storing a fourth identifier corresponding to the second identifier in a fourth memory, the fourth memory being used by the third interrupt node to query the fourth memory based on the second identifier to obtain the fourth identifier corresponding to the second identifier, and in response to the value of the fourth identifier indicating that the first interrupt node is authorized to receive the interrupt request, sending an interrupt request to the first interrupt node.

[0155] In an exemplary embodiment, the method also includes: in response to the first interrupt node being in an abnormal state, determining that the value of the fourth identifier indicates that the first interrupt node is not authorized to receive an interrupt request; in response to the first interrupt node returning to a normal state within a first time, updating the fourth memory so that the value of the fourth identifier indicates that the first interrupt node is authorized to receive an interrupt request; in response to the first interrupt node not returning to a normal state within the first time, updating the second memory and the fourth memory to update the first interrupt node and the target processor cluster included in the transmission path.

[0156] In an exemplary embodiment, the method further includes: storing a fifth identifier corresponding to the interrupt identifier in a fifth memory, and the fifth memory is used by the first interrupt node to query the fifth memory according to the interrupt identifier to obtain the fifth identifier corresponding to the interrupt identifier; wherein, in response to the value of the fifth identifier indicating that the first interrupt node is authorized to send an interrupt request to other interrupt nodes, the first identifier indicates the second interrupt node.

[0157] In an exemplary embodiment, the method also includes: storing a sixth identifier corresponding to the first identifier in a sixth memory, the sixth memory being used by the first interrupt node to query the sixth memory based on the first identifier to obtain the sixth identifier corresponding to the first identifier, and in response to the value of the sixth identifier indicating that the second interrupt node is authorized to receive the interrupt request, sending the interrupt request to the target processor cluster through the second interrupt node.

[0158] In an exemplary embodiment, the method also includes: in response to the second interrupt node being in an abnormal state, determining that the value of the sixth identifier indicates that the second interrupt node is not authorized to receive an interrupt request; in response to the second interrupt node returning to a normal state within a second time, updating the sixth memory so that the value of the sixth identifier indicates that the second interrupt node is authorized to receive an interrupt request; in response to the second interrupt node not returning to a normal state within the second time, updating the first memory and the sixth memory to update the second interrupt node and the target processor cluster included in the transmission path.

[0159] In an exemplary embodiment, the interrupt request is an MSI type interrupt request, and the method further includes: storing a fifth identifier corresponding to the interrupt identifier in a fifth memory, and the fifth memory is used by the first interrupt node to query the fifth memory according to the interrupt identifier to obtain the fifth identifier corresponding to the interrupt identifier; wherein, in response to the value of the fifth identifier indicating that the first interrupt node is not authorized to send an interrupt request to other interrupt nodes, the first identifier indicates a target processor cluster.

[0160] It should be noted that Figure 11 The method shown has the same concept as the controller embodiment described above. The specific implementation process and technical effects thereof are detailed in the controller embodiment and will not be described in detail here.

[0161] Illustratively, an embodiment of the present application further provides a system for processing an interrupt request, the system including the controller and integrated circuit described above.

[0162] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequential sequence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments of the application described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the above exemplary embodiments do not represent all embodiments consistent with this application. Instead, they are merely examples of devices and methods consistent with certain aspects of this application as detailed in the appended claims.

[0163] It should be understood that the term "plurality" as used herein refers to two or more than two. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship.

[0164] The above description is merely an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A controller, characterized in that: The controller is used to: In response to detecting an interrupt request, determining a target processor cluster corresponding to the interrupt request among one or more processor clusters included in an integrated circuit, wherein the interrupt request has an interrupt identifier, the integrated circuit further comprising an interrupt circuit coupled to the one or more processor clusters, the interrupt circuit comprising multiple levels of interrupt nodes; Determining a transmission path of the interrupt request, the transmission path including the target processor cluster and a first interrupt node in the multi-level interrupt nodes; storing a first identifier corresponding to the interrupt identifier in a first memory, wherein the first memory is used for the first interrupt node to query the first memory according to the interrupt identifier after receiving the interrupt request to obtain the first identifier corresponding to the interrupt identifier; In the case where the first identifier indicates a second interrupt node in the multi-level interrupt node, the interrupt request is sent to the second interrupt node, and the interrupt request is used to be transparently transmitted by the second interrupt node so that the target processor cluster processes the interrupt request, or the interrupt request is used to be type-converted by the second interrupt node and sent to the target processor cluster so that the target processor cluster processes the interrupt request after type conversion.

2. The controller according to claim 1, wherein: The transmission path further includes a third interrupt node in the multi-level interrupt nodes, and the controller is further configured to: A second identifier corresponding to the interrupt identifier is stored in a second memory. The second memory is used for the third interrupt node to query the second memory according to the interrupt identifier after receiving the interrupt request, obtain the second identifier corresponding to the interrupt identifier, and send the interrupt request to the first interrupt node indicated by the second identifier.

3. The controller according to claim 2, characterized in that The controller is also used for: A third identifier corresponding to the interrupt identifier is stored in a third memory. The third memory is used by the third interrupt node to query the third memory according to the interrupt identifier to obtain the third identifier corresponding to the interrupt identifier. In response to the value of the third identifier indicating that the third interrupt node is authorized to send the interrupt request to the first interrupt node, the second memory is queried according to the interrupt identifier to obtain a second identifier corresponding to the interrupt identifier.

4. The controller according to claim 2, characterized in that The controller is also used for: A fourth identifier corresponding to the second identifier is stored in a fourth memory, and the fourth memory is used by the third interrupt node to query the fourth memory according to the second identifier to obtain the fourth identifier corresponding to the second identifier, and in response to the value of the fourth identifier indicating that the first interrupt node is authorized to receive the interrupt request, the interrupt request is sent to the first interrupt node.

5. The controller according to claim 4, characterized in that The controller is also used for: In response to the first interrupt node being in an abnormal state, determining that a value of the fourth identifier indicates that the first interrupt node is not authorized to receive the interrupt request; In response to the first interrupt node returning to a normal state within a first time, updating the fourth memory so that the value of the fourth identifier indicates that the first interrupt node is authorized to receive the interrupt request; In response to the first interrupt node not returning to a normal state within the first time, the second memory and the fourth memory are updated to update the first interrupt node and the target processor cluster included in the transmission path.

6. The controller according to any one of claims 1 to 5, characterized in that: The controller is also used for: storing a fifth identifier corresponding to the interrupt identifier in a fifth memory, wherein the fifth memory is used by the first interrupt node to query the fifth memory according to the interrupt identifier to obtain the fifth identifier corresponding to the interrupt identifier; In response to the value of the fifth identifier indicating that the first interrupt node is authorized to send the interrupt request to other interrupt nodes, the first identifier indicates the second interrupt node.

7. The controller according to claim 6, characterized in that The controller is also used for: A sixth identifier corresponding to the first identifier is stored in a sixth memory, and the sixth memory is used by the first interrupt node to query the sixth memory according to the first identifier to obtain the sixth identifier corresponding to the first identifier, and in response to the value of the sixth identifier indicating that the second interrupt node is authorized to receive the interrupt request, send the interrupt request to the second interrupt node.

8. The controller according to claim 7, characterized in that The controller is also used for: In response to the second interrupt node being in an abnormal state, determining that a value of the sixth flag indicates that the second interrupt node is not authorized to receive the interrupt request; In response to the second interrupt node returning to a normal state within a second time, updating the sixth memory so that the value of the sixth flag indicates that the second interrupt node is authorized to receive the interrupt request; In response to the second interrupt node not returning to a normal state within the second time, the first memory and the sixth memory are updated to update the second interrupt node and the target processor cluster included in the transmission path.

9. The controller according to any one of claims 1 to 5, characterized in that: The interrupt request is a message signal interrupt (MSI) type interrupt request, and the controller is further configured to: storing a fifth identifier corresponding to the interrupt identifier in a fifth memory, wherein the fifth memory is used by the first interrupt node to query the fifth memory according to the interrupt identifier to obtain the fifth identifier corresponding to the interrupt identifier; In response to the value of the fifth identifier indicating that the first interrupt node is not authorized to send the interrupt request to other interrupt nodes, the first identifier indicates the target processor cluster.

10. The controller according to any one of claims 1-5, 7 or 8, characterized in that: The controller is used to: Reading a seventh memory to obtain topology information, where the topology information indicates a topological relationship between the multi-level interrupt node and the one or more processor clusters; A transmission path of the interrupt request is determined according to the topology information.

11. A system for processing interrupt requests, characterized in that: The system comprises an integrated circuit and the controller according to any one of claims 1-10.

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