Integrated circuit, method and system for processing interrupt request

Abstract

The present application discloses an integrated circuit, a method and a system for processing interrupt requests, and belongs to the field of computer technology. The integrated circuit includes one or more processor clusters, and a coupled interrupt circuit. The interrupt circuit is used to receive an interrupt request through a first interrupt node in a multi-level interrupt node, query a first memory according to an interrupt identifier of the interrupt request, and obtain a first identifier corresponding to the interrupt identifier. In the case where the first identifier indicates a second interrupt node in a multi-level interrupt node, an interrupt request is sent to a target processor cluster through the first interrupt node and the second interrupt node, or in the case where the first identifier indicates a target processor cluster, an interrupt request is sent to the target processor cluster through the first interrupt node, so that the target processor cluster processes the interrupt request. The first interrupt node routes the interrupt request quickly and flexibly according to the first memory, thereby improving the processing efficiency of the interrupt request.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to an integrated circuit, a method for processing an interrupt request, and a system. Background Art

[0002] In the field of computer technology, interrupt mechanisms exist. In this mechanism, a peripheral device sends an interrupt request to a processor cluster when an emergency occurs. Upon receiving the interrupt request, the processor cluster interrupts other currently executing requests and prioritizes the interrupt request, thereby promptly resolving the emergency. This eliminates the need for the processor cluster to poll peripheral devices and other components for emergency events, improving the performance of the processor cluster. However, ensuring that the processor cluster can handle interrupt requests flexibly and efficiently has become a significant issue. Summary of the Invention

[0003] The embodiments of the present application provide an integrated circuit, a method and a system for processing interrupt requests, which can be used to enable a processor cluster to flexibly and efficiently process interrupt requests. The technical solutions provided by the embodiments of the present application include the following aspects.

[0004] In a first aspect, an integrated circuit is provided, comprising one or more processor clusters and an interrupt circuit coupled to the one or more processor clusters, the interrupt circuit comprising a multi-level interrupt node, the interrupt circuit being configured to: receive an interrupt request through a first interrupt node in the multi-level interrupt nodes, the interrupt request having an interrupt identifier; and query a first memory through the first interrupt node according to the interrupt identifier to obtain a first identifier corresponding to the interrupt identifier.

[0005] In a case where the first identifier indicates the second interrupt node in the multi-level interrupt nodes, the interrupt request is sent to a target processor cluster in the one or more processor clusters through the first interrupt node and the second interrupt node, so that the target processor cluster processes the interrupt request; or, in a case where the first identifier indicates the target processor cluster, the interrupt request is sent directly to the target processor cluster through the first interrupt node, so that the target processor cluster processes the interrupt request.

[0006] In an exemplary embodiment, the interrupt circuit is further used to: receive the interrupt request through a third interrupt node in the multi-level interrupt node; query the second memory according to the interrupt identifier through the third interrupt node to obtain a second identifier corresponding to the interrupt identifier; and send the interrupt request to the first interrupt node indicated by the second identifier through the third interrupt node.

[0007] In an exemplary embodiment, the interrupt circuit is further configured to query a third memory based on the interrupt identifier via the third interrupt node to obtain a third identifier corresponding to the interrupt identifier. The interrupt circuit is configured to query the second memory based on the interrupt identifier via the third interrupt node to obtain a second identifier corresponding to the interrupt identifier if the value of the third identifier indicates that the third interrupt node is authorized to send the interrupt request to the first interrupt node.

[0008] In an exemplary embodiment, the interrupt circuit is further configured to query a fourth memory based on the second identifier via the third interrupt node to obtain a fourth identifier corresponding to the second identifier. The interrupt circuit is configured to send the interrupt request to the first interrupt node via the third interrupt node if the value of the fourth identifier indicates that the first interrupt node is authorized to receive the interrupt request.

[0009] In an exemplary embodiment, the interrupt circuit is further used to: query the fifth memory according to the interrupt identifier through the first interrupt node to obtain a fifth identifier corresponding to the interrupt identifier; wherein, when the value of the fifth identifier indicates that the first interrupt node is authorized to send the interrupt request to other interrupt nodes, the first identifier indicates the second interrupt node.

[0010] In an exemplary embodiment, the interrupt circuit is further configured to query a sixth memory based on the first identifier via the first interrupt node to obtain a sixth identifier corresponding to the first identifier. In an exemplary embodiment, the interrupt circuit is configured to send the interrupt request to the target processor cluster via the first interrupt node and the second interrupt node if the value of the sixth identifier indicates that the second interrupt node is authorized to receive the interrupt request.

[0011] In an exemplary embodiment, the interrupt request is an MSI (Message Signaled Interrupt) type interrupt request; the interrupt circuit is also used to: query the fifth memory according to the interrupt identifier through the first interrupt node to obtain a fifth identifier corresponding to the interrupt identifier; wherein, when the value of the fifth identifier indicates that the first interrupt node is not authorized to send the interrupt request to other interrupt nodes, the first identifier indicates the target processor cluster.

[0012] In a second aspect, a method for processing an interrupt request is provided, the method comprising: receiving an interrupt request through a first interrupt node in a multi-level interrupt node, the interrupt request having an interrupt identifier; querying a first memory according to the interrupt identifier through the first interrupt node to obtain a first identifier corresponding to the interrupt identifier. In the case where the first identifier indicates a second interrupt node in the multi-level interrupt node, sending the interrupt request through the first interrupt node and the second interrupt node to a target processor cluster in one or more processor clusters so that the target processor cluster processes the interrupt request; or, in the case where the first identifier indicates the target processor cluster, sending the interrupt request directly to the target processor cluster through the first interrupt node so that the target processor cluster processes the interrupt request.

[0013] In an exemplary embodiment, the method further includes: receiving the interrupt request through a third interrupt node in the multi-level interrupt node; querying a second memory according to the interrupt identifier through the third interrupt node to obtain a second identifier corresponding to the interrupt identifier; and sending the interrupt request to the first interrupt node indicated by the second identifier through the third interrupt node.

[0014] In an exemplary embodiment, the method further includes: querying a third memory based on the interruption identifier by the third interruption node to obtain a third identifier corresponding to the interruption identifier. Querying a second memory based on the interruption identifier by the third interruption node includes: when the value of the third identifier indicates that the third interruption node is authorized to send the interruption request to the first interruption node, querying the second memory based on the interruption identifier by the third interruption node to obtain a second identifier corresponding to the interruption identifier.

[0015] In an exemplary embodiment, the method further includes: querying a fourth memory according to the second identifier via the third interrupt node to obtain a fourth identifier corresponding to the second identifier. Sending the interrupt request to the first interrupt node indicated by the second identifier via the third interrupt node includes: sending the interrupt request to the first interrupt node via the third interrupt node if the value of the fourth identifier indicates that the first interrupt node is authorized to receive the interrupt request.

[0016] In an exemplary embodiment, the method further includes: querying a fifth memory according to the interrupt identifier through the first interrupt node to obtain a fifth identifier corresponding to the interrupt identifier; wherein, when the value of the fifth identifier indicates that the first interrupt node is authorized to send the interrupt request to other interrupt nodes, the first identifier indicates the second interrupt node.

[0017] In an exemplary embodiment, the method also includes: querying the sixth memory according to the first identifier through the first interrupt node to obtain the sixth identifier corresponding to the first identifier; sending the interrupt request to the target processor cluster in the one or more processor clusters through the first interrupt node and the second interrupt node, including: when the value of the sixth identifier indicates that the second interrupt node is authorized to receive the interrupt request, sending the interrupt request to the target processor cluster through the first interrupt node and the second interrupt node.

[0018] In an exemplary embodiment, the interrupt request is a message signal interrupt (MSI) type interrupt request; the method further includes: querying a fifth memory according to the interrupt identifier through the first interrupt node to obtain a fifth identifier corresponding to the interrupt identifier; wherein, when the value of the fifth identifier indicates that the first interrupt node is not authorized to send the interrupt request to other interrupt nodes, the first identifier indicates the target processor cluster.

[0019] In a third aspect, a system for processing interrupt requests is provided, comprising an acquisition source and the integrated circuit provided by the first aspect or any exemplary embodiment of the first aspect. The acquisition source is configured to acquire an interrupt request and send the interrupt request to the integrated circuit; the integrated circuit is configured to process the interrupt request.

[0020] The technical solutions provided by the embodiments of the present application bring at least the following technical effects.

[0021] In an embodiment of the present application, the first interrupt node included in the interrupt circuit can quickly determine the first identifier by querying the first memory after receiving the interrupt request, thereby realizing fast, accurate and flexible routing of the interrupt request according to the first identifier. It only takes a short time for the target processor cluster to receive (directly receive, or receive through the second interrupt node) and process the interrupt request, thereby improving the processing efficiency of the interrupt request. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a schematic diagram of the structure of a processing integrated circuit provided in an embodiment of the present application;

[0023] Figure 2 is a schematic structural diagram of a first sub-memory provided in an embodiment of the present application;

[0024] Figure 3 is a schematic structural diagram of a fifth sub-memory provided in an embodiment of the present application;

[0025] Figure 4 is a schematic structural diagram of a sixth sub-memory provided in an embodiment of the present application;

[0026] Figure 5 is a schematic structural diagram of another integrated circuit provided in an embodiment of the present application;

[0027] Figure 6 is a schematic structural diagram of a second sub-memory provided in an embodiment of the present application;

[0028] Figure 7 is a schematic structural diagram of a third sub-memory provided in an embodiment of the present application;

[0029] Figure 8 is a schematic structural diagram of a fourth sub-memory provided in an embodiment of the present application;

[0030] Figure 9 This is a schematic diagram of the structure of a multi-chip system provided in an embodiment of the present application;

[0031] Figure 10 This is a flowchart of a method for processing an interrupt request provided by an embodiment of the present application. DETAILED DESCRIPTION

[0032] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0033] The development of modern processors has brought about tremendous changes in various fields of human society. For example, modern processors have promoted the development of industrial automation, healthcare, scientific research, and entertainment. Among them, the processor is, for example, a CPU (central processing unit).

[0034] Modern processor instruction set architectures can be categorized as complex instruction sets (CIS) and RISC (reduced instruction set computer). Complex instruction sets, such as X86, offer a first-mover advantage. RISC, with its lower power consumption and higher frequency, has gradually replaced complex instruction sets in recent years. Examples of RISC include ARM (advanced RISC machine) and RISC-V, where the V stands for five.

[0035] Furthermore, with in-depth research into semiconductor processes and processor architectures, processor performance has also improved significantly, making it possible to design highly complex processor systems. Within such complex processor systems, peripheral devices can be configured based on actual needs to expand the functionality of the complex processor system. Peripheral devices can be connected to the processor, enabling users to access the complex processor system and utilize its additional features.

[0036] The interrupt system improves the processor's efficiency when handling interrupt requests from peripheral devices. When the interrupt system receives an interrupt request from a peripheral device, the processor interrupts the currently executing program and then selects the appropriate interrupt handler to respond and process the interrupt request based on the source of the interrupt request.

[0037] In the RISC-V architecture, traditional interrupt systems only support wired interrupt requests, such as those handled by the platform-level interrupt controller (PLIC). However, in complex processor systems, the number of peripheral devices sending wired interrupt requests (i.e., the source of interrupt requests) is large, as is the number of processors required to handle them. This complicates the layout and routing of the entire interrupt system, reducing its feasibility.

[0038] AIA (Advanced Interrupt Architecture) is a new interrupt system for the RISC-V architecture. AIA adds support for MSI-type interrupt requests. In other words, in AIA, wired interrupt requests are uniformly converted to MSI-type interrupt requests for easier processor processing. This conversion is accomplished by the Advanced Platform Level Interrupt Controller (APLIC).

[0039] However, when there are a large number of peripheral devices, the number of interrupt requests is also large. It takes a long time for the APLIC to process a large number of interrupt requests. Therefore, after the peripheral device sends an interrupt request, the processor needs to wait a long time before receiving the interrupt request to be processed, which affects the efficiency of interrupt request processing. In addition, in multi-chip (die, also called bare die) scenarios, that is, in complex multi-core scenarios, the die that receives the interrupt request and the die where the processor used to process the interrupt request are located may be different dies, so it is necessary to implement interrupt request processing in such scenarios.

[0040] The embodiment of the present application provides an integrated circuit, such as Figure 1 As shown, the integrated circuit includes one or more processor clusters and an interrupt circuit coupled to the one or more processor clusters, wherein the interrupt circuit includes multiple levels of interrupt nodes.

[0041] Among them, multi-level interrupt nodes refer to at least two levels of interrupt nodes. The at least two levels of interrupt nodes include interrupt nodes for interrupt control. The interrupt nodes for interrupt control can have one level. The interrupt nodes for interrupt control are connected to the processor cluster. The interrupt nodes for interrupt control are, for example, APLIC. The at least two levels of interrupt nodes also include interrupt nodes for routing interrupt requests. The interrupt nodes for routing interrupt requests can have one or more levels. When there is one level of interrupt nodes for routing interrupt requests, the interrupt nodes for routing interrupt requests are connected to the interrupt nodes for interrupt control. When there are multiple levels of interrupt nodes for routing interrupt requests, the multiple levels of interrupt nodes for routing interrupt requests are connected in sequence, and one level of interrupt nodes for routing interrupt requests is connected to the interrupt nodes for interrupt control.

[0042] When a multi-level interrupt node includes two levels of interrupt nodes, the two levels of interrupt nodes are a first interrupt node and a second interrupt node. The first interrupt node is an interrupt node for routing interrupt requests, and the second interrupt node is an interrupt node for performing interrupt control (for example, APLIC). The first interrupt node, the second interrupt node, and the processor cluster are connected in sequence. The transmission direction of the interrupt request is, for example, the first interrupt node, the second interrupt node, and the processor cluster. In the multi-level interrupt node, the second interrupt node is the next-level interrupt node of the first interrupt node.

[0043] When the multi-level interrupt node includes three-level interrupt nodes, the three-level interrupt nodes are the first interrupt node, the second interrupt node and the third interrupt node. The first interrupt node and the third interrupt node are interrupt nodes used to route interrupt requests, the second interrupt node is an interrupt node used to perform interrupt control, the third interrupt node, the first interrupt node, the second interrupt node and the processor cluster are connected in sequence, and the transmission direction of the interrupt request is, for example, the third interrupt node, the first interrupt node, the second interrupt node and the processor cluster. In the multi-level interrupt node, the first interrupt node is the next-level interrupt node of the third interrupt node.

[0044] When the multi-level interrupt node includes a fourth-level interrupt node, there may also be a fourth interrupt node. The fourth interrupt node is an interrupt node for routing interrupt requests, and the fourth interrupt node is connected to the third interrupt node, which is the next-level interrupt node of the fourth interrupt node. When the multi-level interrupt node includes a fifth-level interrupt node, there may also be a fifth interrupt node. The fifth interrupt node is an interrupt node for routing interrupt requests, and the fifth interrupt node is connected to the fourth interrupt node, which is the next-level interrupt node of the fifth interrupt node. The above examples are deduced in this manner, and are not further detailed here.

[0045] The aforementioned processor clusters can also be referred to as processor clusters or processor groups. A processor cluster includes a configurable cache and multiple processor cores, such as a level 3 (L3) cache. In one example, a processor cluster includes four cores and one L3 cache, meaning that four cores share one L3 cache. This combination of four cores and one L3 cache is called a CPU Cluster. If a CPU die includes 64 cores, this means the CPU die includes 16 CPU Clusters.

[0046] An interrupt circuit including multi-level interrupt nodes is used to: receive an interrupt request through a first interrupt node in the multi-level interrupt nodes, the interrupt request having an interrupt identifier; query a first memory according to the interrupt identifier through the first interrupt node to obtain a first identifier corresponding to the interrupt identifier; when the first identifier indicates a second interrupt node in the multi-level interrupt nodes, send an interrupt request to a target processor cluster in one or more processor clusters through the first interrupt node and the second interrupt node, so that the target processor cluster processes the interrupt request; or, when the first identifier indicates a target processor cluster, send an interrupt request directly to the target processor cluster through the first interrupt node, so that the target processor cluster processes the interrupt request.

[0047] Among them, the peripheral device can generate an interrupt request when an emergency occurs, and the interrupt request is used to request to improve the emergency event that occurred in the peripheral device. For example, the embodiment of the present application obtains the interrupt request generated by the peripheral device through the HMI (hub management interface), and then performs address conversion on the interrupt request through the IOMMU (input / output memory management unit), and sends the interrupt request after address conversion to the first interrupt node. The interrupt request received by the first interrupt node is the interrupt request after address conversion, and the first interrupt node routes the interrupt request after address conversion to at least one processor cluster in one or more processor clusters, for example, to a target processor cluster. Optionally, address conversion refers to converting the virtual address carried by the interrupt request into a physical address, and the interrupt request after address conversion carries a physical address. The processor cluster that receives the interrupt request after address conversion (such as the target processor cluster as exemplified above) processes the interrupt request by accessing the interrupt file at the physical address.

[0048] In some embodiments, the peripheral device is a wired interrupt device, and the wired interrupt device sends a wired interrupt request. Exemplarily, the IOMMU can send the wired interrupt request to the first interrupt node via the first line, and the wired interrupt request has an interrupt identifier that is a line identifier of the first line.

[0049] In some other embodiments, the peripheral device is a PCI-E (Peripheral Component Interconnect Express) device, and the PCI-E device sends an MSI-type interrupt request. Exemplarily, the IOMMU sends the MSI-type interrupt request to the first interrupt node via a second line (different from the first line described above), and the MSI-type interrupt request has an interrupt identifier that is included in the MSI-type interrupt request.

[0050] Alternatively, an HMI for obtaining wired interrupt requests is also referred to as a wired HMI, and an HMI for obtaining MSI interrupt requests is also referred to as a PCI-E HMI. Wired HMI and PCI-E HMI may be collectively referred to as a device HMI.

[0051] As can be seen, no matter what type of interrupt request the first interrupt node receives, the interrupt request has an interrupt identifier. Interrupt requests and interrupt identifiers correspond one-to-one, and different interrupt requests have different interrupt identifiers. Therefore, the first interrupt node performs a routing process based on the interrupt identifier. The routing process is used to route the interrupt request to the target processor cluster so that the target processor cluster can handle the interrupt request, thereby improving the emergency event occurring in the peripheral device. The first interrupt node can be denoted as an arbiter.

[0052] The first interrupt node queries the first memory according to the interrupt identifier to obtain the first identifier corresponding to the interrupt identifier. The first interrupt node can send an interrupt request to the target processor cluster according to the first identifier, so that the target processor cluster receives and processes the interrupt request. Optionally, the first memory is, for example, a register. The other memories mentioned below may also be registers. The embodiments of the present application do not limit the form of each memory, and each memory may also adopt other forms besides registers. In addition, the value of each memory can be enabled and configured by the operating system, and the operating system and the integrated circuit are located in the same computer device.

[0053] Exemplarily, there are two different situations for the first identification.

[0054] In the first scenario, the first identifier indicates the second interrupt node in the multi-level interrupt node hierarchy, and the second interrupt node corresponds to the target processor cluster. In response, the first interrupt node sends an interrupt request to the second interrupt node indicated by the first identifier. The second interrupt node then forwards the interrupt request to the corresponding target processor cluster, allowing the target processor cluster to process the interrupt request. In other words, the interrupt circuit sends the interrupt request to the target processor cluster via the first and second interrupt nodes.

[0055] The second interrupt node may process the interrupt request (e.g., perform type conversion on the interrupt request, as described below) and then forward the interrupt request to the target processor cluster. This means the second interrupt node forwards the processed interrupt request to the target processor cluster. Alternatively, the second interrupt node may not process the interrupt request (e.g., perform type conversion on the interrupt request) and directly forward the interrupt request to the target processor cluster. This means the second interrupt node transparently transmits the interrupt request.

[0056] Alternatively, in the second scenario, the first identifier indicates a target processor cluster. In this case, the first interrupt node directly sends an interrupt request to the target processor cluster indicated by the first identifier (i.e., without passing through the second interrupt node), so that the target processor cluster processes the interrupt request. In other words, the interrupt circuit directly sends the interrupt request to the target processor cluster via the first interrupt node.

[0057] Whether the second interrupt node transparently transmits the interrupt request in the first case or the interrupt request does not pass through the second interrupt node in the second case, both belong to bypassing the second interrupt node.

[0058] Next, these two situations are described in detail.

[0059] In the first case, a first portion of the first memory (the first portion may be a separate memory, such as a separate register) may store multiple first identifiers, each of which indicates a second interrupt node. Thus, when the first interrupt node queries the first portion of the first memory based on the interrupt identifier, it can obtain the first identifier corresponding to the interrupt identifier from the multiple first identifiers. The second interrupt node indicated by the first identifier obtained through the query is the second interrupt node connected to the target processor cluster, and the second interrupt node is used to receive and forward the interrupt request to the target processor cluster.

[0060] As can be seen from the above description, interrupt requests correspond to interrupt identifiers one-to-one. Since a peripheral device may have multiple emergency events, there may also be multiple interrupt requests, and accordingly, there may be multiple interrupt identifiers. In the embodiment of the present application, the first portion of the first memory stores the interrupt identifier and the first identifier bit by bit, so that the order of an interrupt identifier among the multiple interrupt identifiers is equal to the order of the first identifier corresponding to the interrupt identifier among the multiple first identifiers.

[0061] For example, if interrupt flag 0 is the 0th interrupt flag among the multiple interrupt flags, then the first flag corresponding to interrupt flag 0 is located in the 0th bit group in the first portion of the first memory. For another example, if interrupt flag 1 is the 1st interrupt flag among the multiple interrupt flags, then the first flag corresponding to interrupt flag 1 is located in the 1st bit group in the first portion of the first memory. This is analogous, and examples for other interrupt flags are not given one by one.

[0062] In an exemplary embodiment, the number of bits included in each bit group can be determined based on the number of second interruption nodes. For example, if the number of second interruption nodes is 256 and the corresponding multiple first identifiers are 0 to 255, then the number of bits included in each bit group is 8, because the first identifier 255 with the largest value requires 8 bits to represent. For another example, if the number of second interruption nodes is 512 and the corresponding multiple first identifiers are 0 to 511, then the number of bits included in each bit group is 9, because the first identifier 511 with the largest value requires 9 bits to represent.

[0063] Optionally, the first part of the first memory includes at least one first sub-memory, and each first sub-memory is used to store a portion of the interruption flag and a portion of the first flag in bit order.

[0064] For example, if each bit group includes 8 bits and each first sub-memory is a 64-bit memory, each first sub-memory is used to store 8 bit groups, that is, to store 8 first identifiers corresponding to 8 interrupt identifiers. Based on this, if there are 1024 interrupt identifiers in total, a total of 128 first sub-memories are required.

[0065] The first sub-memory is represented as AB_INTPROUTE[x], and the 128 first sub-memories are represented as AB_INTPROUTE[0] to AB_INTPROUTE

[127] . AB_INTPROUTE[0] is used to store the first identifiers corresponding to interrupt identifiers 0 to 7, AB_INTPROUTE[1] is used to store the first identifiers corresponding to interrupt identifiers 8 to 15, and so on. AB_INTPROUTE

[127] is used to store the first identifiers corresponding to interrupt identifiers 1016 to 1023.

[0066] In an example, the structure of the first sub-memory AB_INTPROUTE[0] can be found in Figure 2 .exist Figure 2 In the example, the first identifier AP_id[0] corresponding to the interrupt identifier 0 occupies bits 0 to 7 (i.e. Figure 2 The width shown is 8, that is, the 0th bit group described above), the first identifier AP_id[1] corresponding to the interrupt identifier 1 occupies the 8th to 15th bits (that is, the 1st bit group described above), and so on, the first identifier AP_id[7] corresponding to the interrupt identifier 7 occupies the 56th to 63rd bits.

[0067] Based on the above description, taking the interrupt request received by the first interrupt node with interrupt identifier 1 as an example, the first interrupt node queries the first bit group according to the interrupt identifier 1, that is, the 8th to 15th bits of AB_INTPROUTE[0], and obtains the first identifier AP_id[1], so that it can send an interrupt request to the second interrupt node indicated by the first identifier AP_id[1].

[0068] Optionally, in addition to sending an interrupt request to a second interrupt node connected to the target processor cluster, the first interrupt node can also send an interrupt request to other second interrupt nodes not connected to the target processor cluster, i.e., the first interrupt node broadcasts the interrupt request. However, in this case, only the second interrupt node connected to the target processor cluster can respond to the interrupt request; the other second interrupt nodes will only receive and ignore the interrupt request. This is because each second interrupt node can have a corresponding source configuration register, also known as a sourcecfg register. The sourcecfg register includes a system management (SM) field, the value of which can be configured by the operating system. When the value of the SM field is 0, it indicates inactive. Therefore, even if the second interrupt node receives an interrupt request, it will not send the interrupt request to the corresponding processor cluster. Alternatively, when the value of the SM field is 1, it indicates active. Therefore, after receiving the interrupt request, the second interrupt node will send the interrupt request to the corresponding processor cluster. Therefore, the embodiment of the present application can set the value of the SM field included in the sourcecfg register corresponding to the second interrupt node connected to the target processor cluster to 1, while the value of the SM field included in the sourcecfg register corresponding to other second interrupt nodes is 0. In this way, it is achieved that only the second interrupt node connected to the target processor cluster can respond to the interrupt request, and the other second interrupt nodes will only receive and ignore the interrupt request.

[0069] After receiving the interrupt request, the second interrupt node connected to the target processor cluster sends the interrupt request to the corresponding target processor cluster among the multiple processor clusters.

[0070] Because the second interrupt node is connected to the first interrupt node, after the first interrupt node sends an interrupt request to the second interrupt node, the second interrupt node can receive the interrupt request. The second interrupt nodes and processor clusters may have a one-to-one correspondence, i.e., each second interrupt node corresponds to a processor cluster, and the second interrupt node connected to the target processor cluster corresponds to the target processor cluster. Therefore, the second interrupt node can send an interrupt request to the target processor cluster.

[0071] For example, after receiving the interrupt request, the second interrupt node may convert the interrupt request type. The interrupt request sent by the second interrupt node to the target processor cluster is the interrupt request after the type conversion. For example, when the interrupt request is of the wired type, the second interrupt node may convert the wired interrupt request to an MSI type interrupt request and send the MSI type interrupt request to the target processor cluster.

[0072] Alternatively, after receiving the interrupt request, the second interrupt node may directly send the interrupt request to the target processor cluster without performing type conversion on the interrupt request, i.e., the second interrupt node transparently transmits the interrupt request. For example, when the interrupt request is of MSI type, the second interrupt node may transparently transmit the MSI type interrupt request.

[0073] Because the target processor cluster is connected to the second interrupt node, the target processor cluster can receive the interrupt request after the second interrupt node sends the interrupt request. Exemplarily, the target processor cluster can process the interrupt request sent by the second interrupt node through the target processing core in at least one processing core to improve the emergency event occurring in the peripheral device.

[0074] When the target processor cluster contains only one processing core, that core is the target processing core. If the target processor cluster contains multiple processing cores, the target processing core can be one of the multiple cores designated by the operating system. For example, when a PCI-E device initiates an interrupt request (wired or MSI), the hypervisor (a virtualization operating system) will assign a target processing core to the interrupt request based on the load of the processors in the multiple processor clusters.

[0075] Optionally, the second interrupt node corresponds to a target register, which can also be configured by the operating system. The target register includes a processing core identifier corresponding to the interrupt identifier of the interrupt request. After the second interrupt node receives the interrupt request, it queries the target register according to the interrupt identifier to obtain the processing core identifier corresponding to the interrupt identifier. The processing core indicated by the processing core identifier is the target processing core for processing the interrupt request. The second interrupt node sends an interrupt request to the target processor cluster where the target processing core is located, so that the target processing core processes the interrupt request.

[0076] In an embodiment of the present application, since the integrated circuit includes a first interrupt node, and the first interrupt node receives an interrupt request and distributes the interrupt request to the second interrupt node according to the first part of the first memory, it is conducive to achieving fast routing of interrupt requests and improving the processing efficiency of the processor cluster.

[0077] In the second case, the second portion of the first memory (the second portion may be a separate memory, such as a separate register) may store multiple first identifiers, each of which corresponds one-to-one to a plurality of processor clusters, with each first identifier indicating one of the plurality of processor clusters. Thus, when the first interrupt node queries the second portion of the first memory based on the interrupt identifier, it can obtain the first identifier corresponding to the interrupt identifier from the plurality of first identifiers, and the processor cluster indicated by the first identifier obtained through the query is the target processor cluster.

[0078] In the embodiment of the present application, the second portion of the first memory stores the interrupt flag and the first flag bit by bit, so that the order of an interrupt flag among the multiple interrupt flags is equal to the order of the first flag corresponding to the interrupt flag among the multiple first flags. This storage method can refer to the storage method described in the first case above and will not be repeated here.

[0079] As previously mentioned, the second interrupt node can convert a wired interrupt request into an MSI interrupt request. If the interrupt request itself is of MSI type, there's no need to perform type conversion via the second interrupt node. In other words, the interrupt request is sent directly to the target processor cluster without passing through the second interrupt node. Accordingly, the target processor cluster can receive and process the interrupt request. The details of how the target processor cluster processes the interrupt request are described in the first scenario above and are not detailed here.

[0080] In an exemplary embodiment, the first interrupt node queries the fifth memory and distinguishes the first situation from the second situation through the fifth identifier stored in the fifth memory.

[0081] The interrupt circuit is further configured to query the fifth memory according to the interrupt identifier through the first interrupt node to obtain a fifth identifier corresponding to the interrupt identifier. The value of the fifth identifier indicates whether the first interrupt node is authorized to send an interrupt request to other interrupt nodes (the next-level interrupt node of the first interrupt node, for example, the second interrupt node). Since the value of the fifth memory is configured by the operating system, the value of the fifth identifier indicates whether the first interrupt node is authorized by the operating system to send an interrupt request to other interrupt nodes. The other "authorized" mentioned below are the same as here and will not be repeated here.

[0082] In one example, all values ​​of the fifth identifier in the fifth memory indicate that the first interrupt node is not authorized to send interrupt requests to other interrupt nodes. That is, for any interrupt request, the first interrupt node will not send it to other interrupt nodes, thereby achieving global interrupt control. In another example, the values ​​of some or all of the fifth identifiers in the fifth memory indicate that the first interrupt node is authorized to send interrupt requests to other interrupt nodes. In this case, the first interrupt node can selectively send interrupt requests to other interrupt nodes, which is more flexible.

[0083] In an exemplary embodiment, the value of the fifth identifier includes the following two cases.

[0084] In case A (corresponding to the first case above), the value of the fifth flag indicates that the first interrupt node is authorized to send interrupt requests to other interrupt nodes. In case A, the first flag indicates the second interrupt node, so the interrupt circuit can send interrupt requests to the target processor cluster through the first interrupt node and the second interrupt node.

[0085] That is to say, the first interrupt node can first query the fifth memory to obtain the fifth identifier. If the value of the fifth identifier indicates that the first interrupt node is authorized to send an interrupt request to other interrupt nodes, the first interrupt node queries the first part of the first memory according to the above instructions and obtains the first identifier indicating the second interrupt node. Then the first interrupt node sends an interrupt request to the second interrupt node.

[0086] If the interrupt request is of a wired type, the second interrupt node converts the wired interrupt request into an MSI type interrupt request and then sends the MSI type interrupt request to the target processor cluster, which then processes the MSI type interrupt request. Alternatively, if the interrupt request is of an MSI type, the second interrupt node transparently transmits the MSI type interrupt request, and the target processor cluster processes the MSI type interrupt request.

[0087] In case B (corresponding to the second case above), when the interrupt request is of the MSI type, the value of the fifth flag indicates that the first interrupt node is not authorized to send interrupt requests to other interrupt nodes. In case B, the first flag indicates the target processor cluster, so the interrupt circuit can send the interrupt request directly to the target processor cluster through the first interrupt node.

[0088] That is to say, the first interrupt node can first query the fifth memory to obtain the fifth identifier. If the value of the fifth identifier indicates that the first interrupt node is not authorized to send an interrupt request to other interrupt nodes, the first interrupt node queries the second part of the first memory according to the above instructions to obtain the first identifier indicating the target processor cluster. Then the first interrupt node does not need to send an MSI type interrupt request to the second interrupt node, but directly sends an MSI type interrupt request to the target processor cluster.

[0089] In the embodiment of the present application, the fifth memory stores the interrupt flag and the fifth flag bit by bit, so that the order of an interrupt flag among multiple interrupt flags is equal to the order of the fifth flag corresponding to the interrupt flag among the multiple fifth flags.

[0090] For example, if interrupt flag 0 is the 0th interrupt flag among the multiple interrupt flags, then the fifth flag corresponding to interrupt flag 0 is located in the 0th bit group in the fifth memory. For another example, if interrupt flag 1 is the 1st interrupt flag among the multiple interrupt flags, then the fifth flag corresponding to interrupt flag 1 is located in the 1st bit group in the fifth memory. This is analogous, and examples for other interrupt flags are not given one by one.

[0091] For example, the number of bits included in each bit group can be determined according to the value of the fifth identifier. For example, if the value of the fifth identifier is 0 and 1, the number of bits included in each bit group is 1, because 0 and 1 only need to be represented by 1 bit. For another example, if the value of the fifth identifier is 2 and 3 (i.e., 10 and 11), the number of bits included in each bit group is 2, because 2 and 3 need to be represented by 2 bits.

[0092] Optionally, the fifth memory includes at least one fifth sub-memory, and each fifth sub-memory is used to store part of the interruption flag and part of the fifth flag bit by bit.

[0093] For example, if each bit group includes 1 bit and each fifth sub-memory is a 64-bit memory, then each fifth sub-memory is used to store 64 bit groups, that is, to store 64 fifth identifiers corresponding to 64 interrupt identifiers. Based on this, if there are 1024 interrupt identifiers in total, a total of 16 fifth sub-memories are required.

[0094] The fifth sub-memory is represented as AB_INTPCTRL[x], and the 16 fifth sub-memories are represented as AB_INTPCTRL[0] to AB_INTPCTRL

[15] . AB_INTPCTRL[0] is used to store the fifth flags corresponding to interrupt flags 0 to 63, AB_INTPCTRL[1] is used to store the fifth flags corresponding to interrupt flags 64 to 127, and so on. AB_INTPCTRL

[15] is used to store the fifth flags corresponding to interrupt flags 960 to 1023.

[0095] In an example, the structure of the fifth sub-memory AB_INTPCTRL[0] can be found in Figure 3 .exist Figure 3 In the figure, the fifth identifier AB_i_en[0] corresponding to the interrupt identifier 0 occupies the 0th bit (the width is 1, that is, the 0th bit group described above), the fifth identifier AB_i_en[1] corresponding to the interrupt identifier 1 occupies the 1st bit (that is, the 1st bit group described above), and so on. The fifth identifier AB_i_en

[63] corresponding to the interrupt identifier 63 occupies the 63rd bit.

[0096] Based on the above description, taking the interrupt request received by the first interrupt node with interrupt identifier 1 as an example, the first interrupt node queries the first bit group according to the interrupt identifier 1, that is, the first bit of AB_INTPCTRL[0], and obtains the fifth identifier AB_i_en[1], so as to determine whether to send an interrupt request to the second interrupt node according to the value of the fifth identifier AB_i_en[1].

[0097] In the first case described above, in an exemplary embodiment, after the first interrupt node obtains the first identifier corresponding to the interrupt request (indicating the second interrupt node), it directly sends the interrupt request to the second interrupt node without performing any other query process. Alternatively, after the first interrupt node obtains the first identifier corresponding to the interrupt request, it further performs the following query process.

[0098] Illustratively, the interrupt circuit is further configured to query a sixth memory according to the first identifier via the first interrupt node to obtain a sixth identifier corresponding to the first identifier. The interrupt circuit is configured to send an interrupt request to the target processor cluster via the first interrupt node and the second interrupt node if the value of the sixth identifier indicates that the second interrupt node is authorized to receive the interrupt request.

[0099] In an embodiment of the present application, the sixth memory stores the first identifier and the sixth identifier bit by bit so that the order of a first identifier among multiple first identifiers is equal to the order of the sixth identifier corresponding to the first identifier among multiple sixth identifiers.

[0100] For example, if the first identifier AP_id[0] is the 0th first identifier among the multiple first identifiers, then the sixth identifier corresponding to the first identifier AP_id[0] is located in the 0th bit group in the sixth memory. For another example, if the first identifier AP_id[1] is the 1st first identifier among the multiple first identifiers, then the sixth identifier corresponding to the first identifier AP_id[1] is located in the 1st bit group in the sixth memory. This is analogous, and examples for other first identifiers are not given one by one.

[0101] Exemplarily, the number of bits included in each bit group is determined according to the value of the sixth identifier. For example, if the value of the sixth identifier is 0 and 1, the number of bits included in each bit group is 1, because 0 and 1 only need to be represented by 1 bit. For another example, if the value of the sixth identifier is 2 and 3 (i.e., 10 and 11), the number of bits included in each bit group is 2, because 2 and 3 need to be represented by 2 bits.

[0102] Optionally, the sixth memory includes at least one sixth sub-memory, and each sixth sub-memory is used to store part of the first identifier and part of the sixth identifier bit by bit.

[0103] For example, if each bit group contains 1 bit and each sixth sub-memory is a 64-bit memory, then each sixth sub-memory is used to store 64 bit groups, that is, to store 64 sixth identifiers corresponding to 64 first identifiers. Based on this, if there are 256 first identifiers, that is, one first interrupt node is connected to 256 second interrupt nodes, then a total of four sixth sub-memories are required.

[0104] The sixth sub-memory is represented as AB_APCTRL[x], and the four sixth sub-memories are represented as AB_APCTRL[0] to AB_APCTRL[3]. AB_APCTRL[0] is used to store the sixth identifiers corresponding to the first identifier AP_id[0] to the first identifier AP_id

[63] , AB_APCTRL[1] is used to store the sixth identifiers corresponding to the first identifier AP_id

[64] to the first identifier AP_id

[127] , and so on. AB_APCTRL[3] is used to store the sixth identifiers corresponding to the first identifier AP_id

[960] to the first identifier AP_id

[1023] .

[0105] In an example, the structure of the sixth sub-memory AB_APCTRL[0] can be found in Figure 4 .exist Figure 3In the figure, the sixth identifier AP_en[0] corresponding to the first identifier AP_id[0] occupies the 0th bit (the width is 1, that is, the 0th bit group described above), the sixth identifier AP_en[1] corresponding to the first identifier AP_id[1] occupies the 1st bit (that is, the 1st bit group described above), and so on. The sixth identifier AP_en

[63] corresponding to the first identifier AP_en

[63] occupies the 63rd bit.

[0106] Based on the above description, taking the first interrupt node querying and obtaining the first identifier AP_id[1] as an example, the first interrupt node queries the first bit group, that is, the first bit of AB_APCTRL[0], according to the first identifier AP_id[1], and obtains the sixth identifier AP_en[1], thereby being able to determine whether the second interrupt node is authorized to receive the interrupt request according to the value of the sixth identifier AP_en[1].

[0107] If the second interrupt node is authorized to receive interrupt requests, the first interrupt node can send an interrupt request to the second interrupt node. If the second interrupt node is not authorized to receive interrupt requests, it means that the target processor cluster corresponding to the second interrupt node may be in an abnormal state, such as an abnormal state where the processing core occupancy rate exceeds a threshold. In this case, the first interrupt node can wait for the value of the sixth identifier corresponding to the first identifier to be updated to indicate that the second interrupt node is authorized to receive interrupt requests before sending the interrupt request to the second interrupt node.

[0108] In an exemplary embodiment, the interrupt circuit is also used to: receive an interrupt request through a third interrupt node in the multi-level interrupt node; query the second memory according to the interrupt identifier through the third interrupt node to obtain a second identifier corresponding to the interrupt identifier; and send an interrupt request to the first interrupt node indicated by the second identifier through the third interrupt node.

[0109] For example, after the peripheral device generates an interrupt request, the HMI obtains the interrupt request, and the IOMMU performs address translation on the interrupt request, thereby sending the interrupt request after address translation to the third interrupt node. After receiving the interrupt request, the third interrupt node sends the interrupt request to the first interrupt node. Figure 5 , Figure 5 An exemplary integrated circuit is shown, wherein the third interrupt node can be denoted as a dispatcher.

[0110] In the embodiment of the present application, the second memory stores the interrupt flag and the second flag bit by bit, so that the order of an interrupt flag among multiple interrupt flags is equal to the order of the second flag corresponding to the interrupt flag among multiple second flags.

[0111] For example, if interrupt flag 0 is the 0th interrupt flag among the multiple interrupt flags, then the second flag corresponding to interrupt flag 0 is located in the 0th bit group in the second memory. For another example, if interrupt flag 1 is the 1st interrupt flag among the multiple interrupt flags, then the second flag corresponding to interrupt flag 1 is located in the 1st bit group in the second memory. This is analogous, and examples for other interrupt flags are not given one by one.

[0112] In an exemplary embodiment, the number of bits included in each bit group may be determined according to the number of first interrupt nodes.

[0113] For example, if the number of first interrupt nodes is 256 and the corresponding second identifiers are 0 to 255, then each bit group includes 8 bits, because the second identifier 255 with the largest value requires 8 bits to represent. For another example, if the number of first interrupt nodes is 512 and the corresponding second identifiers are 0 to 511, then each bit group includes 9 bits, because the second identifier 511 with the largest value requires 9 bits to represent.

[0114] Optionally, the second memory includes at least one second sub-memory, and each second sub-memory is used to store a portion of the interruption identifier and a portion of the second identifier bit by bit.

[0115] For example, if each bit group includes 8 bits and each second sub-memory is a 64-bit memory, each second sub-memory is used to store 8 bit groups, that is, to store 8 second identifiers corresponding to 8 interrupt identifiers. Based on this, if there are 1024 interrupt identifiers in total, a total of 128 second sub-memories are required.

[0116] The second sub-memory is represented as DP_INTPROUTE[x], and the 128 second sub-memories are represented as DP_INTPROUTE[0] to DP_INTPROUTE

[127] . DP_INTPROUTE[0] is used to store the second identifier corresponding to interrupt identifiers 0 to 7, DP_INTPROUTE[1] is used to store the second identifier corresponding to interrupt identifiers 8 to 15, and so on. DP_INTPROUTE

[127] is used to store the second identifier corresponding to interrupt identifiers 1016 to 1023.

[0117] In one example, the structure of the second sub-memory DP_INTPROUTE[0] can be found in Figure 6 .exist Figure 6In the figure, the second identifier AB_id[0] corresponding to the interrupt identifier 0 occupies the 0th to 7th bits (the width is 8, that is, the 0th bit group described above), the second identifier AB_id[1] corresponding to the interrupt identifier 1 occupies the 8th to 15th bits (that is, the 1st bit group described above), and so on. The second identifier AB_id[7] corresponding to the interrupt identifier 7 occupies the 56th to 63rd bits.

[0118] Based on the above description, taking the interrupt request received by the third interrupt node with interrupt identifier 1 as an example, the first interrupt node queries the first bit group according to the interrupt identifier 1, that is, the 8th to 15th bits of DP_INTPROUTE[0], and obtains the second identifier AB_id[1], so that the interrupt request can be sent to the first interrupt node indicated by the second identifier AB_id[1].

[0119] In an exemplary embodiment, the interrupt circuit is also used to: query the third memory according to the interrupt identifier through the third interrupt node to obtain a third identifier corresponding to the interrupt identifier; the interrupt circuit is used to: when the value of the third identifier indicates that the third interrupt node is authorized to send an interrupt request to the first interrupt node, query the second memory according to the interrupt identifier through the third interrupt node to obtain a second identifier corresponding to the interrupt identifier.

[0120] In one example, the values ​​of all third identifiers in the third memory indicate that the third interrupt node is not authorized to send an interrupt request to the first interrupt node. That is, the third interrupt node will not send any interrupt request to the first interrupt node, thereby achieving global interrupt control. In another example, the values ​​of some or all third identifiers in the third memory indicate that the third interrupt node is authorized to send an interrupt request to the first interrupt node. In this case, the third interrupt node can selectively send an interrupt request to the first interrupt node, which is more flexible.

[0121] In the embodiment of the present application, the third memory stores the interrupt flag and the third flag bit by bit, so that the order of an interrupt flag among multiple interrupt flags is equal to the order of the third flag corresponding to the interrupt flag among the multiple third flags.

[0122] For example, if interrupt flag 0 is the 0th interrupt flag among the multiple interrupt flags, then the third flag corresponding to interrupt flag 0 is located in the 0th bit group in the third memory. For another example, if interrupt flag 1 is the 1st interrupt flag among the multiple interrupt flags, then the third flag corresponding to interrupt flag 1 is located in the 1st bit group in the third memory. This is analogous, and examples for other interrupt flags are not given one by one.

[0123] For example, the number of bits included in each bit group can be determined according to the value of the third identifier. For example, if the value of the third identifier is 0 and 1, the number of bits included in each bit group is 1, because 0 and 1 only need to be represented by 1 bit. For another example, if the value of the third identifier is 2 and 3 (i.e., 10 and 11), the number of bits included in each bit group is 2, because 2 and 3 need to be represented by 2 bits.

[0124] Optionally, the third memory includes at least one third sub-memory, and each third sub-memory is used to store part of the interruption flag and part of the third flag bit by bit.

[0125] For example, if each bit group includes 1 bit and each third sub-memory is a 64-bit memory, then each third sub-memory is used to store 64 bit groups, that is, to store 64 third identifiers corresponding to 64 interrupt identifiers. Based on this, if there are 1024 interrupt identifiers in total, a total of 16 third sub-memories are required.

[0126] The third sub-memory is represented as DP_INTPCTRL[x], and the 16 third sub-memories are represented as DP_INTPCTRL[0] to DP_INTPCTRL

[15] . DP_INTPCTRL[0] is used to store the third identifier corresponding to interrupt identifier 0 to interrupt identifier 63, DP_INTPCTRL[1] is used to store the third identifier corresponding to interrupt identifier 64 to interrupt identifier 127, and so on. DP_INTPCTRL

[15] is used to store the third identifier corresponding to interrupt identifier 960 to interrupt identifier 1023.

[0127] In an example, the structure of the third sub-memory DP_INTPCTRL[0] can be found in Figure 7 .exist Figure 7 In the figure, the third identifier DP_i_en[0] corresponding to the interrupt identifier 0 occupies the 0th bit (the width is 1, that is, the 0th bit group described above), the third identifier DP_i_en[1] corresponding to the interrupt identifier 1 occupies the 1st bit (that is, the 1st bit group described above), and so on. The third identifier DP_i_en

[63] corresponding to the interrupt identifier 63 occupies the 63rd bit.

[0128] Based on the above description, taking the interrupt request received by the third interrupt node with interrupt identifier 1 as an example, the first interrupt node queries the first bit group according to the interrupt identifier 1, that is, the first bit of DP_INTPCTRL[0], and obtains the third identifier DP_i_en[1], so as to determine whether to send an interrupt request to the first interrupt node according to the value of the third identifier DP_i_en[1].

[0129] In an exemplary embodiment, the interrupt circuit is also used to: query the fourth memory according to the second identifier through the third interrupt node to obtain the fourth identifier corresponding to the second identifier; the interrupt circuit is used to: send an interrupt request to the first interrupt node through the third interrupt node when the value of the fourth identifier indicates that the first interrupt node is authorized to receive the interrupt request.

[0130] In an embodiment of the present application, the fourth memory stores the second identifier and the fourth identifier bit by bit so that the order of a second identifier among multiple second identifiers is equal to the order of the fourth identifier corresponding to the second identifier among multiple fourth identifiers.

[0131] For example, if the second identifier AB_id[0] is the 0th second identifier among the plurality of second identifiers, then the fourth identifier corresponding to the second identifier AB_id[0] is located in the 0th bit group in the fourth memory. For another example, if the second identifier AB_id[1] is the 1st second identifier among the plurality of second identifiers, then the fourth identifier corresponding to the second identifier AB_id[1] is located in the 1st bit group in the fourth memory. This is analogous, and examples are not given one by one for other second identifiers.

[0132] For example, the number of bits included in each bit group can be determined according to the value of the fourth identifier. For example, if the value of the fourth identifier is 0 and 1, the number of bits included in each bit group is 1, because 0 and 1 only need to be represented by 1 bit. For another example, if the value of the fourth identifier is 2 and 3 (i.e., 10 and 11), the number of bits included in each bit group is 2, because 2 and 3 need to be represented by 2 bits.

[0133] Optionally, the fourth memory includes at least one fourth sub-memory, and each fourth sub-memory is used to store part of the second identifier and part of the fourth identifier bit by bit.

[0134] For example, if each bit group includes 1 bit and each fourth sub-memory is a 64-bit memory, then each fourth sub-memory is used to store 64 bit groups, that is, to store 64 fourth identifiers corresponding to 64 second identifiers. Based on this, if there are 256 second identifiers in total, that is, one third interrupt node is connected to 256 first interrupt nodes, then a total of four fourth sub-memories are required.

[0135] The fourth sub-memory is represented as DP_ABCTRL[x], and the four fourth sub-memories are represented as DP_ABCTRL[0] to DP_ABCTRL[3]. DP_ABCTRL[0] is used to store the fourth identifiers corresponding to the second identifiers AB_id[0] to AB_id

[63] , DP_ABCTRL[1] is used to store the fourth identifiers corresponding to the second identifiers AB_id

[64] to AB_id

[127] , and so on. AB_ABCTRL[3] is used to store the fourth identifiers corresponding to the second identifiers AB_id

[960] to AB_id

[1023] .

[0136] In an example, the structure of the fourth sub-memory DP_ABCTRL[0] can be found in Figure 8 .exist Figure 8 In the figure, the fourth identifier AB_en[0] corresponding to the second identifier AB_id[0] occupies the 0th bit (the width is 1, that is, the 0th bit group described above), the fourth identifier AB_en[1] corresponding to the second identifier AB_id[1] occupies the 1st bit (that is, the 1st bit group described above), and so on. The fourth identifier AB_en

[63] corresponding to the second identifier AB_en

[63] occupies the 63rd bit.

[0137] Based on the above description, taking the example of the third interrupt node querying and obtaining the second identifier AB_id[1], the third interrupt node queries the first bit group, that is, the first bit of DP_ABCTRL[0], based on the second identifier AB_id[1], and obtains the fourth identifier AB_en[1], thereby being able to determine whether the first interrupt node is authorized to receive the interrupt request based on the value of the fourth identifier AB_en[1].

[0138] If the first interrupt node is authorized to receive interrupt requests, the third interrupt node can send an interrupt request to the first interrupt node. If the first interrupt node is not authorized to receive interrupt requests, it means that the target processor cluster corresponding to the first interrupt node may be in an abnormal state, such as an abnormal state where the processing core occupancy rate exceeds a threshold. In this case, the third interrupt node can wait for the value of the fourth identifier corresponding to the second identifier to be updated to indicate that the first interrupt node is authorized to receive interrupt requests before sending the interrupt request to the first interrupt node.

[0139] As mentioned above, there may be multiple levels of interrupt nodes for routing interrupt requests. For example, in addition to the third interrupt node and the first interrupt node, there may also be a fourth interrupt node, a fifth interrupt node, etc. Thus, flexible expansion of the topology in the interrupt circuit is achieved.

[0140] Exemplarily, in addition to the third interrupt node, the fourth interrupt node, the fifth interrupt node, etc. may also be connected to the memory to implement the routing of the interrupt request. For example, the fifth interrupt node is connected to memory A, memory B, and memory C. After the fifth interrupt node receives the interrupt request, based on the interrupt identifier of the interrupt request, it queries memory A to determine whether the fifth interrupt node is authorized to send the interrupt request to the fourth interrupt node of the next level, queries memory B to determine the fourth interrupt node X for receiving the interrupt request, and queries memory C to determine whether the fourth interrupt node X is authorized to receive the interrupt request. Based on this, the fifth interrupt node can send an interrupt request to the fourth interrupt node X if certain conditions are met, so that the fourth interrupt node X continues to route the interrupt request (for example, forwarding the interrupt request to the third interrupt node of the next level), so that the target processor cluster can receive the interrupt request. Wherein, satisfying certain conditions may mean that the fifth interrupt node is authorized to send the interrupt request to the fourth interrupt node of the next level, and the fourth interrupt node X is authorized to receive the interrupt request.

[0141] In an exemplary embodiment, the third interrupt node and the target processor cluster are located on different chips in the . That is to say, the element that receives the interrupt request (i.e., the third interrupt node) and the element that processes the interrupt request (i.e., the target processor cluster) are located on different chips (i.e., dies). In this regard, the second memory can store the second identifiers of all first interrupt nodes included in the interrupt circuit, so that the third interrupt node routes the interrupt request to any first interrupt node in the interrupt circuit, regardless of whether the first interrupt node and the third interrupt node are located on the same die. In addition, the first memory can store all first identifiers included in the integrated circuit (indicating the second interrupt node, or indicating the target processor cluster), so that the first interrupt node routes the interrupt request to the target processor cluster, regardless of whether the first interrupt node and the second interrupt node (or the target processor cluster) are located on the same die. As a result, the routing method is more flexible and suitable for complex situations with multiple dies.

[0142] like Figure 9 As shown in FIG, a D2D (die to die, chip to chip) high-speed interconnection interface is used between dies. Figure 9An exemplary 3DIE architecture is shown, consisting of one IO DIE and two CPU DIEs (CPU DIE 0 and CPU DIE 1), forming a system on chip (SOC). The IO DIE is used to send interrupt requests to the CPU DIE. After the dispatcher (DP) receives the interrupt request, the CPU DIE routes the interrupt request to the corresponding CPU cluster based on actual needs. Each CPU DIE includes one dispatcher, two arbiters (ABs), four APLICs (APs), and four CPU clusters.

[0143] For wired interrupt requests, after the dispatcher (DP 0) in CPU DIE 0 receives the wired interrupt request, it sends the wired interrupt request to the arbiter (AB 1) in CPU DIE 1 through D2D. After the wired interrupt request is converted into an MSI interrupt request by the APLIC (AP), the CPU Cluster processes the MSI interrupt request.

[0144] Alternatively, for an MSI type interrupt request, after the dispatcher (DP 0) in CPU DIE 0 receives the MSI type interrupt request, it sends the MSI type interrupt request to the arbiter (AB 1) in CPU DIE 1 through D2D. The APLIC (AP) transparently transmits the MSI type interrupt request, and the CPU Cluster processes the MSI type interrupt request.

[0145] For MSI type interrupt requests, after receiving the MSI type interrupt request, the Dispatcher (DP 0) in CPU DIE 0 sends the MSI type interrupt request to the Arbiter (AB 1) in CPU DIE 1 through D2D. AB 1 bypasses APLIC (AP), and the CPU Cluster directly receives and processes the MSI type interrupt request. For example, AB 1 is directly connected to the CPU Cluster through a circuit ( Figure 9 (not shown), AB 1 directly sends an MSI type interrupt request to the CPU Cluster through the circuit, thereby bypassing the AP, and the CPU Cluster directly receives and processes the MSI type interrupt request.

[0146] To sum up, in the embodiment of the present application, the first interrupt node included in the interrupt circuit can quickly determine the first identifier by querying the first memory after receiving the interrupt request, thereby realizing fast, accurate and flexible routing of the interrupt request according to the first identifier. It only takes a short time for the target processor cluster to receive (directly receive, or receive through the second interrupt node) and process the interrupt request, thereby improving the processing efficiency of the interrupt request.

[0147] The integrated circuit provided in the embodiment of the present application has a tree topology structure including a third interrupt node (optional), a first interrupt node, a second interrupt node and multiple processor clusters. This topology structure has low complexity, strong scalability and strong robustness, which is conducive to the hierarchical management and routing of interrupt requests, improves routing efficiency, and thus improves the processing efficiency of interrupt requests.

[0148] The embodiment of the present application also provides a method for processing an interrupt request, which can be applied to the integrated circuit described above. Figure 10 As shown, the method includes the following steps 1001 to 1004.

[0149] Step 1001: Receive an interrupt request through a first interrupt node in a multi-level interrupt node, where the interrupt request has an interrupt identifier.

[0150] Step 1002: query the first memory according to the interruption identifier through the first interruption node to obtain a first identifier corresponding to the interruption identifier.

[0151] Step 1003 : When the first identifier indicates the second interrupt node in the multi-level interrupt node, an interrupt request is sent to a target processor cluster in one or more processor clusters through the first interrupt node and the second interrupt node, so that the target processor cluster processes the interrupt request.

[0152] Step 1004 : When the first identifier indicates a target processor cluster, directly send an interrupt request to the target processor cluster through the first interrupt node, so that the target processor cluster processes the interrupt request.

[0153] In an exemplary embodiment, the method further includes: receiving an interrupt request through a third interrupt node in the multi-level interrupt node; querying a second memory according to an interrupt identifier through the third interrupt node to obtain a second identifier corresponding to the interrupt identifier; and sending an interrupt request to a first interrupt node indicated by the second identifier through the third interrupt node.

[0154] In an exemplary embodiment, the method further includes: querying a third memory based on the interruption identifier by a third interruption node to obtain a third identifier corresponding to the interruption identifier. Querying a second memory based on the interruption identifier by the third interruption node includes: when the value of the third identifier indicates that the third interruption node is authorized to send an interruption request to the first interruption node, querying the second memory based on the interruption identifier by the third interruption node to obtain a second identifier corresponding to the interruption identifier.

[0155] In an exemplary embodiment, the method further includes: querying a fourth memory according to the second identifier via a third interrupt node to obtain a fourth identifier corresponding to the second identifier. Sending an interrupt request to the first interrupt node indicated by the second identifier via the third interrupt node includes: sending the interrupt request to the first interrupt node via the third interrupt node if the value of the fourth identifier indicates that the first interrupt node is authorized to receive the interrupt request.

[0156] In an exemplary embodiment, the method further includes: querying a fifth memory according to an interrupt identifier through the first interrupt node to obtain a fifth identifier corresponding to the interrupt identifier; wherein, when the value of the fifth identifier indicates that the first interrupt node is authorized to send an interrupt request to other interrupt nodes, the first identifier indicates the second interrupt node.

[0157] In an exemplary embodiment, the method also includes: querying the sixth memory according to the first identifier through the first interrupt node to obtain the sixth identifier corresponding to the first identifier; sending an interrupt request to the target processor cluster in one or more processor clusters through the first interrupt node and the second interrupt node, including: when the value of the sixth identifier indicates that the second interrupt node is authorized to receive the interrupt request, sending the interrupt request to the target processor cluster through the first interrupt node and the second interrupt node.

[0158] In an exemplary embodiment, the interrupt request is an MSI type interrupt request; the method also includes: querying the fifth memory according to the interrupt identifier through the first interrupt node to obtain a fifth identifier corresponding to the interrupt identifier; wherein, when the value of the fifth identifier indicates that the first interrupt node is not authorized to send an interrupt request to other interrupt nodes, the first identifier indicates the target processor cluster.

[0159] It should be noted that Figure 10 The method shown has the same concept as the integrated circuit embodiment described above. The specific implementation process and technical effects thereof are detailed in the integrated circuit embodiment and will not be described in detail here.

[0160] The present application also provides a system for processing interrupt requests, including an acquisition source (e.g., the aforementioned IO DIE) and an integrated circuit (e.g., the aforementioned CPU DIE). The acquisition source is configured to acquire the interrupt request and send the interrupt request to the integrated circuit; the integrated circuit is configured to process the interrupt request.

[0161] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequential sequence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments of the application described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the above exemplary embodiments do not represent all embodiments consistent with this application. Instead, they are merely examples of devices and methods consistent with certain aspects of this application as detailed in the appended claims.

[0162] It should be understood that the term "plurality" as used herein refers to two or more than two. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0163] The above description is merely an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the principles of the present application shall be included in the scope of protection of the present application.

Claims

1. An integrated circuit, characterized in that: The system comprises one or more processor clusters and an interrupt circuit coupled to the one or more processor clusters, wherein the interrupt circuit comprises a multi-level interrupt node and is configured to: receiving an interrupt request through a first interrupt node in the multi-level interrupt nodes, wherein the interrupt request has an interrupt identifier; querying a first memory according to the interruption identifier through the first interruption node to obtain a first identifier corresponding to the interruption identifier; In a case where the first identifier indicates a second interrupt node in the multi-level interrupt node, sending the interrupt request to the second interrupt node through the first interrupt node, the interrupt request being transparently transmitted by the second interrupt node so that a target processor cluster in the one or more processor clusters processes the interrupt request, or the interrupt request being type-converted by the second interrupt node and sent to the target processor cluster so that the target processor cluster processes the interrupt request after type conversion; Alternatively, when the first identifier indicates the target processor cluster, the interrupt request is directly sent to the target processor cluster through the first interrupt node, so that the target processor cluster processes the interrupt request.

2. The integrated circuit according to claim 1, wherein: The interrupt circuit is further configured to: receiving the interrupt request through a third interrupt node in the multi-level interrupt nodes; querying the second memory according to the interruption identifier through the third interruption node to obtain a second identifier corresponding to the interruption identifier; The interrupt request is sent to the first interrupt node indicated by the second identifier through the third interrupt node.

3. The integrated circuit according to claim 2, wherein: The interrupt circuit is further configured to: querying a third memory according to the interruption identifier through the third interruption node to obtain a third identifier corresponding to the interruption identifier; The interrupt circuit is used to: When the value of the third identifier indicates that the third interrupt node is authorized to send the interrupt request to the first interrupt node, the third interrupt node queries the second memory according to the interrupt identifier to obtain a second identifier corresponding to the interrupt identifier.

4. The integrated circuit according to claim 2, wherein: The interrupt circuit is further configured to: querying a fourth memory according to the second identifier through the third interrupt node to obtain a fourth identifier corresponding to the second identifier; The interrupt circuit is used to: In a case where the value of the fourth identifier indicates that the first interrupt node is authorized to receive the interrupt request, the interrupt request is sent to the first interrupt node through the third interrupt node.

5. The integrated circuit according to any one of claims 1 to 4, characterized in that The interrupt circuit is further configured to: querying a fifth memory according to the interruption identifier through the first interruption node to obtain a fifth identifier corresponding to the interruption identifier; Wherein, when the value of the fifth identifier indicates that the first interruption node is authorized to send the interruption request to other interruption nodes, the first identifier indicates the second interruption node.

6. The integrated circuit according to claim 5, wherein: The interrupt circuit is further configured to: querying a sixth memory according to the first identifier through the first interrupt node to obtain a sixth identifier corresponding to the first identifier; The interrupt circuit is used to: In a case where the value of the sixth flag indicates that the second interrupt node is authorized to receive the interrupt request, the interrupt request is sent to the second interrupt node through the first interrupt node.

7. The integrated circuit according to any one of claims 1 to 4, characterized in that The interrupt request is a message signal interrupt (MSI) type interrupt request; The interrupt circuit is further configured to: querying a fifth memory according to the interruption identifier through the first interruption node to obtain a fifth identifier corresponding to the interruption identifier; Wherein, when the value of the fifth identifier indicates that the first interrupt node is not authorized to send the interrupt request to other interrupt nodes, the first identifier indicates the target processor cluster.

8. A method for processing an interrupt request, characterized in that: The method comprises: receiving an interrupt request through a first interrupt node in a multi-level interrupt node, wherein the interrupt request has an interrupt identifier; querying a first memory according to the interruption identifier through the first interruption node to obtain a first identifier corresponding to the interruption identifier; In a case where the first identifier indicates a second interrupt node in the multi-level interrupt node, sending the interrupt request to the second interrupt node through the first interrupt node, the interrupt request being transparently transmitted by the second interrupt node so that a target processor cluster in one or more processor clusters processes the interrupt request, or the interrupt request being type-converted by the second interrupt node and sent to the target processor cluster so that the target processor cluster processes the interrupt request after type conversion; Alternatively, when the first identifier indicates the target processor cluster, the interrupt request is directly sent to the target processor cluster through the first interrupt node, so that the target processor cluster processes the interrupt request.

9. The method according to claim 8, characterized in that The method further comprises: receiving the interrupt request through a third interrupt node in the multi-level interrupt nodes; querying the second memory according to the interruption identifier through the third interruption node to obtain a second identifier corresponding to the interruption identifier; The interrupt request is sent to the first interrupt node indicated by the second identifier through the third interrupt node.

10. The method according to claim 9, characterized in that The method further includes: querying a third memory according to the interruption identifier through the third interruption node to obtain a third identifier corresponding to the interruption identifier; The querying of the second memory according to the interruption identifier through the third interruption node includes: when the value of the third identifier indicates that the third interruption node is authorized to send the interruption request to the first interruption node, querying the second memory according to the interruption identifier through the third interruption node to obtain a second identifier corresponding to the interruption identifier.

11. The method according to claim 9, characterized in that The method further includes: querying a fourth memory according to the second identifier through the third interrupt node to obtain a fourth identifier corresponding to the second identifier; The sending the interrupt request to the first interrupt node indicated by the second identifier through the third interrupt node includes: sending the interrupt request to the first interrupt node through the third interrupt node when the value of the fourth identifier indicates that the first interrupt node is authorized to receive the interrupt request.

12. The method according to any one of claims 8 to 11, characterized in that The method further includes: querying a fifth memory according to the interruption identifier through the first interruption node to obtain a fifth identifier corresponding to the interruption identifier; Wherein, when the value of the fifth identifier indicates that the first interruption node is authorized to send the interruption request to other interruption nodes, the first identifier indicates the second interruption node.

13. The method according to claim 12, characterized in that The method further includes: querying a sixth memory according to the first identifier through the first interrupt node to obtain a sixth identifier corresponding to the first identifier; The sending the interruption request to the second interruption node through the first interruption node includes: sending the interruption request to the second interruption node through the first interruption node when the value of the sixth identifier indicates that the second interruption node is authorized to receive the interruption request.

14. The method according to any one of claims 8 to 11, characterized in that The interrupt request is a message signal interrupt (MSI) type interrupt request; The method further includes: querying a fifth memory according to the interruption identifier through the first interruption node to obtain a fifth identifier corresponding to the interruption identifier; Wherein, when the value of the fifth identifier indicates that the first interrupt node is not authorized to send the interrupt request to other interrupt nodes, the first identifier indicates the target processor cluster.

15. A system for processing interrupt requests, characterized in that: The system comprises an acquisition source and an integrated circuit according to any one of claims 1 to 7; The acquisition source is used to obtain an interrupt request and send the interrupt request to the integrated circuit; The integrated circuit is used to process the interrupt request.

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