Control method and related device of multi-system-on-chip

Abstract

The present application discloses a control method for multiple system-level chips and related devices, the method comprising: for each system-level chip, obtaining and, based on the first score corresponding to each operator in each intelligent solution of the system-level chip, the target probability corresponding to each intelligent solution of the system-level chip, and the idle score of the system-level chip, obtaining the first target score corresponding to the system-level chip and the intelligent solution, and obtaining the second target score corresponding to each operator in the intelligent solution of the system-level chip; according to the first target score corresponding to each system-level chip and each intelligent solution, and the second target score corresponding to each operator in each intelligent solution of each system-level chip, allocating the operators in multiple intelligent solutions to multiple system-level chips. The method of the present application can improve the utilization rate of the computing power resources of multiple system-level chips.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a control method and related devices for a multi-system-on-chip. Background Art

[0002] In the existing technology, since different intelligent solutions usually consume different computing resources, and the computing resources of different system-level chips cannot be well measured, in some scenarios, some intelligent solutions usually still have a lot of computing resources remaining after running on the system-level chip. Although there are a lot of remaining computing resources, the remaining computing resources of each system-level chip can no longer be allocated to other intelligent solutions. At the same time, the computing resources between different system-level chips cannot be well compared, which results in a large waste of computing resources after the existing intelligent solutions are allocated on multiple system-level chips, resulting in low computing resource utilization of multiple system-level chips. Summary of the Invention

[0003] The main technical problem solved by this application is to provide a control method and related devices for multiple system-level chips, which can improve the utilization rate of computing power resources of multiple system-level chips.

[0004] In order to solve the above technical problems, the first aspect of the present application provides a control method for multiple system-level chips, the method comprising: for each system-level chip, obtaining a first score corresponding to each operator in each intelligent solution of the system-level chip, a target probability corresponding to each intelligent solution of the system-level chip, and an idle score of the system-level chip, wherein the first score represents the computing power resources consumed by the system-level chip within a preset time when running the operator in the intelligent solution, the target probability represents the probability of the system-level chip running the intelligent solution, and the idle score represents the remaining computing power resources of the system-level chip that can run the intelligent solution; for each system-level chip, according to the idle score of the system-level chip, the target probability corresponding to the system-level chip and the intelligent solution, The first target score corresponding to the system-level chip and the intelligent solution and the second target score corresponding to each operator in the intelligent solution are obtained by calculating the rate and the first score corresponding to each system-level chip and each operator in the intelligent solution, wherein the first target score represents the normalized remaining computing power resources within a preset time after the system-level chip runs the intelligent solution, and the second target score represents the normalized remaining computing power resources within a preset time after the system-level chip runs the operator in the intelligent solution; according to the first target score corresponding to each system-level chip and each intelligent solution and the second target score corresponding to each system-level chip and each operator in each intelligent solution, the operators in multiple intelligent solutions are allocated to multiple system-level chips.

[0005] To solve the above technical problems, the second aspect of the present application provides an electronic device, which includes: a memory and a processor coupled to each other, wherein the memory stores program data, and the processor calls the program data to execute the method of the first aspect.

[0006] In order to solve the above technical problems, the third aspect of the present application provides a computer-readable storage medium on which program data is stored, and when the program data is executed by a processor, the method of the above first aspect is implemented.

[0007] Different from the prior art, the present application obtains for each system-level chip and obtains the first target score corresponding to the system-level chip and the intelligent solution and the second target score corresponding to each operator in the intelligent solution according to the first score corresponding to each operator in each intelligent solution, the target probability corresponding to each operator in each intelligent solution and the idle score of the system-level chip. By comprehensively evaluating the first target score corresponding to the system-level chip and the intelligent solution and the second target score corresponding to each operator in the intelligent solution, the operators in multiple intelligent solutions are allocated to multiple system-level chips. The effect is that, on the one hand, by splitting the intelligent solution into multiple operators, the operators required by the operators are The computing power resources are smaller than those of the intelligent solution, and different operators under the same intelligent solution can be allocated to different system-level chips, so that the smaller remaining computing power resources on the system-level chip can be used to run the operator, avoiding the waste of computing power resources caused by the smaller computing power resources in the prior art that cannot run the intelligent solution. On the second hand, through normalization, the first target scores of the intelligent solutions running on different system-level chips and the second target scores of the operators in the intelligent solutions running on different system-level chips can be compared with each other, so as to achieve a comprehensive evaluation of the remaining computing power resources of multiple system-level chips and thus better allocate them. On the third hand, by adding the target probability, the first target score and the second target score are close to the real level. In summary, the solution of the present application can avoid the waste of computing power resources of multiple system-level chips, thereby greatly improving the utilization rate of computing power resources of multiple system-level chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. Among them:

[0009] Figure 1 This is a flow chart of an embodiment of a multi-system-on-chip control method of the present application;

[0010] Figure 2 yes Figure 1 A schematic flow chart of an implementation method of step S200;

[0011] Figure 3 yes Figure 1 A schematic flow chart of another embodiment of step S200;

[0012] Figure 4 yes Figure 1 A schematic flow chart of an embodiment before step S100;

[0013] Figure 5 yes Figure 1 A schematic flow chart of another embodiment before step S100;

[0014] Figure 6 yes Figure 4 A schematic flow chart of an embodiment before step S1000;

[0015] Figure 7 yes Figure 1 A flow chart of another embodiment before step S100;

[0016] Figure 8 yes Figure 1 A schematic flow chart of another embodiment of step S300;

[0017] Figure 9 yes Figure 1 A schematic flow chart of an embodiment before step S300;

[0018] Figure 10 yes Figure 1 A schematic diagram of a flow chart of an embodiment after step S100;

[0019] Figure 11 It is a structural diagram of an embodiment of the control device of the present application;

[0020] Figure 12 This is a schematic structural diagram of an embodiment of the electronic device of the present application;

[0021] Figure 13 It is a structural diagram of an embodiment of a computer-readable storage medium of the present application. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them, and different implementation methods can be adaptively combined. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0023] The terms "system" and "network" are often used interchangeably in this document. The term "and / or" is simply a description of an association between related objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " generally indicates that the related objects are in an "or" relationship. Furthermore, "multiple" in this document means two or more than two.

[0024] See Figure 1 The present application provides a multi-system-on-chip control method, the method comprising:

[0025] S100: For each system-level chip, obtain a first score corresponding to each operator in each intelligent solution, a target probability corresponding to each intelligent solution, and an idle score of the system-level chip, wherein the first score represents the computing power resources consumed by the system-level chip within a preset time when running the operator in the intelligent solution, the target probability represents the probability of the system-level chip running the intelligent solution, and the idle score represents the remaining computing power resources of the system-level chip that can run the intelligent solution.

[0026] Specifically, among multiple system-level chips, some system-level chips may be the same, some system-level chips may be different, all system-level chips may be the same, or all system-level chips may be different. Similarly, among multiple intelligent solutions, some intelligent solutions may be the same, some intelligent solutions may be different, all intelligent solutions may be the same, or all intelligent solutions may be different. This application does not impose specific restrictions on system-level chips and intelligent solutions. The intelligent solution includes multiple operators, for example, any one or a combination of multiple of target detection, target tracking, target scoring, feature extraction and feature comparison can be regarded as an operator. Of course, the operators are not limited to the above examples. At the same time, the system-level chip running the intelligent solution and the system-level chip running all operators under the intelligent solution have exactly the same effect. It should be noted that the concept of score in this application is used to characterize the computing power resources of the system-level chip, that is, the higher the score, the higher the computing power resources. For a better understanding, the solutions in this application are further explained by taking multiple system-level chips including system-level chip SOC1 and system-level chip SOC2, multiple intelligent solutions including intelligent solution A, intelligent solution B and intelligent solution C, intelligent solution A including operator a1 and operator a2, intelligent solution B including operator b1 and operator b2, and intelligent solution C including operator c1 and operator c2 as an example. It can be understood that this does not constitute a limitation on this application. This application does not impose specific restrictions on the number of system-level chips, the number of intelligent solutions, and the number of operators in each intelligent solution.

[0027] When an operator in an intelligent solution runs on a SoC, it consumes computing resources on the SoC. The first score represents the amount of computing resources consumed by the operator within a preset timeframe. It is understood that the higher the first score of an operator in an intelligent solution running on a SoC, the more computing resources the operator consumes. Generally speaking, the first score can be obtained by running the operator on the SoC. The specific method for obtaining this score is described in the following embodiments.

[0028] In an application scenario, the first score of operator a1 running smart solution A on system-on-chip SOC1, the first score of operator a2 running smart solution A, the first score of operator b1 running smart solution B, the first score of operator b2 running smart solution B, the first score of operator c1 running smart solution C, and the first score of operator c2 running smart solution C are obtained.

[0029] Each intelligent solution has the possibility of running on each system-level chip. Therefore, by giving each intelligent solution the probability of running on each system-level chip, it can be ensured that each intelligent solution has at least one system-level chip for its operation. At the same time, the target probability in this application can be set by using the object or obtained based on the operation data. For details, please refer to the implementation method below.

[0030] In an application scenario, the target probabilities of running smart solution A, running smart solution B, and running smart solution C on the system-on-chip SOC1 are obtained, and the target probabilities of running smart solution A, running smart solution B, and running smart solution C on the system-on-chip SOC2 are obtained.

[0031] The idle score of the system-level chip represents the remaining computing power resources of the system-level chip that can run the intelligent solution. That is, when the idle score of the system-level chip is greater than or equal to the first score of the operator in the intelligent solution, the operator can run on the system-level chip. When the idle score of the system-level chip is less than the first score of the operator in the intelligent solution, the operator cannot run on the system-level chip.

[0032] It should be noted that the first score is the SoC score consumed by the operator of the intelligent solution when running on the SoC. However, due to the differences between different SoCs, even the same operator under the same intelligent solution may not necessarily obtain the same first score when running on different SoCs. Therefore, the first scores of operators running on different SoCs cannot be compared. For example, if SoCs SOC1 and SOC2 are completely different, the first score of operator a1 of intelligent solution A running on SoC SOC1 may not be equal to the first score of operator a1 of intelligent solution A running on SoC SOC2. Therefore, it is impossible to use the first score to evaluate the relationship between the computing power resources consumed by the two, and it is even more impossible to evaluate the computing power resources consumed by different operators. Therefore, the first score can be used to evaluate the amount of computing power resources consumed by operators under different intelligent solutions when running on the same SoC, but it cannot be used to evaluate the amount of computing power resources consumed by operators of intelligent solutions when running on different SoCs.

[0033] S200: For each system-level chip, according to the idle score of the system-level chip, the target probability corresponding to the system-level chip and the intelligent solution, and the first score corresponding to each operator in the intelligent solution of the system-level chip, a first target score corresponding to the system-level chip and the intelligent solution and a second target score corresponding to each operator in the intelligent solution of the system-level chip are obtained, wherein the first target score represents the normalized remaining computing power resources within a preset time after the system-level chip runs the intelligent solution, and the second target score represents the normalized remaining computing power resources within a preset time after the system-level chip runs the operators in the intelligent solution.

[0034] Specifically, the first target score corresponding to the system-level chip and the intelligent solution refers to the normalization of the computing power resources remaining within a preset time after running the intelligent solution on the system-level chip, and the second target score corresponding to the operator in the intelligent solution of the system-level chip refers to the normalization of the computing power resources remaining within a preset time after running the operator in the intelligent solution on the system-level chip. Of course, the process of obtaining the first target score and the second target score here does not really require actual operation on the system-level chip, but is obtained based on the data obtained in step S100. Considering that the operators in the intelligent solutions running on different system-level chips cannot be directly compared, a normalization process is adopted, which can make the computing power resources remaining after running the intelligent solution on different system-level chips and the computing power resources remaining after running the operators in the intelligent solution directly comparable, so that the intelligent solution and the size of the computing power resources consumed by the operators in the intelligent solution can be comprehensively evaluated for multiple system-level chips. In addition, by adding the target probability corresponding to the intelligent solution instead of random, the first target score and the second target score can be made closer to the level of actual operation.

[0035] In an application scenario, according to the idle scores of the system-level chip SOC1 and the system-level chip SOC2, the target probabilities of the system-level chip SOC1 and the smart solutions A, B and C, and the target probabilities of the system-level chip SOC2 and the smart solutions A, B and C, the first score of the system-level chip SOC1 and the operator a1 in the smart solution A, the first score of the system-level chip SOC1 and the operator a2 in the smart solution A, the first score of the system-level chip SOC1 and the operator b1 in the smart solution B, the first score of the system-level chip SOC1 and the operator b2 in the smart solution B, the system-level chip SOC1 and the operator b3 in the smart solution B, the system-level chip SOC1 and the operator b4 in the smart solution B, the system-level chip SOC1 and the operator b5 in the smart solution B, the system-level chip SOC1 and the operator b6 in the smart solution B, the system-level chip SOC1 and the operator b7 in the smart solution C, the system-level chip SOC1 and the operator b8 in the smart solution B, the system-level chip SOC1 and the operator b9 in the smart solution C, the system-level chip SOC1 and the operator b1 in the smart solution B, the system-level chip SOC1 and the operator b2 in the smart solution B ...2 in the smart solution C, the system-level chip SOC1 and the operator The first score corresponding to the chip SOC1 and the operator c1 in the smart solution C, the first score corresponding to the system-level chip SOC1 and the operator c2 in the smart solution C, the first score corresponding to the system-level chip SOC2 and the operator a1 in the smart solution A, the first score corresponding to the system-level chip SOC2 and the operator a2 in the smart solution A, the first score corresponding to the system-level chip SOC2 and the operator b1 in the smart solution B, the first score corresponding to the system-level chip SOC2 and the operator b2 in the smart solution B, the first score corresponding to the system-level chip SOC2 and the operator c1 in the smart solution C, and the first score corresponding to the system-level chip SOC2 and the operator c2 in the smart solution C.Obtain the first target score Quality1_A corresponding to the system-level chip SOC1 and the smart solution A, the first target score Quality1_B corresponding to the system-level chip SOC1 and the smart solution B, the first target score Quality1_C corresponding to the system-level chip SOC1 and the smart solution C, the second target score Quality1_a1 corresponding to the system-level chip SOC1 and the operator a1 in the smart solution A, the second target score Quality1_a2 corresponding to the system-level chip SOC1 and the operator a2 in the smart solution A, the second target score Quality1_b1 corresponding to the system-level chip SOC1 and the operator b1 in the smart solution B, the second target score Quality1_b2 corresponding to the system-level chip SOC1 and the operator b2 in the smart solution B, the second target score Quality1_c1 corresponding to the system-level chip SOC1 and the operator c1 in the smart solution C, and the second target score Quality1_c2 corresponding to the system-level chip SOC1 and the operator c2 in the smart solution C. , the first target score Quality2_A corresponding to the system-on-chip SOC2 and smart solution A, the first target score Quality2_B corresponding to the system-on-chip SOC2 and smart solution B, the first target score Quality2_C corresponding to the system-on-chip SOC2 and smart solution C, the second target score Quality2_a1 corresponding to the system-on-chip SOC2 and operator a1 in smart solution A, the second target score Quality2_a2 corresponding to the system-on-chip SOC2 and operator a2 in smart solution A, the second target score Quality2_b1 corresponding to the system-on-chip SOC2 and operator b1 in smart solution B, the second target score Quality2_b2 corresponding to the system-on-chip SOC2 and operator b2 in smart solution B, the second target score Quality2_c1 corresponding to the system-on-chip SOC2 and operator c1 in smart solution C, and the second target score Quality2_c2 corresponding to the system-on-chip SOC2 and operator c2 in smart solution C.

[0036] S300: Allocate operators in multiple smart solutions to multiple SoCs according to a first target score corresponding to each SoC and each smart solution and a second target score corresponding to each SoC and each operator in each smart solution.

[0037] Specifically, all the first target scores and all the second target scores obtained in step S200 are allocated. It can be understood that the lower the target score among all the first target scores and all the second target scores, the lower the computing power resources of the system-level chip within the preset time remaining, which is equivalent to the higher the utilization rate of the computing power resources of the system-level chip. Therefore, all the first target scores and all the second target scores obtained can be sorted from small to large, and all the first target scores and all the second target scores are allocated in order from small to large. It should be noted that in the allocation process, if the intelligent solution has been allocated, all operators in the intelligent solution do not need to be allocated again, and the allocation of operators can be skipped directly. If the operators in the intelligent solution have been allocated, the intelligent solution does not need to be allocated again, which can avoid the problem of repeated allocation.

[0038] For example, if smart solution A has been allocated, operators a1 and a2 in smart solution A do not need to be allocated again. However, if operators a1 and a2 in smart solution A are allocated, smart solution A does not need to be allocated again, because running operators a1 and a2 is equivalent to running smart solution A.

[0039] It can be seen from the above content that the present application obtains and obtains the first target score corresponding to the system-level chip and the intelligent solution and the second target score corresponding to each operator in the intelligent solution for each system-level chip based on the first score corresponding to each operator in each intelligent solution, the target probability corresponding to each operator in each intelligent solution, and the idle score of the system-level chip for each system-level chip. By comprehensively evaluating the first target score corresponding to the system-level chip and the intelligent solution and the second target score corresponding to each operator in the intelligent solution, the operators in multiple intelligent solutions are allocated to multiple system-level chips. The effect is that, on the one hand, by splitting the intelligent solution into multiple operators, the operators required The computing power resources are smaller than those of the intelligent solution, and different operators under the same intelligent solution can be allocated to different system-level chips. In this way, the smaller remaining computing power resources on the system-level chip can be used to run the operator, avoiding the waste of computing power resources caused by the smaller computing power resources in the prior art being unable to run the intelligent solution. Secondly, through normalization, the first target scores of the intelligent solutions running on different system-level chips and the second target scores of the operators in the intelligent solutions running on different system-level chips can be compared with each other, so as to achieve a comprehensive evaluation of the remaining computing power resources of multiple system-level chips and thus better allocate them. Thirdly, by adding the target probability, the first target score and the second target score are close to the real level. In summary, the solution of the present application can avoid the waste of computing power resources of multiple system-level chips, thereby greatly improving the utilization rate of computing power resources of multiple system-level chips.

[0040] In one embodiment, the step S200 includes:

[0041] A first target score corresponding to the system-level chip and the intelligent solution is obtained according to the idle score of the system-level chip, the target probability corresponding to the system-level chip and the intelligent solution, and the second score corresponding to the system-level chip and the intelligent solution, wherein the second score is equal to the sum of the first scores corresponding to the system-level chip and each operator in the intelligent solution.

[0042] Specifically, in the process of obtaining the first target score and the second target score, in addition to the need for the idle score of the system-level chip and the target probability corresponding to the system-level chip and the intelligent solution, the difference is that obtaining the second target score requires the second score corresponding to the system-level chip and the intelligent solution. This requires the first score corresponding to each operator in the system-level chip and the intelligent solution. Because the intelligent solution includes all operators within it, the first score corresponding to each operator in the system-level chip and the intelligent solution is added to obtain the second score corresponding to the system-level chip and the intelligent solution. Then, based on the second score corresponding to the system-level chip and the intelligent solution, the first target score corresponding to the system-level chip and the intelligent solution is obtained. This ensures that the evaluation of the first target score corresponding to the system-level chip and the intelligent solution is more comprehensive. It can be understood that for the evaluation of the second target score corresponding to the operator in the system-level chip and the intelligent solution, only the first score of the corresponding operator itself is required, and the first scores of other operators are not required.

[0043] In one embodiment, see Figure 2 The above step S200 further includes:

[0044] S210: For each SoC, based on the second scores corresponding to the SoC and the smart solution and the target probabilities corresponding to the SoC and the smart solution, obtain an expected score of the SoC corresponding to the smart solution, wherein the expected score represents the average computing power resources consumed by the smart solution during a preset time period when the smart solution runs on the SoC.

[0045] Specifically, the expected score of the SoC corresponding to the smart solution reflects the average level of computing power resources consumed by all smart solutions within a preset time period when running on the SoC. Therefore, it can be inferred that when the expected score of the SoC corresponding to the smart solution is high, the target probability of the smart solution with a higher second score corresponding to the SoC is generally higher, while when the expected score of the SoC corresponding to the smart solution is low, the target probability of the smart solution with a higher second score corresponding to the SoC is generally lower, that is, the target probability of the smart solution with a lower second score corresponding to the SoC is higher. Therefore, it can be understood that the result of the expected score representation is closer to the computing power resources consumed by the smart solution with a higher probability of being allocated within a preset time period when running on the SoC.

[0046] S220: For each system-level chip, according to the idle score of the system-level chip, the second score corresponding to the system-level chip and the intelligent solution, and the expected score of the system-level chip corresponding to the intelligent solution, obtain a first target score corresponding to the system-level chip and the intelligent solution; and, for each system-level chip, according to the idle score of the system-level chip, the first score corresponding to each operator in the intelligent solution of the system-level chip, and the expected score of the system-level chip corresponding to the intelligent solution, obtain a second target score corresponding to each operator in the intelligent solution of the system-level chip.

[0047] Specifically, the first target score and the second target score obtained are both based on the expected scores of the intelligent solution corresponding to the system-level chip, and the expected scores reflect the average level of computing power resources consumed when the intelligent solution runs on the system-level chip. Therefore, the first target score and the second target score obtained in this way are closer to the actual operation level.

[0048] In one embodiment, see Figure 3 The above step S200 further includes:

[0049] S211: For each SoC, calculate the sum of the products of the second scores corresponding to the SoC and the smart solution and the target probabilities corresponding to the SoC and the smart solution to obtain an expected score of the SoC corresponding to the smart solution.

[0050] Specifically, for each system-level chip, the second score corresponding to the system-level chip and each intelligent solution is first multiplied by the target probability corresponding to each intelligent solution, and then the results of all the corresponding intelligent solutions are summed up. The final result is the expected score of the system-level chip corresponding to the intelligent solution, and all system-level chips need to be calculated in this way.

[0051] In one application scenario, the second score Score1(A) corresponding to the system-level chip SOC1 and the smart solution A, the target probability P1(A) corresponding to the system-level chip SOC1 and the smart solution A, the second score Score1(B) corresponding to the system-level chip SOC1 and the smart solution B, the target probability P1(B) corresponding to the system-level chip SOC1 and the smart solution B, the second score Score1(C) corresponding to the system-level chip SOC1 and the smart solution C, and the target probability P1(C) corresponding to the system-level chip SOC1 and the smart solution C; the second score Score2(A) corresponding to the system-level chip SOC2 and the smart solution A, the target probability P2(A) corresponding to the system-level chip SOC2 and the smart solution A, the second score Score2(B) corresponding to the system-level chip SOC2 and the smart solution B, the target probability P2(B) corresponding to the system-level chip SOC2 and the smart solution B, the second score Score2(C) corresponding to the system-level chip SOC2 and the smart solution C, and the target probability P2(C) corresponding to the system-level chip SOC2 and the smart solution C.

[0052] Through calculation, we can get the expected score of the system-on-chip SOC1 corresponding to the intelligent solution:

[0053] Score1=Score1(A)×P1(A)+Score1(B)×P1(B)+Score1(C)×P1(C).

[0054] Through calculation, we can get the expected score of the system-on-chip SOC2 corresponding to the intelligent solution:

[0055] Score2=Score2(A)×P2(A)+Score2(B)×P2(B)+Score2(C)×P2(C).

[0056] S221: For each system-level chip, calculate the first difference between the idle score of the system-level chip and the second score corresponding to the system-level chip and the smart solution, calculate the first difference and divide it by the expected score of the system-level chip corresponding to the smart solution to obtain a first residual value, calculate the first residual value and divide it by the expected score of the system-level chip corresponding to the smart solution to obtain a first ratio, and determine the first ratio as the first target score corresponding to the system-level chip and the smart solution; and, for each operator in the smart solution in each system-level chip, calculate the second difference between the idle score of the system-level chip and the first score corresponding to the operator in the smart solution, calculate the second difference and divide it by the expected score of the system-level chip corresponding to the smart solution to obtain a second residual value, calculate the second residual value and divide it by the expected score of the system-level chip corresponding to the smart solution to obtain a second ratio, and determine the second ratio as the second target score corresponding to each operator in the smart solution.

[0057] Specifically, the first target score is calculated for each intelligent solution in each system-level chip, and the second target score is calculated for each operator in each intelligent solution in each system-level chip. It can be understood that through the calculation of the above steps, a large number of first target scores and second target scores will be generated. The number of results can be the sum of the number of all intelligent solutions and the number of all operators in the intelligent solution. The sum is multiplied by the number of all system-level chips, which is the total number of the calculated first target scores and second target scores.

[0058] Then, the first difference is calculated first. The first difference represents the remaining computing power resources after the system-level chip assumes running an intelligent solution. Then, the first residual is calculated. The first residual represents the remaining computing power resources after assuming that the above-mentioned remaining computing power resources are used to consume the average computing power resources of all intelligent solutions. Finally, the first ratio is calculated. The first ratio represents the normalization of the above-mentioned residuals, so that the first target scores of the intelligent solutions on different system-level chips can be compared with each other.

[0059] Similarly, first calculate the second difference, which represents the remaining computing power resources after the system-level chip assumes running an operator of an intelligent solution. Then calculate the second residual, which represents the remaining computing power resources after assuming that the above-mentioned remaining computing power resources are used to consume the average computing power resources of all intelligent solutions. Finally, calculate the second ratio, which represents the normalization of the above-mentioned residuals, so that the second target scores of operators in intelligent solutions on different system-level chips can be compared with each other.

[0060] At the same time, the normalized first target score and the second target score can also be compared with each other.

[0061] In an application scenario, the idle score Total1 of the system-on-chip SOC1, the second score Score1(A) corresponding to the system-on-chip SOC1 and the smart solution A, the second score Score1(B) corresponding to the system-on-chip SOC1 and the smart solution B, the second score Score1(C) corresponding to the system-on-chip SOC1 and the smart solution C, and the expected score Score1 of the system-on-chip SOC1 corresponding to the smart solution.

[0062] Through calculation, the first target score corresponding to the system-on-chip SOC1 and smart solution A is:

[0063] Quality1_A=((Total1-Score1(A)) mod Score1)÷Score1.

[0064] Through calculation, the first target score corresponding to the system-on-chip SOC1 and smart solution B is:

[0065] Quality1_B=((Total1-Score1(B)) mod Score1)÷Score1.

[0066] Through calculation, the first target score corresponding to the system-on-chip SOC1 and smart solution C is:

[0067] Quality1_C=((Total1-Score1(C)) mod Score1)÷Score1.

[0068] Similarly, the calculation method for the system-level chip SOC2 is exactly the same as that for the system-level chip SOC1. Just replace the data corresponding to the system-level chip SOC1 with the data corresponding to the system-level chip SOC2 and then perform the calculation. This application will not go into details here.

[0069] In an application scenario, the idle score Total1 of the system-level chip SOC1, the first score Score1(a1) corresponding to the system-level chip SOC1 and the operator a1 in the smart solution A, the first score Score1(a2) corresponding to the system-level chip SOC1 and the operator a2 in the smart solution A, the first score Score1(b1) corresponding to the system-level chip SOC1 and the operator b1 in the smart solution B, the first score Score1(b2) corresponding to the system-level chip SOC1 and the operator b2 in the smart solution B, the first score Score1(c1) corresponding to the system-level chip SOC1 and the operator c1 in the smart solution C, the first score Score1(c2) corresponding to the system-level chip SOC1 and the operator c2 in the smart solution C, and the expected score Score1 of the system-level chip SOC1 corresponding to the smart solution.

[0070] Through calculation, the second target score corresponding to the system-on-chip SOC1 and the operator a1 in the smart solution A is:

[0071] Quality1_a1=((Total1-Score1(a1)) mod Score1)÷Score1.

[0072] Through calculation, the second target score corresponding to the system-on-chip SOC1 and operator a2 in smart solution A is:

[0073] Quality1_a2=((Total1-Score1(a2)) mod Score1)÷Score1.

[0074] Through calculation, the second target score corresponding to the system-on-chip SOC1 and the operator b1 in the smart solution B is:

[0075] Quality1_b1=((Total1-Score1(b1)) mod Score1)÷Score1.

[0076] Through calculation, the second target score corresponding to the system-on-chip SOC1 and operator b2 in smart solution B is:

[0077] Quality1_b2=((Total1-Score1(b2)) mod Score1)÷Score1.

[0078] Through calculation, the second target score corresponding to the system-on-chip SOC1 and the operator c1 in the smart solution C is:

[0079] Quality1_c1=((Total1-Score1(c1)) mod Score1)÷Score1.

[0080] Through calculation, the second target score corresponding to the system-on-chip SOC1 and the operator c2 in the smart solution C is:

[0081] Quality1_c2=((Total1-Score1(c2)) mod Score1)÷Score1.

[0082] Similarly, the calculation method for the system-level chip SOC2 is exactly the same as that for the system-level chip SOC1. Just replace the data corresponding to the system-level chip SOC1 with the data corresponding to the system-level chip SOC2 and then perform the calculation. This application will not go into details here.

[0083] Of course, in some other implementations, the expected score of the system-level chip corresponding to the smart solution can also be calculated based on the second scores corresponding to the system-level chip and the smart solution and the geometric mean or weighted mean of the target probabilities corresponding to the system-level chip and the smart solution.

[0084] In one embodiment, see Figure 4 Before step S100, the control method of the present application further includes:

[0085] S1000: For an operator in the intelligent solution, determine a third score corresponding to the system-level chip and the operator based on the total score of the system-level chip and the operating frame rate of the operator, wherein the third score represents the computing power resources consumed by the system-level chip when the operator runs on the system-level chip and the operating frame rate of the operator is represented. The total score of the system-level chip represents the total computing power resources of the system-level chip within a preset time, and the operating frame rate of the operator represents the frame rate of the operator when it runs alone in the system-level chip within the preset time.

[0086] Specifically, the total score of the system-level chip represents the remaining computing power resources obtained based on the system-level chip not running any intelligent solutions and operators. By allowing a certain operator to run alone on the system-level chip, the system-level chip only runs the operator. Within the preset time, the number of frames that the operator can run is the operating frame rate of the operator. Therefore, based on the total score of the system-level chip and the operating frame rate of the operator, the computing power resources consumed by the system-level chip to run a unit frame can be obtained, that is, the third score corresponding to the system-level chip and the operator. Therefore, the third score of each operator corresponding to each system-level chip can be calculated according to the above method.

[0087] S2000: For an operator in the intelligent solution, determine a first score corresponding to the system-on-chip and the operator according to a preset frame rate of the operator and a third score corresponding to the system-on-chip and the operator.

[0088] Specifically, the preset frame rate of an operator refers to the frame rate at which the operator processes an image within a preset time. The preset frame rate can be adjusted based on actual conditions. The preset frame rate is different from the operating frame rate. The operating frame rate is related to both the operator and the SoC, while the preset frame rate is only related to the operator and can be specifically set. Furthermore, it should be noted that the preset frame rate of an operator when processing an image can be divided into two categories: one category is when the operator needs to process every frame in the image, such as target detection, target tracking, and target scoring; the other category is when the operator only needs to process a portion of the image frames, such as feature extraction and feature comparison. Therefore, it is understandable that the preset frame rates of different operators can be the same, but can also be different. The third score of the operator running on the SoC within a unit frame and the preset frame rate of the operator can be used to determine the computing power resources consumed by the operator within the preset time on the SoC, i.e., the first score of the operator. The first score of each operator on each SoC can be determined using the above determination method. After calculating the first score for each operator, the second score for the smart solution is obtained by summing the first scores of all operators in the smart solution. As can be seen from the above, the first score is obtained based on a preset frame rate, which is adjustable. This means that the computing power consumed by an operator can be changed based on the preset frame rate. However, in the prior art, the second score for the smart solution is usually fixed, without considering that the preset frame rate of the operators in the smart solution can be changed, which also leads to a waste of computing power resources.

[0089] In one embodiment, see Figure 5 Before step S100, the control method of the present application includes:

[0090] S1100: For an operator in the intelligent solution, calculate a ratio of a total score of the system-on-chip to an operating frame rate of the operator, and determine the ratio as a third score corresponding to the system-on-chip and the operator.

[0091] Specifically, in short, the third score corresponding to the system-level chip and the operator can be calculated by directly dividing the total score of the system-level chip by the operating frame rate of the operator. All operators in the corresponding intelligent solution on each system-level chip can be calculated in this way, and the third scores of all operators corresponding to all system-level chips can be calculated.

[0092] In one application scenario, the total score of the system-level chip SOC1 is Sum1, the running frame rate of the system-level chip SOC1 running operator a1 is F1(a1), the running frame rate of the system-level chip SOC1 running operator a2 is F1(a2), the total score of the system-level chip SOC2 is Sum2, the running frame rate of the system-level chip SOC2 running operator a1 is F2(a1), and the running frame rate of the system-level chip SOC2 running operator a2 is F2(a2).

[0093] Through calculation, the third score corresponding to the system-on-chip SOC1 and the operator a1 is:

[0094] S1(a1)=Sum1÷F1(a1).

[0095] Through calculation, the third score corresponding to the system-on-chip SOC1 and the operator a2 is:

[0096] S1(a2)=Sum1÷F1(a2).

[0097] Through calculation, the third score corresponding to the system-on-chip SOC2 and the operator a1 is:

[0098] S2(a1)=Sum2÷F2(a1).

[0099] Through calculation, the third score corresponding to the system-on-chip SOC2 and the operator a2 is:

[0100] S2(a2)=Sum2÷F2(a2).

[0101] It can be understood that the calculation method of the third score corresponding to the operator b1, operator b2, operator c1 and operator c2 and the system-on-chip SOC1 and system-on-chip SOC2 respectively is the same as the above, and will not be repeated.

[0102] S2100: For an operator in the intelligent solution, calculate a product of a preset frame rate of the operator and a third score corresponding to the system-on-chip and the operator, and determine the product as a first score corresponding to the system-on-chip and the operator.

[0103] Specifically, the product of the operator's preset frame rate and the third score corresponding to the SoC and operator is used as the first score corresponding to the SoC and operator. The third scores of all operators in all SoCs can then be calculated. After calculating the first score for each operator, the second score of the intelligent solution can be obtained by summing the first scores of all operators in the intelligent solution.

[0104] In one application scenario, the image frame rate is Afps. Operator a1 of Smart Solution A requires processing for every frame, so the preset frame rate of operator a1 is Afps. Operator a2 of Smart Solution A does not require processing for every frame, and the image selection frame rate of operator a2 is Asp. Therefore, the preset frame rate of operator a2 is the ratio of the image frame rate to the image selection frame rate. Simultaneously, the third score corresponding to operator a1 for system-on-chip (SOC1) is S1(a1), the third score corresponding to operator a2 for system-on-chip (SOC1) is S1(a2), the third score corresponding to operator a1 for system-on-chip (SOC2) is S2(a1), and the third score corresponding to operator a2 for system-on-chip (SOC2) is S2(a2).

[0105] Through calculation, the first score corresponding to the system-level chip SOC1 and the operator a1 is:

[0106] Score1(a1)=S1(a1)×Afps.

[0107] Through calculation, the first score corresponding to the system-on-chip SOC1 and the operator a2 is:

[0108] Score1(a2)=S1(a2)×Afps÷Asp.

[0109] Through calculation, the second score corresponding to the system-level chip SOC1 and smart solution A is:

[0110] Score1(A)=Score1(a1)+Score1(a2).

[0111] Through calculation, the first score corresponding to the system-level chip SOC2 and the operator a1 is:

[0112] Score2(a1)=S2(a1)×Afps.

[0113] Through calculation, the first score corresponding to the system-level chip SOC2 and the operator a2 is:

[0114] Score2(a2)=S2(a2)×Afps÷Asp.

[0115] Through calculation, the second score corresponding to the system-level chip SOC2 and smart solution A is:

[0116] Score2(A)=Score2(a1)+Score2(a2).

[0117] It can be understood that the calculation method for the first scores corresponding to operator b1, operator b2, operator c1 and operator c2 and the first scores corresponding to system-on-chip SOC1 and system-on-chip SOC2 respectively, and the calculation method for the first scores corresponding to smart solution B and smart solution C and the system-on-chip SOC1 and system-on-chip SOC2 respectively are the same as above and will not be repeated here.

[0118] In one embodiment, see Figure 6 , the control method of the present application also includes:

[0119] S3000: For each SoC, obtain the running frame rate of each operator in each intelligent solution on the SoC.

[0120] Specifically, the operators in the intelligent solution are run separately on the system-level chip. The frame rate at which the operator can process images within a preset time is the running frame rate. In this step, it is necessary to obtain the running frame rate of each operator in each intelligent solution running in each system-level chip.

[0121] S4000: For each SoC, determine the total score of the SoC based on the running frame rate of each operator in each intelligent solution on the SoC.

[0122] Specifically, when determining the total score of the system-level chip, it is necessary to obtain the running frame rate of all operators in each intelligent solution under the system-level chip running on the system-level chip, and determine the total score of the system-level chip by the running frame rate of all operators in each intelligent solution under the system-level chip running on the system-level chip. The determination method can be determined by the common multiple of all operators, or weighted summation, etc. The total score of all system-level chips is determined according to the above method. The method of the present application simplifies the representation method of the total computing power resources of the system-level chip, and there is no need to detect the actual computing power of the system-level chip, because the actual computing power of the system-level chip and the computing power consumed by the operator are difficult to detect directly, and further simplifies the representation method of the computing power resources consumed by the intelligent solution and the operator in the intelligent solution.

[0123] In one embodiment, the step S4000 includes:

[0124] The lowest common multiple of the running frame rates of all operators within the preset time on the system-level chip is calculated to obtain the total score of the system-level chip.

[0125] It is understandable that the total score of the system-level chip adopts the lowest common multiple of the operating frame rates of all operators running on the system-level chip. The lowest common multiple can reduce the complexity of calculation while keeping the total score of the system-level chip as small as possible.

[0126] In one embodiment, see Figure 7 Before step S100, the control method of the present application further includes:

[0127] S10: For each system-on-chip, determine whether each intelligent solution has a preset probability corresponding to the system-on-chip.

[0128] Specifically, the preset probability refers to the usage probability corresponding to each smart solution on each SoC, as pre-set by the user. If the user is pre-set, there will be a preset probability for each smart solution on each SoC. If the user is not pre-set, there will be no preset probability for each smart solution on each SoC.

[0129] S20: If yes, determine the preset probability of the smart solution and the system-on-chip corresponding to each other as the target probability of the system-on-chip and the smart solution corresponding to each other.

[0130] Specifically, if the user sets a preset probability, the preset probability is directly used as the target probability corresponding to the system-level chip and the intelligent solution.

[0131] S30: If not, obtain the historical running probability of each intelligent solution on the system-level chip, and determine the historical running probability of each intelligent solution on the system-level chip as the target probability corresponding to the system-level chip and each intelligent solution.

[0132] Specifically, if the user does not have a preset probability, the historical probability of each intelligent solution running on the SoC is obtained. The historical probability can be calculated by dividing the number of times the intelligent solution has been run on the SoC by the total number of times the intelligent solution has been run on the SoC. The historical probability can be calculated based on historical data collected within a fixed period and can be continuously updated based on subsequent runs.

[0133] In one embodiment, the control method of the present application further includes:

[0134] For each system-level chip, the difference between the total score of the system-level chip and the reserved score of the system-level chip is calculated, and the idle score of the system-level chip is obtained based on the difference, where the reserved score of the system-level chip represents the computing power resources reserved by the system-level chip, and the total score of the system-level chip represents the total computing power resources of the system-level chip.

[0135] Specifically, generally speaking, SoCs usually do not choose to fully utilize intelligent solutions or operators when running them. Full utilization of the SoC may lead to problems such as decreased processing speed. The operating frame rate obtained by independently operating the operator in the above-mentioned implementation and the total score of the SoC calculated based on the operating frame rate are usually theoretical limits. When used in real time, a reserved score for the SoC is set to ensure the performance of the SoC. The idle score of the SoC is obtained by deducting the reserved score from the total score of the SoC. Allocating intelligent solutions or operators based on the idle score of the SoC can ensure the operational performance and stability of the SoC. Generally speaking, the percentage of the reserved score of the SoC to the total score of the SoC can be set between 5% and 10%.

[0136] Of course, in some other implementations, the reserved fraction of the SoC may not be set, so that the intelligent solution or operator can run fully on the SoC, which may reduce the operating performance of the SoC.

[0137] In one embodiment, before the above step S300, the following steps are included:

[0138] In response to the existence of at least two equal values ​​of first target scores corresponding to the same intelligent solution and multiple system-level chips, the system-level chip with the largest ratio of idle score to total score is searched from the multiple corresponding system-level chips with equal values, and the intelligent solution is allocated to the system-level chip with the largest ratio of idle score to total score; and, in response to the existence of at least two equal values ​​of second target scores corresponding to the same operator and multiple system-level chips, the system-level chip with the largest ratio of idle score to total score is searched from the multiple corresponding system-level chips with equal values, and the intelligent solution is allocated to the system-level chip with the largest ratio of idle score to total score.

[0139] Specifically, when the first target scores corresponding to the same intelligent solution on multiple system-level chips are equal, since the first target score is the result of normalization based on the expected score, its purpose is to facilitate the comparison between multiple system-level chips, and when an equal situation occurs, by calculating the idle score and the total score ratio of multiple system-level chips with equal first target scores of the intelligent solution, the maximum value in the ratio can indicate that the system-level chip has the highest remaining computing power resources. Similarly, when the second target scores corresponding to the same operator on multiple system-level chips are equal, since the second target score is the result of normalization based on the expected score, its purpose is to facilitate the comparison between multiple system-level chips, and when an equal situation occurs, by calculating the idle score and the total score ratio of multiple system-level chips with equal second target scores of the operator, the maximum value in the ratio is selected, which can improve the utilization rate of the computing power resources of multiple system-level chips. As can be seen from the above content, this embodiment provides a solution for how to allocate when the first target score and the second target score are equal, which helps to further improve the utilization rate of the system-level chip.

[0140] In one application scenario, the first target score corresponding to Smart Solution A and System-on-Chip SOC1 is Quality1_A, and the first target score corresponding to Smart Solution A and System-on-Chip SOC2 is Quality2_A. At this time, Quality1_A is equal to Quality2_A, and it is necessary to further compare which of the System-on-Chip SOC1 and System-on-Chip SOC2 has a larger idle score and total score ratio. The idle score Total1 of System-on-Chip SOC1, the total score Sum1 of System-on-Chip SOC1, the idle score Total2 of System-on-Chip SOC2, and the total score Sum2 of System-on-Chip SOC2 can be further calculated to make an allocation. Similarly, in this application scenario, the operator allocation rules are the same as those of the smart solution and will not be repeated here.

[0141] In one embodiment, see Figure 8 , the above step S300 further includes:

[0142] S310: In response to a first target score corresponding to the first system-level chip and the first intelligent solution being greater than a second target score corresponding to the first system-level chip and the first operator in the first intelligent solution, and greater than the second target score corresponding to the first system-level chip and the second operator in the first intelligent solution, and the second target score corresponding to the second operator in the first intelligent solution being greater than the second target score corresponding to the first operator in the first intelligent solution, obtaining a minimum value of the first target score corresponding to the first system-level chip and the first intelligent solution and the second target scores corresponding to the other system-level chips and the second operator in the first intelligent solution.

[0143] Specifically, the first intelligent solution includes a first operator and a second operator. The first target score corresponding to the first intelligent solution running on the first SoC is greater than the second target scores corresponding to the first and second operators running on the first SoC, respectively. This indicates that the remaining computing resources after running the first intelligent solution on the first SoC are relatively large, potentially leading to waste. Therefore, the allocation of the first and second operators in the first intelligent solution needs to be further refined. Furthermore, because the second target score corresponding to the second operator in the first intelligent solution is greater than the second target score corresponding to the first operator in the first intelligent solution, the remaining computing resources after running the first operator are minimal, resulting in high utilization. However, the remaining computing resources after running the second operator are relatively large, requiring further evaluation of the allocation of the second operator. This can be achieved by further comparing the first target scores of the first SoC and the first intelligent solution, and the second target scores of other SoCs and the second operator in the first intelligent solution, and selecting the minimum value. This selection can reduce the waste of computing resources remaining after running the second operator, improve utilization, and thus complete the next step of allocation.

[0144] S320 : In response to the minimum value being the first target score corresponding to the first SoC and the first smart solution, assigning the first smart solution to run on the first SoC.

[0145] Specifically, under this condition, it means that after the second operator runs on other system-level chips, more computing power resources remain, and the waste is relatively greater. Therefore, running the second operator on the first system-level chip can reduce waste, which is equivalent to directly allocating the first intelligent solution to run on the first system-level chip.

[0146] S330: In response to the minimum value being the second target score corresponding to the second system-level chip in the other system-level chips and the second operator in the first intelligent solution, the first operator of the first intelligent solution is assigned to run on the first system-level chip, and the second operator of the first intelligent solution is assigned to run on the second system-level chip.

[0147] Specifically, under this condition, it is shown that the remaining computing power wasted after running the second operator on the second system-level chip in other system-level chips is the least among all system-level chips. Therefore, the first operator and the second operator in the first intelligent solution need to be allocated to different system-level chips for operation.

[0148] In one embodiment, see Figure 9 , before the above step S300, further comprising:

[0149] S250: In response to the idle score of the system-level chip minus the first score of at least part of the operators in at least part of the intelligent solution to obtain a third difference, the second target score of the subtracted operator and the first target score of the intelligent solution are added to the first priority queue, wherein the third difference is less than or equal to the first preset score.

[0150] Specifically, subtracting the first scores of at least some operators in at least some of the smart solutions can be understood as subtracting the first scores of some operators in some of the smart solutions, and / or subtracting the first scores of all operators in some of the smart solutions. It should be noted that when subtracting the first scores of all operators in a certain smart solution, it can be considered as subtracting the second score of the smart solution, and the two effects are equivalent, because the second score of the smart solution is the sum of the first scores of all operators in the smart solution. Therefore, when subtracting the first scores of at least some operators in at least some of the smart solutions from the idle score of the system-level chip, the two cases mentioned above need to be included. The first preset score is usually relatively small. It can generally be considered that the first preset score is usually not available for the operation of any operator, that is, the computing power resources represented by the first preset score are very small. The first preset score can be obtained by multiplying the total score of the system-level chip by a preset percentage. Generally speaking, the preset percentage is between 0% and 5%. The first score, after deducting at least some of the operators in at least some of the smart solutions, can be considered the computing power consumed by the theoretical operation of these operators on the SoC. The third difference refers to the remaining computing power on the SoC after these operators have theoretically been executed. If the third difference is less than the first preset score, it means that the SoC is no longer able to execute any operators, i.e., the remaining computing power is very small. This indicates that the theoretical utilization rate of the SoC for the operators removed is very high. Therefore, the second target score corresponding to these operators and the first target score corresponding to the smart solution can be added to the first priority queue. The first priority queue has the highest allocation priority because the SoC has the highest utilization rate when executing these operators removed.

[0151] S260: In response to subtracting the first scores of at least some operators in at least some smart solutions from the idle score of the system-level chip to obtain a fourth difference, the second target scores of the subtracted operators and the first target scores of the smart solutions are added to a third priority queue, wherein the fourth difference is less than the first preset score, and the fourth difference is greater than the smallest first score of all operators corresponding to all system-level chips and the smart solutions.

[0152] Specifically, if the fourth difference is greater than the first preset score, it means that after deducting the first scores of at least some operators in at least some of the intelligent solutions from the idle score of the SoC, there is still a large amount of remaining computing power resources. At the same time, the fourth difference is also less than the smallest first score of all operators corresponding to all SoCs and the intelligent solutions. In other words, the fourth difference cannot guarantee that at least one operator can run. Therefore, it is understandable that the fourth difference will cause the SoC to waste a large amount of computing power resources after running the subtracted operators. Therefore, the second target scores corresponding to these operators and the first target scores corresponding to the intelligent solutions can be added to the third priority queue. The third priority queue has the lowest allocation priority because the SoC may waste a large amount of computing power resources when running the subtracted operators.

[0153] S270: In response to the idle score of the system-level chip minus the first score of at least part of the operators in at least part of the intelligent solution to obtain a fifth difference, the second target score of the subtracted operator and the first target score of the intelligent solution are added to the second priority queue, wherein the fifth difference is greater than or equal to the smallest first score of all the operators corresponding to all the system-level chips and the intelligent solution, wherein, when subsequently allocating the operators in multiple intelligent solutions to multiple system-level chips, the operators in the first priority queue are first allocated to multiple system-level chips, and then the operators in the second priority queue are allocated to multiple system-level chips, and finally the operators in the third priority queue are allocated to multiple system-level chips.

[0154] Specifically, the fifth difference is greater than or equal to the minimum first score of all operators corresponding to all system-level chips and the intelligent solution. In other words, the fifth difference can ensure that at least one operator can run. Therefore, it can be understood that the fifth difference will ensure that the system-level chip still has computing power resources available to run other operators after running the reduced part of the operators. Therefore, the second target scores corresponding to these operators and the first target scores corresponding to the intelligent solution can be added to the second priority queue. The allocation priority of the second priority queue is in the middle because the corresponding system-level chip can be used to run more operators. Raising the priority of the second priority queue to before the priority of the third priority queue can reduce the waste of computing power resources, but the utilization rate in the second priority queue is lower than that in the first priority queue.

[0155] In one embodiment, after step S250, the method further includes:

[0156] Obtain the minimum value of the first target scores of all smart solutions and the second target scores of all operators in the first priority queue. When the minimum value is the first target score, set a first flag for the system-level chip corresponding to the minimum first target score. When the minimum value is the second target score, set a first flag for the system-level chip corresponding to the minimum second target score. The first flag is used for rapid allocation of smart solutions or operators.

[0157] Specifically, when the smart solutions and operators in the first priority queue run on the corresponding system-level chip, the computing power resource utilization of the system-level chip is very high. Therefore, in order to enable faster allocation next time, a first flag will be set for the smart solutions and operators therein. The first flag is set for the smart solution or operator with the highest computing power resource utilization in the first priority queue. In other words, the minimum value will be found among the first target scores of all smart solutions and the second target scores of all operators in the first priority queue. Regardless of whether the minimum value is the second target score of the operator or the first target score of the smart solution, the first flag will be set on the corresponding system-level chip. Then, when the allocation of smart solutions or operators is started next time, the system-level chip can directly run the smart solution or operator with the first flag, without having to re-compare the first target score and the second target score before allocating. It can be understood that after multiple runs, each run will generate a first flag. As the number of runs increases, the number of smart solutions or operators that need to be allocated will decrease due to the increase in the setting of the first flag, and the number that needs to be allocated based on the first target score and the second target score will decrease, thereby improving the efficiency of allocation.

[0158] In one embodiment, after the above step S100, the method further includes:

[0159] S110: Determine whether a first preset condition is met, wherein the first preset condition includes that a maximum value among the idle scores of multiple system-level chips is less than a minimum value of the second scores of all intelligent solutions in the multiple system-level chips, and is less than a minimum value of the first scores of all operators in all intelligent solutions in the multiple system-level chips, wherein the second score is equal to the sum of the first scores corresponding to the system-level chip and each operator in the intelligent solution.

[0160] Specifically, when the maximum value of the remaining computing power resources in multiple system-level chips cannot be used to run any of all intelligent solutions and cannot be used to run any operator of all operators, that is, no matter how it is allocated, it is impossible to enable a certain intelligent solution or a certain operator to run on any of the multiple system-level chips. In this case, the remaining computing power resources of each system-level chip are insufficient.

[0161] S120: In response to the first preset condition being satisfied, executing the steps of obtaining, for each system-on-chip, a first target score corresponding to the system-on-chip and the intelligent solution according to the idle score of the system-on-chip, the target probability corresponding to the system-on-chip and the intelligent solution, and a second target score corresponding to the system-on-chip and the intelligent solution, and obtaining a second target score corresponding to each operator in the intelligent solution according to the idle score of the system-on-chip, the target probability corresponding to the system-on-chip and the intelligent solution, and the first score corresponding to each operator in the intelligent solution.

[0162] Specifically, the first preset condition is met, that is, the remaining computing resources of the plurality of system-level chips can be allocated, and the above step S200 can be directly executed at this time.

[0163] S130: In response to the first preset condition not being met, reallocate operators already running on the plurality of system-on-chips.

[0164] Specifically, when the first preset condition is met, that is, when the remaining computing power resources of multiple system-level chips are completely insufficient, it is necessary to reallocate the already running intelligent solutions or operators on the multiple system-level chips, so that the multiple system-level chips can meet the first preset condition through permutations and combinations. At the same time, it should be noted that in the process of reallocating the already running intelligent solutions or operators on multiple system-level chips, in order not to affect the use, the intelligent solution can be started and run on another system-level chip without shutting down the system-level chip. After the intelligent solution on the other system-level chip runs normally, the intelligent solution on the original system-level chip can be shut down. This can make the dynamic allocation effect smoother. Of course, the allocation of operators can also be like this.

[0165] See Figure 11 , Figure 11 3 is a schematic structural diagram of an embodiment of a control device of the present application. The control device 300 includes an acquisition module 310 , an obtaining module 320 and an allocation module 330 .

[0166] The acquisition module 310 is used to obtain, for each system-level chip, a first score corresponding to each operator in each intelligent solution, a target probability corresponding to each intelligent solution, and an idle score of the system-level chip, wherein the first score represents the computing power resources consumed by the system-level chip within a preset time when running the operator in the intelligent solution, the target probability represents the probability of the system-level chip running the intelligent solution, and the idle score represents the remaining computing power resources of the system-level chip that can run the intelligent solution.

[0167] The obtaining module 320 is used to obtain, for each system-level chip, a first target score corresponding to the system-level chip and the intelligent solution, and a second target score corresponding to each operator in the intelligent solution according to the idle score of the system-level chip, the target probability corresponding to the system-level chip and the intelligent solution, and the first score corresponding to each operator in the intelligent solution. The first target score represents the normalized remaining computing power resources within a preset time after the system-level chip runs the intelligent solution, and the second target score represents the normalized remaining computing power resources within a preset time after the system-level chip runs the operator in the intelligent solution.

[0168] The allocation module 330 is used to allocate operators in multiple smart solutions to multiple SoCs based on the first target score corresponding to each SoC and each smart solution and the second target score corresponding to each SoC and each operator in each smart solution.

[0169] Among them, the control device 300 executes the method steps in any of the above-mentioned embodiments when working. The detailed method steps can be found in the above-mentioned related content and will not be repeated here.

[0170] The control device 300 may be a device with data processing and storage functions.

[0171] See also Figure 12 , Figure 12 This is a structural diagram of an embodiment of an electronic device of the present application. The electronic device 40 includes a memory 401 and a processor 402 coupled to each other, wherein the memory 401 stores program data (not shown in the figure), and the processor 402 calls the program data to implement the method in any of the above embodiments. For an explanation of the relevant content, please refer to the detailed description of the above method embodiments, which will not be repeated here.

[0172] See also Figure 13 , Figure 13 This is a structural diagram of an embodiment of a computer-readable storage medium of the present application. The computer-readable storage medium 50 stores program data 500. When the program data 500 is executed by the processor, the method in any of the above embodiments is implemented. For an explanation of the relevant content, please refer to the detailed description of the above method embodiments, which will not be repeated here.

[0173] Among them, the computer-readable storage medium 50 can specifically be a device that can store program data 500, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, or it can also be a server that stores the program data 500. The server can send the stored program data 500 to other devices for execution, or it can also execute the stored program data 500 itself.

[0174] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A control method for multiple system-on-chips, characterized in that: The method comprises: For each of the system-level chips, obtaining a first score corresponding to each operator in each intelligent solution, a target probability corresponding to each intelligent solution, and an idle score of the system-level chip, wherein the first score represents the computing power resources consumed by the system-level chip within a preset time when running the operator in the intelligent solution, the target probability represents the probability of the system-level chip running the intelligent solution, and the idle score represents the remaining computing power resources of the system-level chip that can run the intelligent solution; For each of the SoCs, a first target score corresponding to the SoC and the smart solution and a second target score corresponding to each operator in the smart solution are obtained based on the idle score of the SoC, the target probability corresponding to the SoC and the smart solution, and the first score corresponding to each operator in the smart solution. The first target score represents the normalized remaining computing power resources within a preset time after the SoC runs the smart solution, and the second target score represents the normalized remaining computing power resources within a preset time after the SoC runs the operators in the smart solution. The operators in the multiple smart solutions are allocated to the multiple system-level chips according to the first target score corresponding to each system-level chip and each smart solution, and the second target score corresponding to each system-level chip and each operator in each smart solution.

2. The method according to claim 1, characterized in that The step of obtaining a first target score corresponding to the system-level chip and the smart solution and a second target score corresponding to each operator in the smart solution based on the idle score of the system-level chip, the target probability corresponding to the system-level chip and the smart solution, and the first score corresponding to each operator in the smart solution, respectively, includes: A first target score corresponding to the system-level chip and the smart solution is obtained based on the idle score of the system-level chip, the target probability corresponding to the system-level chip and the smart solution, and the second score corresponding to the system-level chip and the smart solution, wherein the second score is equal to the sum of the first scores corresponding to the system-level chip and each operator in the smart solution.

3. The method according to claim 2, characterized in that The method further comprises: For each of the SoCs, obtaining an expected score for the SoC corresponding to the smart solution based on the second scores corresponding to the SoC and the smart solution and the target probabilities corresponding to the SoC and the smart solution, wherein the expected score represents the average computing power resources consumed by the smart solution during a preset time period when the SoC is running; For each of the system-level chips, a first target score corresponding to the system-level chip and the smart solution is obtained based on the idle score of the system-level chip, the second score corresponding to the system-level chip and the smart solution, and the expected score of the system-level chip corresponding to the smart solution; and, for each of the system-level chips, a second target score corresponding to each operator in the smart solution is obtained based on the idle score of the system-level chip, the first score corresponding to each operator in the smart solution, and the expected score of the system-level chip corresponding to the smart solution.

4. The method according to claim 3, characterized in that The method comprises: For each of the system-on-chips, calculating the sum of the second scores corresponding to the system-on-chip and the smart solution multiplied by the product of the target probabilities corresponding to the system-on-chip and the smart solution, to obtain an expected score of the system-on-chip corresponding to the smart solution; For each of the system-level chips, a first difference between the idle score of the system-level chip and the second score corresponding to the system-level chip and the smart solution is calculated, the first difference is divided by the expected score of the system-level chip corresponding to the smart solution to obtain a first residual value, the first residual value is divided by the expected score of the system-level chip corresponding to the smart solution to obtain a first ratio, and the first ratio is determined as the first target score corresponding to the system-level chip and the smart solution; and, for each of the operators in the smart solution in each of the system-level chips, a second difference between the idle score of the system-level chip and the first score corresponding to the operator in the smart solution is calculated, the second difference is divided by the expected score of the system-level chip corresponding to the smart solution to obtain a second residual value, the second residual value is divided by the expected score of the system-level chip corresponding to the smart solution to obtain a second ratio, and the second ratio is determined as the second target score corresponding to each operator in the smart solution.

5. The method according to claim 1, wherein The method further comprises: For the operator in the intelligent solution, determining a third score corresponding to the system-level chip and the operator based on the total score of the system-level chip and the operating frame rate of the operator, wherein the third score represents the computing power resources consumed by the system-level chip when the operator runs on the system-level chip and the system-level chip runs a unit frame, the total score of the system-level chip represents the total computing power resources of the system-level chip within a preset time, and the operating frame rate of the operator represents the frame rate of the operator when it runs alone in the system-level chip within the preset time; For the operator in the intelligent solution, the first score corresponding to the system-on-chip and the operator is determined according to a preset frame rate of the operator and the third score corresponding to the system-on-chip and the operator.

6. The method according to claim 5, characterized in that The method comprises: For the operator in the intelligent solution, calculating a ratio of a total score of the system-on-chip to an operating frame rate of the operator, and determining the ratio as a third score corresponding to the system-on-chip and the operator; For the operator in the intelligent solution, a product of a preset frame rate of the operator and the third score corresponding to the system-level chip and the operator is calculated, and the product is determined as the first score corresponding to the system-level chip and the operator.

7. The method according to claim 5, characterized in that The method further comprises: For each of the system-on-chips, obtaining an operating frame rate of each of the operators in each of the intelligent solutions on the system-on-chip; For each of the system-on-chips, the total score of the system-on-chip is determined according to the running frame rate of each of the operators in each of the intelligent solutions on the system-on-chip.

8. The method according to claim 7, characterized in that The step of determining the total score of the system-on-chip according to the running frame rate of each operator in each intelligent solution within a preset time on the system-on-chip includes: The lowest common multiple of the running frame rates of all the operators within a preset time on the system-on-chip is calculated to obtain a total score of the system-on-chip.

9. The method according to claim 1, characterized in that The method further comprises: For each of the system-on-chips, determining whether each of the smart solutions has a preset probability corresponding to the system-on-chip; If so, determining the preset probability corresponding to the smart solution and the system-on-chip as the target probability corresponding to the system-on-chip and the smart solution; If not, the historical running probability of each of the smart solutions on the system-level chip is obtained, and the historical running probability of each of the smart solutions on the system-level chip is respectively determined as the target probability corresponding to the system-level chip and each of the smart solutions.

10. The method according to claim 1, characterized in that The method further comprises: For each of the system-level chips, the difference between the total score of the system-level chip and the reserved score of the system-level chip is calculated, and based on the difference, the idle score of the system-level chip is obtained, wherein the reserved score of the system-level chip represents the computing power resources reserved for the system-level chip, and the total score of the system-level chip represents the total computing power resources of the system-level chip.

11. The method according to claim 1, wherein Before the step of allocating the operators in the plurality of smart solutions to the plurality of SoCs according to the first target score corresponding to each SoC and each smart solution and the second target score corresponding to each SoC and each operator in the smart solution, the step includes: In response to the fact that at least two values ​​of the first target scores corresponding to the same smart solution and multiple system-level chips are equal, the system-level chip with the largest proportion of the idle score to the total score is searched from the multiple system-level chips corresponding to the equal values, and the smart solution is allocated to the system-level chip with the largest proportion of the idle score to the total score; and, in response to the fact that at least two values ​​of the second target scores corresponding to the same operator and multiple system-level chips are equal, the system-level chip with the largest proportion of the idle score to the total score is searched from the multiple system-level chips corresponding to the equal values, and the smart solution is allocated to the system-level chip with the largest proportion of the idle score to the total score.

12. The method according to claim 1, characterized in that The step of allocating the operators in the plurality of smart solutions to the plurality of SoCs according to the first target score corresponding to each SoC and each smart solution, and the second target score corresponding to each SoC and each operator in the smart solution, comprises: In response to a first target score corresponding to a first system-on-chip and a first intelligent solution being greater than a second target score corresponding to the first system-on-chip and a first operator in the first intelligent solution and greater than a second target score corresponding to the first system-on-chip and a second operator in the first intelligent solution, and the second target score corresponding to the second operator in the first intelligent solution being greater than the second target score corresponding to the first operator in the first intelligent solution, obtaining a minimum value of the first target score corresponding to the first system-on-chip and the first intelligent solution and the second target scores corresponding to the other system-on-chips and the second operator in the first intelligent solution; In response to the minimum value being a first target score corresponding to the first SoC and the first smart solution, allocating the first smart solution to run on the first SoC; In response to the minimum value being the second target score corresponding to the second operator in the first intelligent solution and the second system-level chip among the other system-level chips, the first operator of the first intelligent solution is assigned to run on the first system-level chip, and the second operator of the first intelligent solution is assigned to run on the second system-level chip.

13. The method according to claim 1, wherein Before the step of allocating the operators in the plurality of smart solutions to the plurality of SoCs according to the first target score corresponding to each SoC and each smart solution and the second target score corresponding to each SoC and each operator in the smart solution, the method further includes: In response to subtracting the first scores of at least some operators in the smart solution from the idle score of the system-on-chip to obtain a third difference, adding the subtracted second target scores of the operators and the first target scores of the smart solution to a first priority queue, wherein the third difference is less than or equal to the first preset score; In response to subtracting the first scores of at least some of the operators in the smart solution from the idle score of the system-on-chip to obtain a fourth difference, the subtracted second target scores of the operators and the first target scores of the smart solution are added to a third priority queue, wherein the fourth difference is greater than the first preset score and less than the smallest first score of all the operators corresponding to all the system-on-chips and the smart solution; In response to subtracting the first scores of at least some operators in the smart solution from the idle score of the system-level chip to obtain a fifth difference, the subtracted second target scores of the operators and the first target score of the smart solution are added to the second priority queue, wherein the fifth difference is greater than or equal to the smallest first score of all the operators corresponding to all the system-level chips and the smart solution. Subsequently, when allocating multiple operators in the smart solution to multiple system-level chips, the operators in the first priority queue are first allocated to multiple system-level chips, and then the operators in the second priority queue are allocated to multiple system-level chips, and finally the operators in the third priority queue are allocated to multiple system-level chips.

14. The method according to claim 13, characterized in that After the step of obtaining a third difference value in response to the idle score of the system-on-chip minus the first scores of at least some operators in the intelligent solution, and adding the corresponding operators to the first priority queue, the method further includes: Obtain the minimum value of the first target scores of all the intelligent solutions and the second target scores of all the operators in the first priority queue; when the minimum value is the first target score, set a first flag for the system-level chip corresponding to the minimum first target score; when the minimum value is the second target score, set a first flag for the system-level chip corresponding to the minimum second target score, wherein the first flag is used for the rapid allocation of the intelligent solution or the operator.

15. The method according to claim 1, wherein After the step of acquiring, for each of the SoCs, the first score corresponding to each operator in each smart solution, the target probability corresponding to each of the SoCs and each smart solution, and the idle score of the SoC, the method further includes: Determining whether a first preset condition is met, wherein the first preset condition includes that a maximum value among the idle scores of the plurality of SoCs is less than a minimum value of the second scores of all the smart solutions in the plurality of SoCs, and is less than a minimum value of the first scores of all the operators in all the smart solutions in the plurality of SoCs, wherein the second score is equal to the sum of the first scores corresponding to the SoC and each operator in the smart solution; In response to the first preset condition being met, performing the steps of obtaining, for each SoC, a first target score corresponding to the SoC and the smart solution based on the idle score of the SoC, the target probability corresponding to the SoC and the smart solution, and a second score corresponding to the SoC and the smart solution; and obtaining a second target score corresponding to each operator in the smart solution based on the idle score of the SoC, the target probability corresponding to the SoC and the smart solution, and the first score corresponding to each operator in the smart solution. In response to the first preset condition not being met, operators already running on the plurality of system-on-chips are reallocated.

16. An electronic device, characterized in that: The electronic device includes a processor and a memory, and the processor is used to execute a computer program stored in the memory to implement the multi-system-on-chip control method according to any one of claims 1 to 15.

17. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and the computer program can be executed by a processor to implement the steps in the method according to any one of claims 1 to 15.

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