Data processing method and device, electronic equipment and computer readable storage medium

Abstract

The invention discloses a data processing method and relates to the technical field of chips. According to the method, under the condition that a data processing request of an application program for a first storage space in a memory is received, a memory bypass identifier corresponding to the first storage space is obtained, and the memory bypass identifier is used for indicating a storage mode of using a cache set according to an access demand of the application program for the first storage space; when processing of the associated data of the first storage space is executed according to the obtained memory bypass identifier, the storage mode of the associated data using the cache can be determined according to the access requirement of the application program for the first storage space, so that the cache behavior is controlled based on the access requirement of the application program, and the cache hit rate is improved.

Description

[0001] This application is a divisional application. The application number of the original application is 202211060725.0, and the original application date is August 31, 2022. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0002] The present application relates to the field of chip technology, and in particular to a data processing method, device, electronic device, and computer-readable storage medium. Background Art

[0003] In electronic devices, processors (e.g., central processing units (CPUs)) generally have access to main memory and cache storage space, where the main memory has a large capacity and a high access latency, and the cache has a small space but a low access latency. The CPU usually copies part of the data in the main memory to the cache, and when a pending request needs to access the data, the CPU can quickly obtain the data from the cache. The above probability of hitting the data that the pending request needs to access in the cache can also be called the cache hit rate, which affects the performance of the electronic device.

[0004] However, pending requests often come from applications running in the CPU. When the application accesses data in the cache through the pending requests, there is a problem of low cache hit rate, resulting in poor performance of the electronic device. Therefore, a method for improving the performance of the electronic device is urgently needed. Summary of the invention

[0005] The present application provides a data processing method, device, electronic device and computer-readable storage medium, which can improve cache hit rate.

[0006] In a first aspect, a data processing method is provided, which is applicable to an electronic device, wherein the electronic device includes a first storage medium and a second storage medium, the first storage medium is the memory of the electronic device, and the second storage medium is the cache of the memory, and the implementation process of this method includes: first obtaining a data processing request of an application, and then obtaining a memory bypass identifier corresponding to a first storage space according to the data processing request, and then performing processing of associated data according to the memory bypass identifier, wherein the data processing request is used to indicate processing of associated data of a first storage space in a first storage medium, and the memory bypass identifier is used to indicate a storage method using the second storage medium set according to the application's access requirements to the first storage space.

[0007] This method obtains a memory bypass identifier corresponding to the first storage space when receiving a data processing request from an application to the first storage space in the memory. Since the memory bypass identifier is used to indicate a storage method using a cache that is set according to the application's access requirements to the first storage space, when processing associated data of the first storage space is performed according to the obtained memory bypass identifier, the storage method using the cache for the associated data can be determined according to the application's access requirements to the first storage space, thereby controlling the cache behavior based on the application's access requirements and improving the cache hit rate.

[0008] In a possible implementation, the second storage medium is a high bandwidth memory HBM, and the usage mode of the HBM is a cache mode, where the cache mode is used to indicate that the HBM is used as a memory cache.

[0009] Based on the above possible implementation methods, in an application scenario where HBM is a cache of the first storage medium, a memory bypass flag is used to indicate that the storage space in the memory uses the HBM mode, thereby controlling the cache behavior of the HBM based on the access requirements of the application.

[0010] In another possible implementation, before obtaining the memory bypass identifier corresponding to the first storage space according to the data processing request, the implementation process of this method also includes: first calling the first application programming interface API in the operating system to set the bypass identifier field in the page table item of the page table of the first storage medium, and then adding the memory bypass identifier to the bypass identifier field in the page table item corresponding to the first storage space according to the access requirements recorded in the application, wherein the bypass identifier field is used to store the memory bypass identifier.

[0011] Based on the above possible implementation methods, by calling the first API to set the bypass identification field in the page table, a new memory bypass attribute is added to the page table, so that the bypass identification field can be added to the corresponding page table item according to the application's access requirements to the memory storage space, so that the processor can perceive the application's memory access characteristics through the memory bypass identification corresponding to each storage space in the set first storage medium, so that when the processor accesses the storage space in the memory, it can determine whether to copy the data in the storage space to the cache according to the memory bypass identification, thereby realizing the control of cache behavior based on the access requirements of the application, so that the processor can obtain the data required by the application in the cache later, thereby improving the cache hit rate.

[0012] In another possible implementation, the first API in the operating system is called to set the bypass identification field in the page table entry of the page table of the first storage medium as follows: when the application requests the operating system to allocate storage space in the first storage medium or after the application for allocation of storage space is completed, the first API is called to set the bypass identification field in the page table entry of the page table.

[0013] Based on the above possible implementation methods, when the application applies to the operating system for allocation of storage space in the first storage medium, it is only necessary to modify part of the application code so that the application can set the bypass identification field for the page table entry in the page by calling the first API in the operating system through the processor, which is simple to implement.

[0014] In another possible implementation, the first application programming interface API in the operating system is called, and the bypass identification field is set in the page table entry of the page table of the first storage medium as follows: in the process of compiling the application by the compiler, the first API is called through the second API or the introduction provided by the compiler, and the bypass identification field is set in the page table entry of the page table.

[0015] Based on the above possible implementation method, by modifying part of the code of the application and the compiler, the application can be compiled and the compilation interface in the compiler can be called to call the first API in the operating system to set the bypass identification field for the page table entry in the page, which is simple to implement.

[0016] In another possible implementation, according to the access requirements recorded in the application, the implementation method of adding a memory bypass identifier in the bypass identifier field in the page table entry corresponding to the first storage space includes: first, according to the access requirements recorded in the application, according to the virtual address of the first storage space, querying the page table entry corresponding to the first storage space, and then adding the memory bypass identifier to the queried page table entry.

[0017] In another possible implementation, before obtaining the memory bypass identifier corresponding to the first storage space according to the data processing request, the implementation process of this method also includes: predicting the application's access requirements to the first storage space based on the data transmission properties of at least one storage medium among the first storage medium and the second storage medium, and then setting the memory bypass identifier for the first storage space according to the predicted access requirements, wherein the data transmission properties are used to indicate the impact of the storage medium on the efficiency of transmitting data.

[0018] Based on the above possible implementation methods, the application's access demand for the first storage space is predicted through the current data transmission properties of at least one storage medium, so as to avoid recording the application's access demand for the first storage space in the application, and can also meet the application's real-time access demand for the memory storage space. Therefore, by predicting the memory bypass flag set where the application's access demand for the first storage space is located, the cache behavior can be controlled in real time.

[0019] In another possible implementation, the process of predicting the application's access requirements to the first storage space based on data transmission properties of the first storage medium and at least one of the second storage media includes: inputting the data transmission properties into a prediction network, and predicting the application's access requirements to the first storage space based on the input data transmission properties through the prediction network.

[0020] Based on the above possible implementation methods, the user does not need to modify the application code, and the operating system does not need to provide the first API. As long as the predicted network can be obtained, the bypass identification field can be set for the page table entry in the page table of the first storage medium, and the operation is simple.

[0021] In another possible implementation, the implementation method of setting a memory bypass flag for the first storage space according to the predicted access demand includes: first, according to the predicted access demand, according to the physical address of the first storage space, querying the page table entry corresponding to the first storage space, and then adding the memory bypass flag to the queried page table entry.

[0022] In another possible implementation, the data processing request includes a virtual address of the first storage space. On this basis, according to the data processing request, the implementation process of obtaining the memory bypass identifier corresponding to the first storage space includes: according to the virtual address of the first storage space, querying the page table entry corresponding to the first storage space, and then obtaining the memory bypass identifier in the queried page table entry.

[0023] In another possible implementation, the implementation process of querying the page table entry corresponding to the first storage space according to the virtual address includes: querying the page table entry corresponding to the first storage space in the page table of the first storage medium according to the virtual address; or, querying the page table entry corresponding to the first storage space in the translation lookaside buffer TLB of the processor according to the virtual address.

[0024] In another possible implementation, the implementation process of executing the processing of associated data according to the memory bypass identifier includes the following two situations: if the memory bypass identifier indicates that the second storage medium is used to store the data in the first storage medium, the associated data in the first storage space is processed, and the associated data in the first storage space is copied to the second storage medium; if the memory bypass identifier indicates that the second storage medium is not used to store the data in the first storage medium, the associated data in the first storage space is processed, and the step of copying the associated data in the first storage space to the second storage medium is not executed.

[0025] Based on the above possible implementation methods, according to the storage method of using cache indicated by the memory bypass identifier, a copy of the data in the storage space in the memory is stored in the cache or not stored in the cache, thereby achieving control of the cache behavior according to the memory bypass identifier.

[0026] In a second aspect, a data processing device is provided, which includes modules for executing the data processing method in the first aspect or any possible implementation of the first aspect.

[0027] According to a third aspect, an electronic device is provided. The electronic device includes a processor, and the processor is used to execute program code so that the electronic device executes to implement the operations performed by the above-mentioned data processing method.

[0028] According to a fourth aspect, a chip is provided, wherein the chip is used to implement the operation steps of the data processing method in the first aspect or any possible implementation manner of the first aspect.

[0029] According to a fifth aspect, a processor is provided, wherein the processor is used to implement the operation steps of the data processing method in the first aspect or any possible implementation manner of the first aspect.

[0030] In a sixth aspect, a computer-readable storage medium is provided, in which at least one program code is stored. The program code is read by a processor to enable an electronic device to perform operations performed by the above-mentioned data processing method.

[0031] In the seventh aspect, a computer program product or a computer program is provided, which includes a program code, and the program code is stored in a computer-readable storage medium. A processor of an electronic device reads the program code from the computer-readable storage medium, and the processor executes the program code, so that the electronic device executes the method provided in the above-mentioned first aspect or various optional implementations of the first aspect.

[0032] Based on the implementations provided in the above aspects, this application can also be further combined to provide more implementations. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a structural schematic diagram of a data processing system provided by the present application;

[0034] Figure 2 It is a structural schematic diagram of another data processing system provided by the present application;

[0035] Figure 3 It is a flow chart of a data processing method provided by the present application;

[0036] Figure 4 is a schematic diagram of a data processing system in an electronic device provided by the present application;

[0037] Figure 5 It is a schematic diagram of setting memory bypass attributes provided by this application;

[0038] Figure 6 It is an interactive schematic diagram of a data processing method provided by the present application;

[0039] Figure 7 is another schematic diagram of setting memory bypass attributes provided by the present application;

[0040] Figure 8 is a flow chart of another data processing method provided by the present application;

[0041] Fig. 9 is another schematic diagram of setting memory bypass attributes provided by the present application;

[0042] Fig.10 It is a schematic diagram provided by the present application for predicting the access requirements of an application program to storage space;

[0043] Fig.11 It is a structural schematic diagram of a data processing device provided by the present application;

[0044] Fig.12 It is a schematic diagram of the structure of a chip provided by the present application;

[0045] Fig.13 It is a structural schematic diagram of an electronic device provided by this application. DETAILED DESCRIPTION

[0046] For an electronic device including a first storage medium and a second storage medium, in the case where the first storage medium is a memory of the electronic device and the second storage medium is a cache of the memory, the present application provides a data processing method. In the method, when an application requests to process associated data of a storage space in the first storage medium, the storage mode of the storage space using the second storage medium is first obtained, wherein the storage mode is set according to the application's access requirements for the storage space, and then the associated data is processed using the obtained storage mode.

[0047] At this time, the second storage medium is used in a cache mode, which indicates that the second storage medium is used as a cache of the memory (i.e., the first storage medium). In a possible implementation, the method is executed by a processor (such as a CPU) in the electronic device. Figure 1 and 2 The system architecture composed of the processor, the first storage medium and the second storage medium in cache mode is introduced as follows.

[0048] Figure 1 It is a structural diagram of a data processing system provided by this application, such as Figure 1 As shown, the data processing system 100 includes a first storage medium 101, a second storage medium 102 and a processor 103. The first storage medium 101 serves as a memory of the processor 103 and is used to store data to be processed by the processor 103 (eg, business data, program code or computer instructions). Figure 1 The first storage medium 101 is shown as a double data rate synchronous dynamic random access memory (double data rate SDRAM, DDR) as an example. In some embodiments, the first storage medium 101 may also be a dynamic random access memory (dynamic random access memory, DRAM) or other types of main memory. Here, the embodiment of the application does not limit the medium type of the first storage medium 101.

[0049] The second storage medium 102 is used as a cache of the memory. At this time, the second storage medium 102 is used in a cache mode. Figure 1 The second storage medium 102 is taken as a high bandwidth memory (HBM) as an example. In some embodiments, the second storage medium 102 is a static random-access memory (SRAM) or other types of cache. Here, the embodiment of the present application does not limit the medium type of the second storage medium 102.

[0050] For any storage medium in the first storage medium 101 and the second storage medium 102, the storage medium includes a plurality of storage spaces, and the storage spaces are used to store data. When the processor 103 (such as a CPU) runs an application, the application requests to process the associated data of the storage space in the first storage medium 101 (such as reading the data of the storage space, or writing data to the storage space). According to the request of the application, the associated data to be processed is first queried from the cache of the first storage medium 101. If the processor finds the associated data of the storage space in the cache, it is considered that a cache hit occurs. Otherwise, it is considered that a cache miss occurs. If a cache hit occurs, the processor 103 executes the processing of the associated data in the cache. If a cache miss occurs, the processing of the associated data is executed in the first storage medium 101.

[0051] In some embodiments, the data processing system 100 includes a plurality of second storage media 102, and the plurality of first storage media 102 serve as a multi-level cache of the first storage medium 101. For example, Figure 2 As shown in the structural diagram of another data processing system provided by the present application, the data processing system 200 includes a first storage medium 101, second storage media 102a to 102d, and a processor 103. According to the speed of reading and writing data, the second storage media 102a to 102d and the first storage medium 101 correspond to the levels L1 to L5 one by one, L1>L2>L3>L4>L4>L5, wherein the storage medium with a higher level has a faster speed of reading and writing data.

[0052] like Figure 2 As shown, the second storage media 102a to 102d are all used in Cache mode. Figure 2 The example is that the caches at the L1 to L3 levels are all SRAM, the cache at the L4 level is HBM, and the memory at the L5 level is DDR. In different implementation scenarios, the memory may also have less than 4 or more than 4 caches. Here, the embodiment of the present application does not limit the number of caches in the memory.

[0053] For any cache in the multi-level cache of the second storage medium 102a to 102d, the cache is used to store a copy of part of the data stored in the next-level storage medium. When the processor 103 obtains a request from an application to process the associated data of the storage space in the first storage medium 101, the processor 103 preferentially searches in a high-level cache in descending order whether the associated data of the storage space is stored. For any cache, during the query process, the processor 103 performs the processing of the associated data in the cache. If a cache miss occurs, the processor 103 continues to search in the next-level storage medium of the cache until the associated data of the storage space is queried.

[0054] The above data processing system architecture can be deployed in an electronic device. Based on the above data processing system architecture, the process of executing the data processing method by the electronic device is introduced as follows in conjunction with the accompanying drawings:

[0055] When the application requests to process the associated data of a storage space in the first storage medium, the storage space obtained by the processor uses the storage mode of the second storage medium indicated by the memory bypass identifier, and then the processor performs the processing of the associated data according to the memory bypass identifier. To illustrate this process, see Figure 3 The flowchart of a data processing method provided by the present application is shown in FIG. 1 , and the method is applied to an electronic device, wherein the electronic device includes a first storage medium and a second storage medium, the first storage medium is a memory of the electronic device, and the second storage medium is a cache of the memory. Figure 3 As shown, the method includes the following steps 301 to 305.

[0056] Step 301: An application program calls a first application programming interface (API) in an operating system, and sets a bypass identification field in a page table entry of a page table of a first storage medium, where the bypass identification field is used to store a memory bypass identification.

[0057] The memory bypass identifier is used to indicate a storage mode of using the second storage medium set according to the application's access requirements to the storage space in the first storage medium. The application's access requirements to the storage space in the first storage medium include the application's access requirements to the storage space in the first storage medium recorded in the application or the predicted application's access requirements to the storage space in the first storage medium.

[0058] The memory bypass identifier includes a first memory bypass identifier or a second memory bypass identifier, the first memory bypass identifier is used to indicate that the second storage medium is used to store data in the first storage medium, and the second memory bypass identifier is used to indicate that the second storage medium is not used to store data in the first storage medium. The first memory bypass identifier and the second memory bypass identifier are represented differently, for example, the first memory bypass identifier is 1 and the second memory bypass identifier is 0, or the first memory bypass identifier is 0 and the second memory bypass identifier is 1. Here, the embodiment of the present application does not limit the representation of the first memory bypass identifier and the second memory bypass identifier.

[0059] by Figure 4 Taking the schematic diagram of a data processing system in an electronic device provided by the present application as an example, for a process running in the electronic device, the operating system (OS) manages the memory in pages, and uses a page table to save the mapping relationship between the virtual address of the first storage medium and the physical address. The corresponding virtual address and physical address are used to indicate the same storage space in the memory, the virtual address includes the page number of the page where the storage space is located (i.e., the page number of the virtual address) and the offset address of the storage space in the page, and the physical address includes the page frame number of the page frame where the storage space is located (i.e., the page number of the physical address).

[0060] Taking the page table shown in Table 1 as an example, the page table includes N+1 page table entries, each of which includes a page number and a page frame number to indicate that the page indicated by the page number is mapped to the page frame corresponding to the page frame number, where N is a positive integer.

[0061] Table 1

[0062]

[0063]

[0064] In an embodiment of the present application, the function of the page table entry in the page table is further extended. Taking the page table shown in Table 2 as an example, a bypass identification field is extended in the page table entry, and the bypass identification field is used to store a memory bypass identification, so that the page table has a memory bypass attribute.

[0065] Table 2

[0066] Page Table Entries Page Number Page frame number Bypass ID field Page Table Entry 0 0 0 Memory bypass flag Page Table Entry 1 1 1 Memory bypass flag … … … Memory bypass flag Page table entry N N N Memory bypass flag

[0067] Still Figure 4For example, the page table managed by the operating system is stored in the first storage medium, and the processor of the electronic device (such as the core of the CPU) uses a translation lookaside buffer (TLB) as a cache of the page table. For example, at least one page table entry in the page table is used as a TLB entry, so that the TLB entry has a bypass identification field, and the TLB has a memory bypass attribute.

[0068] The application sets a bypass identification field in a page table entry of a page table of a first storage medium by calling a first API in the operating system to add a memory bypass attribute to the page table. In a possible implementation, the first API is a user-defined API for setting a memory bypass attribute or is an existing API for extending a memory bypass attribute. Here, the embodiment of the present application does not limit the type of the first API.

[0069] In the case where the first API is an extension of an existing API with a memory bypass attribute set, the first API includes memory mapping file functions, memory mapping protection functions, and other types of functions. Here, the embodiment of the present application does not limit the function type of the first API.

[0070] The memory mapping file function is represented as: void*mmap(void*addr,size_t length,intprot,int flags,int fd,off_t offset), where addr in the memory mapping file function refers to the clue (HINT) of memory allocation; length indicates the length of the data mapped to the memory in the file; prot indicates the protection method of the mapping area of ​​the file in the memory. In the embodiment of the present application, the port function is extended, and a bypass attribute setting identifier is added to the port, and the bypass attribute setting identifier indicates setting a bypass identification field for the page table entry in the page table; Flags indicates various characteristics of the mapping area; fd is a file descriptor, indicating the file mapped to the memory. Offset is the offset of the file mapping.

[0071] The memory mapping protection function is expressed as: int mprotect(void*addr,size_t len,int prot), where addr in the memory mapping file function indicates the starting address of the protection attribute area to be modified in the memory; len is the length of the protection attribute area; prot indicates various attributes of the protection attribute area. In the embodiment of the present application, the port function is extended, and a bypass attribute setting identifier is added to the port, and the bypass attribute setting identifier indicates that a bypass identifier field is set for the page table entry in the page table.

[0072] In a possible implementation, the application program calls the first API in the operating system through any one of the following methods 1 or 2.

[0073] Mode 1: When the application program applies to the operating system for allocation of storage space in the first storage medium or after the application for allocation of the storage space is completed, the application program calls the first API and sets the bypass identification field in the page table entry of the page table.

[0074] The application is any application installed in the electronic device. Figure 4 For example, when applying for memory storage space, the application (APP) calls the first API in the operating system and sets the bypass identification field. Figure 5 and Figure 6 The process is described as follows:

[0075] in, Figure 5 This is a schematic diagram of setting memory bypass properties provided by this application. Figure 6 It is an interactive schematic diagram of a data processing method provided by this application, such as Figure 5 and Figure 6 As shown, when the application is started, it sends a memory allocation request to the operating system (such as a memory management module in the kernel of the operating system), and the memory allocation request is used to indicate that storage space in the first storage medium is allocated to the application, that is, to apply for memory from the operating system. After receiving the memory allocation request, the operating system allocates storage space in the first storage medium to the application, and returns a first virtual address segment to the application, and the first virtual address segment corresponds to the physical address of at least one storage space allocated to the application. In addition, when the application sends a memory allocation request to the operating system, the memory allocation request triggers a call to the first API in the operating system, and a bypass attribute setting identifier is input to the first API. The operating system (such as the memory management module) sets the bypass attribute setting identifier through the first API, and sets the bypass identifier field in the page table item in the page table, thereby adding a memory bypass attribute to the page table. In this case, the first API may be a user-defined API or a memory-mapped file function.

[0076] After the application completes the application to allocate storage space to the operating system, Figure 5 For example, if the application receives the first virtual address segment returned by the operating system based on the memory allocation request, the application calls the first API in the operating system and inputs the bypass attribute setting flag to the first API. The operating system sets the bypass flag field for the page table entry in the page table through the memory bypass flag input by the first API. In this case, the first API may be a user-defined API or a memory mapping protection function.

[0077] When the application requests the operating system to allocate storage space in the first storage medium, by modifying part of the application code, the application calls the first API in the operating system through the processor, and the bypass identification field can be set for the page table entry in the page, which is simple to implement.

[0078] Mode 2: The first API is encapsulated as a compilation interface in the compiler. During the process of compiling the application program through the compiler, the application program calls the first API through the second API or introduction in the compiler to set the bypass identification field for the page table entry of the page table.

[0079] The second API may be an API extended based on an existing API or may be a newly added API. Here, the embodiment of the present application does not limit the implementation method of the second API.

[0080] by Figure 4 For example, the application APP calls the first API in the operating system when it is compiled, combined with Figure 7 The process is described as follows:

[0081] in, Figure 7 is another schematic diagram of setting memory bypass properties provided by this application, such as Figure 7 As shown, the first API is encapsulated in the second API or preamble in the compiler. During the process of the compiler compiling the application, the application calls the second API or preamble in the compiler and inputs a bypass attribute setting identifier into the second API or preamble. When the second API or preamble receives the bypass attribute setting identifier, it calls the first API in the operating system and inputs the bypass attribute setting identifier into the first API. The operating system (such as a memory management module in the kernel of the operating system) sets the bypass identifier field in the page table entry in the page table through the bypass attribute setting identifier input by the first API, thereby adding a memory bypass attribute to the page table.

[0082] For this implementation, by modifying part of the application and compiler code, the application can be compiled and the compilation interface in the compiler can be called to call the first API in the operating system to set the bypass identification field for the page table entry in the page, which is simple to implement.

[0083] Still Figure 5-7 For example, after the operating system sets a bypass flag field for a page table entry in a page table, the processor (such as a core of the processor) also synchronizes the bypass flag field from the operating system's page table to the TLB option of the TLB to set the bypass flag field for the TLB option, thereby adding a memory bypass attribute to the processor.

[0084] In another possible implementation, a target application is installed in the electronic device, and the target application is used to call the first API. For example, when a processor in the electronic device runs the target application, the target application calls the first API to set the bypass identification field for the page table entry of the page table without calling the first API interface through each application.

[0085] This step 301 is an optional step. In some embodiments, if the bypass identification field has been set in the page table, the operating system does not need to perform this step 301. In other embodiments, the operating system has the function of actively setting the bypass identification field in the page table. For example, when the electronic device is powered on and the operating system is initialized, the operating system sets the bypass identification field in the page table. In this case, it is not necessary to perform this step 301. And this step 301 only needs to be performed once, and does not need to be performed multiple times.

[0086] Step 302: The operating system adds the memory bypass identifier to the bypass identifier field in the page table entry corresponding to the first storage space according to the access requirement of the application program to the first storage space recorded in the application program.

[0087] Among them, the first storage space is any storage space in the first storage medium. In the embodiment of the present application, the data stored in the first storage space is called associated data, and the application's access demand to the first storage space in the first storage space is the application's access demand to the associated data. The application's access demand to the associated data, for example, the application needs to access the associated data at least a target number of times within the first time period, or the associated data is the business data of the target business to be accessed by the application within the first time period. Among them, the first time period is the time period after the current moment, that is, the future time period. Here, the embodiment of the present application does not limit the length of the first time period.

[0088] In a possible implementation, if the first storage space has been allocated to the application, the operating system adds a memory bypass identifier to the page table entry according to the access requirement recorded in the application. For example, steps 3021 to 3022 are described below.

[0089] Step 3021: The operating system queries the page table entry corresponding to the first storage space according to the access requirement recorded in the application program and the virtual address of the first storage space.

[0090] by Figure 6 For example, the application program requests the operating system to set a memory bypass flag for the first storage space according to the access requirement recorded by the application program, so that when the operating system receives the request of the application program, the operating system queries the page table entry corresponding to the first storage space according to the virtual address of the first storage space. For example, the following steps A1 to A2.

[0091] Step A1: If the first storage space in the first storage medium has been allocated to an application, the application sends a bypass flag setting request to the operating system, where the bypass flag setting request indicates setting a memory bypass flag for the first storage space.

[0092] In which, the bypass identifier setting request includes the virtual address where the associated data of the first storage space is located, or the bypass identifier setting request includes the starting address of the virtual address segment of the memory bypass identifier to be set and the length of the virtual address segment, wherein the storage space indicated by the virtual address segment includes the first storage space, or the bypass identifier setting request includes the virtual address segment.

[0093] like Figure 6 As shown, when the application requests the operating system to allocate memory, the operating system (such as a memory management module in the kernel of the operating system) sets a bypass identification field for the page table entry of the page table. After the application requests the operating system to allocate the storage space of the first storage medium, the operating system (such as the memory management module) allocates at least one storage space in the first storage medium to the application, creates at least one page for the application, and the at least one page corresponds to the at least one storage space. Afterwards, the operating system creates a page table for the application based on the at least one page and the at least one storage space, the page table includes at least one page table entry, each page table entry is used to store the page number of a page and the page frame number of the corresponding storage space. Based on the at least one page, the operating system returns a first virtual address segment to the application, and the first virtual address segment is used to indicate the at least one page. For example, the starting address of the first virtual address segment is the starting address of the first page in the at least one page, and the ending address of the first virtual address segment is the ending address of the last page in the at least one page. The length of the first virtual address segment is the length of the at least one page.

[0094] When the application receives the first virtual address segment, all relevant data used by the processor in the process of running the application can be stored in the storage space corresponding to the first virtual address segment.

[0095] For at least one data to be accessed by the application, if a demand identifier corresponding to any data is recorded in the application, and the any data is stored at a certain virtual address in the first virtual address segment, a bypass identifier setting request including the virtual address is generated by taking the page frame corresponding to the page where the virtual address is located as the first storage space and taking any data as the associated data of the first storage space. The demand identifier indicates the application's access demand for the at least one data.

[0096] In some embodiments, if the multiple data to be accessed by the application program all correspond to the demand identifier, the application program uses the virtual address in the first virtual address segment for storing the multiple data as the virtual address segment (i.e., the second virtual address segment) for setting the memory bypass identifier, and generates a bypass identifier setting request including the second virtual address segment. Alternatively, if the virtual address in the second virtual address segment is a continuous virtual address, the bypass identifier setting request does not include the second virtual address segment, but includes the starting address of the second virtual address segment and the length of the second virtual address segment.

[0097] In another possible implementation, the bypass flag setting request further includes at least one of a memory bypass flag and a requirement flag of the second storage medium. Of course, the bypass flag setting request may also not include a memory bypass flag and a requirement flag.

[0098] Step A2: The operating system receives the bypass flag setting request, and based on the bypass flag setting request, queries a page table entry corresponding to the first storage space according to the virtual address of the first storage space.

[0099] After the operating system receives the bypass flag setting request, if the bypass flag setting request includes the virtual address of the first storage space, the operating system obtains the page number in the virtual address, which indicates the page where the first storage space is located. Thereafter, the operating system queries the page table entry including the page number in the page table.

[0100] If the bypass identification setting request includes a second virtual address field, the operating system determines the page numbers of each page corresponding to the second virtual address field based on the second virtual address field. Address page alignment is achieved. For ease of description, each page corresponding to the second virtual address field is referred to as the first page. Alternatively, if the bypass identification setting request includes the starting address and length of the second virtual address field, the operating system determines the page indicated by the starting address based on the starting address, and determines the page indicated by the starting address and the target number of pages after the page as the first page based on the length of the second virtual address field, wherein if the multiple between the length of the second virtual address field and the length of a single page is an integer, the target number is equal to the multiple, and if the multiple is not an integer, the target number is 1 greater than the multiple.

[0101] After determining the first pages corresponding to the second virtual address segment, for any first page, the operating system searches the page table for a page table entry including the page number of the first page. If the first page is a page where the first storage space is located, the operating system searches the page table for a page table entry including the page number of the first page, that is, searches for a page table entry corresponding to the first storage space.

[0102] Step 3022: The operating system adds a memory bypass identifier in the page table entry corresponding to the first storage space in the page table.

[0103] For any first page, if any page table entry in the page table includes the page number of the first page, the operating system adds the first memory bypass identifier to the bypass identifier field of the any page table entry. For example, the following situations 1 and 2.

[0104] Case 1: When creating the page table, the operating system adds a second memory bypass identifier in the bypass identifier field of each page table entry in the page table. If any page table entry in the page table includes the page number of the first page, the second memory bypass identifier in the bypass identifier field of any page table entry is modified to the first memory bypass identifier.

[0105] Case 2: When the operating system creates the page table, it does not add anything to the bypass identification field of each page table entry in the page table, so that the bypass identification field is empty. If any page table entry in the page table includes the page number of the first page, the operating system adds the first memory bypass identification to the bypass identification field of any page table entry.

[0106] During the first time period after the current time, the application may also need to access part of the storage space in the first storage medium less than the target number of times, and the operating system sets a second memory bypass identifier for the page (i.e., the second page) where this part of the storage space is located. It is understandable that the second page is each page other than the first page in at least one page created for the application. For case 1, the page table entries in the page table that do not modify the memory bypass identifier are page table entries corresponding to the second page. Since the memory bypass identifier in the page table entry corresponding to the second page is the second memory bypass identifier, the operating system does not need to set the second memory bypass identifier again for the page table entry corresponding to the second page. For case 2, since the bypass identifier field of the page table entry corresponding to the second page is empty, the operating system adds the second memory bypass identifier to the bypass identifier field of the page table entry corresponding to the second page.

[0107] In another possible implementation, the application sends the bypass identifier setting request to the operating system based on the first virtual address segment, and the bypass identifier setting request includes the second virtual address segment and the third virtual address segment, wherein the second virtual address segment corresponds to the demand identifier or the first memory bypass identifier, and the third virtual address segment includes the virtual address in the first virtual address segment except the second virtual address segment. Afterwards, the operating system adds the first memory bypass identifier to the page table entries corresponding to each first page in the page table based on the second virtual address segment in the bypass identifier setting request and the corresponding demand identifier or the first memory bypass identifier, determines the page number of the second page based on the third virtual address segment in the bypass identifier setting request, and adds the second memory bypass identifier to the page table entry in the page table that includes the page number of the second page.

[0108] like Figure 6 As shown, the operating system (such as a memory management module) adds a memory bypass identifier to each page table entry in the page table. In addition, the processor may continuously access data in the storage space of the first storage medium during the execution of the application. For a certain storage space in the first storage medium accessed by the processor in the current time period, the processor reads the page table entry corresponding to the storage space in the page table into the TLB as a TLB table entry. That is, when the processor (such as the core of the processor) updates the TLB table, it reads the page table entry including the memory bypass identifier into the TLB. Accordingly, the processor synchronizes the memory bypass identifier in the page table stored in the first storage medium to the memory bypass identifier field of the TLB table entry. Figure 3 For example, the core of the processor adds page table entries 0-K in the page table to the TLB to obtain TLB table entries 0-K, and the TLB table entries 0-K all include a memory bypass flag.

[0109] Step 303: The processor obtains a data processing request from the application program, where the data processing request is used to instruct processing of associated data in the first storage space in the first storage medium.

[0110] The first storage space is a storage space in the first storage medium that includes the associated data, and the data processing request includes a virtual address of the first storage space. In a possible implementation, the data processing request is a data read request or a data write request, the data read request indicates reading the associated data in the first storage space, the data write request indicates writing the associated data into the first storage space, and the data write request also includes the associated data.

[0111] When the processor is running the application, if there is a need to access the first storage space, the processor generates the data processing request. For example, when the application is running, if the application wants to write data to the first storage space, the data processing request generated by the processor is a data write request, and if the application wants to read data in the first storage space, the data processing request generated by the processor is a data read request.

[0112] Step 304: The processor obtains a memory bypass identifier corresponding to the first storage space according to the data processing request, where the memory bypass identifier is used to indicate a storage mode of using the second storage medium that is set according to the application's access requirement to the first storage space.

[0113] In one possible implementation, the processor queries the page table entry corresponding to the first storage space according to the virtual address of the first storage space in the data processing request, and obtains the memory bypass identifier of the first storage space from the queried page table entry (such as obtaining the memory bypass identifier from the memory bypass field of the page table entry).

[0114] Regarding the process of the processor querying the page table entry corresponding to the first storage space, the processor queries the page table entry corresponding to the first storage space in the TLB of the processor according to the virtual address, or queries the page table entry corresponding to the first storage space in the page table of the first storage medium according to the virtual address.

[0115] For example, the processor determines the page number and the page offset of the page where the first storage space is located based on the virtual address. Afterwards, based on the page number of the page, the TLB is queried for a TLB table entry including the page number. If a TLB table entry including the page number is found, the memory bypass identifier is obtained from the bypass identifier field of the TLB table entry. If the TLB table entry including the page number cannot be found in the TLB, the processor reads the page table entry including the page number from the page table to the TLB, and then obtains the memory bypass identifier from the page table entry in the TLB. Alternatively, the processor first obtains the memory bypass identifier from the page table entry, and then reads the page table entry to the TLB.

[0116] Step 305: The processor executes processing of the associated data according to the memory bypass identifier.

[0117] Among them, for different memory bypass identifiers, the processor performs different processing of associated data. For example, if the memory bypass identifier indicates that the second storage medium is used to store the data in the first storage medium, the processor processes the associated data of the first storage space and copies the associated data in the first storage space to the second storage medium. If the memory bypass identifier indicates that the second storage medium is not used to store the data in the first storage medium, the processor processes the associated data of the first storage space and does not execute the step of copying the associated data in the first storage space to the second storage medium.

[0118] In addition, the processor determines that the data in the first storage space has been stored in the second storage medium by querying the TLB. If a TLB table entry is found to include the page number of the page where the first storage space is located, it means that the data in the first storage space has been stored in the second storage medium. Then, by accessing the second storage medium, the associated data of the first storage space is processed. Otherwise, by accessing the first storage medium, the associated data of the first storage space is processed.

[0119] The following describes step 305 based on the TLB entry or page table entry including the page number found:

[0120] If the memory bypass identifier is obtained from the TLB table entry, the processor obtains the page frame number of the first storage space from the queried TLB table entry, and concatenates the page frame number and the page offset in the virtual address of the first storage space to obtain the physical address of the first storage space. Based on the physical address, the processor queries the cache line including the data in the first storage space in the second storage medium, and based on the data processing request, accesses the cache space corresponding to the first storage space in the cache line to process the associated data of the first storage space. For example, if the data processing request is a data read request, the processor reads data from the cache space, and the data read at this time is also the associated data of the first storage space. If the data processing request is a data write request, the processor writes the data write request carrying the associated data to the cache space.

[0121] At this time, the second storage medium has already stored the associated data in the first storage space in the first storage medium. Therefore, based on the queried memory bypass identifier, the processor does not perform any operation on the data in the first storage space in the first storage medium, and only processes the data write request.

[0122] If the processor obtains the memory bypass identifier from the page table entry in the page table, the processor obtains the page frame number of the first storage space from the queried page table entry, and concatenates the page frame number and the page offset in the virtual address of the first storage space to obtain the physical address of the first storage space. Based on the data processing request, the processor accesses the first storage space indicated by the physical address in the first storage medium to process the associated data of the first storage space. For example, if the data processing request is a data read request, the processor reads data from the first storage space, and if the data processing request is a data write request, the processor writes the data write request with the associated data to the first storage space.

[0123] At this time, if the memory bypass identifier is the first memory bypass identifier, the processor copies the data in the first storage space (i.e., the associated data) to the cache line in the second storage medium. If the memory bypass identifier is the second memory bypass identifier, the processor does not perform the step of copying the data in the first storage space to the cache line in the second storage medium.

[0124] by Figure 3 For example, in Figure 3In the example, it is assumed that the first storage medium is DDR and the second storage medium is HBM. The processor (such as the core of the processor) queries the page table or TLB, adds the memory bypass identifier corresponding to the storage space to be accessed in the DDR in the data processing request of the APP, and sends the data processing request carrying the memory bypass identifier to the judgment module in the processor. The judgment module determines whether the data in the storage space needs to be copied to the HBM based on the memory bypass identifier. If the hot data in the storage space needs to be copied to the HBM, it means that the data in the storage space is hot data. The data processing request is a data read request. After the judgment module reads the hot data from the storage space in the DDR, the hot data is copied to the HBM. After that, when the processor reads the hot data in the storage space again, it can be directly read in the HBM. If the data in the storage space does not need to be copied to the HBM, it means that the data in the storage space is cold data. The data processing request is a data read request. After the processor reads the cold data from the storage space in the DDR, the cold data is not copied to the HBM.

[0125] In a possible implementation, when the size of the first storage space is smaller than the size of the cache line in the second storage medium, if the data in the first storage space is copied to the cache line in the second storage medium, the processor will also copy the data of other storage spaces in the first storage medium to the cache line to fill up the cache line. In addition, when the free cache lines of the second storage medium are insufficient, the processor will eliminate the data in the non-free cache lines in the second memory from the second storage medium, so that the non-free cache lines become free cache lines, and then the processor will copy the data in the first storage space in the first storage medium together with the data of other storage spaces to the free cache line.

[0126] Next, combine Figure 6 The above steps 304 and 305 are introduced as follows: after receiving the data processing request of the application, the core of the processor sends the data processing request to the core of the processor. The core of the processor queries the memory bypass identifier corresponding to the first storage space from the TLB or page table according to the data processing request, adds the queried memory bypass identifier to the data processing request, and sends the data processing request carrying the memory bypass identifier to the non-core (uncore) part of the processor. Afterwards, the non-core part determines whether it is necessary to copy the associated data of the first storage space to the second storage medium according to the memory bypass identifier in the data processing request, and executes the relevant processing process. It can be understood that the non-core part includes Figure 4 The judgment module in can realize the function of the judgment module.

[0127] The method provided by the present application obtains the memory bypass identifier corresponding to the first storage space when receiving a data processing request from an application to the first storage space in the memory. Since the memory bypass identifier is used to indicate the storage mode of using the cache set according to the access requirements of the application to the first storage space, when the associated data of the first storage space is processed according to the obtained memory bypass identifier, the storage mode of using the cache for the associated data can be determined according to the access requirements of the application to the first storage space, thereby controlling the cache behavior based on the access requirements of the application and improving the cache hit rate. In addition, only when the memory bypass identifier corresponding to the first storage space is the first memory bypass identifier, the processor will copy the associated data of the first storage space to the cache, thereby avoiding frequent copying of data from the first storage medium to the cache and reducing the memory bandwidth consumption of the first storage medium.

[0128] In another possible implementation, the operating system can also add a memory bypass identifier to the corresponding bypass identifier field based on the predicted access requirements of the application program to the first storage space. Figure 8 The flowchart of another data processing method provided by the present application is shown in FIG. 1 , and the method is applied to an electronic device, wherein the electronic device includes a first storage medium and a second storage medium, the first storage medium is a memory of the electronic device, and the second storage medium is a cache of the memory. Figure 8 As shown, the method includes the following steps 801 to 807.

[0129] Step 801: An operating system in an electronic device sets a bypass identification field in a page table entry in a first storage medium.

[0130] In a possible implementation, when the operating system in the electronic device starts to run, a bypass identification field is set in a page table entry in a page table of the first storage medium and a processor is triggered to set a bypass identification field in a TLB table entry in the TLB.

[0131] Or, if Fig. 9 In the schematic diagram of another method of setting a memory bypass attribute provided by the present application, an operating system (such as a memory management module in the kernel of the operating system) sets a bypass identification field in a page table entry in a page table of a first storage medium based on a prediction network to add a memory bypass attribute in the operating system. Afterwards, a processor (such as a core of a processor) also synchronizes the bypass identification field from the page table of the operating system to the TLB option of the TLB to add a memory bypass attribute in the processor.

[0132] The prediction network is used to predict the access requirements of the application to each storage space of the first storage medium. The prediction network is an artificial intelligence (AI) model, and the AI ​​model includes a machine learning model, a deep learning model, or a reinforcement learning model, for example, the prediction network is a convolutional neural network or a decision tree.

[0133] like Figure 3 As shown, the server completes the training of the prediction network so that the prediction network has the ability to predict the access requirements of the application to each storage space of the first storage medium, and then the electronic device obtains the prediction network from the server. Alternatively, the electronic device completes the training of the prediction network, thereby obtaining the trained prediction network. The server is a local server or a cloud server, and the embodiment of the present application does not limit the type of the server.

[0134] Then Figure 3 and Fig. 9 For example, when the electronic device obtains the predicted network, it triggers the operating system (such as the memory management module in the operating system) to set the bypass identification field for the page table entry in the page table of the first storage medium, thereby adding a new memory bypass attribute in the page table. In addition, the processor adds a new memory bypass attribute (refer to the relevant introduction in the previous text).

[0135] For this implementation, the user does not need to modify the application code, and the operating system does not need to provide the first API. As long as the predicted network can be obtained, the bypass identification field can be set for the page table entry in the page table of the first storage medium, and the operation is simple.

[0136] In addition, this step 801 is an optional step. In some embodiments, if the bypass identification field has been set in the page table, the operating system does not need to execute this step 801. And this step 801 can be executed once without being executed multiple times.

[0137] Step 802: The operating system obtains a data transmission attribute of at least one of the first storage medium and the second storage medium, where the data transmission attribute is used to indicate the impact of the storage medium on the efficiency of transmitting data.

[0138] Among them, the data transmission attribute includes at least one of the memory bottleneck (Mem bound) of the processor, the data read and write delay of the processor, the read bandwidth of the first storage medium, the write bandwidth of the first storage medium, the read bandwidth of the second storage medium, the write bandwidth of the second storage medium and the write-back ratio of the second storage medium.

[0139] The memory bottleneck is the memory bandwidth between the processor and caches and memories at all levels. The data read and write latency is the latency (such as average latency) when the processor reads and writes data in caches and memories at all levels. The read bandwidth of the first storage medium is the bandwidth occupied by the processor when reading data from the first storage medium. The write bandwidth of the first storage medium is the bandwidth occupied by the processor when writing data to the first storage medium. The read bandwidth of the second storage medium is the bandwidth occupied by the processor when reading data from the second storage medium. The write bandwidth of the second storage medium is the bandwidth occupied by the processor when writing data to the second storage medium. The write-back ratio of the second storage medium is the proportion of data written back to the first storage medium in the eliminated data of the second storage medium.

[0140] When the processor runs the operating system, the data transmission properties of the at least one storage medium are collected at intervals of the second time period, so as to periodically obtain the data transmission properties of the at least one storage medium, thereby reducing the occupation of processor resources. The length of the second time period can be set according to the specific implementation scenario. Here, the embodiment of the present application does not limit the length of the second time period.

[0141] For example, every time after a second time period, the operating system samples at least one of the memory bottleneck of the processor, the data read and write delay of the processor, the read bandwidth of the first storage medium, the write bandwidth of the first storage medium, the read bandwidth of the second storage medium, the write bandwidth of the second storage medium, and the write-back ratio of the second storage medium in the second time period to obtain the data transmission attribute.

[0142] Step 803: The operating system predicts the application's need to access the first storage space based on a data transmission attribute of at least one of the first storage medium and the second storage medium.

[0143] In a possible implementation, the operating system inputs the data transmission attribute into a prediction network, and through the prediction network, based on the input data transmission attribute, predicts the application's access requirements to the first storage space.

[0144] by Fig.10 For example, Fig.10This is a schematic diagram of predicting the access requirements of an application to a storage space provided by the present application. When the operating system is running, the operating system obtains the data transmission attributes of at least one of the first storage medium and the second storage medium based on sampling: the memory bottleneck of the processor and the data read and write latency; the read bandwidth, write bandwidth and write-back ratio of the second storage medium; the read bandwidth and write bandwidth of the first storage medium. The operating system inputs the data transmission attribute into the prediction network, and the prediction network predicts the access requirements of the first application to at least one storage space in the first storage medium based on the input data transmission attribute, and outputs at least one prediction result. Among them, the at least one prediction result corresponds to the at least one storage space one by one, and the prediction result is used to indicate the predicted access requirements of the application to a single storage space. The single storage space is a page frame in the first storage medium. The prediction result corresponding to the page frame to which the first storage space belongs is also the predicted access requirement of the application to the first storage space.

[0145] There are two possible situations for the predicted application's access requirements to a single storage space (e.g., a single page): the number of times the application needs to access the storage space is less than the target number of times in the first time period after the current time; and the application needs to access the storage space at least the target number of times in the first time period. For ease of description, these two situations are respectively referred to as the application not having an access requirement to the storage space and the application having an access requirement to the storage space.

[0146] Then Figure 4 and Fig. 9 Taking the above steps 802 and 803 as an example, the operating system (such as a feature collection module in the operating system) collects the data transmission attribute once every second time period, and inputs the collected data transmission attribute into the prediction network, and the prediction network predicts the access requirement of the first application to at least one storage space in the first storage medium based on the input data transmission attribute.

[0147] Step 804: The operating system sets the memory bypass flag for the first storage space according to the predicted access demand.

[0148] In one possible implementation, the operating system queries the page table entry corresponding to the first storage space according to the predicted application's access requirements to the first storage space and the physical address of the first storage space, and then adds a memory bypass identifier corresponding to the first storage space in the page table entry.

[0149] For example, if the prediction network predicts the application's access requirements to page frames in units of page frames, at least one prediction result output by the prediction network corresponds to the page frame number of at least one page frame. For any page frame number corresponding to any prediction result, the operating system queries the page table entry including the page frame number in the page table (or TLB).

[0150] Taking the first storage space as any page frame in the first storage medium as an example, the physical address of the first storage space is the page frame number of the any page frame, and the operating system queries the page table entry including the page frame number in the page table (or TLB). Afterwards, if the prediction result corresponding to the page frame to which the first storage space belongs indicates that the application has an access requirement to the corresponding storage space, the operating system adds a first memory bypass identifier to the queried page table entry. If the prediction result indicates that the storage space corresponding to the application does not have an access requirement, the operating system adds a second memory bypass identifier to the queried page table entry.

[0151] Step 805: The processor obtains a data processing request from the application program, where the data processing request is used to instruct the processor to process the associated data in the first storage space in the first storage medium.

[0152] Among them, this step 805 is the same as step 303, and here, the embodiment of the present application will not repeat this step 805.

[0153] Step 806: The processor obtains a memory bypass identifier corresponding to the first storage space according to the data processing request, where the memory bypass identifier is used to indicate a storage mode of using the second storage medium that is set according to the application's access requirement to the first storage space.

[0154] Among them, this step 806 is the same as step 304, and here, the embodiment of the present application will not repeat this step 806.

[0155] Step 807: The processor executes processing of the associated data according to the memory bypass identifier.

[0156] Among them, this step 807 is the same as step 305, and here, the embodiment of the present application will not repeat this step 807.

[0157] The method provided in the embodiment of the present application obtains the memory bypass identifier corresponding to the first storage space when receiving a data processing request from an application to the first storage space in the memory. Since the memory bypass identifier is used to indicate the storage mode of using the cache set according to the access requirements of the application to the first storage space, when the associated data of the first storage space is processed according to the obtained memory bypass identifier, the storage mode of using the cache for the associated data can be determined according to the access requirements of the application to the first storage space, thereby controlling the cache behavior based on the access requirements of the application and improving the cache hit rate. In addition, the access requirements of the application to the first storage space are predicted through the current data transmission attributes of at least one storage medium, avoiding recording the access requirements of the application to the first storage space in the application, and also meeting the real-time access requirements of the application to the storage space of the memory, thereby controlling the cache behavior in real time by predicting the memory bypass identifier set according to the access requirements of the application to the first storage space.

[0158] The above steps 302 and 804 are both processes in which the operating system sets a memory bypass identification process for the first storage space according to the application's access requirements for the first storage space, so that the processor can perceive the application's access memory characteristics through the memory bypass identification corresponding to each storage space in the set first storage medium, thereby overcoming the problem that the processor cannot perceive the application's access memory characteristics, so that when the processor accesses the storage space in the memory, it can determine whether to copy the data in the storage space to the cache according to the memory bypass identification, thereby realizing the control of the cache behavior based on the application's access requirements, so that the processor can later obtain the data required by the application in the cache, thereby improving the cache hit rate.

[0159] In addition, in order to reflect the interactive process within the electronic device, step 301 of the present application is executed by the application, and step 302 and step 801 to step 804 are introduced with the operating system as the execution body. It should be understood that these steps should be implemented by hardware (such as a processor) running the application or operating system.

[0160] The above method embodiment is illustrated by taking the bypass identification field as an example for storing the memory bypass identification of a single cache. In another possible implementation, the bypass identification field includes multiple indicator bits, which may be reserved bits in the page table entry or bits extended by the page table entry. The multiple indicator bits correspond one-to-one to the caches of multiple levels of the first storage medium (i.e., multiple second storage media), and each indicator bit is used to store the memory bypass identification of the corresponding cache. Taking the page table shown in Table 3 as an example, the bypass identification field has M indicator bits, and the M indicator bits correspond one-to-one to the M caches of the levels L1-LM, where M is a positive integer.

[0161] Table 3

[0162]

[0163] At this time, the memory bypass indicator indicates the storage mode of using the corresponding cache according to the access requirement of the application to the storage space in the first storage medium. Figure 2 For example, at this time, M=4, the first storage medium is memory, and the caches of levels L1-L4 correspond to the 4 identification bits of the bypass identification field respectively, or the first storage medium is the cache of level L1, and the second storage medium is the cache of level L2. It can be understood that the second storage medium is the cache of the first storage medium.

[0164] In this case, the processor may query multiple memory bypass identifiers when querying the memory bypass identifier corresponding to the first storage medium. In this case, step 305 is described as follows:

[0165] For any memory bypass identifier among the multiple memory bypass identifiers, the cache corresponding to the indicator bit where the memory bypass identifier is located in the bypass identifier field is the second storage medium.

[0166] After obtaining the physical address of a storage space in the memory to be accessed, the processor queries the cache line including the data in the first storage space in the second storage medium based on the physical address. If the cache line is found to exist in the second storage medium, the processor accesses the cache space corresponding to the first storage space in the cache line based on the data processing request. If the cache line corresponding to the first storage space does not exist in the second storage medium, and the first storage medium is a cache, the processor queries the cache line including the data in the first storage space in the first storage medium based on the physical address. If the cache line is found to exist in the first storage medium, the processor accesses the cache line corresponding to the first storage space in the first storage medium based on the data processing request. If any memory bypass identifier is the first memory bypass identifier, the processor copies the data in the first storage space in the cache line to the second storage medium. If any memory bypass identifier is the second memory bypass identifier, the processor does not perform the step of copying the data in the first storage space in the cache line to the second storage medium. If it is found that the cache line does not exist in the first storage medium, the processor continues to query the data in the first storage space in the next level cache of the first storage medium based on the physical address, until the target storage space storing the data in the first storage space is queried in the cache or memory of a level smaller than the first storage medium, and the processor accesses the target storage space based on the data processing request. If any memory bypass identifier is a first memory bypass identifier, the processor copies the data in the target storage space to the second storage medium and the cache of a level smaller than the second storage medium. If any memory bypass identifier is a second memory bypass identifier, the processor does not execute the step of copying the data in the target storage space to the second storage medium and the cache of a level smaller than the second storage medium.

[0167] The data processing method provided by the present application is introduced above. Next, the device, chip and electronic device provided by the present application are further introduced in conjunction with the accompanying drawings. It should be understood that the device, chip and electronic device introduced below can implement any function of the electronic device or part of the electronic device in any of the above methods.

[0168] See also Fig.11 , the present application provides a structural schematic diagram of a data processing device, Fig.11 The device 1100 shown can be an electronic device or a part of an electronic device in the previous embodiments, and is used to execute the data processing method executed by the electronic device. The device 1100 includes a first storage medium 1101, a second storage medium 1102, a first acquisition unit 1103, a second acquisition unit 1104 and an execution unit 1105.

[0169] A first acquisition unit 1103 is used to acquire a data processing request of an application, wherein the data processing request is used to instruct to process the associated data of the first storage space in the first storage medium 1101, wherein the first storage medium 1101 is a memory of the electronic device, and the second storage medium 1102 is a cache of the memory;

[0170] A second acquisition unit 1104 is used to acquire a memory bypass identifier corresponding to the first storage space according to the data processing request, wherein the memory bypass identifier is used to indicate a storage mode of using the second storage medium 1102 set according to the access requirement of the application to the first storage space;

[0171] The execution unit 1105 is used to execute the processing of the associated data according to the memory bypass identifier.

[0172] It should be understood that the device 1100 of the embodiment of the present application can be implemented by a CPU, an application-specific integrated circuit (ASIC), or a programmable logic device (PLD), and the PLD can be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), a data processing unit (DPU), a system on chip (SoC), or any combination thereof. The device 1100 can also be implemented by software. Figures 3 to 10 When the data processing method shown is implemented by software, the device 1100 and its various modules may also be software modules.

[0173] In a possible implementation, the second storage medium 1102 is a high bandwidth memory HBM, and the HBM is used in a cache mode, where the cache mode is used to indicate that the HBM is used as a cache of the memory.

[0174] In a possible implementation, the apparatus 1100 further includes:

[0175] A calling unit, used to call a first application programming interface API in the operating system, and set a bypass identification field in a page table entry of the page table of the first storage medium 1101, wherein the bypass identification field is used to store the memory bypass identification;

[0176] An adding unit is used to add the memory bypass identifier in the bypass identifier field in the page table entry corresponding to the first storage space according to the access requirement recorded in the application.

[0177] In a possible implementation, the calling unit is used to:

[0178] When the application program applies to the operating system for allocation of storage space in the first storage medium 1101 or after the application for allocation of the storage space is completed, the first API is called to set the bypass identification field in the page table entry of the page table.

[0179] In a possible implementation, the calling unit is used to:

[0180] In the process of compiling the application program by a compiler, the first API is called through a second API or a preamble provided by the compiler, and the bypass identification field is set in a page table entry of the page table.

[0181] In a possible implementation, the adding unit is used to:

[0182] According to the access requirement recorded in the application program, querying a page table entry corresponding to the first storage space according to a virtual address of the first storage space;

[0183] The memory bypass identifier is added to the page table entry.

[0184] In a possible implementation, the apparatus 1100 further includes:

[0185] a prediction unit, configured to predict the access requirement of the application to the first storage space based on a data transmission attribute of at least one storage medium of the first storage medium 1101 and the second storage medium 1102, wherein the data transmission attribute is used to indicate the influence of the storage medium on the efficiency of transmitting data;

[0186] A setting unit is used to set the memory bypass flag for the first storage space according to the predicted access demand.

[0187] In a possible implementation manner, the prediction unit is used to:

[0188] The data transmission attribute is input into a prediction network, and the prediction network predicts the access requirement of the application program to the first storage space based on the input data transmission attribute.

[0189] In a possible implementation manner, the setting unit is used to:

[0190] According to the predicted access demand, querying a page table entry corresponding to the first storage space according to the physical address of the first storage space;

[0191] The memory bypass identifier is added to the page table entry.

[0192] In a possible implementation, the data processing request includes a virtual address of the first storage space, and the second obtaining unit 1104 is used to:

[0193] According to the virtual address, query the page table entry corresponding to the first storage space;

[0194] The memory bypass identifier is obtained in the page table entry.

[0195] In a possible implementation, the second acquiring unit 1104 is further configured to:

[0196] According to the virtual address, in the page table of the first storage medium 1101, query the page table entry corresponding to the first storage space; or,

[0197] According to the virtual address, a page table entry corresponding to the first storage space is queried in a translation lookaside buffer TLB of a processor.

[0198] In a possible implementation, the execution unit 1105 is used to:

[0199] If the memory bypass flag indicates that the second storage medium 1102 is used to store the data in the first storage medium 1101, the associated data in the first storage space is processed, and the associated data in the first storage space is copied to the second storage medium 1102;

[0200] If the memory bypass identifier indicates that the second storage medium 1102 is not used to store the data in the first storage medium 1101, the associated data of the first storage space is processed, and the step of copying the associated data in the first storage space to the second storage medium 1101 is not performed.

[0201] It should be understood that device 1100 corresponds to the electronic device in the above-mentioned method embodiment, and the various modules in device 1100 and the above-mentioned other operations and / or functions are respectively for implementing the various steps and methods implemented by the electronic device in the method embodiment. The specific details can be found in the above-mentioned method embodiment. For the sake of brevity, they will not be repeated here.

[0202] It should be understood that when the device 1100 performs data processing, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device 1100 is divided into different functional modules to complete all or part of the functions described above. In addition, the device 1100 provided in the above embodiment and the above method embodiment belong to the same concept, and the specific implementation process is detailed in the above method embodiment, which will not be repeated here.

[0203] It should be understood that the apparatus 1100 may be equivalent to the data processing system 100 (or 200), or equivalent to an execution component in the data processing system 100 (or 200).

[0204] Fig.12 is a schematic diagram of the structure of a chip provided by this application, such as Fig.12 As shown, the chip 1200 includes a processor 1201 and an interface circuit 1202, wherein the interface circuit 1202 is used to receive instructions and transmit them to the processor 1201. The processor 1201, for example, may be Fig.11 A specific implementation form of the device 1100 shown can be used to execute the above-mentioned data processing method applied to electronic devices. The processor 1201 is coupled to the memory 1203, and the memory 1203 is used to store program codes. When the program codes are executed by the processor 1201, the chip system composed of the processor 1201, the interface circuit 1202 and the memory 1203 implements the above-mentioned Figures 3 to 10 The operating steps of the method in any one of the method embodiments. Figure 7 For example, the processor 1201 reads the program code of the compiler from the memory 1203, compiles the application by running the program code of the compiler, and calls the second API or introduction of the compiler to add a bypass identification field in the page table. Subsequently, the processor 1201 implements the above-mentioned data processing method based on the added bypass identification field in the page table during the process of running the application.

[0205] Optionally, there is at least one processor 1201 in the chip system. It should be understood that in the embodiment of the present application, the processor 1201 may be a CPU or other general-purpose processor. The processor 1201 may also be one or more integrated circuits for implementing the solution of the present application, such as a digital signal processor (DSP), ASIC, PLD, FPGA or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0206] Optionally, the memory 1203 in the chip system may be one or more. The memory 1203 may be integrated with the processor 1201, or may be separated from the processor 1201, which is not limited in the present application. For example, the memory 1203 may be integrated with the processor 1201 on the same chip, such as Fig.12 As shown, the memory 1203 and the processor 1201 may also be arranged on different chips respectively. The present application does not specifically limit the type of the memory 1203 and the arrangement of the memory 1203 and the processor 1201.

[0207] Among them, the memory 1203 may include a read-only memory and a random access memory, and provide instructions and data to the processor 1201. The memory 1203 may also include a non-volatile random access memory. For example, the memory 1203 may also store information about the device type. The memory 1203 may also be a volatile memory, or may include both volatile and non-volatile memories.

[0208] Among them, the non-volatile memory can be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable programmable read-only memory (EEPROM) or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous connection dynamic random access memory (SLDRAM) and direct memory bus random access memory (DR RAM).

[0209] Exemplarily, the chip system can be an FPGA, an ASIC, a SoC, a CPU, a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a PLD or other integrated chips.

[0210] Fig.13 1300 is a schematic diagram of the structure of an electronic device provided by the present application. As shown in the figure, the electronic device 1300 includes a processor 1301, a memory 1302, a communication interface 1303, a bus 1304 and a storage device 1305. Among them, the processor 1301, the memory 1302, the communication interface 1303, and the storage device 1305 communicate through the bus 1304, and can also communicate through other means such as wireless transmission. The memory 1302 is used to store instructions, and the processor 1301 is used to execute the instructions stored in the memory 1302. The memory 1302 stores program code, and the processor 1301 can call the program code stored in the memory 1302 to execute the above-mentioned data processing method (such as the above-mentioned Figures 3 to 10 ) steps provided.

[0211] Exemplarily, the processor 1301 may include one or more CPUs, such as Fig.13 CPU0 and CPU1 are shown in the figure.

[0212] Exemplarily, the electronic device 1300 may include multiple processors, such as Fig.13 1 and 1306. Each of these processors may be a single-CPU or a multi-CPU. A processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0213] It should be understood that in this application, the processor 1301 and Fig.12 The processor 1201 in the embodiment is implemented in a similar manner, and the memory 1302 and Fig.12 The implementation method of the memory 1203 in is similar, and here, the implementation method of the processor 1301 and the memory 1302 is not repeated in detail in the embodiment of the present application.

[0214] The communication interface 1303 uses any transceiver-like device for communicating with other devices or communication networks. The communication interface 1304 includes a wired communication interface and may also include a wireless communication interface. Among them, the wired communication interface may be, for example, an Ethernet interface. The Ethernet interface may be an optical interface, an electrical interface, or a combination thereof. The wireless communication interface may be a wireless local area network (WLAN) interface, a cellular network communication interface, or a combination thereof, etc.

[0215] The bus 1304 is used to transmit information between the above components. In addition to the communication bus, the bus 1304 may also include a power bus and a status signal bus. However, for the sake of clarity, various buses are marked as bus 1304 in the figure. Among them, the communication bus can be divided into an address bus, a data bus, a control bus, etc. Exemplarily, the communication bus can be a Peripheral Component Interconnect Express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a computer express link (CXL) or a cache coherent interconnect for accelerators (CCIX), etc.

[0216] The storage device 1305 may be a ROM or other type of static storage device capable of storing static information and instructions, or a RAM or other type of dynamic storage device capable of storing information and instructions, or an EEPROM, a compact disc read-only memory (CD-ROM) or other optical disc storage, an optical disc storage (including a compressed optical disc, a laser disc, an optical disc, a digital versatile disc, a Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium capable of carrying or storing the desired program code in the form of an instruction or data structure and capable of being accessed by the processor 1301, and the storage device includes at least one memory 1302, but is not limited thereto. The storage device 1305 may exist independently and be connected to the processor 1301 via the bus 1304. The storage device 1305 may also be integrated with the processor 1301.

[0217] Exemplarily, the memory 1302 and the storage device 1305 may be the first storage medium or the second storage medium in the electronic device 1300, and at least one of the memory 1302 and the storage device 1305 may store a program code for implementing the data processing method of the present application. The processor 1301 enables the electronic device 1300 to implement the data processing method of the present application by reading and running the program code.

[0218] In some embodiments, the electronic device 1300 may further include an output device 1307 and an input device 1308. The output device 1307 communicates with the processor 1301 and may display information in a variety of ways. For example, the output device 1307 may be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. The input device 1308 communicates with the processor 1301 and may receive user input in a variety of ways. For example, the input device 1308 may be a mouse, a keyboard, a touch screen device, or a sensor device.

[0219] It should be understood that the device 1100 for implementing data processing according to the present application may correspond to the electronic device 1300 in the embodiment of the present application, and may correspond to the corresponding subject in executing the data processing method according to the embodiment of the present application, and the above and other operations and / or functions of each module in the electronic device 1300 are respectively for implementing Figures 3 to 10 For the sake of brevity, the corresponding processes of each method in are not repeated here.

[0220] The present application also provides a computer-readable storage medium, such as a memory including a program code, and the program code can be executed by a processor in an electronic device (or chip) to complete the data processing method in the above embodiment. The implementation of the computer-readable storage medium can refer to Fig.12 Memory 1203 in.

[0221] The present application also provides a computer program product or a computer program, which includes a program code, and the program code is stored in a computer-readable storage medium. A processor of an electronic device reads the program code from the computer-readable storage medium, and the processor executes the program code, so that the processor executes the above-mentioned data processing method.

[0222] In addition, the present application also provides a device, which can specifically be a chip, component or module, and the device may include a connected processor and memory; wherein the memory is used to store computer execution instructions, and when the device is running, the processor can execute the computer execution instructions stored in the memory so that the chip executes the data processing method in the above-mentioned method embodiments.

[0223] Among them, the devices, equipment, computer-readable storage media, computer program products or chips provided in this application are all used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods provided above, and will not be repeated here.

[0224] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiment of the present application of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD) or a semiconductor medium. The semiconductor medium can be a solid state disk (SSD).

[0225] The above is only a specific implementation of the present application. Those skilled in the art may conceive of changes or substitutions based on the specific implementation provided by the present application, which should all be included in the protection scope of the present application.

Claims

1. A data processing method, characterized in that: The method is applicable to an electronic device, the electronic device includes a first storage medium and a second storage medium, the first storage medium is a memory of the electronic device, and the second storage medium is a cache of the memory, and the method includes: Obtaining a data processing request of an application, wherein the data processing request is used to instruct processing of associated data in a first storage space in the first storage medium; According to the data processing request, a memory bypass identifier corresponding to the first storage space is obtained, where the memory bypass identifier is used to indicate a storage mode of using the second storage medium, and the storage mode is set according to the access requirement of the application program to the first storage space; The associated data is processed according to the memory bypass identifier.

2. The method according to claim 1, characterized in that: The second storage medium is a high bandwidth memory HBM, and the usage mode of the HBM is a cache mode. The cache mode is used to indicate that the HBM is used as a cache of the memory.

3. The method according to claim 1 or 2, characterized in that: Before obtaining the memory bypass identifier corresponding to the first storage space according to the data processing request, the method further includes: Calling a first application programming interface API in the operating system, setting a bypass identification field in a page table entry of the first storage medium, wherein the bypass identification field is used to store the memory bypass identification; According to the access requirement recorded in the application, the memory bypass identifier is added to the bypass identifier field in the page table entry corresponding to the first storage space.

4. The method according to claim 3, characterized in that The calling of a first application programming interface API in the operating system and setting a bypass identification field in a page table entry of a page table of the first storage medium comprises: When the application program applies to the operating system for allocation of storage space in the first storage medium or after the application for allocation of the storage space is completed, the first API is called to set the bypass identification field in the page table entry of the page table.

5. The method according to claim 3, characterized in that: The calling of a first application programming interface API in the operating system and setting a bypass identification field in a page table entry of a page table of the first storage medium comprises: In the process of compiling the application program by a compiler, the first API is called through a second API or a preamble provided by the compiler, and the bypass identification field is set in a page table entry of the page table.

6. The method according to claim 3, characterized in that The adding the memory bypass identifier in the bypass identifier field in the page table entry corresponding to the first storage space according to the access requirement recorded in the application program includes: According to the access requirement recorded in the application program, querying a page table entry corresponding to the first storage space according to a virtual address of the first storage space; The memory bypass identifier is added to the page table entry.

7. The method according to claim 1 or 2, characterized in that: Before obtaining the memory bypass identifier corresponding to the first storage space according to the data processing request, the method further includes: predicting the access requirement of the application to the first storage space based on a data transmission attribute of at least one storage medium of the first storage medium and the second storage medium, wherein the data transmission attribute is used to indicate the influence of the storage medium on the efficiency of transmitting data; The memory bypass flag is set for the first storage space according to the predicted access demand.

8. The method according to claim 7, characterized in that The predicting the access requirement of the application to the first storage space based on the data transmission attribute of at least one storage medium in the first storage medium and the second storage includes: The data transmission attribute is input into a prediction network, and the prediction network predicts the access requirement of the application program to the first storage space based on the input data transmission attribute.

9. The method according to claim 7, characterized in that: The step of setting the memory bypass flag for the first storage space according to the predicted access requirement includes: According to the predicted access demand, querying a page table entry corresponding to the first storage space according to the physical address of the first storage space; The memory bypass identifier is added to the page table entry.

10. The method according to claim 1, 2, 4, 5, 6, 8 or 9, characterized in that The data processing request includes a virtual address of the first storage space, and acquiring a memory bypass identifier corresponding to the first storage space according to the data processing request includes: According to the virtual address, query the page table entry corresponding to the first storage space; The memory bypass identifier is obtained in the page table entry.

11. The method according to claim 10, characterized in that The querying, according to the virtual address, a page table entry corresponding to the first storage space comprises: According to the virtual address, querying a page table entry corresponding to the first storage space in a page table of the first storage medium; or, According to the virtual address, a page table entry corresponding to the first storage space is queried in a translation lookaside buffer TLB of a processor.

12. The method according to claim 1, 2, 4, 5, 6, 8, 9 or 11, characterized in that The processing of executing the associated data according to the memory bypass identifier includes: If the memory bypass flag indicates that the second storage medium is used to store the data in the first storage medium, the associated data in the first storage space is processed, and the associated data in the first storage space is copied to the second storage medium; If the memory bypass flag indicates that the second storage medium is not used to store the data in the first storage medium, the associated data in the first storage space is processed, and the step of copying the associated data in the first storage space to the second storage medium is not performed.

13. A data processing device, characterized in that: The device includes a first storage medium and a second storage medium, the first storage medium is a memory of the electronic device, and the second storage medium is a cache of the memory, and the device further includes: A first acquisition unit, configured to acquire a data processing request of an application, wherein the data processing request is used to instruct processing of associated data of a first storage space in the first storage medium; a second acquisition unit, configured to acquire, according to the data processing request, a memory bypass identifier corresponding to the first storage space, wherein the memory bypass identifier is used to indicate a storage mode of using the second storage medium, and the storage mode is set according to an access requirement of the application program to the first storage space; An execution unit is used to execute processing of the associated data according to the memory bypass identifier.

14. An electronic device, characterized in that: The electronic device comprises a processor, and the processor is used to execute at least one program code, so that the electronic device performs the data processing method according to any one of claims 1 to claim 12.

15. A computer-readable storage medium, characterized in that: At least one program code is stored in the storage medium, and the at least one program code is read by the processor to enable the electronic device to execute the data processing method according to any one of claims 1 to 12.

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