Data processing method, device, electronic device and computer-readable storage medium

Abstract

A data processing method, which relates to the field of chip technology. In the case of receiving a data processing request from an application program for the data in the first storage space in the memory, the memory bypass identifier corresponding to the first storage space is obtained. Since the memory bypass identifier is used to indicate the storage method of using the cache set according to the access requirements of the application program for the first storage space, when processing the associated data of the first storage space according to the obtained memory bypass identifier, it is possible to determine the storage method of using the cache for the associated data according to the access requirements of the application program for the first storage space, thereby realizing the control of the cache behavior based on the access requirements of the application program and improving the cache hit rate.

Description

[0001] This application is a divisional application. The application number of the original application is 202211060725.0, and the original application date is August 31, 2022. The entire content of the original application is incorporated herein by reference. Technical Field

[0002] This application relates to the field of chip technology, and particularly to a data processing method, apparatus, electronic device, and computer-readable storage medium. Background Art

[0003] In an electronic device, a processor (e.g., a central processing unit (CPU)) can generally access the storage spaces of the main memory and the cache. Among them, the main memory has a large capacity but a high access latency; the cache has a small space but a low access latency. The CPU usually copies some data from the main memory to the cache. When a processing request needs to access this data, the CPU can quickly obtain the data from the cache. The probability of hitting the data to be accessed by the processing request in the cache can also be referred to as the cache hit rate, and the cache hit rate affects the performance of the electronic device.

[0004] However, the processing requests often come from application programs running on the CPU. When an application program accesses the data in the cache through a processing request, there is a problem of low cache hit rate, resulting in poor performance of the electronic device. Therefore, there is an urgent need for a method to improve the performance of the electronic device. Summary of the Invention

[0005] This application provides a data processing method, apparatus, electronic device, and computer-readable storage medium, which can improve the cache hit rate.

[0006] In a first aspect, a data processing method is provided. This method is applicable to an electronic device, where the electronic device includes a first storage medium and a second storage medium. The first storage medium is the memory of the electronic device, and the second storage medium is the cache of the memory. The implementation process of this method includes: first obtaining a data processing request of an application program, then obtaining a memory bypass identifier corresponding to a first storage space according to the data processing request, and then performing processing on associated data according to the memory bypass identifier, where the data processing request is used to indicate processing of associated data in a first storage space in the first storage medium, and the memory bypass identifier is used to indicate a storage method of using the second storage medium set according to the access requirement of the application program for the first storage space.

[0007] In this method, when a data processing request from an application program for the data in the first storage space in the memory is received, the memory bypass identifier corresponding to the first storage space is obtained. Since the memory bypass identifier is used to indicate the storage method of using the cache set according to the access requirement of the application program for the first storage space, when processing the associated data of the first storage space according to the obtained memory bypass identifier, the storage method of using the cache for the associated data can be determined according to the access requirement of the application program for the first storage space, so as to control the cache behavior based on the access requirement of the application program and improve the cache hit rate.

[0008] In a possible implementation manner, the second storage medium is a high-bandwidth memory (HBM), and the usage mode of the HBM is the cache mode, and the cache mode is used to indicate that the HBM is used as the cache of the memory.

[0009] Based on the above possible implementation manner, in the application scenario where the HBM is the cache of the first storage medium, the memory bypass identifier is used to indicate the use of the HBM method for the storage space in the memory, and the cache behavior of the HBM is controlled based on the access requirement of the application program.

[0010] In another possible implementation manner, before obtaining the memory bypass identifier corresponding to the first storage space according to the data processing request, the implementation process of this method further includes: first calling the first application programming interface (API) in the operating system to set the bypass identifier field in the page table entry of the first storage medium, and then adding the memory bypass identifier to the bypass identifier field in the page table entry corresponding to the first storage space according to the access requirement recorded in the application program, where the bypass identifier field is used to store the memory bypass identifier.

[0011] Based on the above possible implementation manner, by calling the first API to set the bypass identifier field in the page table, a new memory bypass attribute is added to the page table, so that later, according to the access requirement of the application program for the storage space in the memory, the bypass identifier field can be added to the corresponding page table entry, enabling the processor to perceive the access memory characteristics of the application program through the memory bypass identifiers corresponding to each storage space in the set first storage medium. When the processor accesses the storage space in the memory, it can determine whether to copy the data in the storage space to the cache according to the memory bypass identifier, thus realizing the control of the cache behavior based on the access requirement of the application program, facilitating the processor to obtain the data required by the application program in the cache later and improving the cache hit rate.

[0012] In another possible implementation, the implementation of setting a bypass identification field in a page table entry of a first storage medium by invoking a first API in an operating system is as follows: when an application program applies to the operating system for allocating storage space in the first storage medium or after the application for allocating storage space is completed, the first API is invoked to set the bypass identification field in the page table entry of the page table.

[0013] Based on the above possible implementation, in the case where the application program applies to the operating system for allocating storage space in the first storage medium, only some codes of the application program need to be modified so that the application program can call the first API in the operating system through a processor, and then the bypass identification field can be set in the page table entry of the page, and the implementation is simple.

[0014] In another possible implementation, the implementation of setting a bypass identification field in a page table entry of a first storage medium by invoking a first application programming interface (API) in an operating system is as follows: during the process of compiling the application program by a compiler, the first API is invoked through a second API or a guiding statement provided by the compiler to set the bypass identification field in the page table entry of the page table.

[0015] Based on the above possible implementation, by modifying some codes of the application program and the compiler, the application program can call the first API in the operating system when being compiled by invoking a compilation interface in the compiler, so as to set the bypass identification field in the page table entry of the page, and the implementation is simple.

[0016] In another possible implementation, the implementation of adding a memory bypass identification to the bypass identification field in the page table entry corresponding to a first storage space according to the access requirements recorded in the application program includes: first, according to the access requirements recorded in the application program, query the page table entry corresponding to the first storage space according to the virtual address of the first storage space, and then add the memory bypass identification to the queried page table entry.

[0017] In another possible implementation, before obtaining the memory bypass identification corresponding to the first storage space according to a data processing request, the implementation process of this method further includes: predicting the access requirements of the application program for the first storage space based on the data transmission attributes of at least one of the first storage medium and the second storage medium, and then setting the memory bypass identification for the first storage space according to the predicted access requirements, where the data transmission attribute is used to indicate the influence of the storage medium on the efficiency of transmitting data.

[0018] Based on the above possible implementation methods, by using the current data transmission attributes of at least one storage medium, the access requirements of the application program for the first storage space are predicted, avoiding recording the access requirements of the application program for the first storage space in the application program, and also being able to meet the real-time access requirements of the application program for the memory storage space. Thus, by setting the memory bypass identifier based on the predicted access requirements of the application program for the first storage space, the cache behavior can be controlled in real time.

[0019] In another possible implementation method, the implementation process of predicting the access requirements of the application program for the first storage space based on the data transmission attributes of at least one of the first storage medium and the second storage medium includes: inputting the data transmission attributes into a prediction network, and through the prediction network, predicting the access requirements of the application program for the first storage space based on the input data transmission attributes.

[0020] Based on the above possible implementation methods, there is no need for the user to modify the code of the application program, and there is no need for the operating system to provide the first API. As long as the prediction network can be obtained, the bypass identifier field can be set for the page table entries in the page table of the first storage medium, and the operation is simple.

[0021] In another possible implementation method, the implementation method of setting the memory bypass identifier for the first storage space according to the predicted access requirements includes: first, according to the predicted access requirements, query the page table entry corresponding to the first storage space according to the physical address of the first storage space, and then add the memory bypass identifier to the queried page table entry.

[0022] In another possible implementation method, the data processing request includes the virtual address of the first storage space. On this basis, the implementation process of obtaining the memory bypass identifier corresponding to the first storage space according to the data processing request includes: querying the page table entry corresponding to the first storage space according to the virtual address of the first storage space, and then obtaining the memory bypass identifier from the queried page table entry.

[0023] In another possible implementation method, the implementation process of querying the page table entry corresponding to the first storage space according to the virtual address includes: querying the page table entry corresponding to the first storage space in the page table of the first storage medium according to the virtual address; or querying the page table entry corresponding to the first storage space in the translation lookaside buffer (TLB) of the processor according to the virtual address.

[0024] In another possible implementation, the implementation process of processing associated data according to the memory bypass flag includes the following two cases: If the memory bypass flag indicates to use the second storage medium to store the data in the first storage medium, process the associated data in the first storage space and copy the associated data in the first storage space to the second storage medium; If the memory bypass flag indicates not to use the second storage medium to store the data in the first storage medium, process the associated data in the first storage space and do not perform the step of copying the associated data in the first storage space to the second storage medium.

[0025] Based on the above possible implementation, according to the storage method using the cache indicated by the memory bypass flag, a copy of the data in the storage space in the memory is stored in the cache or not stored in the cache, thereby realizing the control of the cache behavior according to the memory bypass flag.

[0026] In a second aspect, a data processing device is provided, and the device includes various modules for executing the data processing method in the first aspect or any one of the possible implementation manners of the first aspect.

[0027] In a third aspect, an electronic device is provided, and the electronic device includes a processor, and the processor is used to execute program code so that the electronic device performs operations to implement the operations performed by the above data processing method.

[0028] In a fourth aspect, a chip is provided, and the chip is used to implement the operation steps of the data processing method in the first aspect or any one of the possible implementation manners of the first aspect.

[0029] In a fifth aspect, a processor is provided, and the processor is used to implement the operation steps of the data processing method in the first aspect or any one of the possible implementation manners of the first aspect.

[0030] In a sixth aspect, a computer-readable storage medium is provided, and at least one program code is stored in the storage medium, and the program code is read by the processor so that the electronic device performs the operations performed by the above data processing method.

[0031] In a seventh aspect, a computer program product or a computer program is provided, and the computer program product or the computer program includes program code, the program code is stored in a computer-readable storage medium, the processor of the electronic device reads the program code from the computer-readable storage medium, and the processor executes the program code so that the electronic device executes the method provided in the above first aspect or various alternative implementation manners of the first aspect.

[0032] Based on the implementation manners provided in the above aspects of the present application, further combinations can be made to provide more implementation manners. Description of the Drawings

[0033] Figure 1 It is a schematic structural diagram of a data processing system provided by this application;

[0034] Figure 2 It is a schematic structural diagram of another data processing system provided by this application;

[0035] Figure 3 It is a flowchart of a data processing method provided by this application;

[0036] Figure 4 It is a schematic diagram of a data processing system in an electronic device provided by this application;

[0037] Figure 5 It is a schematic diagram of setting a memory bypass attribute provided by this application;

[0038] Figure 6 It is an interaction schematic diagram of a data processing method provided by this application;

[0039] Figure 7 It is a schematic diagram of another setting of a memory bypass attribute provided by this application;

[0040] Figure 8 It is a flowchart of another data processing method provided by this application;

[0041] Figure 9 It is a schematic diagram of another setting of a memory bypass attribute provided by this application;

[0042] Figure 10 It is a schematic diagram of predicting the access requirement of an application program for a storage space provided by this application;

[0043] Figure 11 It is a schematic structural diagram of a data processing device provided by this application;

[0044] Figure 12 It is a schematic structural diagram of a chip provided by this application;

[0045] Figure 13 It is a schematic structural diagram of an electronic device provided by this application. Detailed implementation manners

[0046] For an electronic device including a first storage medium and a second storage medium, when the first storage medium is the memory of the electronic device and the second storage medium is the cache of the memory, the present application provides a data processing method. In this method, when an application requests to process associated data in a certain storage space of the first storage medium, first obtain the storage method of this storage space using the second storage medium, where the storage method is set according to the access requirements of the application for this storage space, and then perform the processing of the associated data according to the obtained storage method.

[0047] At this time, the usage mode of the second storage medium is the cache (Cache) mode, and the cache mode indicates that the second storage medium is used as the cache of the memory (i.e., the first storage medium). In a possible implementation manner, this method is executed by a processor (such as a CPU) in the electronic device. The following will be combined with the attached Figure 1 and 2 The system architecture composed of the processor, the first storage medium, and the second storage medium in the cache mode is introduced as follows.

[0048] Figure 1 is a schematic structural diagram of a data processing system provided by the present application, as Figure 1 shown, the data processing system 100 includes a first storage medium 101, a second storage medium 102, and a processor 103. Among them, the first storage medium 101 serves as the memory of the processor 103 and is used to store data (such as service data, program code, or computer instructions) to be processed by the processor 103. Figure 1 Taking the first storage medium 101 as a double data rate synchronous dynamic random access memory (doubledata Rate SDRAM, DDR) as an example, in some embodiments, the first storage medium 101 may also be a dynamic random access memory (dynamic random access memory, DRAM) or other types of main memory. Here, the present application embodiments do not limit the medium type of the first storage medium 101.

[0049] The second storage medium 102 is used as the cache of the memory. At this time, the usage mode of the second storage medium 102 is the Cache mode. Among them, Figure 1 Taking the second storage medium 102 as a high bandwidth memory (high bandwidth memory, HBM) as an example, in some embodiments, the second storage medium 102 is a static random access memory (static random-access memory, SRAM) or other types of caches. Here, the present application embodiments do not limit the medium type of the second storage medium 102.

[0050] For any one of the first storage medium 101 and the second storage medium 102, the storage medium includes a plurality of storage spaces for storing data. When the processor 103 (such as a CPU) runs an application program, the application program requests to process the associated data in the storage space of the first storage medium 101 (such as reading the data in the storage space or writing data to the storage space). According to the request of the application program, first query the associated data to be processed from the cache of the first storage medium 101. If the processor finds the associated data of the storage space in the cache, it is considered that a cache hit occurs; otherwise, it is considered that a cache miss occurs. If a cache hit occurs, the processor 103 processes the associated data in the cache. If a cache miss occurs, the associated data is processed in the first storage medium 101.

[0051] In some embodiments, the data processing system 100 includes a plurality of second storage media 102, and the plurality of second storage media 102 serve as multiple-level caches of the first storage medium 101. For example, Figure 2 As shown in the structural schematic diagram of another data processing system provided in the present application, the data processing system 200 includes a first storage medium 101, second storage media 102a to 102d, and a processor 103. According to the speed of reading and writing data, the second storage media 102a to 102d, the first storage medium 101 correspond to levels L1 to L5 one by one, where L1 > L2 > L3 > L4 > L4 > L5. Among them, the higher the level of the storage medium, the faster the speed of reading and writing data.

[0052] Such as Figure 2 As shown, the usage modes of the second storage media 102a to 102d are all Cache modes. Figure 2 Taking the caches at levels L1 to L3 as SRAM, the cache at level L4 as HBM, and the memory at level L5 as DDR as an example. In different implementation scenarios, the memory may also have less than 4 or more than 4 caches. Here, the embodiments of the present application do not limit the number of caches of the memory.

[0053] For any cache in the multi-level caches of the second storage media 102a to 102d, the cache is used to store a copy of part of the data stored in the next-level storage media. When the processor 103 obtains a request from an application to process the associated data in the storage space of the first storage media 101, the processor 103 preferentially searches in the higher-level caches in the order from the highest level to the lowest level to check if the associated data of the storage space is stored. For any cache, during the query process, the processor 103 processes the associated data in the cache. If a cache miss occurs, the processor 103 continues to search in the next-level storage media of the cache until the associated data of the storage space is found.

[0054] The above data processing system architecture can be deployed in an electronic device. Based on the above data processing system architecture, the following describes the process of the electronic device executing the data processing method in conjunction with the accompanying drawings:

[0055] When an application requests to process the associated data of a certain storage space in the first storage media, the storage method of the storage space obtained by the processor using the second storage media is indicated by a memory bypass flag. Then, the processor processes the associated data according to the memory bypass flag. To illustrate this process, refer to Figure 3 the flowchart of a data processing method provided in the present application as shown. The method is applied to an electronic device, where the electronic device includes a first storage media and a second storage media. The first storage media is the memory of the electronic device, and the second storage media is the cache of the memory. As Figure 3 shown, the method includes the following steps 301 to 305.

[0056] Step 301: The application calls the first application programming interface (API) in the operating system and sets a bypass flag field in the page table entry of the page table of the first storage media. The bypass flag field is used to store the memory bypass flag.

[0057] Among them, the memory bypass flag is used to indicate the storage method using the second storage media set according to the access requirements of the application for the storage space in the first storage media. The access requirements of the application for the storage space in the first storage media include the access requirements recorded in the application for the storage space in the first storage media or the predicted access requirements of the application for the storage space in the first storage media.

[0058] The memory bypass identifier includes a first memory bypass identifier or a second memory bypass identifier. The first memory bypass identifier is used to indicate storing data in the first storage medium using a second storage medium, and the second memory bypass identifier is used to indicate not storing data in the first storage medium using the second storage medium. Among them, the representation methods of the first memory bypass identifier and the second memory bypass identifier are different. For example, the first memory bypass identifier is 1 and the second memory bypass identifier is 0, or the first memory bypass identifier is 0 and the second memory bypass identifier is 1. Here, the embodiments of the present application do not limit the representation methods of the first memory bypass identifier and the second memory bypass identifier.

[0059] Taking Figure 4 the schematic diagram of a data processing system in an electronic device provided by the present application shown as an example, for a process running in the electronic device, the operating system (OS) manages the memory in units of pages and uses a page table to save the mapping relationship from the virtual address to the physical address of the first storage medium. The corresponding virtual address and physical address are used to indicate the same storage space in the memory. The virtual address includes the page number of the page where the storage space is located (i.e., the page number of the virtual address) and the offset address of the storage space in the page. The physical address includes the page frame number of the page frame where the storage space is located (i.e., the page number of the physical address).

[0060] Taking the page table shown in Table 1 as an example, the page table includes N + 1 page table entries, and each page table entry includes a page number and a page frame number to indicate that the page indicated by the page number is mapped to the page frame corresponding to the page frame number, where N is a positive integer.

[0061] Table 1

[0062]

[0063]

[0064] In the embodiments of the present application, the function of the page table entries in the page table is further extended. Taking the page table shown in Table 2 as an example, a bypass identifier field is extended in the page table entry, and this bypass identifier field is used to store the memory bypass identifier, so that the page table has the memory bypass attribute.

[0065] Table 2

[0066] Page table entry Page number Page frame number Bypass identification field Page table entry 0 0 0 Memory bypass identification Page table entry 1 1 1 Memory bypass identification … … … Memory bypass identification Page table entry N N N Memory bypass identification

[0067] Still taking Figure 4For example, the page table managed by the operating system is stored in the first storage medium. In addition, a processor of the electronic device (such as the core of the CPU) uses a translation lookaside buffer (TLB) as a cache for the page table. For example, at least one page table entry in the page table serves as a TLB entry, so that the TLB entry has a bypass identification field, and further the TLB has a memory bypass attribute.

[0068] The application program sets a bypass identification field for the page table entry of the page table in the first storage medium by calling a first API in the operating system, so as to add a memory bypass attribute to the page table. In a possible implementation manner, the first API is a user-defined API for setting the memory bypass attribute or an existing API extended with the function of setting the memory bypass attribute. Here, the embodiment of the present application does not limit the type of the first API.

[0069] In the case where the first API is an existing API extended with the function of setting the memory bypass attribute, the first API includes a memory mapping file function, a memory mapping protection function, and other types of functions. Here, the embodiment of the present application does not limit the function type of the first API.

[0070] Among them, the memory mapping file function is expressed as: void* mmap(void* addr, size_t length, int prot, int flags, int fd, off_t offset). In the memory mapping file function, addr refers to the hint during memory allocation; length indicates the length of the data in the file mapped to the memory; prot indicates the protection method for the mapped area of the file in the memory. In the embodiment of the present application, the port function is extended, and a bypass attribute setting identifier is added to the port. The bypass attribute setting identifier indicates to set a bypass identification field for the page table entry in the page table; Flags indicates various characteristics of the mapped area; fd is a file descriptor indicating the file mapped to the memory. offset is the offset of the file mapping.

[0071] The memory mapping protection function is expressed as: int mprotect(void* addr, size_t len, int prot). In the memory mapping file function, addr indicates the starting address of the protection attribute area to be modified in the memory; len is the length of the protection attribute area; prot indicates various attributes of the protection attribute area. In the embodiment of the present application, the port function is extended, and a bypass attribute setting identifier is added to the port. The bypass attribute setting identifier indicates to set a bypass identification field for the page table entry in the page table.

[0072] In a possible implementation, the application calls the first API in the operating system in any one of the following Method 1 or Method 2.

[0073] Method 1: When the application applies to the operating system for allocating storage space in the first storage medium or after the application finishes applying for allocating the storage space, the application calls the first API and sets the bypass identification field in the page table entry of the page table.

[0074] Among them, the application is any application installed in the electronic device. For Figure 4 example, when the application (application, APP) applies for storage space of memory, it calls the first API in the operating system to set the bypass identification field. Combining Figure 5 and Figure 6 introduce this process as follows:

[0075] Among them, Figure 5 is a schematic diagram of setting memory bypass attributes provided by this application, Figure 6 is an interaction schematic diagram of a data processing method provided by this application. As Figure 5 and Figure 6 shown, when the application starts, it sends a memory allocation request to the operating system (such as the memory management module in the kernel of the operating system). The memory allocation request is used to indicate allocating storage space in the first storage medium for the application, that is, applying for memory from the operating system. After receiving the memory allocation request, the operating system allocates storage space in the first storage medium for the application and returns a first virtual address segment to the application. The first virtual address segment corresponds to the physical address of at least one storage space allocated for the application. In addition, when the application sends a memory allocation request to the operating system, the memory allocation request triggers the call of the first API in the operating system. The application inputs a bypass attribute setting identifier to the first API. The operating system (such as the memory management module) sets the bypass identification field in the page table entry of the page table through the bypass attribute setting identifier input by the first API, thereby adding a memory bypass attribute to the page table. In this case, the first API may be a user-defined API or a memory mapping file function.

[0076] For after the application finishes applying to the operating system for allocating storage space, still taking Figure 5 as an example, if the application receives the first virtual address segment returned by the operating system based on the memory allocation request, the application calls the first API in the operating system, inputs a bypass attribute setting identifier to the first API, and the operating system sets the bypass identification field for the page table entry of the page table through the memory bypass identifier input by the first API. In this case, the first API may be a user-defined API or a memory mapping protection function.

[0077] When the application requests the operating system to allocate storage space in the first storage medium, by modifying part of the code of the application, the application can set the bypass identification field for the page table entry in the page by calling the first API in the operating system through the processor, which is simple to implement.

[0078] Method 2: The first API is encapsulated in the compilation interface of the compiler. During the compilation of the application by the compiler, the application calls the first API through the second API or leading statement in the compiler to set the bypass identification field for the page table entry of the page table.

[0079] Among them, the second API may be an API extended based on the existing API or a newly added API. Here, the embodiments of the present application do not limit the implementation manner of the second API.

[0080] Take Figure 4 as an example. When the application APP is compiled, it calls the first API in the operating system. The process is introduced as follows: Figure 7 For this process, the following is an introduction:

[0081] Among them, Figure 7 is another schematic diagram for setting the memory bypass attribute provided by the present application. As shown in Figure 7 , the first API is encapsulated in the second API or leading statement in the compiler. During the compilation of the application by the compiler, the application calls the second API or leading statement in the compiler, inputs the bypass attribute setting identifier to the second API or leading statement. When the second API or leading statement receives the bypass attribute setting identifier, it calls the first API in the operating system, inputs the bypass attribute setting identifier to the first API. The operating system (such as the memory management module in the kernel of the operating system) sets the bypass identification field for the page table entry in the page table through the bypass attribute setting identifier input by the first API, thereby adding the memory bypass attribute to the page table.

[0082] For this implementation manner, by modifying part of the code of the application and the compiler, the application can call the first API in the operating system during compilation by calling the compilation interface in the compiler, so as to set the bypass identification field for the page table entry in the page, which is simple to implement.

[0083] Still take Figures 5 - 7 as an example. After the operating system sets the bypass identification field for the page table entry in the page table, the processor (such as the core of the processor) also synchronizes the bypass identification field from the page table of the operating system to the TLB option of the TLB to set the bypass identification field for the TLB option, thereby adding the memory bypass attribute in the processor.

[0084] In another possible implementation, a target application is installed in the electronic device, and the target application is used to call the first API. For example, during the process of the processor in the electronic device running the target application, the target application calls the first API to set the bypass identification field for the page table entry of the page table, without the need for each application to call the first API interface.

[0085] This step 301 is an optional step. In some embodiments, if the bypass identification field has been set in the page table, the operating system does not need to execute this step 301. In other embodiments, the operating system has the function of actively setting the bypass identification field in the page table. For example, when the electronic device is powered on and the operating system is initialized, the operating system sets the bypass identification field in the page table. At this time, this step 301 does not need to be executed. And this step 301 only needs to be executed once and does not need to be executed multiple times.

[0086] Step 302: The operating system adds the memory bypass identification to the bypass identification field in the page table entry corresponding to the first storage space according to the access requirements of the application program recorded in the application program.

[0087] Wherein, the first storage space is any storage space in the first storage medium. In the embodiments of the present application, the data stored in the first storage space is called associated data, and the access requirement of the application program for the first storage space in the first storage space is the access requirement of the application program for the associated data. The access requirement of the application program for the associated data is, for example, that the application program needs to access the target number of times of the associated data at least within the first time period, or the associated data is the service data of the target service to be accessed by the application program within the first time period. Wherein, the first time period is a time period after the current moment, that is, a future time period. Here, the duration of the first time period is not limited in the embodiments of the present application.

[0088] In a possible implementation, if the first storage space has been allocated to the application program, the operating system adds a memory bypass identification to the page table entry according to the access requirement recorded in the application program. For example, the following steps 3021 to 3022.

[0089] Step 3021: The operating system queries the page table entry corresponding to the first storage space according to the access requirement recorded in the application program and in accordance with the virtual address of the first storage space.

[0090] For Figure 6 example, the application program requests the operating system to set a memory bypass identification for the first storage space according to the access requirement recorded by itself. Thus, when the operating system receives the request of the application program, it queries the page table entry corresponding to the first storage space according to the virtual address of the first storage space. For example, the following steps A1 to step A2.

[0091] Step A1: If the first storage space in the first storage medium has been allocated to an application, the application sends a bypass flag setting request to the operating system, and the bypass flag setting request indicates to set a memory bypass flag for the first storage space.

[0092] Wherein, the bypass flag setting request includes the virtual address where the associated data of the first storage space is located, or the bypass flag setting request includes the start address of the virtual address segment for which the memory bypass flag is to be set and the length of the virtual address segment, wherein the storage space indicated by the virtual address segment includes the first storage space, or the bypass flag setting request includes the virtual address segment.

[0093] As Figure 6 shown, when the application requests the operating system to allocate memory, the operating system (such as the memory management module in the kernel of the operating system) sets a bypass flag field for the page table entry of the page table. After the application requests the operating system to allocate the storage space of the first storage medium, the operating system (such as the memory management module) allocates at least one storage space in the first storage medium to the application, creates at least one page for the application, and the at least one page corresponds to the at least one storage space. Then, the operating system creates a page table for the application based on the at least one page and the at least one storage space, and the page table includes at least one page table entry, and each page table entry is used to store the page number of a page and the page frame number of the corresponding storage space. The operating system returns a first virtual address segment to the application based on the at least one page, and the first virtual address segment is used to indicate the at least one page. For example, the start address of the first virtual address segment is the start address of the first page in the at least one page, the end address of the first virtual address segment is the end address of the last page in the at least one page, and the length of the first virtual address segment is the length of the at least one page.

[0094] When the application receives the first virtual address segment, all relevant data used by the processor during the running of the application can be stored in the storage space corresponding to the first virtual address segment.

[0095] For at least one data to be accessed by the application, if the application records a demand identifier corresponding to any data, and the any data is stored at a certain virtual address in the first virtual address segment, then using the page frame corresponding to the page where the virtual address is located as the first storage space, and using the any data as the associated data of the first storage space, a bypass flag setting request including the virtual address is generated. Wherein, the demand identifier indicates the access demand of the application for the at least one data.

[0096] In some embodiments, if multiple data to be accessed by an application all correspond to requirement identifiers, the application uses the virtual addresses in the first virtual address segment for storing the multiple data as the virtual address segment for which a memory bypass identifier is to be set (i.e., the second virtual address segment), and generates a bypass identifier setting request including the second virtual address segment. Alternatively, if the virtual addresses in the second virtual address segment are consecutive virtual addresses, the bypass identifier setting request does not include the second virtual address segment, but includes the start address of the second virtual address segment and the length of the second virtual address segment.

[0097] In another possible implementation, the bypass identifier setting request further includes at least one of the memory bypass identifier of the second storage medium and the requirement identifier. Of course, the bypass identifier setting request may also not include the memory bypass identifier and the requirement identifier.

[0098] Step A2: The operating system receives the bypass identifier setting request, and based on the bypass identifier setting request, queries the page table entry corresponding to the first storage space according to the virtual address of the first storage space.

[0099] After the operating system receives the bypass identifier setting request, if the bypass identifier setting request includes the virtual address of the first storage space, the operating system obtains the page number in the virtual address, and the page number indicates the page where the first storage space is located. Then, the operating system queries the page table entry including the page number in the page table.

[0100] If the bypass identifier setting request includes the second virtual address field, the operating system determines the page numbers of the respective pages corresponding to the second virtual address field, achieving address page alignment. For ease of description, the respective pages corresponding to the second virtual address field are referred to as the first pages. Alternatively, if the bypass identifier setting request includes the start address and the length of the second virtual address field, the operating system determines the page indicated by the start address based on the start address, and based on the length of the second virtual address field, determines the page indicated by the start address and the target number of pages after that page as the first pages, where if the multiple of the length of the second virtual address field and the length of a single page is an integer, the target number is equal to the multiple, and if the multiple is not an integer, the target number is 1 greater than the multiple.

[0101] After determining the respective first pages corresponding to the second virtual address segment, for any first page, the operating system queries the page table entry including the page number of the first page in the page table. Among them, if the first page is the page where the first storage space is located, the operating system querying the page table entry including the page number of the first page in the page table is also querying the page table entry corresponding to the first storage space.

[0102] Step 3022: The operating system adds a memory bypass flag to the page table entry corresponding to the first storage space in the page table.

[0103] For any first page, if any page table entry in the page table includes the page number of the first page, the operating system adds a first memory bypass flag to the bypass flag field of the any page table entry. For example, the following cases 1 and 2.

[0104] Case 1: When creating the page table, the operating system adds a second memory bypass flag to the bypass flag field of each page table entry in the page table. If any page table entry in the page table includes the page number of the first page, the second memory bypass flag in the bypass flag field of the any page table entry is modified to the first memory bypass flag.

[0105] Case 2: When creating the page table, the operating system does not add any content to the bypass flag field of each page table entry in the page table, making the bypass flag field empty. If any page table entry in the page table includes the page number of the first page, the operating system adds the first memory bypass flag to the bypass flag field of the any page table entry.

[0106] Within the first time period after the current time, the application may also access some storage spaces in the first storage medium less than the target number of times. The operating system sets a second memory bypass flag for the pages where these storage spaces are located (i.e., the second pages). It can be understood that the second pages are each page other than the first page among the at least one page created for the application. For case 1, the page table entries in the page table that have not been modified with the memory bypass flag are the page table entries corresponding to the second pages. Since the memory bypass flag in the page table entries corresponding to the second pages is the second memory bypass flag, the operating system does not need to set the second memory bypass flag for the page table entries corresponding to the second pages again. For case 2, since the bypass flag field of the page table entries corresponding to the second pages is empty, the operating system adds the second memory bypass flag to the bypass flag field of the page table entries corresponding to the second pages.

[0107] In another possible implementation, the application sends the bypass flag setting request to the operating system based on the first virtual address segment. At this time, the bypass flag setting request includes a second virtual address segment and a third virtual address segment. Among them, the second virtual address segment corresponds to a demand flag or the first memory bypass flag, and the third virtual address segment includes the virtual addresses in the first virtual address segment except the second virtual address segment. Then, the operating system adds the first memory bypass flag to the page table entries corresponding to each first page in the page table based on the second virtual address segment and the corresponding demand flag or the first memory bypass flag in the bypass flag setting request, determines the page number of the second page based on the third virtual address segment in the bypass flag setting request, and adds the second memory bypass flag to the page table entries in the page table that include the page number of the second page.

[0108] As shown Figure 6 in the figure, the operating system (such as the memory management module) adds a memory bypass flag to each page table entry in the page table. In addition, during the process of running the application program, the processor may continuously access the data in the storage space of the first storage medium. For a certain storage space in the first storage medium accessed by the processor during the current time period, the processor reads the page table entry corresponding to this storage space in the page table into the TLB as a TLB table entry. That is, when the processor (such as the core of the processor) updates the TLB table, it reads the page table entry including the memory bypass flag into the TLB. Correspondingly, the processor synchronizes the memory bypass flag in the page table stored in the first storage medium to the memory bypass flag field of the TLB table entry. Still taking Figure 3 as an example, the core of the processor adds the page table entries 0-K in the page table to the TLB to obtain the TLB table entries 0-K, and the TLB table entries 0-K all include the memory bypass flag.

[0109] Step 303: The processor obtains a data processing request of the application program, and this data processing request is used to indicate to process the associated data in the first storage space of the first storage medium.

[0110] Among them, the first storage space is the storage space in the first storage medium that includes the associated data, and this data processing request includes the virtual address of the first storage space. In a possible implementation manner, this data processing request is a data read request or a data write request. The data read request indicates to read the associated data in the first storage space, and the data write request indicates to write the associated data into the first storage space, and this data write request further includes the associated data.

[0111] During the process of running the application program by the processor, if there is a need to access the first storage space, the processor generates this data processing request. For example, during the process of running the application program, if the application program wants to write data to the first storage space, the data processing request generated by the processor is a data write request; if the application program wants to read the data in the first storage space, the data processing request generated by the processor is a data read request.

[0112] Step 304: The processor obtains the memory bypass flag corresponding to the first storage space according to this data processing request, and this memory bypass flag is used to indicate the storage method of using the second storage medium set according to the access requirement of the application program for the first storage space.

[0113] In a possible implementation, the processor queries the page table entry corresponding to the first storage space according to the virtual address in the data processing request, and obtains the memory bypass identifier of the first storage space from the queried page table entry (such as obtaining the memory bypass identifier from the memory bypass field of the page table entry).

[0114] For the process in which the processor queries the page table entry corresponding to the first storage space, the processor queries the page table entry corresponding to the first storage space in the TLB of the processor according to the virtual address, or queries the page table entry corresponding to the first storage space in the page table of the first storage medium according to the virtual address.

[0115] For example, the processor determines the page number and the offset within the page of the page where the first storage space is located based on the virtual address. Then, based on the page number of the page, it queries the TLB entry including the page number in the TLB. If the TLB entry including the page number is queried, the memory bypass identifier is obtained from the bypass identifier field of the TLB entry. If the TLB entry including the page number is not queried in the TLB, the processor reads the page table entry including the page number from the page table into the TLB, and then obtains the memory bypass identifier from the page table entry in the TLB. Alternatively, the processor first obtains the memory bypass identifier from the page table entry, and then reads the page table entry into the TLB.

[0116] Step 305: The processor processes the associated data according to the memory bypass identifier.

[0117] Among them, for different memory bypass identifiers, the processor processes the associated data in different ways. For example, if the memory bypass identifier indicates that the second storage medium is used to store the data in the first storage medium, the processor processes the associated data of the first storage space and copies the associated data in the first storage space to the second storage medium. If the memory bypass identifier indicates that the second storage medium is not used to store the data in the first storage medium, the processor processes the associated data of the first storage space and does not perform the step of copying the associated data in the first storage space to the second storage medium.

[0118] In addition, if the processor determines through querying the TLB that the data in the first storage space has been stored in the second storage medium, if a certain TLB entry is queried to include the page number of the page where the first storage space is located, it means that the data in the first storage space has been stored in the second storage medium, and then the associated data of the first storage space is processed by accessing the second storage medium; otherwise, the associated data of the first storage space is processed by accessing the first storage medium.

[0119] The following describes step 305 as follows according to the TLB entry or page table entry that is queried to include the page number:

[0120] If the memory bypass identifier is obtained from the TLB entry, the processor obtains the page frame number of the first storage space from the queried TLB entry, and splices the page frame number and the page offset in the virtual address of the first storage space to obtain the physical address of the first storage space. Based on this physical address, the processor queries the cache line including the data in the first storage space in the second storage medium, and accesses the cache space corresponding to the first storage space in the cache line based on the data processing request to process the associated data in the first storage space. For example, if the data processing request is a data read request, the processor reads the data from the cache space, and at this time, the read data is also the associated data of the first storage space. If the data processing request is a data write request, the processor writes the data write request carrying the associated data into the cache space.

[0121] At this time, if the associated data in the first storage space in the first storage medium has been stored in the second storage medium, the processor does not perform any operation on the data in the first storage space in the first storage medium based on the queried memory bypass identifier, and only processes the data write request.

[0122] If the processor obtains the memory bypass identifier from the page table entry in the page table, the processor obtains the page frame number of the first storage space from the queried page table entry, and splices the page frame number and the page offset in the virtual address of the first storage space to obtain the physical address of the first storage space. The processor accesses the first storage space indicated by the physical address in the first storage medium based on the data processing request to process the associated data in the first storage space. For example, if the data processing request is a data read request, the processor reads the data from the first storage space, and if the data processing request is a data write request, the processor writes the data write request carrying the associated data into the first storage space.

[0123] At this time, if the memory bypass identifier is the first memory bypass identifier, the processor copies the data (i.e., the associated data) in the first storage space to the cache line in the second storage medium. If the memory bypass identifier is the second memory bypass identifier, the processor does not perform the step of copying the data in the first storage space to the cache line in the second storage medium.

[0124] Take Figure 3 as an example, in Figure 3It is assumed that the first storage medium is DDR and the second storage medium is HBM. The processor (such as the core of the processor) queries the page table or TLB and adds a memory bypass identifier corresponding to the storage space to be accessed in the DDR to the data processing request of the APP, and sends the data processing request carrying the memory bypass identifier to the judgment module in the processor. Based on this memory bypass identifier, the judgment module determines whether it is necessary to copy the data in this storage space to the HBM. If it is necessary to copy the hot data in this storage space to the HBM, it means that the data in this storage space is hot data. Taking the data processing request as a data read request, after the judgment module reads the hot data from this storage space in the DDR, it copies the hot data to the HBM. After that, when the processor reads the hot data in this storage space again, it can directly read it from the HBM. If it is not necessary to copy the data in this storage space to the HBM, it means that the data in this storage space is cold data. Taking the data processing request as a data read request, after the processor reads the cold data from this storage space in the DDR, it does not copy the cold data to the HBM.

[0125] In a possible implementation, when the size of the first storage space is smaller than the size of the cache line in the second storage medium, if the data in the first storage space is copied to the cache line in the second storage medium, the processor also copies the data in other storage spaces in the first storage medium to this cache line to fill this cache line. In addition, when there are insufficient free cache lines in the second storage medium, the processor evicts the data in the non-free cache lines in the second memory from the second storage medium, so that the non-free cache lines become free cache lines. Then the processor copies the data in the first storage space and the data in other storage spaces in the first storage medium to this free cache line.

[0126] Next, in combination with Figure 6 The above steps 304 and 305 are introduced as follows: After receiving the data processing request of the application program, the core of the processor sends the data processing request to the core of the processor. The core of the processor queries the memory bypass identifier corresponding to the first storage space from the TLB or the page table according to the data processing request, adds the queried memory bypass identifier to the data processing request, and sends the data processing request carrying the memory bypass identifier to the uncore part of the processor. After that, the uncore part determines whether it is necessary to copy the associated data of the first storage space to the second storage medium according to the memory bypass identifier in the data processing request, and executes the relevant processing process. It can be understood that the uncore part includes Figure 4 the judgment module in

[0127] The method provided by this application, when receiving a data processing request from an application for the data in the first storage space in the memory, obtains the memory bypass identifier corresponding to the first storage space. Since the memory bypass identifier is used to indicate the storage method of using the cache set according to the access requirement of the application for the first storage space, when processing the associated data of the first storage space according to the obtained memory bypass identifier, it is possible to determine the storage method of using the cache for the associated data according to the access requirement of the application for the first storage space, thereby realizing the control of the cache behavior based on the access requirement of the application and improving the cache hit rate. In addition, when the memory bypass identifier corresponding to the first storage space is the first memory bypass identifier, the processor will copy the associated data of the first storage space to the cache, thus avoiding the frequent copying of data from the first storage medium to the cache and reducing the consumption of the memory bandwidth of the first storage medium.

[0128] In another possible implementation, the operating system can also add a memory bypass identifier to the corresponding bypass identifier field based on the predicted access requirement of the application for the first storage space. For example, Figure 8 As shown in the flowchart of another data processing method provided by this application, this method is applied to an electronic device. The electronic device includes a first storage medium and a second storage medium. The first storage medium is the memory of the electronic device, and the second storage medium is the cache of the memory. As Figure 8 shown, this method includes the following steps 801 to step 807.

[0129] Step 801: The operating system in the electronic device sets a bypass identifier field in the page table entry in the page table of the first storage medium.

[0130] In a possible implementation, when the operating system in the electronic device starts running, it sets a bypass identifier field in the page table entry in the page table of the first storage medium and triggers the processor to set a bypass identifier field in the TLB entry in the TLB.

[0131] Or, as Figure 9 shown in the schematic diagram of another method for setting the memory bypass attribute provided by this application, the operating system (such as the memory management module in the kernel of the operating system) sets a bypass identifier field in the page table entry in the page table of the first storage medium based on the prediction network to add a memory bypass attribute in the operating system. Then, the processor (such as the core of the processor) also synchronizes the bypass identifier field from the page table of the operating system to the TLB option of the TLB to add a memory bypass attribute in the processor.

[0132] Among them, the prediction network is used to predict the access requirements of the application program for each storage space of the first storage medium. The prediction network is an artificial intelligent (AI) model, and the AI model includes machine learning models, deep learning models, reinforcement learning models, etc. For example, the prediction network is a convolutional neural network or a decision tree, etc.

[0133] As Figure 3 shown, the server completes the training of the prediction network so that the prediction network has the ability to predict the access requirements of the application program for each storage space of the first storage medium. After that, the electronic device obtains the prediction network from the server. Alternatively, the electronic device completes the training of the prediction network to obtain the trained prediction network. Among them, the server is a local server or a cloud server. Here, the embodiments of the present application do not limit the type of the server.

[0134] Taking Figure 3 and Figure 9 as an example, when the electronic device obtains the prediction network, it triggers the operating system (such as the memory management module in the operating system) to set a bypass identification field for the page table entries in the page table of the first storage medium, so as to add a memory bypass attribute in the page table. In addition, the processor adds a memory bypass attribute (which can refer to the relevant introduction above).

[0135] For this implementation method, it is not necessary for the user to modify the code of the application program, and it is not necessary for the operating system to provide the first API. As long as the prediction network can be obtained and the bypass identification field can be set for the page table entries in the page table of the first storage medium, the operation is simple.

[0136] In addition, this step 801 is an optional step. In some embodiments, if the bypass identification field has been set in the page table, the operating system does not need to execute this step 801. And this step 801 only needs to be executed once and does not need to be executed multiple times.

[0137] Step 802, the operating system obtains the data transmission attributes of at least one of the first storage medium and the second storage medium, and the data transmission attributes are used to indicate the influence of the storage medium on the efficiency of the transmitted data.

[0138] Among them, the data transmission attributes include at least one of the memory bottleneck (Mem bound) of the processor, the data read / write latency of the processor, the read bandwidth of the first storage medium, the write bandwidth of the first storage medium, the read bandwidth of the second storage medium, the write bandwidth of the second storage medium, and the write-back ratio of the second storage medium.

[0139] The memory bottleneck is the memory bandwidth between the processor and each level of cache and memory. The data read / write latency is the latency (such as the average latency) when the processor reads and writes data in each level of cache and memory. The read bandwidth of the first storage medium is the bandwidth occupied when the processor reads data from the first storage medium. The write bandwidth of the first storage medium is the bandwidth occupied when the processor writes data to the first storage medium. The read bandwidth of the second storage medium is the bandwidth occupied when the processor reads data from the second storage medium. The write bandwidth of the second storage medium is the bandwidth occupied when the processor writes data to the second storage medium. The write-back ratio of the second storage medium is the proportion of the data that is written back to the first storage medium among the evicted data of the second storage medium.

[0140] When the processor runs the operating system, every second time period, the data transmission attributes of the at least one storage medium are collected, so as to periodically obtain the data transmission attributes of the at least one storage medium and reduce the occupation of processor resources. The duration of the second time period can be set according to the specific implementation scenario. Here, the embodiments of the present application do not limit the duration of the second time period.

[0141] For example, every time the second time period passes, the operating system samples at least one of the memory bottleneck of the processor, the data read / write latency of the processor, the read bandwidth of the first storage medium, the write bandwidth of the first storage medium, the read bandwidth of the second storage medium, the write bandwidth of the second storage medium, and the write-back ratio of the second storage medium in the second time period to obtain the data transmission attributes.

[0142] Step 803: The operating system predicts the access demand of the application program for the first storage space based on the data transmission attributes of at least one of the first storage medium and the second storage medium.

[0143] In a possible implementation manner, the operating system inputs the data transmission attributes into a prediction network, and through the prediction network, based on the input data transmission attributes, predicts the access demand of the application program for the first storage space.

[0144] Take Figure 10 as an example. Figure 10It is a schematic diagram for predicting the access requirements of an application program for storage space provided by this application. When the operating system is running, the operating system obtains the data transmission attributes of at least one of the first storage medium and the second storage medium based on sampling: the memory bottleneck of the processor and the data read / write latency; the read bandwidth, write bandwidth, and write-back ratio of the second storage medium; the read bandwidth and write bandwidth of the first storage medium. The operating system inputs the data transmission attributes into a prediction network, and the prediction network predicts the access requirements of the first application program for at least one storage space in the first storage medium based on the input data transmission attributes, and outputs at least one prediction result. Among them, the at least one prediction result corresponds one-to-one with the at least one storage space, and the prediction result is used to indicate the predicted access requirements of the application program for a single storage space. The single storage space is a page frame in the first storage medium. The prediction result corresponding to the page frame to which the first storage space belongs is also the predicted access requirements of the application program for the first storage space.

[0145] Among them, there are two possible situations for the predicted access requirements of the application program for a single storage space (such as a single page): the number of times the application program needs to access the storage space within the first time period after the current time is less than the target number; the application program needs to access the storage space at least the target number of times within the first time period. For the sake of easy description, these two situations are respectively referred to as the application program having no access requirements for the storage space and the application program having access requirements for the storage space.

[0146] Taking Figure 4 and Figure 9 as an example, the above steps 802 and 803 are introduced as follows. The operating system (such as the feature collection module in the operating system) collects the data transmission attributes once every second time period, inputs the collected data transmission attributes into the prediction network, and the prediction network predicts the access requirements of the first application program for at least one storage space in the first storage medium based on the input data transmission attributes.

[0147] Step 804, the operating system sets the memory bypass flag for the first storage space according to the predicted access requirements.

[0148] In a possible implementation manner, the operating system queries the page table entry corresponding to the first storage space according to the predicted access requirements of the application program for the first storage space, and then adds the memory bypass flag corresponding to the first storage space to the page table entry.

[0149] For example, if the prediction network predicts the access requirements of an application for page frames in units of page frames, at least one prediction result output by the prediction network corresponds to the page frame numbers of at least one page frame. For the page frame number corresponding to any prediction result, the operating system queries the page table entry including the page frame number in the page table (or TLB).

[0150] Taking any page frame in the first storage medium as the first storage space as an example, the physical address of the first storage space is the page frame number of the any page frame. The operating system queries the page table entry including the page frame number in the page table (or TLB). After that, if the prediction result corresponding to the page frame to which the first storage space belongs indicates that the application has an access requirement for the corresponding storage space, the operating system adds a first memory bypass flag to the queried page table entry. If the prediction result indicates that the application does not have an access requirement for the corresponding storage space, the operating system adds a second memory bypass flag to the queried page table entry.

[0151] Step 805: The processor obtains a data processing request of the application, and the data processing request is used to instruct the processor to process the associated data of the first storage space in the first storage medium.

[0152] Among them, this step 805 is the same as step 303. Here, the embodiments of the present application will not elaborate on this step 805 again.

[0153] Step 806: The processor obtains the memory bypass flag corresponding to the first storage space according to the data processing request, and the memory bypass flag is used to indicate the storage method of using the second storage medium set according to the access requirement of the application for the first storage space.

[0154] Among them, this step 806 is the same as step 304. Here, the embodiments of the present application will not elaborate on this step 806 again.

[0155] Step 807: The processor processes the associated data according to the memory bypass flag.

[0156] Among them, this step 807 is the same as step 305. Here, the embodiments of the present application will not elaborate on this step 807 again.

[0157] The method provided by the embodiments of the present application, when receiving a data processing request of an application program for the data in the first storage space in the memory, obtains the memory bypass identifier corresponding to the first storage space. Since the memory bypass identifier is used to indicate the storage method of using the cache set according to the access requirements of the application program for the first storage space, when processing the associated data of the first storage space according to the obtained memory bypass identifier, it is possible to determine the storage method of using the cache for the associated data according to the access requirements of the application program for the first storage space, thereby realizing the control of the cache behavior based on the access requirements of the application program and improving the cache hit rate. In addition, by the current data transmission attributes of at least one storage medium, predict the access requirements of the application program for the first storage space, avoid recording the access requirements of the application program for the first storage space in the application program, and can also meet the real-time access requirements of the application program for the storage space in the memory. Therefore, by predicting the memory bypass identifier set according to the access requirements of the application program for the first storage space, the cache behavior can be controlled in real time.

[0158] The above steps 302 and 804 are both processes in which the operating system sets the memory bypass identifier for the first storage space according to the access requirements of the application program for the first storage space, so that the processor can perceive the memory access characteristics of the application program through the memory bypass identifiers corresponding to each storage space in the set first storage medium, thereby overcoming the problem that the processor cannot perceive the memory access characteristics of the application program. So that when the processor accesses the storage space in the memory, it can determine whether to copy the data in the storage space to the cache according to the memory bypass identifier, thereby realizing the control of the cache behavior based on the access requirements of the application program, facilitating the processor to obtain the data required by the application program in the cache later, and improving the cache hit rate.

[0159] In addition, in order to reflect the interaction process within the electronic device in the present application, step 301 takes the application program as the execution subject, and steps 302, 801 to 804 take the operating system as the execution subject. It should be understood that these steps should be implemented by hardware (such as a processor) running the application program or the operating system.

[0160] The above method embodiment is described by taking the bypass identifier field for storing the memory bypass identifier of a single cache as an example. In another possible implementation, the bypass identifier field includes multiple indication bits, and these multiple indication bits may be reserved bits in the page table entry or extended bits of the page table entry. The multiple indication bits correspond one-to-one to multiple levels of caches (i.e., multiple second storage media) of the first storage medium, and each indication bit is used to store the memory bypass identifier of the corresponding cache. Taking the page table shown in Table 3 as an example, the bypass identifier field has M indication bits, and the M indication bits correspond one-to-one to M caches at levels L1-LM, where M is a positive integer.

[0161] Table 3

[0162]

[0163] At this time, the memory bypass flag indicates a storage method using the corresponding cache set according to the access requirements of the application program for the storage space in the first storage medium. At this time, the first storage medium is the memory or cache of the electronic device, and still taking Figure 2 as an example, at this time, M = 4, the first storage medium is the memory, and the caches of levels L1 - L4 respectively correspond to 4 identification bits of the bypass flag field, or the first storage medium is the cache of level L1, and the second storage medium is the cache of level L2. It can be understood that the second storage medium is the cache of the first storage medium.

[0164] For this case, when the processor queries the memory bypass flag corresponding to the first storage medium, it may query multiple memory bypass flags. In this case, step 305 is described as follows:

[0165] For any one of the multiple memory bypass flags, the cache corresponding to the indication bit where the memory bypass flag is located in the bypass flag field is the second storage medium.

[0166] After obtaining the physical address of a storage space in the memory to be accessed, the processor queries, based on the physical address, a cache line including the data in the first storage space in the second storage medium. If the cache line is found to exist in the second storage medium, the processor accesses, based on the data processing request, the cache space corresponding to the first storage space in the cache line. If the cache line including the cache line corresponding to the first storage space does not exist in the second storage medium and the first storage medium is a cache, the processor queries, based on the physical address, a cache line including the data in the first storage space in the first storage medium. If the cache line is found to exist in the first storage medium, the processor accesses, based on the data processing request, the cache line in the first storage medium corresponding to the first storage space. If any memory bypass flag is the first memory bypass flag, the processor copies the data in the first storage space in the cache line to the second storage medium. If any memory bypass flag is the second memory bypass flag, the processor does not perform the step of copying the data in the first storage space in the cache line to the second storage medium. If the cache line is not found to exist in the first storage medium, the processor continues to query the data in the first storage space in the next-level cache of the first storage medium until a target storage space storing the data in the first storage space is found in a cache or memory with a level lower than that of the first storage medium. The processor accesses, based on the data processing request, the target storage space. If any memory bypass flag is the first memory bypass flag, the processor copies the data in the target storage space to the second storage medium and caches with levels lower than that of the second storage medium. If any memory bypass flag is the second memory bypass flag, the processor does not perform the step of copying the data in the target storage space to the second storage medium and caches with levels lower than that of the second storage medium.

[0167] The data processing method provided by the present application is introduced above. Next, the apparatus, chip, and electronic device provided by the present application will be further introduced with reference to the accompanying drawings. It should be understood that the apparatus, chip, and electronic device introduced below can implement any function of the electronic device or a part of the electronic device in any of the above methods.

[0168] See Figure 11 , a schematic structural diagram of a data processing apparatus provided by the present application is shown. Figure 11 The apparatus 1100 shown can be the electronic device or a part of the electronic device in the foregoing embodiments, and is used to execute the data processing method executed by the electronic device. The apparatus 1100 includes a first storage medium 1101, a second storage medium 1102, a first obtaining unit 1103, a second obtaining unit 1104, and an execution unit 1105.

[0169] A first acquisition unit 1103, configured to acquire a data processing request of an application, where the data processing request is used to indicate to process associated data in a first storage space in the first storage medium 1101, and where the first storage medium 1101 is the memory of the electronic device, and the second storage medium 1102 is a cache of the memory;

[0170] A second acquisition unit 1104, configured to acquire, according to the data processing request, a memory bypass identifier corresponding to the first storage space, where the memory bypass identifier is used to indicate a storage mode of using the second storage medium 1102 set according to an access requirement of the application to the first storage space;

[0171] An execution unit 1105, configured to process the associated data according to the memory bypass identifier.

[0172] It should be understood that the device 1100 in the embodiments of the present application may be implemented by a CPU, or may be implemented by an application-specific integrated circuit (ASIC), or may be implemented by a programmable logic device (PLD). The above PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), a data processing unit (DPU), a system on chip (SoC), or any combination thereof. The device 1100 may also be implemented by software Figures 3 to 10 For the data processing method shown, when implemented by software, the device 1100 and its various modules may also be software modules.

[0173] In a possible implementation manner, the second storage medium 1102 is a high-bandwidth memory HBM, and the usage mode of the HBM is a cache mode, and the cache mode is used to indicate that the HBM is used as a cache of the memory.

[0174] In a possible implementation manner, the device 1100 further includes:

[0175] An invocation unit, configured to invoke a first application programming interface API in the operating system, and set a bypass identifier field in a page table entry of the first storage medium 1101, where the bypass identifier field is used to store the memory bypass identifier;

[0176] An adding unit, configured to add the memory bypass identifier to the bypass identifier field in the page table entry corresponding to the first storage space according to the access requirement recorded in the application program.

[0177] In a possible implementation manner, the calling unit is configured to:

[0178] When the application program applies to the operating system for allocating the storage space in the first storage medium 1101 or after the allocation of the storage space is completed, call the first API to set the bypass identifier field in the page table entry of the page table.

[0179] In a possible implementation manner, the calling unit is configured to:

[0180] During the process of compiling the application program by the compiler, call the first API through the second API or guiding statement provided by the compiler to set the bypass identifier field in the page table entry of the page table.

[0181] In a possible implementation manner, the adding unit is configured to:

[0182] Query the page table entry corresponding to the first storage space according to the access requirement recorded in the application program and according to the virtual address of the first storage space;

[0183] Add the memory bypass identifier to the page table entry.

[0184] In a possible implementation manner, the apparatus 1100 further includes:

[0185] A prediction unit, configured to predict the access requirement of the application program for the first storage space based on the data transmission attribute of at least one of the first storage medium 1101 and the second storage medium 1102, where the data transmission attribute is used to indicate the influence of the storage medium on the efficiency of transmitting data;

[0186] A setting unit, configured to set the memory bypass identifier for the first storage space according to the predicted access requirement.

[0187] In a possible implementation manner, the prediction unit is configured to:

[0188] Input the data transmission attribute into a prediction network, and through the prediction network, predict the access requirement of the application program for the first storage space based on the input data transmission attribute.

[0189] In a possible implementation manner, the setting unit is configured to:

[0190] According to the predicted access requirement, query the page table entry corresponding to the first storage space according to the physical address of the first storage space;

[0191] Add the memory bypass flag to the page table entry.

[0192] In a possible implementation, the data processing request includes the virtual address of the first storage space, and the second obtaining unit 1104 is configured to:

[0193] Query the page table entry corresponding to the first storage space according to the virtual address;

[0194] Obtain the memory bypass flag from the page table entry.

[0195] In a possible implementation, the second obtaining unit 1104 is further configured to:

[0196] Query the page table entry corresponding to the first storage space in the page table of the first storage medium 1101 according to the virtual address; or,

[0197] Query the page table entry corresponding to the first storage space in the translation lookaside buffer TLB of the processor according to the virtual address.

[0198] In a possible implementation, the execution unit 1105 is configured to:

[0199] If the memory bypass flag indicates to use the second storage medium 1102 to store the data in the first storage medium 1101, process the associated data of the first storage space, and copy the associated data in the first storage space to the second storage medium 1102;

[0200] If the memory bypass flag indicates not to use the second storage medium 1102 to store the data in the first storage medium 1101, process the associated data of the first storage space, and do not execute the step of copying the associated data in the first storage space to the second storage medium 1102.

[0201] It should be understood that the apparatus 1100 corresponds to the electronic device in the above method embodiment. Each module in the apparatus 1100 and the above other operations and / or functions respectively implement the various steps and methods implemented by the electronic device in the method embodiment. For specific details, reference may be made to the above method embodiment. For the sake of brevity, it will not be elaborated here.

[0202] It should be understood that when the device 1100 performs data processing, only the division of the above-mentioned functional modules is used as an example for illustration. In practical applications, the above-mentioned functions can be assigned to different functional modules according to needs, that is, the internal structure of the device 1100 is divided into different functional modules to complete all or part of the functions described above. In addition, the device 1100 provided in the above embodiment and the above method embodiment belong to the same concept. For the specific implementation process, please refer to the above method embodiment and will not be elaborated here.

[0203] It should be understood that the device 1100 may be equivalent to the data processing system 100 (or 200), or equivalent to an execution component in the data processing system 100 (or 200).

[0204] Figure 12 is a schematic structural diagram of a chip provided by the present application, as Figure 12 shown, the chip 1200 includes a processor 1201 and an interface circuit 1202. Among them, the interface circuit 1202 is used to receive instructions and transmit them to the processor 1201. The processor 1201, for example, may be Figure 11 a specific implementation form of the device 1100 shown, and can be used to execute the above-mentioned data processing method applied to an electronic device. The processor 1201 is coupled to a memory 1203. The memory 1203 is used to store program codes. When the program codes are executed by the processor 1201, the chip system composed of the processor 1201, the interface circuit 1202, and the memory 1203 implements the above Figures 3 to 10 operation steps of the method in any of the method embodiments. Taking the above Figure 7 as an example, the processor 1201 reads the program code of the compiler from the memory 1203, compiles the application program by running the program code of the compiler, and calls the second API of the compiler or the lead to add a bypass identification field in the page table. Subsequently, during the process of running the application program by the processor 1201, based on the bypass identification field added in the page table, the above-mentioned data processing method is implemented.

[0205] Optionally, there is at least one processor 1201 in the chip system. It should be understood that in the embodiments of the present application, the processor 1201 may be a CPU or other general-purpose processors. The processor 1201 may also be one or more integrated circuits for implementing the solution of the present application. For example, a digital signal processor (DSP), an ASIC, a PLD, an FPGA, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0206] Optionally, there may also be one or more memories 1203 in the chip system. The memory 1203 may be integrated with the processor 1201 or may be separately provided from the processor 1201, which is not limited in this application. Exemplarily, the memory 1203 may be integrated with the processor 1201 on the same chip, such as Figure 12 shown. The memory 1203 may also be separately provided from the processor 1201 on different chips. This application does not specifically limit the type of the memory 1203 and the setting manner of the memory 1203 and the processor 1201.

[0207] Among them, the memory 1203 may include a read-only memory and a random access memory, and provide instructions and data to the processor 1201. The memory 1203 may also include a non-volatile random access memory. For example, the memory 1203 may also store information about the device type. The memory 1203 may also be a volatile memory, or may include both volatile and non-volatile memories.

[0208] Among them, the non-volatile memory may be a read-only memory (ROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0209] Exemplarily, the chip system can be an FPGA, an ASIC, an SoC, a CPU, a network processor (NP), a digital signal processor (DSP), a micro controller unit (MCU), a PLD, or other integrated chips.

[0210] Figure 13 FIG. is a schematic structural diagram of an electronic device provided by the present application. As shown in the figure, the electronic device 1300 includes a processor 1301, a memory 1302, a communication interface 1303, a bus 1304, and a storage device 1305. Among them, the processor 1301, the memory 1302, the communication interface 1303, and the storage device 1305 communicate through the bus 1304, and can also communicate through other means such as wireless transmission. The memory 1302 is used to store instructions, and the processor 1301 is used to execute the instructions stored in the memory 1302. The memory 1302 stores program codes, and the processor 1301 can call the program codes stored in the memory 1302 to execute the steps provided by the above data processing method (such as the Figures 3 to 10 ).

[0211] Exemplarily, the processor 1301 may include one or more CPUs, such as Figure 13 the CPU0 and CPU1 shown in FIG. Figure 13 .

[0212] Exemplarily, the electronic device 1300 may include multiple processors, such as Figure 13 the processor 1301 and the processor 1306 shown in FIG. Figure 13 . Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). Here, the processor may refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0213] It should be understood that in the present application, the implementation manner of the processor 1301 and the Figure 12 processor 1201 in FIG. Figure 12 is similar, and the implementation manner of the memory 1302 and the Figure 12 memory 1203 in FIG. Figure 12 is similar. Here, the embodiments of the present application do not elaborate on the implementation manners of the processor 1301 and the memory 1302.

[0214] The communication interface 1303 uses any transceiver-like device for communicating with other devices or communication networks. The communication interface 1304 includes a wired communication interface and may also include a wireless communication interface. Among them, the wired communication interface can be, for example, an Ethernet interface. The Ethernet interface can be an optical interface, an electrical interface, or a combination thereof. The wireless communication interface can be a wireless local area networks (WLAN) interface, a cellular network communication interface, or a combination thereof, etc.

[0215] The bus 1304 is used to transfer information between the above components. In addition to the communication bus, the bus 1304 may also include a power bus, a status signal bus, etc. However, for the sake of clear illustration, all kinds of buses are labeled as the bus 1304 in the figure. Among them, the communication bus can be divided into an address bus, a data bus, a control bus, etc. Exemplarily, the communication bus can be a Peripheral Component Interconnect Express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), or a cache coherent interconnect for accelerators (CCIX), etc.

[0216] The storage device 1305 can be a ROM or other types of static storage devices that can store static information and instructions, or it can be a RAM or other types of dynamic storage devices that can store information and instructions. It can also be an EEPROM, a compact disc read-only memory (CD-ROM), or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by the processor 1301. The storage device 1305 includes at least one memory 1302, but is not limited thereto. The storage device 1305 can exist independently and be connected to the processor 1301 through the bus 1304. The storage device 1305 can also be integrated with the processor 1301.

[0217] Exemplarily, the memory 1302 and the storage device 1305 may be the first storage medium or the second storage medium in the electronic device 1300. At least one of the memory 1302 and the storage device 1305 may store program code for implementing the data processing method of the present application. By reading and running the program code, the processor 1301 enables the electronic device 1300 to implement the data processing method of the present application.

[0218] In some embodiments, the electronic device 1300 may further include an output device 1307 and an input device 1308. The output device 1307 communicates with the processor 1301 and can display information in various ways. For example, the output device 1307 may be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector, etc. The input device 1308 communicates with the processor 1301 and can receive user input in various ways. For example, the input device 1308 may be a mouse, a keyboard, a touch screen device, or a sensing device, etc.

[0219] It should be understood that the apparatus 1100 for implementing data processing according to the present application may correspond to the electronic device 1300 in the embodiments of the present application and may correspond to the corresponding subject executing the data processing method according to the embodiments of the present application. The above and other operations and / or functions of each module in the electronic device 1300 are respectively for implementing Figures 3 to 10 the corresponding processes of the respective methods in, and for the sake of brevity, will not be elaborated herein.

[0220] The present application also provides a computer-readable storage medium, such as a memory including program code. The above program code can be executed by a processor in an electronic device (or chip) to complete the data processing method in the above embodiments. The implementation manner of this computer-readable storage medium can refer to the Figure 12 memory 1203 in.

[0221] The present application also provides a computer program product or a computer program. The computer program product or the computer program includes program code. The program code is stored in a computer-readable storage medium. The processor of the electronic device reads the program code from the computer-readable storage medium, and the processor executes the program code, so that the processor executes the above data processing method.

[0222] In addition, the present application also provides a device, which may specifically be a chip, component or module. The device may include a processor and a memory connected to each other. The memory is used to store computer-executable instructions. When the device runs, the processor may execute the computer-executable instructions stored in the memory, so that the chip executes the data processing methods in the above method embodiments.

[0223] Among them, the device, equipment, computer-readable storage medium, computer program product or chip provided by the present application are all used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods provided above, and will not be elaborated here.

[0224] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the processes or functions described in the embodiments of the present application of the present invention are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center to another website, computer, server or data center in a wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) manner. The computer-readable storage medium can be any available medium that the computer can access or a data storage device such as a server or data center that includes a collection of one or more available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a DVD) or a semiconductor medium. The semiconductor medium can be a solid state disk (SSD).

[0225] The above is only the specific implementation manner of the present application. Those skilled in the technical field can think of changes or substitutions according to the specific implementation manner provided by the present application, and all should be covered by the protection scope of the present application.

Claims

1. A data processing method, characterized in that, the method is applicable to an electronic device, the electronic device includes a first storage medium and a second storage medium, the first storage medium is the memory of the electronic device, the second storage medium is the cache of the memory, and the method includes: Obtain a data processing request of an application, where the data processing request is used to indicate processing of associated data in a first storage space in the first storage medium; According to the data processing request, obtain a memory bypass identifier corresponding to the first storage space, where the memory bypass identifier is used to indicate a storage method using the second storage medium, and the storage method is set according to the access requirement of the application to the first storage space; Execute the processing of the associated data according to the memory bypass identifier.

2. The method according to claim 1, characterized in that, the second storage medium is a high bandwidth memory HBM, and the usage mode of the HBM is a cache Cache mode, and the Cache mode is used to indicate that the HBM is used as a cache of the memory.

3. The method according to claim 1 or 2, characterized in that, before obtaining the memory bypass identifier corresponding to the first storage space according to the data processing request, the method further includes: Call a first application programming interface API in the operating system, and set a bypass identifier field in a page table entry of the first storage medium, where the bypass identifier field is used to store the memory bypass identifier; According to the access requirement recorded in the application, add the memory bypass identifier to the bypass identifier field in the page table entry corresponding to the first storage space.

4. The method according to claim 3, characterized in that, the calling the first application programming interface API in the operating system to set a bypass identifier field in a page table entry of the first storage medium includes: When the application applies to the operating system for allocating a storage space in the first storage medium or after the application for allocating the storage space is completed, call the first API to set the bypass identifier field in the page table entry.

5. The method according to claim 3, characterized in that, the calling the first application programming interface API in the operating system to set a bypass identifier field in a page table entry of the first storage medium includes: During the process of compiling the application by a compiler, call the first API through a second API or a lead provided by the compiler to set the bypass identifier field in the page table entry.

6. The method according to claim 3, characterized in that, the adding the memory bypass identifier to the bypass identifier field in the page table entry corresponding to the first storage space according to the access requirement recorded in the application includes: According to the access requirement recorded in the application, query the page table entry corresponding to the first storage space according to the virtual address of the first storage space; Add the memory bypass identifier to the page table entry.

7. The method according to claim 1 or 2, Characterized in that, Before obtaining the memory bypass identifier corresponding to the first storage space according to the data processing request, the method further includes: Based on the data transmission attributes of at least one of the first storage medium and the second storage medium, predicting the access demand of the application program for the first storage space, where the data transmission attribute is used to indicate the impact of the storage medium on the efficiency of transmitting data; According to the predicted access demand, setting the memory bypass identifier for the first storage space.

8. The method according to claim 7, Characterized in that, The predicting the access demand of the application program for the first storage space based on the data transmission attributes of at least one of the first storage medium and the second storage medium includes: Inputting the data transmission attribute into a prediction network, and through the prediction network, predicting the access demand of the application program for the first storage space based on the input data transmission attribute.

9. The method according to claim 7, Characterized in that, The setting the memory bypass identifier for the first storage space according to the predicted access demand includes: According to the predicted access demand, querying the page table entry corresponding to the first storage space according to the physical address of the first storage space; Adding the memory bypass identifier to the page table entry.

10. The method according to claim 1, 2, 4, 5, 6, 8 or 9, Characterized in that, The data processing request includes the virtual address of the first storage space, and the obtaining the memory bypass identifier corresponding to the first storage space according to the data processing request includes: According to the virtual address, querying the page table entry corresponding to the first storage space; Obtaining the memory bypass identifier in the page table entry.

11. The method according to claim 10, Characterized in that, The querying the page table entry corresponding to the first storage space according to the virtual address includes: According to the virtual address, querying the page table entry corresponding to the first storage space in the page table of the first storage medium; or, According to the virtual address, querying the page table entry corresponding to the first storage space in the translation lookaside buffer (TLB) of the processor.

12. The method according to claim 1, 2, 4, 5, 6, 8, 9 or 11, Characterized in that, The performing the processing of the associated data according to the memory bypass identifier includes: If the memory bypass identifier indicates to use the second storage medium to store the data in the first storage medium, processing the associated data of the first storage space and copying the associated data in the first storage space to the second storage medium; If the memory bypass identifier indicates not to use the second storage medium to store the data in the first storage medium, processing the associated data of the first storage space and not performing the step of copying the associated data in the first storage space to the second storage medium.

13. A data processing device, Characterized in that, The device includes a first storage medium and a second storage medium. The first storage medium is the memory of the electronic device, and the second storage medium is the cache of the memory. The device further includes: A first acquisition unit, configured to acquire a data processing request of an application program, where the data processing request is used to indicate processing of associated data in a first storage space in the first storage medium; A second acquisition unit, configured to acquire, according to the data processing request, a memory bypass identifier corresponding to the first storage space, where the memory bypass identifier is used to indicate a storage manner of using the second storage medium, and the storage manner is set according to an access requirement of the application program for the first storage space; An execution unit, configured to execute the processing of the associated data according to the memory bypass identifier.

14. An electronic device characterized in that the electronic device includes a processor, and the processor is configured to execute at least one program code, so that the electronic device executes the data processing method according to any one of claims 1 to 12.

15. A computer-readable storage medium characterized in that at least one program code is stored in the storage medium, and the at least one program code is read by a processor to enable an electronic device to execute the data processing method according to any one of claims 1 to 12.

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