An address translation exception analysis method, system and storage medium

Abstract

The embodiment of the application provides an address conversion exception analysis method, system and storage medium, and belongs to the technical field of data analysis.The method comprises the following steps: executing a firmware log analysis thread, extracting request parameter information and response data information of any admin command in a firmware log of the NVMe acceleration card; executing a PCIe message analysis thread, extracting any PCIe message generated by a PCIe protocol analyzer between the host and the NVMe acceleration card, wherein the PCIe message represents request data or response data of any admin command or request data or response data of any IO command; and determining whether the NVMe acceleration card has address abnormal conversion for any admin command and any IO command according to the request parameter information and the response data information of any admin command extracted from the firmware log and any PCIe message extracted. The embodiment of the application aims to improve the analysis efficiency of address conversion errors.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of data analysis, and in particular, relate to an address translation exception analysis method and system and a storage medium. BACKGROUND

[0002] With the development of information technologies such as artificial intelligence, Internet of Things and cloud computing, the storage bandwidth requirement for data center servers is getting higher and higher. In order to improve the hard disk IO performance, researchers have designed many devices for accelerating the hard disk IO process, such as NVMe acceleration cards, which can accelerate the IO command execution process of the NVMe protocol, including the IO command transmission and execution process.

[0003] During the product development stage of the NVMe acceleration card, many host command address translation exception problems are often encountered. For example, when the NVMe acceleration card firmware processes the admin command issued by the host or the NVMe acceleration card hardware processes the IO command issued by the host, problems such as PRP address translation error and command response information DMA address calculation error occur. Address translation error will cause the host connected to the NVMe acceleration card to behave abnormally, such as the host NVMe driver executing to a null pointer, further causing the host to restart.

[0004] When the host is abnormal, such as the host NVMe driver restarting when encountering a null pointer, the developer can compare the firmware log and the PCIe message log, analyze the memory DMA process of the admin / IO command between the host and the NVMe acceleration card, and check the part of the address translation error. However, based on the process of comparing each line by the developer, it is difficult to debug the NVMe, resulting in a large difficulty in analyzing the address translation error, thereby leading to low efficiency in analyzing the address translation error. SUMMARY

[0005] Embodiments of the present application provide an address translation exception analysis method, system and storage medium, aiming to improve the analysis efficiency of address translation error.

[0006] In a first aspect, embodiments of the present application provide an address translation exception analysis method applied to a computer system, wherein the computer system includes a host and an NVMe acceleration card, and the method includes:

[0007] executing a firmware log analysis thread to extract request parameter information and response data information of any admin command in a firmware log of the NVMe acceleration card;

[0008] executing a PCIe message analysis thread to extract any PCIe message generated by a PCIe protocol analyzer between the host and the NVMe acceleration card, wherein the PCIe message represents request data or response data of any admin command or request data or response data of any IO command.

[0009] According to the request parameter information and the response data information of any admin command extracted from the firmware log and any PCIe message extracted, it is determined whether there is an address exception conversion for any admin command and any IO command by the NVMe acceleration card.

[0010] Optionally, according to the request parameter information and the response data information of any admin command extracted from the firmware log and any PCIe message extracted, it is determined whether there is an address exception conversion for any admin command and any IO command by the NVMe acceleration card, comprising:

[0011] According to the message header address of any PCIe message, it is determined that the message data of the PCIe message belongs to any one of a queue base address, a queue depth or an MSI-X address;

[0012] According to the message length of any PCIe message, it is determined to execute any one of an MSI-X address checking process, an NVMe command request checking process, an NVMe command response checking process and a PRP address checking process;

[0013] The MSI-X address checking process is used to determine whether the firmware of the NVMe acceleration card is interrupted; the NVMe command request checking process is used to determine whether there is an address exception conversion for any admin command request; the NVMe command response checking process is used to determine whether any admin command response or any IO command response is incorrect; and the PRP address checking process is used to determine whether there is an address exception conversion for any IO command request.

[0014] Optionally, according to the message header address of any PCIe message, it is determined that the message data of the PCIe message belongs to any one of a queue base address, a queue depth or an MSI-X address, comprising:

[0015] When the message header address of any PCIe message is the base register address of the request queue or the response queue of any admin command, the message data of the PCIe message is saved in the queue attribute set as a queue base address;

[0016] When the message header address of any PCIe message is the depth register address of the request queue or the response queue of any admin command, the message data of the PCIe message is saved in the queue attribute set as a queue depth;

[0017] When the message first address of any PCIe message is the MSI-X interrupt register address of any admin command response queue, the message data of the PCIe message is saved in the MSI-X address set as the MSI-X address.

[0018] Optionally, according to the message length of any PCIe message, it is determined to execute any one of the MSI-X address checking process, the NVMe command request checking process, the NVMe command response checking process and the PRP address checking process, including:

[0019] When the PCIe message length is 4 bytes, the MSI-X address checking process is executed.

[0020] When the PCIe message length is 64 bytes, the NVMe command request checking process is executed.

[0021] When the PCIe message length is 16 bytes, the NVMe command response checking process is executed.

[0022] When the PCIe message length is not any one of 4, 16 and 64 bytes, the PRP address checking process is executed.

[0023] Optionally, the MSI-X address checking process is executed, including:

[0024] It is detected whether the message first address of the PCIe message is located in the MSI-X address set or not.

[0025] When the message first address of the PCIe message is located in the MSI-X address set, it is represented that the firmware of the NVMe acceleration card triggers the MSI-X interrupt.

[0026] When the message first address of the PCIe message is not located in the MSI-X address set, the PRP address checking process is executed.

[0027] Optionally, the NVMe command request checking process is executed, including:

[0028] When the message first address of the PCIe message is within the address range of any admin command request queue, the message data of the PCIe message is taken as an admin command request, and an admin command request checking process is executed, the admin command request checking process including:

[0029] convert the binary message data of the PCIe message into a target admin command request, compare parameter content of the target admin command request with parameter content of any admin command request in the firmware log, if no consistent parameter content is matched, it is represented that any admin command request has address abnormal conversion; when consistent parameter content is matched, through the opcode field of the target admin command request, it is determined that the command type corresponding to the target admin command request is creation of an IO request queue or creation of an IO response queue, and the queue information and the interrupt vector of the IO request queue or the IO response queue are extracted from the target admin command request and added in the queue attribute set;

[0030] when the message header address of the PCIe message is in the address range of any IO command request queue, the message data is taken as an IO command request, and an IO command request checking process is performed, the IO command request checking process includes:

[0031] after the binary message data of the PCIe message is converted into a target IO command request, according to the opcode field of the target IO command request, it is judged that the command type of the target IO command request is a read command request or a write command request;

[0032] when the command type of the target IO command request is a read command request or a write command request, the corresponding PRP table address is obtained from the target IO command request and saved in an IO PRP address set;

[0033] when the command type of the target IO command request is not a read command request or a write command request, the PCIe message is stopped to be processed;

[0034] when the message header address of the PCIe message is not in the address range of any admin command request queue and not in the address range of any IO command request queue, a PRP address checking process is performed.

[0035] optionally, the NVMe command response checking process includes:

[0036] when the message header address of the PCIe message is in the address range of any admin command response queue, the message data of the PCIe message is taken as an admin command response, and an admin command response checking process is performed, the admin command response checking process includes:

[0037] the binary message data of the PCIe message is converted into a target admin command response, and the queue identifier and the queue head pointer of the target admin command response are extracted, it is checked whether the queue identifier exists in the queue attribute set and the queue head pointer is less than the queue depth;

[0038] when the check fails, indicating that the target admin command response is erroneous; and

[0039] when the message header address of the PCIe message is within the address range of any IO command response queue, the message data is taken as an IO command response, and an IO command response checking procedure is performed, the IO command response checking procedure comprising:

[0040] the binary message data of the PCIe message is converted into a target IO command response, and the queue identifier and the queue head pointer of the target IO command response are extracted, and it is checked whether the queue identifier exists in the queue attribute set and the queue head pointer is less than the queue depth;

[0041] when the check fails, indicating that the target IO command response is erroneous;

[0042] when the message header address of the PCIe message is not within the address range of any admin command response queue and not within the address range of any IO command response queue, a PRP address checking procedure is performed.

[0043] Optionally, the PRP address checking procedure comprises:

[0044] when it is checked that the message header address of the PCIe message simultaneously satisfies: the PRP table address corresponding to any admin command read in the firmware log is inconsistent, the PRP table address corresponding to the target IO command request is inconsistent, is not in the admin PRP address set composed of the PRP table addresses of the admin commands, and is not in the IO PRP address set composed of the PRP table addresses of the IO commands, it is determined that any IO command request has address abnormal conversion.

[0045] Optionally, the method further comprises:

[0046] the number of times of any address match in the plurality of address matches in the PCIe message analysis thread is counted respectively;

[0047] according to the number of times of any address match, the execution priority of the plurality of address matches is updated in time, wherein the more the number of times of any address match, the higher the execution priority;

[0048] the PCIe message analysis thread is executed according to the execution priority of the plurality of address matches.

[0049] In a second aspect, the embodiments of the present application provide a computer system including a host and an NVMe acceleration card, and the computer system is configured to execute the address conversion exception analysis method of the first aspect.

[0050] In a third aspect, the embodiments of the present application provide a non-volatile readable storage medium storing a computer program, wherein the computer program is configured to execute the address conversion exception analysis method of the first aspect when executed by a processor.

[0051] Advantages:

[0052] The method extracts the request parameter information and the response data information of any admin command in the firmware log of the NVMe acceleration card by executing a firmware log analysis thread, extracts any PCIe message generated by a PCIe protocol analyzer between the host and the NVMe acceleration card by executing a PCIe message analysis thread, and the PCIe message represents the request data or the response data of any admin command or the request data or the response data of any IO command. The method determines whether there is an address conversion exception of any admin command or any IO command of the NVMe acceleration card according to the request parameter information and the response data information of any admin command extracted from the firmware log and the any PCIe message extracted.

[0053] Based on the request parameter information and the response data information of the admin command in the firmware log of the NVMe acceleration card and the any PCIe message generated by the PCIe protocol analyzer, the address conversion exception of the NVMe admin / IO command address conversion process can be deduced and verified, so that the analysis efficiency of the address conversion error can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0054] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed in the embodiments or the prior art description will be briefly introduced as follows.

[0055] Figure 1 A flowchart of an existing host command address conversion exception debugging process is shown;

[0056] Figure 2 A schematic diagram showing the content of the firmware log of the existing NVMe acceleration card and the PCIe message log of the PCIe protocol analyzer is shown;

[0057] Figure 3 A step flowchart of the address conversion exception analysis method provided by the embodiments of the present application is shown;

[0058] Figure 4A flow chart of a process of executing a PCIe message analysis thread is shown.

[0059] Figure 5 A flow chart of a process of executing an MSI-X address verification process is shown.

[0060] Figure 6 A flow chart of a process of executing an NVMe command request check process is shown.

[0061] Figure 7 A flow chart of a process of executing an NVMe command response check process is shown.

[0062] Figure 8 A flow chart of a process of executing a PRP address verification process is shown.

[0063] Figure 9 A schematic diagram of dynamically adjusting the execution order of address matching is shown. DETAILED DESCRIPTION

[0064] The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.

[0065] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art can understand that, in the embodiments of the present application, many technical details are presented in order to make the readers better understand the present application. However, the technical solutions claimed by the present application can be implemented even without these technical details and based on various changes and modifications of the following embodiments. The division of the following embodiments is for the convenience of description, and should not constitute any limitation on the specific implementation of the present application. The embodiments can be combined and referenced to each other without contradiction.

[0066] PCIe: a hardware interface of a host and a peripheral, a PCIe bus protocol implemented through a PCIe hardware link, enabling the host and the peripheral to interact with data based on the PCIe interface, with characteristics such as high-speed transmission, exception recovery, and power management.

[0067] MSI: message interrupt, an interrupt mode defined by a PCIe protocol, a device can trigger an interrupt signal of a host hardware by writing message data into an MSI address of the host, thereby notifying the host NVMe device driver to perform corresponding interrupt processing.

[0068] NVMe: an application layer protocol running on top of hardware PCIe protocol, defines a set of management and IO request / response queue interfaces, which can realize high concurrency and asynchronous submission of IO request commands and processing of IO responses from the host to the device.

[0069] admin command: a command used by NVMe protocol to manage the device, including creating a queue, deleting a queue, configuring a feature, etc.

[0070] IO command: a command used by NVMe protocol to read and write device memory, including read, write, format, check, etc.

[0071] MSI-X: a more advanced PCIe protocol interrupt method, which defines multiple MSI interrupts through MSI table. The host NVMe driver can use this interrupt method to assign a unique MSI interrupt number to each admin / IO command response queue. When the device writes admin / IO command responses to the host command response queue, it can use different MSI interrupt numbers to trigger different MSI interrupts to the host, thereby notifying the host to read admin / IO command response information from different admin / IO command response queues.

[0072] DMA: Direct Data Transfer, used to transfer data from one address to another through hardware other than CPU

[0073] PRP address: Physical Region Page, representing the IO data memory page address contained in the IO command.

[0074] PRP table: NVMe protocol defines a PRP address table containing multiple PRP addresses, representing the transfer of multiple memory page data between the host and the NVMe device through DMA at a time. Each PRP table entry is a PRP address.

[0075] flash: a non-volatile data storage, commonly used to store data inside the device (such as hard disk).

[0076] PCIe link can provide physical transmission media, data flow control and retransmission, and various data transmission transactions in units of PCIe messages. NVMe protocol is an application layer data storage protocol, its underlying is PCIe link, NVMe is built on PCIe, which can support 1 admin and up to 65536 IO command request / response queues, and the request / response queue depth can be up to 65536. It provides a simple, easy-to-use, high-concurrency and high-reliability data transmission interface for application layer software in units of queues.

[0077] With the development of information technologies such as artificial intelligence, Internet of Things and cloud computing, the requirement for the storage bandwidth of a data center server is higher and higher. In order to improve the IO performance of a hard disk, researchers have designed many devices for accelerating the IO process of a hard disk, such as an NVMe acceleration card, which can accelerate the IO command execution process of an NVMe protocol, including the transmission and execution of an IO command.

[0078] During the product research and development stage of the NVMe acceleration card, many host command address conversion exception problems are often encountered. For example, when the NVMe acceleration card firmware processes an admin command issued by a host or the NVMe acceleration card hardware processes an IO command issued by a host, PRP address conversion errors and command response information DMA address calculation errors occur. The address conversion error will cause the host connected to the NVMe acceleration card to behave abnormally, such as the host NVMe driver executing to a null pointer, which further causes the host to restart.

[0079] With reference to Figure 1 , a flowchart of an existing host command address conversion exception debugging process is shown. The current debugging method for the NVMe acceleration card host command address conversion exception includes the following steps:

[0080] S001: The host NVMe device driver submits an admin / IO command to an admin / IO command request queue;

[0081] S002: The firmware of the NVMe acceleration card executes an admin command, and the hardware executes an IO command. When the firmware / hardware polls that the admin / IO command request queue is not empty, the command is moved from the host by DMA, and the PRP address table address, data block number and flash address of the host are taken out;

[0082] S003: The NVMe acceleration card firmware / hardware moves the PRP table from the host to the local cache by DMA, and then extracts all the table entries from the PRP table. Any table entry includes a PRP address. According to the data block number and flash address parameters contained in the command, the IO data is moved from the host memory address pointed to by the PRP address to the local flash address by DMA;

[0083] S004: The NVMe acceleration card firmware writes the response result of the admin command into the host admin command response queue by DMA, and then writes the host MSI-X address to trigger an interrupt. The interrupt is used to notify the host to further read the command response result of the admin command;

[0084] S005: In the process of handling the admin command, the firmware records the request parameters of the admin command in the firmware log, including the PRP table address, PRP address, data block length, and flash address, and the command response result, including whether the command is successful, the command request queue head pointer (indicating the command address index in the "command request queue" that the firmware has just finished processing), the command request queue identifier (indicating the unique identifier of the "command request queue" to which the command response information corresponds, used to distinguish other "command request queues"), and the command identifier (indicating the unique identifier of the admin command in the "command request queue", used to distinguish other commands in the queue).

[0085] S006: In the process of executing the IO command by the NVMe acceleration card hardware, the PCIe protocol analyzer connected between the host and the NVMe acceleration card monitors all PCIe messages and records the data transmission behavior on all PCIe links, including monitoring the host reading and writing the device, i.e., the NVMe acceleration card register, monitoring the device reading and writing the host address (various DMA processes such as data transfer according to the PRP address), and monitoring the device triggering the MSI interrupt (the NVMe acceleration card triggers the host to generate an interrupt by writing the host MSI-X address).

[0086] Referring to Figure 2 , a schematic diagram of the contents of the existing NVMe acceleration card firmware log and the PCIe message log of the PCIe protocol analyzer is shown. The firmware log includes the request parameters and the parameters in the command response result corresponding to any admin command. The request parameters corresponding to the admin command include the PRP table address, PRP address, data block length, and flash address. The parameters in the command response result include whether the command is successful, the command request queue head pointer, the command request queue identifier, and the command identifier. The PCIe message log includes the parameters of any PCIe message. Each PCIe message includes the transmission direction (0 indicates reading the host memory by DMA, and 1 indicates writing the host memory by DMA), the message first address (the host memory address as the DMA source / destination address), the message length (DMA length), and multiple message data segments (representing binary data for one DMA transmission).

[0087] When the host abnormally restarts, such as when the host NVMe driver encounters a null pointer, the developer can compare the firmware log and the PCIe message log to analyze the memory DMA process of the admin / IO command between the host and the NVMe acceleration card, check which parameter (command request, command response, PRP data, MSI, queue head / tail pointer) address conversion error of which command caused the data to be written to the wrong host address, and further caused the host to restart.

[0088] Based on the process of comparing each item by the R&D personnel, although the host command address translation exception can be located, the following problems still exist:

[0089] 1) It is difficult to debug NVMe; because the NVMe and PCIe protocols are relatively complex, analyzing the PCIe protocol message and converting the PCIe binary data into NVMe protocol command require deep protocol knowledge, so it is difficult to debug;

[0090] 2) The speed of debugging problem is slow; because the automatic comparison of NVMe acceleration card firmware log and PCIe message is lacking, and the automatic conversion of PCIe message into NVMe command and the checking of command execution process are lacking, each command execution process needs to be analyzed manually, and when the host issues more admin / IO commands, it will cause the problem to be located slowly;

[0091] 3) It is difficult to summarize the debugging experience; because the debugging method is not recorded and summarized, when the R&D personnel are replaced, the new R&D personnel need to re-summarize the address exception problem positioning steps of the NVMe acceleration card, which is not conducive to the experience dissemination;

[0092] 4) The debugging steps are less optimized; because the address exception problem positioning steps of the NVMe acceleration card are not summarized and reviewed, the R&D personnel will check the command parameters and command execution process from the PCIe message according to the same steps every time they debug the problem, and some command parameters are not frequently caused by address exception, but because they are not summarized and reviewed, they will frequently check the parameters, which causes the address exception problem to be located according to the optimal parameter checking order.

[0093] Therefore, in order to quickly analyze the host command address translation exception problem of the NVMe acceleration card, the address translation exception analysis method provided in the embodiment can solve the problems of large debugging difficulty, slow speed and less optimization in the analysis process of the host command address translation exception of the NVMe acceleration card.

[0094] Referring to Figure 3 , a step flowchart of an address translation exception analysis method provided by the embodiment of the application is shown, the method is applied to a computer system, the computer system includes a host and an NVMe acceleration card, and the method can include the following steps:

[0095] S101: Execute a firmware log analysis thread to extract the request parameter information and response data information of any admin command in the firmware log of the NVMe acceleration card.

[0096] The firmware of the NVMe acceleration card stores the request parameter information and response data information of any admin command in the firmware log when processing the admin command, wherein the request parameter information includes a PRP table address, a PRP address, a data block length and a flash address; and the response data information includes whether the command is successful, a command request queue head pointer, a command request queue identifier and a command identifier.

[0097] In actual implementation, the request parameter information and response data information of each admin command in the firmware log of the NVMe acceleration card can be read in a loop, and after the request parameter information and response data information of any admin command are extracted, the next admin command can be read after the verification of the PCIe message analysis thread is completed.

[0098] S102: Execute the PCIe message analysis thread to extract any PCIe message generated by a PCIe protocol analyzer between the host and the NVMe acceleration card, wherein the PCIe message represents the request data or response data of any admin command or the request data or response data of any IO command.

[0099] The PCIe message is generated by the PCIe protocol analyzer between the host and the NVMe acceleration card and is stored in the PCIe message log of the PCIe protocol analyzer, and each PCIe message is read from the PCIe message log in a loop when the PCIe message analysis thread is executed.

[0100] The PCIe message represents the request data or response data of any admin command or the request data or response data of any IO command, and the PCIe message includes a transmission direction, a message first address, a message length and message data, wherein the transmission direction is 0, indicating that the host memory is read through DMA, and the transmission direction is 1, indicating that the host memory is written through DMA; the message first address is the host memory address of the DMA source / destination address; the message length refers to the length of each DMA; and the message data represents the binary data of one DMA transmission.

[0101] S103: According to the request parameter information and response data information of any admin command extracted from the firmware log and any PCIe message extracted, determine whether the NVMe acceleration card has address exception conversion for any admin command and whether the NVMe acceleration card has address exception conversion for any IO command.

[0102] Refer to Figure 4, shows the processing flowchart of executing the PCIe message analysis thread provided by the embodiment of the application. In a feasible implementation manner, first, the message data of the PCIe message is determined to belong to any one of the queue base address, the queue depth or the MSI-X address according to the message header address of the PCIe message.

[0103] Specifically, when the message header address of any PCIe message is the base register address of the request queue or the response queue of any admin command, the message data of the PCIe message is saved as the queue base address in the queue attribute set.

[0104] When the message header address of any PCIe message is the depth register address of the request queue or the response queue of any admin command, the message data of the PCIe message is saved as the queue depth in the queue attribute set.

[0105] When the message header address of any PCIe message is the MSI-X interrupt register address of the response queue of any admin command, the message data of the PCIe message is saved as the MSI-X address in the MSI-X address set.

[0106] Then, according to the relationship between the data length processed in the NVMe protocol and the task executed, it can be determined that the PCIe message is triggering the MSI-X interrupt, executing the admin command request or the IO command request, executing the admin command response or the IO command response.

[0107] Specifically, the message data length for triggering the MSI-X interrupt in the NVMe protocol is 4 bytes, the data length of the admin command request or the IO command request is 64 bytes, the data length of the admin command response or the IO command response is 16 bytes, and the remaining NVMe data transmission is the "host memory pointed by the PRP address" to the device flash address data transmission.

[0108] Therefore, according to the message length of the PCIe message, the address verification sub-processes that need to be executed can be determined, and the address verification sub-processes include the MSI-X address verification process, the NVMe command request checking process, the NVMe command response checking process and the PRP address verification process; the MSI-X address verification process is used to determine whether the firmware of the NVMe acceleration card is interrupted; the NVMe command request checking process is used to determine whether there is an address abnormal conversion for any admin command request; the NVMe command response checking process is used to determine whether any admin command response or any IO command response is incorrect; and the PRP address verification process is used to determine whether there is an address abnormal conversion for any IO command request.

[0109] In an implementable embodiment, according to the message length of any PCIe message, it is determined to execute any one of the MSI-X address checking procedure, the NVMe command request checking procedure, the NVMe command response checking procedure and the PRP address checking procedure, specifically comprising:

[0110] When the PCIe message length is 4 bytes, the MSI-X address checking procedure is executed.

[0111] When the PCIe message length is 64 bytes, the NVMe command request checking procedure is executed.

[0112] When the PCIe message length is 16 bytes, the NVMe command response checking procedure is executed.

[0113] When the PCIe message length is not any one of 4, 16 and 64 bytes, the PRP address checking procedure is executed.

[0114] Referring to Figure 5 , a flowchart of the MSI-X address checking procedure provided by the embodiment of the application is shown, and the MSI-X address checking procedure comprises:

[0115] It is detected whether the message first address of the PCIe message is located in the MSI-X address set or not; when the message first address of the PCIe message is located in the MSI-X address set, it is represented that the firmware of the NVMe acceleration card triggers the MSI-X interrupt; when the message first address of the PCIe message is not located in the MSI-X address set, it is possible that the firmware of the NVMe acceleration card reads and writes the host RPR address data, at this time, the PRP address checking procedure is executed.

[0116] The NVMe command request checking procedure comprises the admin command request checking procedure and the IO command request checking procedure, therefore, when the NVMe command request checking procedure is executed, address matching needs to be performed first to determine whether the admin command request checking procedure is executed or the IO command request checking procedure is executed.

[0117] Specifically, it is judged whether the message first address of the PCIe message is located in the address range of any admin command request queue or in the address range of any IO command request queue, for example, in the queue attribute set, it is determined whether the message first address of the PCIe message is located in the address range determined by the base address and the depth of any admin command request queue or any IO command request queue.

[0118] When the message first address of the PCIe message is located in the address range of any admin command request queue, the message data of the PCIe message is taken as the admin command request, and the admin command request checking procedure is executed.

[0119] When the message header address of the PCIe message is within the address range of any IO command request queue, the message data is taken as an IO command request, and an IO command request checking process is performed.

[0120] When the message header address of the PCIe message is not within the address range of any admin command request queue and the address range of any IO command request queue, a PRP address checking process is performed.

[0121] Referring to Figure 6 , a flowchart of an NVMe command request checking process provided by an embodiment of the present application is shown, wherein the admin command request checking process includes:

[0122] The binary message data of the PCIe message is converted into a target admin command request according to an admin command request format defined by the NVMe protocol, and the parameter content of the target admin command request is compared with the parameter content of any admin command request in the firmware log.

[0123] When no consistent parameter content is matched, it is indicated that any admin command request has an address abnormal conversion, and the process of firmware parsing the admin command is wrong. For example, the firmware parsing the admin command can be printed as wrong, and the wrong command field is checked.

[0124] When the consistent parameter content is matched, whether the command type corresponding to the target admin command request is an IO request queue creation or an IO response queue creation is determined through the operation code field of the target admin command request. If the target admin command request is an IO request queue creation or an IO response queue creation, the queue information and the interrupt vector of the IO request queue or the IO response queue are extracted from the target admin command request and added in the queue attribute set. The queue information includes the base address, the depth and the identifier of the IO response queue.

[0125] As Figure 6 , the IO command request checking process includes:

[0126] After the binary message data of the PCIe message is converted into a target IO command request according to an IO command request format defined by the NVMe protocol, whether the command type of the target IO command request is a read command request or a write command request is determined according to the operation code field of the target IO command request.

[0127] When the command type of the target IO command request is a read command request or a write command request, it indicates that the device will subsequently read and write data from the memory pointed to by the host PRP address. The PRP table address of the PRP address set is saved first, and all PRP addresses will be taken out from the PRP table in the subsequent process. Therefore, the corresponding PRP table address is obtained from the target IO command request and saved in the IO PRP address set.

[0128] When the command type of the target IO command request is not a read command request or a write command request, it indicates that the target IO command request is a non-read-write command. The non-read-write command does not involve moving PRP data, and therefore the PCIe message can be stopped.

[0129] The NVMe command response checking process includes an admin command response checking process and an IO command response checking process. Therefore, when the NVMe command response checking process is executed, address matching needs to be performed first to determine whether to execute the admin command response checking process or the IO command response checking process.

[0130] Specifically, it is determined whether the message first address of the PCIe message is within the address range of any admin command response queue or within the address range of any IO command response queue. For example, in the queue attribute set, it is determined whether the message first address of the PCIe message is within the address range determined by the base address and the depth of any admin command response queue or any IO command response queue.

[0131] When the message first address of the PCIe message is within the address range of any admin command response queue, the message data of the PCIe message is taken as an admin command response, and the admin command response checking process is executed.

[0132] When the message first address of the PCIe message is within the address range of any IO command response queue, the message data is taken as an IO command response, and the IO command response checking process is executed.

[0133] When the message first address of the PCIe message is not within the address range of any admin command response queue and not within the address range of any IO command response queue, the PRP address checking process is executed.

[0134] Referring to Figure 7 , a flowchart of the NVMe command response checking process provided by the embodiments of the present application is shown, wherein the admin command response checking process includes:

[0135] The binary message data of the PCIe message is converted into a target admin command response according to an admin command response format defined by the NVMe protocol, and a queue identifier and a queue head pointer of the target admin command response are extracted, and it is checked whether the queue identifier exists in the queue attribute set and whether the queue head pointer is less than the queue depth.

[0136] When the check fails, the target admin command response is characterized as an error, and at this time, the admin command response content illegal and the admin command content can be printed.

[0137] When the check passes, the firmware log analysis thread is notified to read the next admin command.

[0138] As Figure 7 , the IO command response verification process includes:

[0139] The binary message data of the PCIe message is converted into a target IO command response according to an IO command response format defined by the NVMe protocol, and a queue identifier and a queue head pointer of the target IO command response are extracted, and it is checked whether the queue identifier exists in the queue attribute set and whether the queue head pointer is less than the queue depth.

[0140] When the check fails, the target IO command response is characterized as an error, and the IO command response content illegal and the IO command content are printed.

[0141] Referring to Figure 8 , a flowchart of a PRP address verification process provided by an embodiment of the present application is shown, and the PRP address verification process includes:

[0142] When it is checked that the message first address of the PCIe message simultaneously satisfies: the PRP table address corresponding to any admin command read from the firmware log is inconsistent, the PRP table address corresponding to the target IO command request is inconsistent, is not in the admin PRP address set composed of the PRP table addresses of the admin command, and is not in the IO PRP address set composed of the PRP table addresses of the IO command, it is determined that any IO command request has address abnormal conversion.

[0143] As Figure 8 is shown, specifically, first, it is checked whether the message first address of the PCIe message is consistent with the PRP table address of the admin command read from the firmware log.

[0144] If consistent, then add the PCIe message data as PRP table item, i.e. PRP address, to the admin PRP address set, because the firmware / hardware of the NVMe acceleration card will read all PRP addresses from the host memory pointed by the RRP table address, and this process will be logged by the firmware / PCIe message.

[0145] If inconsistent, then according to the NVMe protocol, the NVMe acceleration card may be reading / writing host PRP address data, so continue to compare whether the message first address of the PCIe message is consistent with the IO PRP address obtained in the IO command request check process.

[0146] If consistent with the IO PRP address, then add the message data as PRP table item to the IO PRP address set.

[0147] If inconsistent with the IO PRP address, then check whether the message first address is in the admin PRP address set, if yes, end; if not, check whether the message first address is in the IO PRP address set.

[0148] If in the IO PRP address set, end.

[0149] If not in the IO PRP address set, print hardware IO command address exception and complete IO command content.

[0150] In a feasible implementation, in the process of executing the PCIe message analysis thread, multiple address matches need to be performed, including address match when executing the main process of the PCIe message analysis thread, address match when executing the NVMe command request check process, address match when executing the NVMe command response check process, and address match when executing the PRP address check process.

[0151] Specifically, the address match when executing the main process of the PCIe message analysis thread includes: the message first address is the base register address of the request queue of the admin command, the message first address is the base register address of the response queue of the admin command, the message first address is the depth register address of the request queue of the admin command, the message first address is the depth register address of the response queue of the admin command, the message first address is the MSI-X interrupt register address, the message length is 4, the message length is 16, the message length is 64, and the message length is not 4, 16, or 64 bytes.

[0152] The address match when executing the NVMe command request check process includes: the message first address is in the address range of the admin command request queue and the message first address is in the address range of the IO command request queue.

[0153] The address matching when performing the NVMe command response check procedure includes that the packet header address is within the address range of the admin command response queue and the packet header address is within the address range of the IO command response queue.

[0154] The address matching when performing the PRP address check procedure includes that the packet header address is consistent with the IO PRP table address, the packet header address is in the IO PRP address set, the packet header address is consistent with the admin PRP table address, and the packet header address is in the admin PRP address set.

[0155] That is, when performing the PCIe packet analysis thread, it needs to be determined to achieve the above address matching. For example, for the packet data of a PCIe packet, when determining the relationship between the packet data and the byte length, there are four matching processes of 4 bytes, 16 bytes, 64 bytes, and non-4, 16, and 64 bytes. The address matching can be completed through at least one comparison, and at most four comparisons.

[0156] Considering that different matching conditions will lead to different matching probabilities due to different actual product test focuses, the address matching order defined in the initial stage is not necessarily the matching order with the fastest matching speed. For example:

[0157] 1. When repeatedly testing the NVMe acceleration card device reset, since the device initialization is repeatedly performed, the host NVMe driver is frequently loaded, and thus the MSI-X address register of the device is frequently configured. Therefore, “the packet length is 4 bytes” is the highest probability matching condition, and matching “the packet length is 4 bytes” first can make the address matching process the fastest.

[0158] 2. When repeatedly testing the admin command transmission, since the MSI-X address register is initialized and configured only once, and most admin commands only transmit the command request (64 bytes) and the command response (16 bytes), “the packet length is 64 / 16 bytes” is the highest probability matching condition, and matching “the packet length is 64 / 16 bytes” first can make the address matching process the fastest.

[0159] 3. When repeatedly testing the IO data transmission, since the MSI-X address register is initialized and configured only once, and a single IO command contains a large amount of PRP data transmission, a single PRP data transmission needs multiple DMAs, and the length of a single DMA is determined by the device PCIeMax Payload Size register and is generally 512 bytes. Therefore, “the packet length is not 4, 16, or 64 bytes” is the highest probability matching condition, and matching “the packet length is not 4, 16, or 64 bytes” first can make the address matching process the fastest.

[0160] Therefore, in order to improve the address matching process of the PCIe message analysis thread, the execution order of the matching conditions can be dynamically adjusted.

[0161] In an implementation, the method further comprises:

[0162] The number of times that each address matching in the PCIe message analysis thread is executed is counted, and the execution priority of the address matching is updated according to the number of times that each address matching is executed, wherein the more the number of times that each address matching is executed, the higher the execution priority of the address matching; and the PCIe message analysis thread is executed according to the execution priority of the address matching.

[0163] That is, the more the number of times that an address matching is hit, the greater the probability of subsequent hits, and therefore the higher the execution priority of the address matching, and thus the PCIe message analysis thread can be accelerated by executing the address matching in priority.

[0164] Referring to Figure 9 , a schematic diagram of dynamically adjusting the execution order of address matching provided by the embodiments of the present application is shown, and for the old address matching order, the address matching order is sequentially reduced from top to bottom, and the PCIe message analysis thread is executed according to the order from high to low priority; for example, if the execution priority of “message length is 4 bytes”, “message length is not 4, 16, or 64 bytes”, “message length is 16 bytes”, and “message length is 64 bytes” is sequentially reduced, when determining to execute any one of the MSI-X address verification process, the NVMe command request checking process, the NVMe command response checking process, and the PRP address verification process according to the message length of any PCIe message, it is determined whether the message length is 4 bytes in priority, and if not, it is determined whether the message length is not 4, 16, or 64 bytes.

[0165] Next, the number of times that each address matching is executed when the PCIe message analysis thread is executed, when the NVMe command request checking process is executed, when the NVMe command response checking process is executed, and when the PRP address verification process is executed is counted, and the number of times refers to the number of times of successful matching or hitting.

[0166] Then, at a fixed time interval, the old address matching order is updated to generate a new address matching order, the PCIe message analysis thread is executed according to the new address matching order, and the number of times of each address matching condition is counted again.

[0167] The method provided by the embodiments has at least the following beneficial effects:

[0168] 1. An NVMe accelerator card host command exception address analysis tool is developed, which is divided into two parts: firmware log analysis thread and PCIe message analysis thread. The firmware log analysis thread is used to extract and analyze the related information of the admin command request / response of the NVMe accelerator card device firmware. The PCIe message analysis thread is used to extract and analyze the PCIe message of the PCIe protocol analyzer between the NVMe accelerator card and the host, translate the binary data of the PCIe message into NVMe IO command request / response information, and then compare the admin command differences between the firmware log and the PCIe message log to check whether the device firmware processing admin command has an error in address conversion when parsing or executing the host admin command. By comparing the IO command address range issued by the host in the PCIe message log and the IO command address range actually executed by the device hardware, it is checked whether the device hardware has an error in executing the host IO command address conversion.

[0169] 2. The debugging difficulty is low; the PCIe message can be automatically analyzed, and the PCIe binary data can be converted into NVMe protocol commands for analysis, so the debugging difficulty is low;

[0170] 3. The debugging problem speed is fast; since the NVMe accelerator card firmware log and the PCIe message can be automatically compared, and the PCIe message can be automatically converted into NVMe commands and checked for command execution process, each command execution process does not need to be manually analyzed, and when the host issues a large number of IO commands, the problem positioning speed can be greatly improved;

[0171] 4. The debugging experience is easy to summarize; since the tool records and summarizes the address exception problem positioning steps of the NVMe accelerator card, when a new R&D personnel is replaced, the new R&D personnel does not need to re-summarize the address exception problem positioning steps of the NVMe accelerator card;

[0172] 5. The debugging steps can be dynamically optimized; the address matching order can be dynamically adjusted according to different test scenarios, so as to optimize the execution time of the algorithm and speed up the positioning of the host command address conversion exception problem.

[0173] The embodiment of the application also provides a computer system, which comprises a host and an NVMe accelerator card, and is used to execute the address conversion exception analysis method of the embodiment.

[0174] The embodiment of the application also provides a non-volatile readable storage medium, which stores a computer program, wherein the computer program is executed by a processor to execute the address conversion exception analysis method of the embodiment.

[0175] The various embodiments in the specification are described in progressive manner, and each embodiment focuses on the difference from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0176] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, device, or computer program product. Therefore, the embodiments of the present application can adopt a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present application can adopt a computer program product in the form of being implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program codes.

[0177] The embodiments of the present application are described with reference to flowcharts and / or block diagrams according to the method, terminal device (system), and computer program product of the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of the flows and / or blocks can be implemented by computer program instructions. These computer program instructions can be provided to a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the computer or other programmable data processing terminal device produce a device implemented in the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that performs the functions specified in the flow(s) or block(s).

[0178] These computer program instructions can also be stored in a computer readable memory capable of directing the computer or other programmable data processing terminal device to work in a specific manner, so that the instructions stored in the computer readable memory produce a manufactured product including instruction apparatus, which implements the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that performs the functions specified in the flow(s) or block(s).

[0179] These computer program instructions can also be loaded into a computer or other programmable data processing terminal device, so that a series of operation steps are performed on the computer or other programmable terminal device to produce a computer implemented process, so that the instructions executed on the computer or other programmable terminal device provide a process for implementing the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that performs the functions specified in the flow(s) or block(s).

[0180] Although preferred embodiments of the application have been described herein, changes and modifications can be suggested to one skilled in the art, and it is intended that the scope of the application be limited only by the appended claims.

[0181] Finally, it is to be understood that the phraseology or terminology employed herein, such as "first" and "second", etc., are for descriptive purposes and should not be construed as limiting. Also, the use of "including" and "comprising" as well as other like terms is used herein to mean and convey the idea of "including but not limited to" or "comprising but not limited to" and is not intended to (and should not be construed as) signifying that the scope of the application is intended to be limited to whatever specific phenomena the term recited in the clause is used to describe.

[0182] The principles and implementations of the present application have been described above with the specific examples. The above description is only intended to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation and application range can be changed, and the above description should not be understood as limiting the present application.

Claims

1. A method for address translation anomaly analysis, characterized in that, Applied to a computer system, the computer system including a host and an NVMe acceleration card, the method includes: Execute the firmware log analysis thread to extract the request parameter information and response data information of any admin command in the firmware log of the NVMe accelerator card; The PCIe packet analysis thread is executed to extract any PCIe packet generated by the PCIe protocol analyzer between the host and the NVMe acceleration card. The PCIe packet represents the request data or response data of any admin command or the request data or response data of any IO command. Based on the request parameter information and response data information of any admin command extracted from the firmware log and any extracted PCIe message, determine whether the NVMe accelerator card has any abnormal address translation for any admin command and any abnormal address translation for any IO command. Specifically, when the length of any PCIe message is 64 bytes and the starting address of the message is within the address range of any admin command request queue, the admin command request verification process is executed. The binary message data of the PCIe message is converted into a target admin command request. The parameter content of the target admin command request is compared with the parameter content of any admin command request in the firmware log. When no matching parameter content is found, it indicates that any admin command request has an abnormal address conversion. When the length of any PCIe packet is 64 bytes and the packet's starting address is within the address range of any IO command request queue, the IO command request verification process is executed. The binary packet data of the PCIe packet is converted into a target IO command request. When the command type of the target IO command request is a read command request or a write command request, the corresponding PRP table address is obtained from the target IO command request and stored in the IO PRP address set. The PRP address verification process is executed when any of the following conditions exist: when the PCIe packet length is 64 bytes and the packet header address is not within the address range of any admin command request queue and not within the address range of any IO command request queue; when the PCIe packet length is 16 bytes and the packet header address is not within the address range of any admin command response queue and not within the address range of any IO command response queue; and when the PCIe packet length is not any of 4, 16, or 64 bytes. During the execution of the PRP address verification process, if the packet header address of any PCIe packet simultaneously satisfies the following conditions: it is inconsistent with the PRP table address corresponding to any admin command read from the firmware log, it is inconsistent with the PRP table address obtained from the target IO command request, it is not in the admin PRP address set composed of the PRP table addresses of the admin commands, and it is not in the IO PRP address set composed of the PRP table addresses of the IO commands, then it is determined that any IO command request has an address abnormal translation.

2. The method according to claim 1, characterized in that, Based on the request parameter information and response data information of any admin command extracted from the firmware log, and any extracted PCIe packet, determine whether the NVMe accelerator card exhibits abnormal address translation for any admin command and abnormal address translation for any IO command, including: Based on the header address of any PCIe message, determine whether the message data of the PCIe message belongs to any one of the queue base address, queue depth, or MSI-X address. Based on the message length of any PCIe message, determine which of the following processes to execute: MSI-X address verification process, NVMe command request check process, NVMe command response check process, and PRP address verification process. The MSI-X address verification process is used to determine whether the firmware of the NVMe accelerator card has been interrupted; the NVMe command request check process is used to determine whether any admin command request has an abnormal address translation; the NVMe command response check process is used to determine whether any admin command response or any IO command response is incorrect; and the PRP address verification process is used to determine whether any IO command request has an abnormal address translation.

3. The method according to claim 2, characterized in that, Based on the header address of any PCIe packet, determine whether the packet data belongs to any of the following: queue base address, queue depth, or MSI-X address: When the header address of any PCIe message is the base address register address of the request queue or response queue of any admin command, the message data of that PCIe message is used as the queue base address and stored in the queue attribute set. When the header address of any PCIe packet is the depth register address of the request queue or response queue of any admin command, the packet data of the PCIe packet is used as the queue depth and stored in the queue attribute set. When the starting address of any PCIe message is the MSI-X interrupt register address of the response queue of any admin command, the message data of that PCIe message is used as the MSI-X address and stored in the MSI-X address set.

4. The method according to claim 3, characterized in that, Based on the message length of any PCIe message, determine whether to execute any one of the following procedures: MSI-X address verification process, NVMe command request check process, NVMe command response check process, and PRP address verification process, including: When the PCIe packet length is 4 bytes, the MSI-X address verification process is executed. When the PCIe packet length is 64 bytes, the NVMe command request check process is executed; When the PCIe packet length is 16 bytes, the NVMe command response check process is executed; When the PCIe packet length is not any of 4, 16, or 64 bytes, the PRP address verification process is executed.

5. The method according to claim 4, characterized in that, The execution of the MSI-X address verification process includes: Detect whether the starting address of the PCIe packet is located in the MSI-X address set; When the header address of the PCIe message is located in the MSI-X address set, it indicates that the firmware of the NVMe accelerator card has triggered an MSI-X interrupt. When the header address of the PCIe packet is not in the MSI-X address set, the PRP address verification process is executed.

6. The method according to claim 4, characterized in that, The NVMe command request check process includes: When the starting address of the PCIe packet is within the address range of any admin command request queue, the packet data of the PCIe packet is treated as an admin command request, and the admin command request verification process is executed. The admin command request verification process includes: The binary message data of the PCIe packet is converted into a target admin command request. The parameter content of the target admin command request is compared with the parameter content of any admin command request in the firmware log. If no matching parameter content is found, it indicates that any admin command request has an address anomaly. When a matching parameter content is found, the command type corresponding to the target admin command request is determined to be either creating an IO request queue or creating an IO response queue through the opcode field of the target admin command request. The queue information and interrupt vector of the IO request queue or IO response queue are extracted from the target admin command request and added to the queue attribute set. When the starting address of the PCIe packet is within the address range of any IO command request queue, the packet data is treated as an IO command request, and the IO command request verification process is executed. The IO command request verification process includes: After converting the binary message data of the PCIe message into a target IO command request, the command type of the target IO command request is determined to be a read command request or a write command request based on the opcode field of the target IO command request. When the command type of the target IO command request is a read command request or a write command request, the corresponding PRP table address is obtained from the target IO command request and stored in the IO PRP address set; When the command type of the target I / O command request is not a read command request or a write command request, stop processing the PCIe message; When the header address of the PCIe packet is not within the address range of any admin command request queue and not within the address range of any IO command request queue, the PRP address verification process is executed.

7. The method according to claim 4, characterized in that, The NVMe command response check process includes: When the starting address of the PCIe packet is within the address range of any admin command response queue, the packet data of the PCIe packet is used as an admin command response, and the admin command response verification process is executed. The admin command response verification process includes: The binary message data of the PCIe message is converted into a target admin command response, and the queue identifier and queue head pointer of the target admin command response are extracted. The queue identifier is checked to see if it exists in the queue attribute set and if the queue head pointer is less than the queue depth. If the check fails, it indicates that the target admin command has an error response; if the check passes, the firmware log analysis thread is notified to read the next admin command. When the starting address of the PCIe packet is within the address range of any IO command response queue, the packet data is treated as an IO command response, and an IO command response verification process is executed. The IO command response verification process includes: The binary message data of the PCIe message is converted into a target IO command response, and the queue identifier and queue head pointer of the target IO command response are extracted. The queue identifier is checked to see if it exists in the queue attribute set and if the queue head pointer is less than the queue depth. When the check fails, it indicates that the target I / O command response is incorrect; When the header address of the PCIe packet is not within the address range of any admin command response queue and not within the address range of any IO command response queue, the PRP address verification process is executed.

8. The method according to claim 7, characterized in that, The PRP address verification process includes: When the starting address of a PCIe message is found to simultaneously meet the following conditions: it is inconsistent with the PRP table address corresponding to any admin command read from the firmware log, it is inconsistent with the corresponding PRP table address obtained from the target IO command request, it is not in the admin PRP address set composed of the PRP table addresses of the admin commands, and it is not in the IO PRP address set composed of the PRP table addresses of the IO commands, then it is determined that any IO command request has an address translation error.

9. The method according to claim 8, characterized in that, The method further includes: Count the number of times any address matches among multiple address matches in the PCIe packet analysis thread; The execution priority of the multiple address matches is updated periodically based on the number of times any address matches, wherein the more times any address matches, the higher the execution priority. The PCIe packet analysis thread is executed according to the execution priority of multiple address matching.

10. A computer system, characterized in that, The computer system includes a host and an NVMe acceleration card, and the computer system is used to execute the address translation anomaly analysis method according to any one of claims 1-9.

11. A non-volatile readable storage medium, characterized in that, The non-volatile readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it performs the address translation anomaly analysis method according to any one of claims 1-9.

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