Reconstruction method and system for programmable logic device

Abstract

The invention discloses a programmable logic device reconfiguration method and system, and relates to the technical field of power electronics, the method is applied to an FPGA reconfiguration system comprising an FPGA, a refresh chip and at least one memory, and the method comprises the following steps: after it is determined that reconfiguration information contained in a received reconfiguration instruction is valid, reconfiguration information contained in the reconfiguration instruction is valid; the received reconstructed data packet is verified; after it is determined that the reconfiguration data packet passes verification, the reconfiguration data packet is sent to the refresh chip, so that the refresh chip writes the reconfiguration data packet into each memory; after a reconfiguration starting instruction is received, a reconfiguration instruction is sent to the refreshing chip, so that the refreshing chip reconfigures the FPGA according to a firmware package obtained from any one of the storages according to the reconfiguration instruction, and the firmware package is determined according to the reconfiguration data package. According to the technical scheme, on the premise that programmable components are not added, FPGA reconstruction is achieved, the stability of FPGA reconstruction is improved, and the cost of FPGA reconstruction is reduced.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of power electronics technology, and in particular to a method and system for reconfiguring a programmable logic device. Background Art

[0002] Field Programmable Gate Array (FPGA) is an integrated circuit that can be programmed to change its logical functions according to user needs. It has high flexibility and can be customized for various digital logic designs. It has been widely used in many fields, such as communications, aerospace, automotive electronics, consumer electronics, etc. In some application scenarios with extremely harsh electromagnetic environments, such as 5G communication base stations, underground mine detection devices, or spacecraft, there are extremely high requirements for the stability and reliability of FPGA operation. In these application scenarios, FPGAs are usually deployed in locations that are inconvenient for maintenance personnel to directly access. Therefore, remote reconstruction of FPGAs has become a technical problem that needs to be solved urgently.

[0003] In the prior art, the FPGA is usually remotely reconfigured based on an FPGA system including an FPGA, a central processing unit (CPU), a memory, and a refresh chip. After the CPU receives the reconstruction instruction and reconstruction data, the reconfiguration data is stored in the memory through the refresh chip. The refresh chip obtains the reconstruction data from the memory and writes the reconstruction data into the FPGA, thereby realizing the remote reconstruction of the FPGA.

[0004] However, the cost of an FPGA system including two programmable components, FPGA and CPU, is relatively high, and the failure rate is relatively high. Summary of the invention

[0005] The present invention provides a programmable logic device reconstruction method and system, which realize FPGA reconstruction at a relatively low cost.

[0006] In a first aspect, an embodiment of the present invention provides a method for reconfiguring a programmable logic device (FPGA), characterized in that the method is applied to an FPGA reconstruction system including an FPGA, a refresh chip, and at least one memory, and the method includes:

[0007] After determining that the reconstruction information contained in the received reconstruction instruction is valid, verifying the received reconstruction data packet;

[0008] After determining that the reconstructed data packet passes verification, sending the reconstructed data packet to the refresh chip, so that the refresh chip writes the reconstructed data packet into each of the memories;

[0009] After receiving the start reconstruction instruction, a reconstruction instruction is sent to the refresh chip, so that the refresh chip reconstructs the FPGA according to the firmware package obtained from any of the memories by the reconstruction instruction, wherein the firmware package is determined according to the reconstruction data packet.

[0010] The technical solution of an embodiment of the present invention provides a method for reconstructing a programmable logic device (FPGA), which is applied to an FPGA reconstruction system including an FPGA, a refresh chip and at least one memory. The method includes: after determining that the reconstruction information contained in the received reconstruction instruction is valid, verifying the received reconstruction data packet; after determining that the reconstruction data packet has passed the verification, sending the reconstruction data packet to the refresh chip so that the refresh chip writes the reconstruction data packet into each of the memories; after receiving a start reconstruction instruction, sending a reconstruction instruction to the refresh chip so that the refresh chip reconstructs the FPGA according to a firmware package obtained from any of the memories by the reconstruction instruction, wherein the firmware package is determined based on the reconstruction data packet. In the above technical solution, after the FPGA receives the reconstruction instruction, it first judges the validity of the reconstruction information contained in the reconstruction instruction based on the core CPU integrated inside it. After determining that the reconstruction information is valid, it verifies the received reconstruction data packet, and implements the validity judgment of the reconstruction information and the verification of the reconstruction data packet based on the core CPU to reduce costs. After determining that the reconstruction data packet has passed the verification, the reconstruction data packet is sent to the refresh chip, so that the refresh chip writes the reconstruction data packet into the memory to realize the storage of the reconstruction data packet. After receiving the start reconstruction instruction, the reconstruction instruction is sent to the refresh chip, so that the refresh chip reconstructs the FPGA according to the firmware package obtained from the memory by the reconstruction instruction, and the reconstruction of the FPGA is realized without increasing the programmable components, thereby improving the stability of the FPGA reconstruction and reducing the cost of the FPGA reconstruction.

[0011] Furthermore, it also includes:

[0012] Determining the validity of the reconstruction information according to the firmware version number, firmware package size, and firmware identity authentication information contained in the reconstruction information;

[0013] In the case where it is determined that the firmware version number is higher than the current version number, the firmware package size is not larger than the storage capacity of the memory, and the firmware identity authentication information passes authentication, it is determined that the reconstruction information is valid.

[0014] Furthermore, the memory is a Flash memory. Accordingly, after determining that the reconstruction information included in the received reconstruction instruction is valid, the method further includes:

[0015] A space preparation instruction is sent to the refresh chip, so that the refresh chip formats a storage space in the Flash memory that is consistent with the size of the firmware package based on the size of the firmware package included in the space preparation instruction.

[0016] Furthermore, the received reconstructed data packet is verified, including:

[0017] Performing a correctness check on the reconstructed data packet through a redundancy check, and performing an integrity check on the reconstructed data packet based on a hash algorithm;

[0018] In the case where it is determined that the reconstructed data packet passes the correctness check and the integrity check, it is determined that the reconstructed data packet passes the check.

[0019] Furthermore, it also includes:

[0020] In response to the received reconstruction query instruction, the current firmware version is determined and returned.

[0021] In the second aspect, an embodiment of the present invention also provides an FPGA reconstruction system, comprising: an FPGA, a refresh chip and at least one memory, wherein the FPGA is used to verify a received reconstruction data packet after the FPGA determines that the reconstruction information contained in the received reconstruction instruction is valid; after determining that the reconstruction data packet has passed the verification, the reconstruction data packet is sent to the refresh chip; after receiving the start reconstruction instruction, the reconstruction instruction is sent to the refresh chip, so that the refresh chip reconstructs the FPGA according to the firmware package obtained from any of the memories according to the reconstruction instruction, wherein the firmware package is determined according to the reconstruction data packet; the refresh chip is used to send the reconstruction data packet to the memory; and is also used to reconstruct the FPGA according to the firmware package obtained from the memory according to the reconstruction instruction; each of the memories is used to store the reconstruction data packet.

[0022] Furthermore, the FPGA includes a status register, and the status register is used to detect the verification status of configuration information and data information in the firmware package.

[0023] Furthermore, the refresh chip is also used for:

[0024] After the reconstruction is completed, determining the reconstruction result of the FPGA based on the status bit of the status register;

[0025] When it is determined that the reconstruction result is a reconstruction failure, if the number of reconstruction times is not greater than a preset number, the FPGA is reconstructed according to the firmware package obtained from the memory; otherwise, the FPGA is reconstructed according to the original firmware package obtained from the memory.

[0026] Furthermore, the refresh chip is also used for:

[0027] When it is determined that the reconstruction result is a successful reconstruction, the configuration information and the state information in the firmware package are obtained from the memory at every preset time interval, and the FPGA is refreshed based on the configuration information and the state information.

[0028] Furthermore, the refresh chip is specifically used for:

[0029] Determine the verification status of the configuration information and data information in the firmware package based on the status bit of the status register;

[0030] When it is determined that the verification condition of the configuration information and / or data information is a verification abnormality, the reconstruction result of the FPGA is determined to be a reconstruction failure.

[0031] The description of the second aspect in this application can refer to the detailed description of the first aspect; and the beneficial effects of the description of the second aspect can refer to the analysis of the beneficial effects of the first aspect, which will not be repeated here.

[0032] These and other aspects of the present application will become more apparent from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 A schematic diagram of the structure of an FPGA system provided by the prior art;

[0035] Figure 2 A schematic diagram of the structure of another FPGA system provided by the prior art;

[0036] Figure 3 A flowchart of an FPGA reconstruction method provided by an embodiment of the present invention;

[0037] Figure 4 A schematic diagram of the structure of an FPGA reconstruction system provided by an embodiment of the present invention;

[0038] Figure 5 A flowchart of another FPGA reconstruction method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0039] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0040] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0041] The terms "first" and "second" and the like in the specification and drawings of this application are used to distinguish different objects, or to distinguish different processing of the same object, rather than to describe a specific order of objects.

[0042] In addition, the terms "including" and "having" and any variations thereof mentioned in the description of the present application are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include other steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices.

[0043] It should be mentioned before discussing exemplary embodiments in more detail that some exemplary embodiments are described as processes or methods depicted as flow charts. Although the flow charts describe various operations (or steps) as sequential processes, many operations therein can be implemented in parallel, concurrently or simultaneously. In addition, the order of various operations can be rearranged. The process can be terminated when its operation is completed, but can also have additional steps not included in the accompanying drawings. The process can correspond to methods, functions, procedures, subroutines, subprograms, etc. In addition, the embodiments in the present invention and the features in the embodiments can be combined with each other without conflict.

[0044] It should be noted that, in the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0045] In the description of the present application, unless otherwise specified, “plurality” means two or more.

[0046] Figure 1 A schematic diagram of the structure of an FPGA system provided by the prior art, such as Figure 1 As shown, the FPGA system includes an FPGA, a CPU, a memory, and a refresh chip. The FPGA is the main processor of the FPGA system and is used to process core services. The CPU is a coprocessor of the FPGA system and is used to assist the main processor in completing certain specific services, for example, jointly with the refresh chip to implement FPGA remote reconstruction services. The memory is responsible for storing the running firmware of the FPGA. The single line segment with an arrow indicates the data flow during the FPGA reconstruction process. When the CPU receives the reconstruction instruction and reconstruction data through the data interface, it will issue an instruction to the refresh chip to store the reconstruction data in the memory. After the memory completes writing the reconstruction data, the refresh chip can obtain the reconstruction data from the memory and write the reconstruction data into the FPGA to realize remote reconstruction of the FPGA.

[0047] However, this FPGA system uses a combination of FPGA and CPU. There are two programmable components in the system. The more components there are in the system, especially the more programmable components there are, the higher the failure rate of the system will be, and the lower the reliability and stability will be. In addition, the more components there are, the higher the manufacturing cost of the system will be.

[0048] Figure 2 A structural diagram of another FPGA system provided by the prior art, such as Figure 2 As shown, the FPGA system includes a master FPGA, a slave FPGA, and a memory. The master FPGA and the slave FPGA are of different models. The master FPGA has stronger performance and can be used as a master processor to process core business. The slave FPGA has weaker performance and can be used as a slave processor to refresh and reconstruct the master FPGA. The memory is responsible for storing the running firmware of the FPGA. The single line segment with an arrow indicates the data flow during the FPGA reconstruction process. When the master FPGA receives the reconstruction instruction and reconstruction data through the data interface, it will issue an instruction to the slave FPGA to store the reconstruction data in the memory. After the memory completes writing the reconstruction data, the slave FPGA can obtain the reconstruction data from the memory and write the reconstruction data to the FPGA, thereby realizing remote reconstruction of the FPGA.

[0049] However, this FPGA system uses a combination of a master FPGA and a slave FPGA. Although the use of refresh chips is reduced, there are still two programmable components in the system, and the programs of the two FPGAs need to be maintained, which has a high maintenance cost. In addition, the price of FPGA is usually higher than that of refresh chips and CPUs, and the manufacturing cost of the system is not advantageous.

[0050] Therefore, the present application proposes an FPGA reconstruction method to improve the reliability of reconstruction and reduce the reconstruction cost.

[0051] The FPGA reconstruction method proposed in this application will be described in detail below with reference to the diagrams and embodiments.

[0052] Figure 3 A flowchart of an FPGA reconstruction method provided in an embodiment of the present invention. This embodiment is applicable to situations where FPGA reconstruction is required. The method is applied to Figure 4 The FPGA reconstruction system shown in Figure 4 As shown, the FPGA reconstruction system includes an FPGA, a refresh chip and at least one memory, such as Figure 3 As shown, the method specifically comprises the following steps:

[0053] Step 310: After determining that the reconstruction information contained in the received reconstruction instruction is valid, verify the received reconstruction data packet.

[0054] FPGA is a programmable logic device that can be programmed and reconfigured at the hardware level to achieve parallel operation, similar to embedding multiple CPUs in a single chip, and its performance far exceeds that of a single CPU. FPGA integrates the collaborative functions that the CPU is responsible for in existing technologies into the internal implementation of FPGA by building a core CPU internally, and FPGA independently completes all business functions.

[0055] The reconstruction instruction may be understood as an instruction issued by a reconstruction system or server, and the reconstruction instruction includes reconstruction information.

[0056] Specifically, after the FPGA receives the reconstruction instruction sent by the reconstruction system or server, it can first determine the validity of the reconstruction information contained in the reconstruction instruction. After determining that the reconstruction information contained in the received reconstruction instruction is valid, it can return a valid instruction to the reconstruction system or server. After the reconstruction system or server receives the valid instruction, it can continue to send the reconstruction data packet. After the FPGA receives the reconstruction data packet, it can verify the reconstruction data packet to determine whether the reconstruction data packet is the data packet required for FPGA reconstruction and whether it is complete.

[0057] It should be noted that the validity judgment of the reconstruction information and the verification of the reconstructed data packet are both performed by the core CPU.

[0058] In the embodiment of the present invention, the FPGA implements the validity judgment of the reconstruction information contained in the received reconstruction instruction and the verification of the received reconstruction data packet based on the core CPU integrated therein, thereby avoiding the additional addition of programmable components and reducing costs.

[0059] Step 320: After determining that the reconstructed data packet passes verification, send the reconstructed data packet to the refresh chip, so that the refresh chip writes the reconstructed data packet into each of the memories.

[0060] Among them, the refresh chip is responsible for refreshing and reconstructing the FPGA. The refresh operation is a daily process of writing the configuration information and status information of the FPGA firmware in the memory (including internal logic units, such as lookup tables LUTs, registers, etc.) into the FPGA. The purpose is to redeploy the configuration information and status information, etc., to correct data loss and errors caused by some reasons inside the FPGA. For example, in extreme environments, the charge of the internal storage unit of the FPGA will be lost over time, resulting in data loss or errors. The reconstruction operation is the process of writing the firmware package (binary bit stream file) in the memory into the FPGA. The purpose is to make the FPGA run according to the program of the new version of the firmware.

[0061] The refresh chip supports a variety of memories, such as Nor Flash memory with parallel communication interface, Flash memory with SPI serial interface (Nor Flash memory or NAND Flash memory) and PROM memory. The size of FPGA firmware package is generally in the order of tens of MB, so the memory is generally selected from Nor Flash memory with smaller capacity and lower cost.

[0062] The memory constituting the FPGA reconstruction system may be at least one. When the memory is two or more, the memory may be a heterogeneous memory (a memory with a different circuit architecture) to store and back up the FPGA firmware or the key business data of the FPGA reconstruction system. For example, a Nor Flash memory with a parallel communication interface and a PROM memory are selected as the memory constituting the FPGA reconstruction system. The circuit architectures of these two types of memories are different. In a harsh environment, the probability of two memories with different structures being disturbed at the same time is much lower than that of two memories with the same structure, which improves the stability of the FPGA reconstruction system.

[0063] Specifically, after determining that the reconstruction data packet has passed the verification, the reconstruction data packet can be sent to the refresh chip so that the refresh chip writes the reconstruction data packet into the memory. After the storage is completed, the memory can send a storage completion response to the refresh chip, and the refresh chip can send the storage completion response to the FPGA, and the FPGA can further send the storage completion response to the reconstruction system or server.

[0064] It should be noted that sending the reconstruction data packet to the refresh chip, receiving the storage completion response sent by the refresh chip, and sending the storage completion response to the reconstruction system or server are all performed by the core CPU.

[0065] In the embodiment of the present invention, after it is determined that the reconstructed data packet has passed the verification, the reconstructed data packet may be sent to the refresh chip, and the refresh chip may write the received reconstructed data packet into the memory to implement the storage of the reconstructed data packet.

[0066] Step 330: After receiving the start-reconstruction instruction, send the reconstruction instruction to the refresh chip, so that the refresh chip reconstructs the FPGA according to the firmware package obtained from any of the memories by the reconstruction instruction.

[0067] The firmware package is determined according to the reconstructed data package.

[0068] Specifically, after receiving the storage completion response, the reconstruction system or server can send a start reconstruction instruction to the FPGA. After receiving the start reconstruction instruction, the FPGA can send a reconstruction instruction to the refresh chip. The refresh chip can obtain the firmware package required for FPGA reconstruction in any memory constituting the FPGA reconstruction system. It can be understood that the firmware package required for FPGA reconstruction is determined by the reconstruction data packet stored in the memory by the refresh chip. The refresh chip can also write the firmware package required for FPGA reconstruction into the FPGA to realize the firmware reconstruction of the FPGA.

[0069] It should be noted that the core CPU receives the start reconstruction instruction sent by the reconstruction system or server and sends the reconstruction instruction to the refresh chip.

[0070] In an embodiment of the present invention, after receiving a start reconstruction instruction, a reconstruction instruction is sent to a refresh chip so that the refresh chip reconstructs the FPGA according to a firmware package obtained from a memory according to the reconstruction instruction, thereby realizing reconstruction of the FPGA without adding programmable components, improving the stability of FPGA reconstruction, and reducing the cost of FPGA reconstruction.

[0071] An FPGA reconstruction method provided by an embodiment of the present invention is applied to an FPGA reconstruction system including an FPGA, a refresh chip and at least one memory. The method includes: after determining that the reconstruction information contained in the received reconstruction instruction is valid, verifying the received reconstruction data packet; after determining that the reconstruction data packet has passed the verification, sending the reconstruction data packet to the refresh chip so that the refresh chip writes the reconstruction data packet into each of the memories; after receiving a start reconstruction instruction, sending the reconstruction instruction to the refresh chip so that the refresh chip reconstructs the FPGA according to a firmware package obtained from any of the memories by the reconstruction instruction, wherein the firmware package is determined based on the reconstruction data packet. In the above technical solution, after the FPGA receives the reconstruction instruction, it first judges the validity of the reconstruction information contained in the reconstruction instruction based on the core CPU integrated inside it. After determining that the reconstruction information is valid, it verifies the received reconstruction data packet, and implements the validity judgment of the reconstruction information and the verification of the reconstruction data packet based on the core CPU to reduce costs. After determining that the reconstruction data packet has passed the verification, the reconstruction data packet is sent to the refresh chip, so that the refresh chip writes the reconstruction data packet into the memory to realize the storage of the reconstruction data packet. After receiving the start reconstruction instruction, the reconstruction instruction is sent to the refresh chip, so that the refresh chip reconstructs the FPGA according to the firmware package obtained from the memory by the reconstruction instruction, and the reconstruction of the FPGA is realized without increasing the programmable components, thereby improving the stability of the FPGA reconstruction and reducing the cost of the FPGA reconstruction.

[0072] Figure 5 Flow chart of another FPGA reconstruction method provided by an embodiment of the present invention, this embodiment is concretized on the basis of the above embodiment. Figure 5 As shown, in this embodiment, the method may further include:

[0073] Step 510: Determine the validity of the reconstruction information according to the firmware version number, firmware package size, and firmware identity authentication information included in the reconstruction information included in the received reconstruction instruction.

[0074] Among them, the reconstruction information includes the firmware version number, firmware package size and firmware authentication information. The firmware authentication information can be understood as the authentication information of the reconstruction system or server that sends the reconstruction information, which is used to determine whether the reconstruction system or server that sends the reconstruction information is legal.

[0075] Specifically, after the FPGA receives the reconstruction instruction sent by the reconstruction system or server, it can first judge the validity of the reconstruction information contained in the reconstruction instruction. Specifically, the validity of the reconstruction information can be judged based on the firmware version number, firmware package size and firmware authentication information contained in the reconstruction information. For example, it can check whether the firmware version number is higher than the current version number, whether the firmware package size exceeds the limit, and whether the firmware authentication information passes the authentication.

[0076] Step 520: When it is determined that the firmware version number is higher than the current version number, the firmware package size is not larger than the storage capacity of the memory, and the firmware identity authentication information passes authentication, determine that the reconstruction information is valid.

[0077] Specifically, when it is determined that the reconstruction information satisfies the conditions that the firmware version number is higher than the current version number, the firmware package size is not larger than the storage capacity of the memory, and the firmware identity authentication information passes authentication, the reconstruction information is determined to be valid; when it is determined that the reconstruction information does not satisfy any one of the conditions that the firmware version number is higher than the current version number, the firmware package size is not larger than the storage capacity of the memory, and the firmware identity authentication information passes authentication, the reconstruction information is determined to be invalid.

[0078] In the embodiment of the present invention, the validity judgment of the reconstruction information contained in the received reconstruction instruction is implemented.

[0079] It should be noted that, when the memory is a Flash memory, step 530 is executed after step 520 to format the storage space, and when the memory is other memory, step 540 is executed after step 520 without executing step 530.

[0080] Step 530: Send a space preparation instruction to the refresh chip, so that the refresh chip formats the storage space in the Flash memory that is consistent with the size of the firmware package based on the size of the firmware package included in the space preparation instruction.

[0081] Among them, the Flash memory uses two different stable states (usually a high level and a low level) to represent the data bits 0 and 1, and only 1 can be written as 0, and 0 cannot be written as 1.

[0082] Specifically, since the Flash type memory cannot write 0 as 1, if any memory constituting the FPGA reconstruction system is a Flash type memory, after determining that the reconstruction information is valid, a space preparation instruction can be sent to the refresh chip. The refresh chip can format the storage space in the Flash type memory that is consistent with the firmware package size based on the firmware package size contained in the space preparation instruction, so as to set the data bits of the storage space in the Flash type memory that is consistent with the firmware package size to 1, thereby facilitating data storage in the Flash type memory.

[0083] Of course, after completing formatting, the Flash memory can send a formatting completion response to the refresh chip, the refresh chip can send the formatting completion response to the FPGA, and the FPGA can further send the formatting completion response to the reconstruction system or server.

[0084] In the embodiment of the present invention, the Flash memory is formatted so that the Flash memory has the ability to store data.

[0085] Step 540: Verify the received reconstructed data packet.

[0086] In one implementation, step 540 may specifically include:

[0087] The correctness of the reconstructed data packet is checked by redundancy check, and the integrity of the reconstructed data packet is checked based on a hash algorithm; if it is determined that the reconstructed data packet passes the correctness check and the integrity check, it is determined that the reconstructed data packet has passed the check.

[0088] Specifically, after receiving the formatting completion response, the reconstruction system or server can send a reconstruction data packet. After the FPGA receives the reconstruction data packet, it can verify the reconstruction data packet, that is, it can verify the correctness and integrity of the reconstruction data packet to determine whether the reconstruction data packet is the data packet required for FPGA reconstruction and whether it is complete.

[0089] Specifically, each data in the reconstructed data packet is composed of a data body, a redundant check code and a hash value. The redundant check code is obtained by processing the data body based on the redundant check rule. Therefore, by determining whether each redundant check code can be obtained by processing the corresponding data body through the redundant check rule, the correctness of each data can be checked, and then the correctness of the reconstructed data packet can be checked. The hash value is obtained by processing the data body based on the hash algorithm. Therefore, by determining whether each hash value can be obtained by processing the corresponding data body through the hash algorithm, the integrity of each data can be checked, and then the integrity of the reconstructed data packet can be checked.

[0090] When it is determined that the reconstructed data packet passes the correctness check and the integrity check, it is determined that the reconstructed data packet passes the check.

[0091] In the embodiment of the present invention, the correctness and integrity check of the received reconstructed data packet is implemented.

[0092] Step 550: Send the reconstructed data packet to the refresh chip, so that the refresh chip writes the reconstructed data packet into each of the memories.

[0093] Specifically, when it is determined that the reconstructed data packet has passed the correctness and integrity check, it can be determined that the reconstructed data packet has passed the check, and then, a data storage instruction can be sent to the refresh chip. After receiving the data storage response instruction sent by the refresh chip, the reconstructed data packet is sent to the refresh chip, so that the refresh chip writes the reconstructed data packet into the memory.

[0094] As mentioned above, after storage is completed, the memory can send a storage completion response to the refresh chip, the refresh chip can send the storage completion response to the FPGA, and the FPGA can further send the storage completion response to the reconstruction system or server.

[0095] In the embodiment of the present invention, after it is determined that the reconstructed data packet has passed the verification, the reconstructed data packet may be sent to the refresh chip, and the refresh chip may write the received reconstructed data packet into the memory to implement the storage of the reconstructed data packet.

[0096] Step 560: After receiving the start-reconstruction instruction, send the reconstruction instruction to the refresh chip, so that the refresh chip reconstructs the FPGA according to the firmware package obtained from any of the memories by the reconstruction instruction.

[0097] As mentioned above, after receiving the storage completion response, the reconstruction system or server can send a start reconstruction instruction to the FPGA. After receiving the start reconstruction instruction, the FPGA can send a reconstruction instruction to the refresh chip. The refresh chip can obtain the firmware package required for FPGA reconstruction in any memory constituting the FPGA reconstruction system. Furthermore, the refresh chip can write the firmware package required for FPGA reconstruction into the FPGA to realize the firmware reconstruction of the FPGA.

[0098] In an embodiment of the present invention, after receiving a start reconstruction instruction, a reconstruction instruction is sent to a refresh chip so that the refresh chip reconstructs the FPGA according to a firmware package obtained from a memory according to the reconstruction instruction, thereby realizing reconstruction of the FPGA without adding programmable components, improving the stability of FPGA reconstruction, and reducing the cost of FPGA reconstruction.

[0099] Step 570: In response to the received reconstruction query instruction, determine and return the current firmware version.

[0100] Specifically, the reconstruction system or server can send a reconstruction query instruction to the FPGA to verify whether the FPGA is reconstructed successfully. After receiving the reconstruction query instruction, the FPGA can determine the current firmware version and send the reconstruction query response instruction to the reconstruction system or server to send the current firmware version.

[0101] In the embodiment of the present invention, in response to the received reconstruction query instruction, the current firmware version can be determined and returned to implement verification of the FPGA reconstruction.

[0102] An FPGA reconstruction method provided by an embodiment of the present invention is applied to an FPGA reconstruction system including an FPGA, a refresh chip and at least one memory, and the method includes: judging the validity of the reconstruction information according to the firmware version number, firmware package size and firmware identity authentication information contained in the reconstruction information; determining that the reconstruction information is valid when it is determined that the firmware version number is higher than the current version number, the firmware package size is not greater than the storage capacity of the memory and the firmware identity authentication information passes the authentication; sending a space preparation instruction to the refresh chip so that the refresh chip formats the storage space in the Flash memory that is consistent with the firmware package size based on the firmware package size contained in the space preparation instruction; verifying the received reconstruction data packet; sending the reconstruction data packet to the refresh chip so that the refresh chip writes the reconstruction data packet into each of the memories; after receiving the start reconstruction instruction, sending the reconstruction instruction to the refresh chip so that the refresh chip reconstructs the FPGA according to the firmware package obtained from any of the memories by the reconstruction instruction; and determining and returning the current firmware version in response to the received reconstruction query instruction. In the above technical solution, after the FPGA receives the reconstruction instruction, it first judges the validity of the reconstruction information based on the firmware version number, firmware package size and firmware identity authentication information contained in the reconstruction information contained in the reconstruction instruction based on the core CPU integrated inside it. When it is determined that the firmware version number is higher than the current version number, the firmware package size is not greater than the storage capacity of the memory and the firmware identity authentication information passes the authentication, it is determined that the reconstruction information is valid. After determining that the reconstruction information is valid, a space preparation instruction is sent to the refresh chip, so that the refresh chip formats the storage space in the Flash type memory that is consistent with the firmware package size based on the firmware package size contained in the space preparation instruction, thereby realizing the formatting of the Flash type memory, so that the Flash type memory has the ability to store data. Then, the correctness and integrity of the received reconstruction data packet can be checked, and the validity judgment of the reconstruction information and the verification of the reconstruction data packet can be realized based on the core CPU, so as to reduce the cost. After determining that the reconstruction data packet has passed the verification, the reconstruction data packet is sent to the refresh chip, so that the refresh chip writes the reconstruction data packet into the memory, and the storage of the reconstruction data packet is realized. After receiving the start reconstruction instruction, the reconstruction instruction is sent to the refresh chip, so that the refresh chip reconstructs the FPGA according to the firmware package obtained from the memory by the reconstruction instruction, and the reconstruction of the FPGA is realized without adding programmable components, thereby improving the stability of the FPGA reconstruction, reducing the cost of the FPGA reconstruction, and reducing the maintenance cost of the programmable device code. In addition, after receiving the reconstruction query instruction, in response to the reconstruction query instruction, the current firmware version can be determined and returned to realize the verification of the FPGA reconstruction.

[0103] The embodiment of the present invention also provides an FPGA reconstruction system, such as Figure 3 As shown, the system includes: an FPGA, a refresh chip and at least one memory, wherein the FPGA is used to verify the received reconstruction data packet after the FPGA determines that the reconstruction information contained in the received reconstruction instruction is valid; after determining that the reconstruction data packet has passed the verification, the reconstruction data packet is sent to the refresh chip; after receiving the start reconstruction instruction, the reconstruction instruction is sent to the refresh chip, so that the refresh chip reconstructs the FPGA according to the firmware package obtained from any of the memories according to the reconstruction instruction, wherein the firmware package is determined according to the reconstruction data packet; the refresh chip is used to send the reconstruction data packet to the memory; and is also used to reconstruct the FPGA according to the firmware package obtained from the memory according to the reconstruction instruction; each of the memories is used to store the reconstruction data packet.

[0104] Among them, FPGA is the main processor of the FPGA reconstruction system, which is used to communicate with the external communication system and adopts a universal communication protocol. The protocol usually uses Ethernet, WIFI, SPI, UART, IIC, CAN, Zigbee, RS485, RS422, RS232, but is not limited to the above protocols. FPGA can be an SRAM type FPGA, that is, the FPGA integrates a configuration space similar to SRAM inside, which is used to temporarily cache the reconstruction data when executing the reconstruction process.

[0105] Refresh chips usually support Select Map interface and protocol for data transmission with FPGA. They also support UART, SPI or I2C interface and protocol for receiving control instructions from FPGA. They also support SPI and other interfaces to support expansion connections for driving multiple memories.

[0106] In one implementation, the FPGA includes a status register, and the status register is used to detect the verification status of configuration information and data information in the firmware package.

[0107] Among them, the "CRC error" and "BAD PACKET error" status bits of the status register respectively indicate the verification status of the configuration information and data information in the FPGA firmware package. When the "CRC error" and / or "BAD PACKET error" error flags appear, it can be known that the firmware package being written this time has an abnormality and the firmware package writing fails.

[0108] In one embodiment, the refresh chip is also used to: after the reconstruction is completed, determine the reconstruction result of the FPGA based on the status bit of the status register; when it is determined that the reconstruction result is a reconstruction failure, if the number of reconstructions is not greater than a preset number, reconstruct the FPGA according to the firmware package obtained from the memory; otherwise, reconstruct the FPGA according to the original firmware package obtained from the memory.

[0109] In one embodiment, the refresh chip is specifically used to: determine the verification status of the configuration information and data information in the firmware package based on the status bit of the status register; when it is determined that the verification status of the configuration information and / or data information is a verification abnormality, determine that the reconstruction result of the FPGA is a reconstruction failure.

[0110] In one embodiment, the refresh chip is further used to: when it is determined that the reconstruction result is a successful reconstruction, obtain the configuration information and status information in the firmware package from the memory at every preset time interval, and refresh the FPGA based on the configuration information and the status information.

[0111] Specifically, after determining that the FPGA reconstruction is completed, the refresh chip can obtain the "CRC error" and "BAD PACKET error" status bits of the status register, and determine the verification status of the configuration information and data information in the firmware package according to the "CRC error" and "BAD PACKET error" status bits. Specifically, when an error flag appears in the "CRC error", it is determined that the verification status of the configuration information is a verification exception; when an error flag appears in the "BAD PACKET error" status bit, it is determined that the verification status of the data information is a verification exception.

[0112] When it is determined that the verification of the configuration information and / or data information is abnormal, the reconstruction result of the FPGA is determined to be a reconstruction failure. At this time, the number of reconstructions of the FPGA can be determined. If the number of reconstructions is not greater than the preset number, the firmware package is obtained from the memory again, and the FPGA is reconstructed based on the firmware package to achieve multiple reconstructions of the FPGA. If the number of reconstructions is greater than the preset number, the original firmware package is obtained from the memory, and the FPGA is reconstructed based on the original firmware package to achieve firmware version rollback of the FPGA.

[0113] When it is determined that the configuration information and the data information are both verified normally, the reconstruction result of the FPGA is determined to be successful. At this time, the configuration information and state information in the firmware package can be obtained from the memory at a preset time interval.

[0114] The FPGA reconstruction system provided in the embodiment of the present invention can execute the FPGA reconstruction method provided in any embodiment of the present invention, and has the corresponding beneficial effects of the execution method.

[0115] In addition, the memory stores the original firmware package and the latest firmware package, realizing dual storage of the firmware package. Moreover, multiple memories ensure that there are firmware packages that can be used normally in harsh environments, improving the robustness and stability of the FPGA reconstruction system. The refresh chip continuously refreshes the FPGA based on the configuration information and status information, so that the FPGA is always in a stable working state, improving the stability of the FPGA.

[0116] In addition, the acquisition, storage, use, and processing of data in the technical solution of the present invention are in compliance with the relevant provisions of national laws and regulations.

[0117] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A method for reconfiguring a programmable logic device (FPGA), characterized in that: Applied to an FPGA reconstruction system including an FPGA, a refresh chip and at least one memory, the method comprises: After determining that the reconstruction information contained in the received reconstruction instruction is valid, verifying the received reconstruction data packet; After determining that the reconstructed data packet passes verification, sending the reconstructed data packet to the refresh chip, so that the refresh chip writes the reconstructed data packet into each of the memories; After receiving the start reconstruction instruction, a reconstruction instruction is sent to the refresh chip, so that the refresh chip reconstructs the FPGA according to the firmware package obtained from any of the memories by the reconstruction instruction, wherein the firmware package is determined according to the reconstruction data packet.

2. The FPGA reconstruction method according to claim 1, characterized in that: Also includes: Determining the validity of the reconstruction information according to the firmware version number, firmware package size, and firmware identity authentication information contained in the reconstruction information; In the case where it is determined that the firmware version number is higher than the current version number, the firmware package size is not larger than the storage capacity of the memory, and the firmware identity authentication information passes authentication, it is determined that the reconstruction information is valid.

3. The FPGA reconstruction method according to claim 2, characterized in that: The memory is a Flash memory. Accordingly, after determining that the reconstruction information included in the received reconstruction instruction is valid, the method further includes: A space preparation instruction is sent to the refresh chip, so that the refresh chip formats a storage space in the Flash memory that is consistent with the size of the firmware package based on the size of the firmware package included in the space preparation instruction.

4. The FPGA reconstruction method according to claim 1, characterized in that: Verify the received reconstructed data packet, including: Performing a correctness check on the reconstructed data packet through a redundancy check, and performing an integrity check on the reconstructed data packet based on a hash algorithm; In the case where it is determined that the reconstructed data packet passes the correctness check and the integrity check, it is determined that the reconstructed data packet passes the check.

5. The FPGA reconstruction method according to claim 1, characterized in that: Also includes: In response to the received reconstruction query instruction, the current firmware version is determined and returned.

6. An FPGA reconstruction system, characterized in that: include: An FPGA, a refresh chip and at least one memory, wherein the FPGA is used to verify a received reconstruction data packet after the FPGA determines that the reconstruction information contained in the received reconstruction instruction is valid; after determining that the reconstruction data packet has passed the verification, the reconstruction data packet is sent to the refresh chip; after receiving a start reconstruction instruction, the reconstruction instruction is sent to the refresh chip, so that the refresh chip reconstructs the FPGA according to a firmware package obtained from any of the memories according to the reconstruction instruction, wherein the firmware package is determined according to the reconstruction data packet; the refresh chip is used to send the reconstruction data packet to the memory; and is also used to reconstruct the FPGA according to the firmware package obtained from the memory according to the reconstruction instruction; each of the memories is used to store the reconstruction data packet.

7. The FPGA reconstruction system according to claim 6, characterized in that: The FPGA includes a status register, and the status register is used to detect the verification status of configuration information and data information in the firmware package.

8. The FPGA reconstruction system according to claim 7, characterized in that: The refresh chip is also used for: After the reconstruction is completed, determining the reconstruction result of the FPGA based on the status bit of the status register; When it is determined that the reconstruction result is a reconstruction failure, if the number of reconstruction times is not greater than a preset number, the FPGA is reconstructed according to the firmware package obtained from the memory; otherwise, the FPGA is reconstructed according to the original firmware package obtained from the memory.

9. The FPGA reconstruction system according to claim 8, characterized in that: The refresh chip is also used for: When it is determined that the reconstruction result is a successful reconstruction, the configuration information and the state information in the firmware package are obtained from the memory at a preset time interval, and the FPGA is refreshed based on the configuration information and the state information.

10. The FPGA reconstruction system according to claim 8, characterized in that: The refresh chip is specifically used for: Determine the verification status of the configuration information and data information in the firmware package based on the status bit of the status register; When it is determined that the verification condition of the configuration information and / or data information is a verification abnormality, the reconstruction result of the FPGA is determined to be a reconstruction failure.

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