A design method and system for a power device

Abstract

The present invention provides a design method and system for a power device, and relates to the technical field of chip design. The method includes: determining the expected breakdown voltage of a power field effect tube; determining the epitaxial layer doping concentration, epitaxial layer thickness and epitaxial layer resistivity of the power field effect tube; determining the well width and well depth of the power field effect tube in combination with the electric field uniformity principle; calculating the estimated on-resistance of the power field effect tube under different geometric unit types and different well spacings in combination with the distribution mode of the electric field in the depletion region of the power field effect tube; determining the target geometric unit type; calculating the optimal well spacing of the power field effect tube based on the target geometric unit type; and outputting the epitaxial layer doping concentration, epitaxial layer thickness, epitaxial layer resistivity, well width, well depth, target geometric unit type and optimal well spacing as design parameters. While ensuring the high performance of the power device design, the design cycle is shortened and the design cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a design method and system for a power device. Background Art

[0002] Power devices refer to semiconductor devices used to control and convert high-power electrical energy. They are mainly used for power management and driving of electronic equipment, such as power switching, rectification, amplification and inversion. Common power devices include power diodes, thyristors, power field-effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), etc. Power field-effect transistors (PowerMOSFETs) are semiconductor devices that can switch and control electrical energy under high-frequency and high-current conditions. It uses a metal oxide semiconductor structure to control the conduction state between the source and the drain through the gate voltage, and has the advantages of fast switching speed and low loss. The purpose of power device design is to optimize the performance parameters of the device to ensure that the device meets the safety and reliability requirements of the application while operating efficiently.

[0003] Power field effect transistors are important in modern electronic devices. Due to their high-frequency switching capability, low on-resistance and high reliability, they are widely used in power management, motor drive and inverter fields, improving the efficiency and stability of the system. They are key devices for promoting efficient power conversion and miniaturization. Designing power devices is the basis for meeting the needs of modern electronic systems, especially in terms of energy saving, efficient power conversion and miniaturization. Through reasonable design, energy loss can be reduced, device performance can be optimized, and it can be adapted to complex application environments. In addition, the design can also customize device parameters according to specific application scenarios to improve the overall efficiency and stability of the system, thereby promoting technological progress and economic benefits.

[0004] However, in the design process of existing power devices, the power device parameters are often determined based on a large number of experimental processes. However, due to the large number of variable parameters of power devices, the target optimization of multiple variable parameters through this method is extremely inefficient and costly, and leads to a long design cycle of power devices. Summary of the invention

[0005] In order to solve the technical problem that the existing power devices in the prior art are often designed based on a large number of test processes to determine the power device parameters, but due to the large number of variable parameters of the power device, the target optimization of multiple variable parameters by this method is extremely inefficient and costly, and the design cycle of the power device is too long, the present invention provides a design method and system for a power device.

[0006] The technical solution provided by the embodiment of the present invention is as follows:

[0007] First aspect

[0008] An embodiment of the present invention provides a method for designing a power device, comprising:

[0009] S1: Determine the expected breakdown voltage of the power field effect transistor;

[0010] S2: Determine the epitaxial layer doping concentration, epitaxial layer thickness and epitaxial layer resistivity of the power field effect transistor with the expected breakdown voltage as a constraint;

[0011] S3: Based on the expected breakdown voltage and the principle of electric field uniformity, the well width and well depth of the power field effect transistor are determined;

[0012] S4: Based on the distribution of the electric field in the depletion region of the power field effect transistor, the estimated on-resistance of the power field effect transistor under different geometric unit types and different well spacings is calculated, where the well spacing is the spacing distance between two adjacent P-type wells in the horizontal direction;

[0013] S5: Determine the geometric unit type that makes the estimated on-resistance take the minimum value among the different geometric unit types as the target geometric unit type;

[0014] S6: Calculate the optimal well spacing of the power field effect transistor based on the target geometric unit type with the goal of minimizing the estimated on-resistance;

[0015] S7: Output epitaxial layer doping concentration, epitaxial layer thickness, epitaxial layer resistivity, well width, well depth, target geometric unit type and optimal well spacing as design parameters of the power field effect transistor.

[0016] Second aspect

[0017] An embodiment of the present invention provides a power device design system, including:

[0018] processor;

[0019] A memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the power device design method of the first aspect is implemented.

[0020] The third aspect

[0021] An embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, the power device design method according to the first aspect is implemented.

[0022] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0023] In the present invention, the epitaxial layer doping concentration, epitaxial layer thickness and epitaxial layer resistivity of the power field effect tube are determined based on the expected breakdown voltage, and the on-resistance is optimized while meeting the high voltage requirements, balancing the device performance and efficiency, and realizing customized design for different application scenarios, thereby improving the overall performance and reliability of the power device. The well width and well depth of the power field effect tube are determined in combination with the principle of electric field uniformity, which can effectively reduce the breakdown risk caused by local electric field concentration, while improving the reliability and withstand voltage performance of the device, and optimizing the current distribution, further reducing the on-resistance, and improving the overall efficiency of the power device. For the geometric unit type and well spacing of the power field effect tube, the geometric unit type with a small estimated on-resistance is selected in combination with the distribution mode of the electric field in the depletion region of the power field effect tube, which can effectively optimize the current path and thermal management performance of the power device, reduce the design complexity, solve the problem that the geometric parameters are difficult to determine, and improve the efficiency and stability of the device. After determining the geometric unit type, the optimal well spacing is determined with the estimated minimum on-resistance as a constraint to achieve a precise balance between performance and efficiency and reduce energy loss. This power device design approach reduces on-resistance while meeting high voltage requirements, and combines the electric field uniformity principle to determine the well width and well depth, effectively reducing the risk of electric field concentration and breakdown, while optimizing the geometric unit type and well spacing to minimize on-resistance and improve current path and thermal management performance. This comprehensive design approach can accurately balance multiple variable parameters while ensuring that the power device meets the requirements, which not only improves the efficiency, reliability and adaptability of the power device, but also meets the needs of diverse applications, while reducing design difficulty, ensuring a precise balance between performance and efficiency, and greatly reducing design costs and design cycles. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 A schematic diagram of a flow chart of a method for designing a power device provided by an embodiment of the present invention;

[0026] Figure 2 A schematic diagram of the structure of a power device design system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The technical solution of the present invention is described below in conjunction with the accompanying drawings.

[0028] In the embodiments of the present invention, words such as "exemplarily" and "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the word "example" is intended to present the concept in a specific way. In addition, in the embodiments of the present invention, the meaning expressed by "and / or" can be both, or it can be either of the two.

[0029] In order to make the technical problems, technical solutions and advantages to be solved by the present invention more clear, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.

[0030] Reference Manual Attached Figure 1 , showing a schematic flow chart of a method for designing a power device provided in an embodiment of the present invention.

[0031] An embodiment of the present invention provides a design method for a power device, which is applied to a power field effect transistor.

[0032] Methods include:

[0033] S1: Determine the expected breakdown voltage of the power FET.

[0034] Among them, the expected breakdown voltage of the power field effect tube is the core parameter during design, which is used to determine the maximum voltage range applicable to the device. Low doping and thick epitaxial layers are usually used for devices with high breakdown voltage, but will result in higher on-resistance. When optimizing the design, it is necessary to balance the trade-off between breakdown voltage and on-resistance. The power field effect tube is also called power MOSFET. Optionally, it can be a MOSFET with a silicon-based substrate.

[0035] S2: Determine the epitaxial layer doping concentration, epitaxial layer thickness and epitaxial layer resistivity of the power field effect transistor with the expected breakdown voltage as a constraint.

[0036] Among them, the epitaxial layer doping concentration refers to the concentration of the doping material in the epitaxial layer, which determines the width of the depletion region and the breakdown voltage of the device. A lower doping concentration helps to achieve a higher breakdown voltage, but it will lead to an increase in on-resistance. The epitaxial layer thickness refers to the physical thickness of the epitaxial layer, which is proportional to the doping concentration and the breakdown voltage. A larger thickness can increase the breakdown voltage, but it will also increase the on-resistance. The resistivity of the epitaxial layer refers to the resistance of the epitaxial layer per unit volume, which is affected by the doping concentration and electron mobility. The lower the resistivity, the smaller the on-resistance, but the breakdown voltage will be reduced. By optimizing the design of the epitaxial layer doping concentration, thickness and resistivity with the expected breakdown voltage as a constraint, it is possible to minimize the on-resistance while meeting high voltage requirements, and achieve balanced optimization of power device performance.

[0037] In a possible implementation manner, the doping concentration of the epitaxial layer is calculated as follows:

[0038]

[0039] in, represents the expected breakdown voltage, E c It represents the critical breakdown field of the substrate of the power field effect tube. represents the dielectric constant of the substrate of the power field effect tube, q represents the amount of electron charge, Represents the doping concentration of the epitaxial layer.

[0040] Optionally, the substrate may be silicon-based, in which case, .

[0041] It should be noted that the combination of the expected breakdown voltage, the critical breakdown field of the material and the dielectric constant can directly reflect the relationship between the physical properties and the design requirements, ensuring that the doping concentration not only meets the requirements of high breakdown voltage, but also controls the on-resistance within a reasonable range, thereby achieving design accuracy and reliability.

[0042] In a possible implementation manner, the thickness of the epitaxial layer is calculated as follows:

[0043]

[0044] Wherein, W represents the thickness of the epitaxial layer.

[0045] It should be noted that in the calculation process of the epitaxial layer thickness, the expected breakdown voltage is directly linked to the critical breakdown field of the material, ensuring that the thickness design meets the voltage resistance requirements. At the same time, the electric field distribution and breakdown performance of the epitaxial layer are optimized, providing a balanced design basis for reliability and efficiency for power devices.

[0046] In a possible implementation manner, the resistivity of the epitaxial layer is calculated as follows:

[0047]

[0048] in, represents the resistivity of the epitaxial layer, Indicates the electron mobility related to the substrate of the power field effect transistor.

[0049] It should be noted that calculating the resistivity of the epitaxial layer by combining the expected breakdown voltage, electron mobility and critical breakdown field of the material can accurately match the conduction performance and breakdown requirements of the power device, while optimizing the on-resistance and improving the efficiency and reliability of the device.

[0050] S3: Based on the expected breakdown voltage and the principle of electric field uniformity, the well width and depth of the power field effect transistor are determined.

[0051] Among them, the principle of electric field uniformity refers to the optimization of the geometric structure to make the electric field distribution in the depletion region as uniform as possible when designing a power field effect tube. The uniform electric field distribution can reduce the tip electric field effect, reduce the risk of breakdown caused by excessive local electric field, and improve the voltage resistance of the device. The well width and well depth specifically refer to the lateral width of the P-type well region of the power field effect tube and the longitudinal depth of the P-type well from the surface to the bottom. The well width affects the expansion range of the depletion region, the uniformity of the current path, and the on-resistance. The well depth affects the longitudinal gradient of the electric field distribution and determines the breakdown voltage and current distribution characteristics of the device. By combining the principle of electric field uniformity to design the well width and well depth, the electric field distribution is optimized, the risk of local breakdown is reduced, and the on-resistance is reduced, thereby improving the voltage resistance and working reliability of the device.

[0052] In a possible implementation, S3 specifically includes:

[0053] S301: The well depth is determined based on the critical breakdown field of the substrate in order to meet the desired breakdown voltage:

[0054]

[0055] Here, h represents the well depth.

[0056] S302: According to the process requirements based on area utilization and the principle of electric field uniformity, combined with the thermal resistance constraint of the power field effect transistor, the associated constraint function between the well depth and the well width is determined:

[0057]

[0058] in, It represents the thermal resistance of the power field effect tube, that is, the resistance of heat transfer from the power field effect tube to the outside, k represents the thermal conductivity of the substrate of the power field effect tube, L represents the available heat dissipation size of a single power unit of the power field effect tube, represents the well width, Represents the width of a single power unit, Indicates the effective area utilization of the power field effect tube, Represents an adjustable factor.

[0059] Among them, the adjustable factor can provide a certain flexibility for the well width while satisfying the electric field uniformity constraint to adapt to other design requirements. When it is equal to 1, it means strictly following the theoretical formula and maintaining the electric field uniformity principle. When it is greater than 1, it means relaxing the electric field uniformity constraint and increasing the well width to optimize other performance (such as thermal management or area utilization). When it is less than 1, it can be used for some special applications, but it may increase the risk of local breakdown. The area utilization rate generally needs to meet the process requirements and is usually between 50% and 80%.

[0060] Among them, thermal resistance describes an indicator of the device's heat dissipation capability, indicating the resistance to heat transfer from the inside to the outside.

[0061] S303: Solve the associated constraint function to obtain the well width.

[0062] It should be noted that the expected breakdown voltage and the critical breakdown field of the material are combined to ensure that the well depth meets the withstand voltage requirements. The well width and well depth are associated with the area utilization formula to achieve a balance between electric field uniformity and heat dissipation performance. This method can optimize thermal resistance and area utilization efficiency, avoid local breakdown, and provide design flexibility to meet a variety of process and performance requirements and improve device reliability and efficiency.

[0063] S4: Based on the distribution of the electric field in the depletion region of the power field effect transistor, calculate the estimated on-resistance of the power field effect transistor under different geometric unit types and different well spacings.

[0064] The well spacing is the distance between two adjacent P-type wells in the horizontal direction.

[0065] Among them, the power field effect tube depletion region is a part of the power field effect tube near the PN junction or P-type well region, which is formed due to the depletion of carriers. In the depletion region, the electric field distribution and the current expansion path are affected by the doping concentration and geometric structure, which determines the breakdown voltage and conduction characteristics of the device. In the depletion region, the electric field usually expands in a trapezoidal or symmetrical distribution, and its distribution is determined by the doping concentration, well width, well depth and geometric structure. Uniform electric field distribution helps to reduce local breakdown and improve the reliability and withstand voltage performance of the device. The geometric unit type refers to the arrangement structure of the gate, source and P-type well in the power field effect tube. At present, common types include linear units and hexagonal units. Different types affect the current path and area utilization of the device. The well spacing is the horizontal distance between two adjacent P-type wells. The well spacing affects the expansion range of the depletion region, the uniformity of the current path, and the size of the on-resistance. The on-resistance is the total resistance of the power field effect tube in the on state, including the epitaxial layer resistance, JFET resistance, accumulation layer resistance and channel resistance. The estimated on-resistance is used to quantify the impact of geometric unit type and well spacing on device performance. By analyzing the electric field distribution in the depletion region, calculating the on-resistance under different geometric unit types and well spacing, and selecting the optimal structure to balance the conduction performance and withstand voltage performance, the power device design is optimized.

[0066] In a possible implementation, the geometric unit types include linear units and hexagonal units.

[0067] Among them, the linear unit is a type of geometric unit of a power field effect tube, in which the gate, source and P-type well are arranged in a linear shape, usually with a parallel structure. The linear unit has a simple structure and is suitable for traditional planar design. Its characteristics are relatively simple manufacturing process, but due to the linear characteristics of the layout, the on-resistance is high, the current density utilization efficiency is low, and the heat distribution and electric field distribution are relatively uneven. The hexagonal unit is another type of geometric unit of the power field effect tube, in which the gate, source and P-type well are arranged in a hexagonal array on the plane. This structure can utilize the area more effectively and provide higher current density. The geometric characteristics of the hexagonal unit make its electric field distribution more uniform, thereby reducing the risk of local breakdown caused by the tip effect. At the same time, its on-resistance is lower and the heat distribution is more uniform, which is suitable for the design of high-performance power devices.

[0068] When the geometry element type is a linear element, the estimated on-resistance is calculated as follows:

[0069]

[0070] in, They represent the estimated on-resistance, epitaxial layer resistance, JFET resistance, accumulation layer resistance and channel resistance of the power field effect transistor when the geometry unit type is a linear unit. represents the depletion region depth, represents the effective depth of the current extension in the depletion region, b represents the well spacing, i.e., the horizontal spacing between adjacent power units, and ln represents the natural logarithm. represents the geometric factor associated with the linear unit, The depletion region electric field affects the well width. The extended well width formed by the expansion, represents the surface resistivity of the accumulation layer, represents the channel length, Indicates the channel width per unit area of ​​the power field effect transistor when the geometric unit type is a linear unit. Material- and temperature-dependent electron mobility, is the gate oxide capacitance, represents the gate voltage, It represents the threshold voltage, which is the minimum gate voltage required to form an inversion channel.

[0071] The surface resistivity of the accumulation layer is the carrier layer induced on the semiconductor surface due to the gate voltage applied, and its resistivity indicates the conductivity of the accumulation layer per unit area. Specifically, ,in, Represents the carrier concentration in the accumulation layer, which is related to the gate voltage V g and threshold voltage V T related, It represents the electron mobility which is related to material properties and temperature, and it represents the electron charge. The electron mobility related to materials and temperature refers to the ability of electrons to move in semiconductor materials under the action of electric fields, which is closely related to material properties and temperature. Gate oxide capacitance refers to the capacitance formed by the isolation of the gate and the semiconductor channel through the oxide layer in MOSFET. It is a very important physical parameter in MOSFET, which directly affects the switching performance, threshold voltage and current driving capability of the device. Specifically, ,in, represents the dielectric constant of the oxide layer associated with the material, Represents the thickness of the gate oxide layer, which is generally 10nm.

[0072] It should be noted that when the geometric unit type is a linear unit, this method of calculating the estimated on-resistance comprehensively considers the effects of the epitaxial layer resistance, JFET resistance, accumulation layer resistance, and channel resistance through a formula. By calculating the estimated on-resistance in this way, the resistance characteristics of different regions can be accurately described, such as the relationship between the depletion region depth and the current extension depth, the optimization effect of the well spacing on the current path, and the effect of the accumulation layer surface resistivity and channel parameters on the overall conduction performance. The formula also takes into account the gate oxide layer capacitance and the electric field extension effect, which can fully reflect the complex influence of the device geometry and material properties, thereby achieving accurate estimation of the on-resistance and providing a reliable theoretical basis for device optimization.

[0073] In a possible implementation manner, when the geometric unit type is a hexagonal unit, the calculation method of estimating the on-resistance is specifically as follows:

[0074]

[0075] in, They represent the estimated on-resistance, epitaxial layer resistance, JFET resistance, accumulation layer resistance and channel resistance of the power field effect transistor when the geometric unit type is a hexagonal unit. represents the geometric factor associated with the hexagonal unit, Indicates the channel width per unit area of ​​the power field effect transistor when the geometric unit type is a hexagonal unit.

[0076] It should be noted that in power MOSFET, the electric field expansion in the power field effect tube depletion region has an approximate uniformity feature. The current path in the power MOSFET is determined by the trapezoidal area formed by the expansion of the P-type well, and the 45-degree expansion angle assumption simplifies this complex three-dimensional electric field and current diffusion problem into a two-dimensional model, which can intuitively calculate the effective conductive area and thus quickly estimate the on-resistance. In addition, the model can well reflect the actual distribution of the electric field and current in most actual geometric units, making the deviation between theoretical analysis and experimental results small, and can achieve comprehensive analysis and optimization of different geometric unit types and well spacings, ensuring that the calculated results are close to the actual device performance.

[0077] Specifically, the calculation method of well width and well depth in the case of hexagonal units simplifies the complex three-dimensional electric field and current diffusion problems through the electric field diffusion method at a 45-degree angle, describes it with a two-dimensional model, and combines the geometric factors and parameters in the formula, such as the electric field expansion effect of the accumulation layer resistance and JFET resistance, as well as key factors such as channel width. This method can not only accurately describe the impact of well width and well depth on the electric field distribution, but also effectively optimize the current path and resistance distribution. By calculating in this way, the on-resistance can be quickly estimated on the basis of ensuring uniform distribution of the electric field, while ensuring the consistency between design optimization and actual performance, thereby improving the overall reliability and efficiency of the device.

[0078] S5: Determine a geometric unit type that minimizes the estimated on-resistance among different geometric unit types as a target geometric unit type.

[0079] It should be noted that by comparing the estimated on-resistance under different geometric unit types, the geometric unit type with the smallest on-resistance is selected as the target design, and the current path and electric field distribution are optimized, thereby reducing energy loss and improving the efficiency and reliability of power devices.

[0080] S6: Calculate the optimal well spacing of the power field effect transistor based on the target geometry cell type with the goal of minimizing the estimated on-resistance.

[0081] Among them, the optimal well spacing refers to the minimum well spacing value for the on-resistance of the power field effect tube by adjusting the horizontal spacing between two adjacent P-type wells under a specific geometric unit type. This spacing directly affects the electric field distribution, current path and device performance. By optimizing the well spacing under the target geometric unit type and minimizing the on-resistance, the on-performance and withstand voltage performance of the power device are balanced, thereby improving the overall efficiency and reliability.

[0082] In a possible implementation manner, the optimal well spacing is calculated as follows:

[0083]

[0084] in, represents the estimated on-resistance for the target geometry type, The optimal well spacing is the well spacing that minimizes the estimated on-resistance of the target geometry cell type. .

[0085] It should be noted that the advantage of calculating the optimal well spacing in this way is that the estimated on-resistance function under the target geometric unit type Take the derivative and find the minimum point , can accurately determine the well spacing with the smallest on-resistance. The first-order derivative in the formula , to ensure that the extreme point of the on-resistance is found, the second-order derivative Then verify that this point is the minimum value, thereby optimizing the performance of the device. In addition, this method is based on a mathematical optimization model and can be applied to a variety of geometric types, improving the flexibility and efficiency of the design while ensuring the accuracy and practicality of the calculation results.

[0086] S7: Output epitaxial layer doping concentration, epitaxial layer thickness, epitaxial layer resistivity, well width, well depth, target geometric unit type and optimal well spacing as design parameters of the power field effect transistor.

[0087] In actual application, based on the expected breakdown voltage, the epitaxial layer parameters (doping concentration, thickness and resistivity) of the power field effect transistor are optimized, the well width and well depth are designed in combination with the principle of electric field uniformity, the electric field distribution in the depletion region is analyzed, and the on-resistance under different geometric unit types and well spacings is calculated. The geometric unit type with the smallest on-resistance is selected as the target type, and the well spacing is optimized based on this to minimize the on-resistance. Finally, the epitaxial layer parameters, geometric structure and optimal well spacing are output to ensure the high efficiency, reliability and adaptability of the device.

[0088] Reference Manual Attached Figure 2 , showing a schematic structural diagram of a power device design system provided by the present invention.

[0089] The present invention further provides a power device design system 20, which is applied to the above-mentioned power device design method, and comprises:

[0090] Processor 201.

[0091] The memory 202 stores computer-readable instructions. When the computer-readable instructions are executed by the processor 201 , the power device design method according to the method embodiment is implemented.

[0092] The power device design system 20 provided by the present invention can execute the above-mentioned power device design method and achieve the same or similar technical effects. To avoid repetition, the present invention will not elaborate on them.

[0093] It should be understood that the processor in the embodiment of the present invention may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0094] It should also be understood that the memory in the embodiments of the present invention may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0095] The above embodiments can be implemented in whole or in part by software, hardware (such as circuits), firmware or any other combination. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When a computer instruction or computer program is loaded or executed on a computer, a process or function according to an embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state hard disk.

[0096] It should be understood that the term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship, but it may also indicate an "and / or" relationship. Please refer to the context for specific understanding.

[0097] In the present invention, "at least one" means one or more, and "plurality" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0098] It should be understood that in various embodiments of the present invention, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0099] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0100] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described equipment, devices and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0101] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0102] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0103] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0104] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods of various embodiments of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0105] An embodiment of the present invention provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, a design method for a power device as described in the method embodiment is implemented.

[0106] A computer-readable storage medium provided by the present invention can implement the steps and effects of the power device design method of the above method embodiment, and to avoid repetition, the present invention will not go into details.

[0107] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0108] In the present invention, the epitaxial layer doping concentration, epitaxial layer thickness and epitaxial layer resistivity of the power field effect tube are determined based on the expected breakdown voltage, and the on-resistance is optimized while meeting the high voltage requirements, balancing the device performance and efficiency, and realizing customized design for different application scenarios, thereby improving the overall performance and reliability of the power device. The well width and well depth of the power field effect tube are determined in combination with the principle of electric field uniformity, which can effectively reduce the breakdown risk caused by local electric field concentration, while improving the reliability and withstand voltage performance of the device, and optimizing the current distribution, further reducing the on-resistance, and improving the overall efficiency of the power device. For the geometric unit type and well spacing of the power field effect tube, the geometric unit type with a small estimated on-resistance is selected in combination with the distribution mode of the electric field in the depletion region of the power field effect tube, which can effectively optimize the current path and thermal management performance of the power device, reduce the design complexity, solve the problem that the geometric parameters are difficult to determine, and improve the efficiency and stability of the device. After determining the geometric unit type, the optimal well spacing is determined with the estimated minimum on-resistance as a constraint to achieve a precise balance between performance and efficiency and reduce energy loss. This power device design approach reduces on-resistance while meeting high voltage requirements, and combines the electric field uniformity principle to determine the well width and well depth, effectively reducing the risk of electric field concentration and breakdown, while optimizing the geometric unit type and well spacing to minimize on-resistance and improve current path and thermal management performance. This comprehensive design approach can accurately balance multiple variable parameters while ensuring that the power device meets the requirements, which not only improves the efficiency, reliability and adaptability of the power device, but also meets the needs of diverse applications, while reducing design difficulty, ensuring a precise balance between performance and efficiency, and greatly reducing design costs and design cycles.

[0109] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

[0110] There are a few points to note:

[0111] (1) The drawings of the embodiments of the present invention only relate to the structures related to the embodiments of the present invention. Other structures may refer to the general design.

[0112] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present invention, the thickness of layers or regions is exaggerated or reduced, that is, these drawings are not drawn according to the actual scale. It is understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element or there may be intermediate elements.

[0113] (3) In the absence of conflict, the embodiments of the present invention and the features therein may be combined with each other to obtain new embodiments.

[0114] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. The protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A method for designing a power device, characterized in that: Applied to power field effect transistors; the methods include: S1: Determine the expected breakdown voltage of the power field effect transistor; S2: Determine the epitaxial layer doping concentration, epitaxial layer thickness and epitaxial layer resistivity of the power field effect transistor with the expected breakdown voltage as a constraint; S3: Based on the expected breakdown voltage and in combination with the electric field uniformity principle, determine the well width and well depth of the power field effect transistor; S4: Calculate the estimated on-resistance of the power field effect transistor under different geometric unit types and different well spacings in combination with the distribution of the electric field in the depletion region of the power field effect transistor, wherein the well spacing is the spacing distance between two adjacent P-type wells in the horizontal direction; S5: Determine the geometric unit type that makes the estimated on-resistance take the minimum value among the different geometric unit types as the target geometric unit type; S6: taking the estimated on-resistance as minimum as the goal, calculating the optimal well spacing of the power field effect transistor based on the target geometric unit type; S7: Output the epitaxial layer doping concentration, the epitaxial layer thickness, the epitaxial layer resistivity, the well width, the well depth, the target geometric unit type and the optimal well spacing as design parameters of the power field effect transistor.

2. The method for designing a power device according to claim 1, characterized in that: The calculation method of the doping concentration of the epitaxial layer is specifically as follows: ， in, represents the expected breakdown voltage, E c It represents the critical breakdown field of the substrate of the power field effect tube. represents the dielectric constant of the substrate of the power field effect tube, q represents the amount of electron charge, Represents the doping concentration of the epitaxial layer.

3. The method for designing a power device according to claim 2, characterized in that: The calculation method of the epitaxial layer thickness is specifically as follows: ， Wherein, W represents the thickness of the epitaxial layer.

4. The method for designing a power device according to claim 2, characterized in that: The specific calculation method of the resistivity of the epitaxial layer is: ， in, represents the resistivity of the epitaxial layer, Indicates the electron mobility related to the substrate of the power field effect transistor.

5. The method for designing a power device according to claim 2, characterized in that: The S3 specifically includes: S301: The well depth is determined in combination with the critical breakdown field of the substrate with the goal of satisfying the desired breakdown voltage: ， Where h represents the well depth; S302: According to the process requirements based on area utilization and the principle of electric field uniformity, combined with the thermal resistance constraint of the power field effect transistor, a correlation constraint function between the well depth and the well width is determined: ， in, It represents the thermal resistance of the power field effect tube, that is, the resistance of heat transfer from the power field effect tube to the outside, k represents the thermal conductivity of the substrate of the power field effect tube, L represents the available heat dissipation size of a single power unit of the power field effect tube, represents the well width, o Represents the width of a single power unit, Indicates the effective area utilization of the power field effect tube, represents the adjustable factor; S303: Solving the associated constraint function to obtain the well width.

6. The method for designing a power device according to claim 1, characterized in that: The geometric unit types include linear units and hexagonal units; When the geometric unit type is a linear unit, the estimated on-resistance is calculated as follows: ， in, They represent the estimated on-resistance, epitaxial layer resistance, JFET resistance, accumulation layer resistance and channel resistance of the power field effect transistor when the geometry unit type is a linear unit. represents the depletion region depth, represents the effective depth of the current extension in the depletion region, b represents the well spacing, i.e., the horizontal spacing between adjacent power units, and ln represents the natural logarithm. represents the geometric factor associated with the linear unit, The depletion region electric field affects the well width. The extended well width formed by the expansion, represents the surface resistivity of the accumulation layer, represents the channel length, Indicates the channel width per unit area of ​​the power field effect transistor when the geometric unit type is a linear unit. Material- and temperature-dependent electron mobility, is the gate oxide capacitance, represents the gate voltage, It represents the threshold voltage, which is the minimum gate voltage required to form an inversion channel.

7. The method for designing a power device according to claim 6, characterized in that: When the geometric unit type is a hexagonal unit, the estimated on-resistance is calculated as follows: ， in, They represent the estimated on-resistance, epitaxial layer resistance, JFET resistance, accumulation layer resistance and channel resistance of the power field effect transistor when the geometric unit type is a hexagonal unit. represents the geometric factor associated with the hexagonal unit, Indicates the channel width per unit area of ​​the power field effect transistor when the geometric unit type is a hexagonal unit.

8. The method for designing a power device according to claim 1, characterized in that: The optimal well spacing is calculated as follows: ， in, represents the estimated on-resistance for the target geometry type, The optimal well spacing is the well spacing that minimizes the estimated on-resistance of the target geometry cell type. .

9. A power device design system, characterized in that: include: processor; A memory having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by the processor, the method for designing a power device according to any one of claims 1 to 8 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the power device design method according to any one of claims 1 to 8 is implemented.

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